Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Low-level exception handling code |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> |
| 6 | * Will Deacon <will.deacon@arm.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/linkage.h> |
| 23 | |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 24 | #include <asm/alternative.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 25 | #include <asm/assembler.h> |
| 26 | #include <asm/asm-offsets.h> |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 27 | #include <asm/cpufeature.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 28 | #include <asm/errno.h> |
Marc Zyngier | 5c1ce6f | 2013-04-08 17:17:03 +0100 | [diff] [blame] | 29 | #include <asm/esr.h> |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 30 | #include <asm/irq.h> |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 31 | #include <asm/memory.h> |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 32 | #include <asm/mmu.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 33 | #include <asm/ptrace.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 34 | #include <asm/thread_info.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 35 | #include <asm/uaccess.h> |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 36 | #include <asm/asm-uaccess.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 37 | #include <asm/unistd.h> |
| 38 | |
| 39 | /* |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 40 | * Context tracking subsystem. Used to instrument transitions |
| 41 | * between user and kernel mode. |
| 42 | */ |
| 43 | .macro ct_user_exit, syscall = 0 |
| 44 | #ifdef CONFIG_CONTEXT_TRACKING |
| 45 | bl context_tracking_user_exit |
| 46 | .if \syscall == 1 |
| 47 | /* |
| 48 | * Save/restore needed during syscalls. Restore syscall arguments from |
| 49 | * the values already saved on stack during kernel_entry. |
| 50 | */ |
| 51 | ldp x0, x1, [sp] |
| 52 | ldp x2, x3, [sp, #S_X2] |
| 53 | ldp x4, x5, [sp, #S_X4] |
| 54 | ldp x6, x7, [sp, #S_X6] |
| 55 | .endif |
| 56 | #endif |
| 57 | .endm |
| 58 | |
| 59 | .macro ct_user_enter |
| 60 | #ifdef CONFIG_CONTEXT_TRACKING |
| 61 | bl context_tracking_user_enter |
| 62 | #endif |
| 63 | .endm |
| 64 | |
| 65 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 66 | * Bad Abort numbers |
| 67 | *----------------- |
| 68 | */ |
| 69 | #define BAD_SYNC 0 |
| 70 | #define BAD_IRQ 1 |
| 71 | #define BAD_FIQ 2 |
| 72 | #define BAD_ERROR 3 |
| 73 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 74 | .macro kernel_ventry, el, label, regsize = 64 |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 75 | .align 7 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 76 | sub sp, sp, #S_FRAME_SIZE |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 77 | b el\()\el\()_\label |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 78 | .endm |
| 79 | |
| 80 | .macro kernel_entry, el, regsize = 64 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 81 | .if \regsize == 32 |
| 82 | mov w0, w0 // zero upper 32 bits of x0 |
| 83 | .endif |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 84 | stp x0, x1, [sp, #16 * 0] |
| 85 | stp x2, x3, [sp, #16 * 1] |
| 86 | stp x4, x5, [sp, #16 * 2] |
| 87 | stp x6, x7, [sp, #16 * 3] |
| 88 | stp x8, x9, [sp, #16 * 4] |
| 89 | stp x10, x11, [sp, #16 * 5] |
| 90 | stp x12, x13, [sp, #16 * 6] |
| 91 | stp x14, x15, [sp, #16 * 7] |
| 92 | stp x16, x17, [sp, #16 * 8] |
| 93 | stp x18, x19, [sp, #16 * 9] |
| 94 | stp x20, x21, [sp, #16 * 10] |
| 95 | stp x22, x23, [sp, #16 * 11] |
| 96 | stp x24, x25, [sp, #16 * 12] |
| 97 | stp x26, x27, [sp, #16 * 13] |
| 98 | stp x28, x29, [sp, #16 * 14] |
| 99 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 100 | .if \el == 0 |
| 101 | mrs x21, sp_el0 |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 102 | mov tsk, sp |
| 103 | and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 104 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug |
| 105 | disable_step_tsk x19, x20 // exceptions when scheduling. |
James Morse | 49003a8 | 2015-12-10 10:22:41 +0000 | [diff] [blame] | 106 | |
| 107 | mov x29, xzr // fp pointed to user-space |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 108 | .else |
| 109 | add x21, sp, #S_FRAME_SIZE |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 110 | get_thread_info tsk |
| 111 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ |
| 112 | ldr x20, [tsk, #TI_ADDR_LIMIT] |
| 113 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
| 114 | mov x20, #TASK_SIZE_64 |
| 115 | str x20, [tsk, #TI_ADDR_LIMIT] |
Vladimir Murzin | 563cada | 2016-09-01 14:35:59 +0100 | [diff] [blame] | 116 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 117 | .endif /* \el == 0 */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 118 | mrs x22, elr_el1 |
| 119 | mrs x23, spsr_el1 |
| 120 | stp lr, x21, [sp, #S_LR] |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 121 | |
| 122 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 123 | /* |
| 124 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from |
| 125 | * EL0, there is no need to check the state of TTBR0_EL1 since |
| 126 | * accesses are always enabled. |
| 127 | * Note that the meaning of this bit differs from the ARMv8.1 PAN |
| 128 | * feature as all TTBR0_EL1 accesses are disabled, not just those to |
| 129 | * user mappings. |
| 130 | */ |
| 131 | alternative_if ARM64_HAS_PAN |
| 132 | b 1f // skip TTBR0 PAN |
| 133 | alternative_else_nop_endif |
| 134 | |
| 135 | .if \el != 0 |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 136 | mrs x21, ttbr1_el1 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 137 | tst x21, #0xffff << 48 // Check for the reserved ASID |
| 138 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR |
| 139 | b.eq 1f // TTBR0 access already disabled |
| 140 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR |
| 141 | .endif |
| 142 | |
| 143 | __uaccess_ttbr0_disable x21 |
| 144 | 1: |
| 145 | #endif |
| 146 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 147 | stp x22, x23, [sp, #S_PC] |
| 148 | |
| 149 | /* |
| 150 | * Set syscallno to -1 by default (overridden later if real syscall). |
| 151 | */ |
| 152 | .if \el == 0 |
| 153 | mvn x21, xzr |
| 154 | str x21, [sp, #S_SYSCALLNO] |
| 155 | .endif |
| 156 | |
| 157 | /* |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 158 | * Set sp_el0 to current thread_info. |
| 159 | */ |
| 160 | .if \el == 0 |
| 161 | msr sp_el0, tsk |
| 162 | .endif |
| 163 | |
| 164 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 165 | * Registers that may be useful after this macro is invoked: |
| 166 | * |
| 167 | * x21 - aborted SP |
| 168 | * x22 - aborted PC |
| 169 | * x23 - aborted PSTATE |
| 170 | */ |
| 171 | .endm |
| 172 | |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 173 | .macro kernel_exit, el |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 174 | .if \el != 0 |
| 175 | /* Restore the task's original addr_limit. */ |
| 176 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] |
| 177 | str x20, [tsk, #TI_ADDR_LIMIT] |
| 178 | |
| 179 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ |
| 180 | .endif |
| 181 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 182 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
| 183 | .if \el == 0 |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 184 | ct_user_enter |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 185 | .endif |
| 186 | |
| 187 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 188 | /* |
| 189 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR |
| 190 | * PAN bit checking. |
| 191 | */ |
| 192 | alternative_if ARM64_HAS_PAN |
| 193 | b 2f // skip TTBR0 PAN |
| 194 | alternative_else_nop_endif |
| 195 | |
| 196 | .if \el != 0 |
| 197 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set |
| 198 | .endif |
| 199 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 200 | __uaccess_ttbr0_enable x0, x1 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 201 | |
| 202 | .if \el == 0 |
| 203 | /* |
| 204 | * Enable errata workarounds only if returning to user. The only |
| 205 | * workaround currently required for TTBR0_EL1 changes are for the |
| 206 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache |
| 207 | * corruption). |
| 208 | */ |
Will Deacon | 071a49f | 2017-08-10 13:34:30 +0100 | [diff] [blame] | 209 | post_ttbr_update_workaround |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 210 | .endif |
| 211 | 1: |
| 212 | .if \el != 0 |
| 213 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit |
| 214 | .endif |
| 215 | 2: |
| 216 | #endif |
| 217 | |
| 218 | .if \el == 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 219 | ldr x23, [sp, #S_SP] // load return stack pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 220 | msr sp_el0, x23 |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 221 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 222 | alternative_if ARM64_WORKAROUND_845719 |
Daniel Thompson | e28cabf | 2015-07-22 12:21:03 +0100 | [diff] [blame] | 223 | tbz x22, #4, 1f |
| 224 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
| 225 | mrs x29, contextidr_el1 |
| 226 | msr contextidr_el1, x29 |
| 227 | #else |
| 228 | msr contextidr_el1, xzr |
| 229 | #endif |
| 230 | 1: |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 231 | alternative_else_nop_endif |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 232 | #endif |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 233 | .endif |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 234 | |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 235 | msr elr_el1, x21 // set up the return data |
| 236 | msr spsr_el1, x22 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 237 | ldp x0, x1, [sp, #16 * 0] |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 238 | ldp x2, x3, [sp, #16 * 1] |
| 239 | ldp x4, x5, [sp, #16 * 2] |
| 240 | ldp x6, x7, [sp, #16 * 3] |
| 241 | ldp x8, x9, [sp, #16 * 4] |
| 242 | ldp x10, x11, [sp, #16 * 5] |
| 243 | ldp x12, x13, [sp, #16 * 6] |
| 244 | ldp x14, x15, [sp, #16 * 7] |
| 245 | ldp x16, x17, [sp, #16 * 8] |
| 246 | ldp x18, x19, [sp, #16 * 9] |
| 247 | ldp x20, x21, [sp, #16 * 10] |
| 248 | ldp x22, x23, [sp, #16 * 11] |
| 249 | ldp x24, x25, [sp, #16 * 12] |
| 250 | ldp x26, x27, [sp, #16 * 13] |
| 251 | ldp x28, x29, [sp, #16 * 14] |
| 252 | ldr lr, [sp, #S_LR] |
| 253 | add sp, sp, #S_FRAME_SIZE // restore sp |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 254 | eret // return to kernel |
| 255 | .endm |
| 256 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 257 | .macro irq_stack_entry |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 258 | mov x19, sp // preserve the original sp |
| 259 | |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 260 | /* |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 261 | * Compare sp with the current thread_info, if the top |
| 262 | * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and |
| 263 | * should switch to the irq stack. |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 264 | */ |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 265 | and x25, x19, #~(THREAD_SIZE - 1) |
| 266 | cmp x25, tsk |
| 267 | b.ne 9998f |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 268 | |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 269 | this_cpu_ptr irq_stack, x25, x26 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 270 | mov x26, #IRQ_STACK_START_SP |
| 271 | add x26, x25, x26 |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 272 | |
| 273 | /* switch to the irq stack */ |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 274 | mov sp, x26 |
| 275 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 276 | /* |
| 277 | * Add a dummy stack frame, this non-standard format is fixed up |
| 278 | * by unwind_frame() |
| 279 | */ |
| 280 | stp x29, x19, [sp, #-16]! |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 281 | mov x29, sp |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 282 | |
| 283 | 9998: |
| 284 | .endm |
| 285 | |
| 286 | /* |
| 287 | * x19 should be preserved between irq_stack_entry and |
| 288 | * irq_stack_exit. |
| 289 | */ |
| 290 | .macro irq_stack_exit |
| 291 | mov sp, x19 |
| 292 | .endm |
| 293 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 294 | /* |
| 295 | * These are the registers used in the syscall handler, and allow us to |
| 296 | * have in theory up to 7 arguments to a function - x0 to x6. |
| 297 | * |
| 298 | * x7 is reserved for the system call number in 32-bit mode. |
| 299 | */ |
| 300 | sc_nr .req x25 // number of system calls |
| 301 | scno .req x26 // syscall number |
| 302 | stbl .req x27 // syscall table pointer |
| 303 | tsk .req x28 // current thread_info |
| 304 | |
| 305 | /* |
| 306 | * Interrupt handling. |
| 307 | */ |
| 308 | .macro irq_handler |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 309 | ldr_l x1, handle_arch_irq |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 310 | mov x0, sp |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 311 | irq_stack_entry |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 312 | blr x1 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 313 | irq_stack_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 314 | .endm |
| 315 | |
| 316 | .text |
| 317 | |
| 318 | /* |
| 319 | * Exception vectors. |
| 320 | */ |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 321 | .pushsection ".entry.text", "ax" |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 322 | |
| 323 | .align 11 |
| 324 | ENTRY(vectors) |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 325 | kernel_ventry 1, sync_invalid // Synchronous EL1t |
| 326 | kernel_ventry 1, irq_invalid // IRQ EL1t |
| 327 | kernel_ventry 1, fiq_invalid // FIQ EL1t |
| 328 | kernel_ventry 1, error_invalid // Error EL1t |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 329 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 330 | kernel_ventry 1, sync // Synchronous EL1h |
| 331 | kernel_ventry 1, irq // IRQ EL1h |
| 332 | kernel_ventry 1, fiq_invalid // FIQ EL1h |
| 333 | kernel_ventry 1, error_invalid // Error EL1h |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 334 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 335 | kernel_ventry 0, sync // Synchronous 64-bit EL0 |
| 336 | kernel_ventry 0, irq // IRQ 64-bit EL0 |
| 337 | kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 |
| 338 | kernel_ventry 0, error_invalid // Error 64-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 339 | |
| 340 | #ifdef CONFIG_COMPAT |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 341 | kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 |
| 342 | kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 |
| 343 | kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 |
| 344 | kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 345 | #else |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame^] | 346 | kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 |
| 347 | kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 |
| 348 | kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 |
| 349 | kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 350 | #endif |
| 351 | END(vectors) |
| 352 | |
| 353 | /* |
| 354 | * Invalid mode handlers |
| 355 | */ |
| 356 | .macro inv_entry, el, reason, regsize = 64 |
Ard Biesheuvel | b660950 | 2016-03-18 10:58:09 +0100 | [diff] [blame] | 357 | kernel_entry \el, \regsize |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 358 | mov x0, sp |
| 359 | mov x1, #\reason |
| 360 | mrs x2, esr_el1 |
| 361 | b bad_mode |
| 362 | .endm |
| 363 | |
| 364 | el0_sync_invalid: |
| 365 | inv_entry 0, BAD_SYNC |
| 366 | ENDPROC(el0_sync_invalid) |
| 367 | |
| 368 | el0_irq_invalid: |
| 369 | inv_entry 0, BAD_IRQ |
| 370 | ENDPROC(el0_irq_invalid) |
| 371 | |
| 372 | el0_fiq_invalid: |
| 373 | inv_entry 0, BAD_FIQ |
| 374 | ENDPROC(el0_fiq_invalid) |
| 375 | |
| 376 | el0_error_invalid: |
| 377 | inv_entry 0, BAD_ERROR |
| 378 | ENDPROC(el0_error_invalid) |
| 379 | |
| 380 | #ifdef CONFIG_COMPAT |
| 381 | el0_fiq_invalid_compat: |
| 382 | inv_entry 0, BAD_FIQ, 32 |
| 383 | ENDPROC(el0_fiq_invalid_compat) |
| 384 | |
| 385 | el0_error_invalid_compat: |
| 386 | inv_entry 0, BAD_ERROR, 32 |
| 387 | ENDPROC(el0_error_invalid_compat) |
| 388 | #endif |
| 389 | |
| 390 | el1_sync_invalid: |
| 391 | inv_entry 1, BAD_SYNC |
| 392 | ENDPROC(el1_sync_invalid) |
| 393 | |
| 394 | el1_irq_invalid: |
| 395 | inv_entry 1, BAD_IRQ |
| 396 | ENDPROC(el1_irq_invalid) |
| 397 | |
| 398 | el1_fiq_invalid: |
| 399 | inv_entry 1, BAD_FIQ |
| 400 | ENDPROC(el1_fiq_invalid) |
| 401 | |
| 402 | el1_error_invalid: |
| 403 | inv_entry 1, BAD_ERROR |
| 404 | ENDPROC(el1_error_invalid) |
| 405 | |
| 406 | /* |
| 407 | * EL1 mode handlers. |
| 408 | */ |
| 409 | .align 6 |
| 410 | el1_sync: |
| 411 | kernel_entry 1 |
| 412 | mrs x1, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 413 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
| 414 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 415 | b.eq el1_da |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 416 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
| 417 | b.eq el1_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 418 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 419 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 420 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 421 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 422 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 423 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 424 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 425 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 426 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 427 | b.ge el1_dbg |
| 428 | b el1_inv |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 429 | |
| 430 | el1_ia: |
| 431 | /* |
| 432 | * Fall through to the Data abort case |
| 433 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 434 | el1_da: |
| 435 | /* |
| 436 | * Data abort handling |
| 437 | */ |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 438 | mrs x3, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 439 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 440 | // re-enable interrupts if they were enabled in the aborted context |
| 441 | tbnz x23, #7, 1f // PSR_I_BIT |
| 442 | enable_irq |
| 443 | 1: |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 444 | clear_address_tag x0, x3 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 445 | mov x2, sp // struct pt_regs |
| 446 | bl do_mem_abort |
| 447 | |
| 448 | // disable interrupts before pulling preserved data off the stack |
| 449 | disable_irq |
| 450 | kernel_exit 1 |
| 451 | el1_sp_pc: |
| 452 | /* |
| 453 | * Stack or PC alignment exception handling |
| 454 | */ |
| 455 | mrs x0, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 456 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 457 | mov x2, sp |
| 458 | b do_sp_pc_abort |
| 459 | el1_undef: |
| 460 | /* |
| 461 | * Undefined instruction |
| 462 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 463 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 464 | mov x0, sp |
| 465 | b do_undefinstr |
| 466 | el1_dbg: |
| 467 | /* |
| 468 | * Debug exception handling |
| 469 | */ |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 470 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
Sandeepa Prabhu | ee6214c | 2013-12-04 05:50:20 +0000 | [diff] [blame] | 471 | cinc x24, x24, eq // set bit '0' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 472 | tbz x24, #0, el1_inv // EL1 only |
| 473 | mrs x0, far_el1 |
| 474 | mov x2, sp // struct pt_regs |
| 475 | bl do_debug_exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 476 | kernel_exit 1 |
| 477 | el1_inv: |
| 478 | // TODO: add support for undefined instructions in kernel mode |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 479 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 480 | mov x0, sp |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 481 | mov x2, x1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 482 | mov x1, #BAD_SYNC |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 483 | b bad_mode |
| 484 | ENDPROC(el1_sync) |
| 485 | |
| 486 | .align 6 |
| 487 | el1_irq: |
| 488 | kernel_entry 1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 489 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 490 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 491 | bl trace_hardirqs_off |
| 492 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 493 | |
| 494 | irq_handler |
| 495 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 496 | #ifdef CONFIG_PREEMPT |
Neil Zhang | 883c057 | 2014-01-13 08:57:56 +0000 | [diff] [blame] | 497 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
Marc Zyngier | 717321f | 2013-11-04 20:14:58 +0000 | [diff] [blame] | 498 | cbnz w24, 1f // preempt count != 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 499 | ldr x0, [tsk, #TI_FLAGS] // get flags |
| 500 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
| 501 | bl el1_preempt |
| 502 | 1: |
| 503 | #endif |
| 504 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 505 | bl trace_hardirqs_on |
| 506 | #endif |
| 507 | kernel_exit 1 |
| 508 | ENDPROC(el1_irq) |
| 509 | |
| 510 | #ifdef CONFIG_PREEMPT |
| 511 | el1_preempt: |
| 512 | mov x24, lr |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 513 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 514 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
| 515 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
| 516 | ret x24 |
| 517 | #endif |
| 518 | |
| 519 | /* |
| 520 | * EL0 mode handlers. |
| 521 | */ |
| 522 | .align 6 |
| 523 | el0_sync: |
| 524 | kernel_entry 0 |
| 525 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 526 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 527 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 528 | b.eq el0_svc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 529 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 530 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 531 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 532 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 533 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 534 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 535 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 536 | b.eq el0_fpsimd_exc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 537 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 538 | b.eq el0_sys |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 539 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 540 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 541 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 542 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 543 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 544 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 545 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 546 | b.ge el0_dbg |
| 547 | b el0_inv |
| 548 | |
| 549 | #ifdef CONFIG_COMPAT |
| 550 | .align 6 |
| 551 | el0_sync_compat: |
| 552 | kernel_entry 0, 32 |
| 553 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 554 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 555 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 556 | b.eq el0_svc_compat |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 557 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 558 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 559 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 560 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 561 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 562 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 563 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 564 | b.eq el0_fpsimd_exc |
Mark Salyzyn | 77f3228f | 2015-10-13 14:30:51 -0700 | [diff] [blame] | 565 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 566 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 567 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 568 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 569 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 570 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 571 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 572 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 573 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 574 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 575 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 576 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 577 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 578 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 579 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 580 | b.ge el0_dbg |
| 581 | b el0_inv |
| 582 | el0_svc_compat: |
| 583 | /* |
| 584 | * AArch32 syscall handling |
| 585 | */ |
Catalin Marinas | 0156411 | 2015-01-06 16:42:32 +0000 | [diff] [blame] | 586 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 587 | uxtw scno, w7 // syscall number in w7 (r7) |
| 588 | mov sc_nr, #__NR_compat_syscalls |
| 589 | b el0_svc_naked |
| 590 | |
| 591 | .align 6 |
| 592 | el0_irq_compat: |
| 593 | kernel_entry 0, 32 |
| 594 | b el0_irq_naked |
| 595 | #endif |
| 596 | |
| 597 | el0_da: |
| 598 | /* |
| 599 | * Data abort handling |
| 600 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 601 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 602 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 603 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 604 | ct_user_exit |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 605 | clear_address_tag x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 606 | mov x1, x25 |
| 607 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 608 | bl do_mem_abort |
| 609 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 610 | el0_ia: |
| 611 | /* |
| 612 | * Instruction abort handling |
| 613 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 614 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 615 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 616 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 617 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 618 | mov x0, x26 |
Mark Rutland | 541ec87 | 2016-05-31 12:33:03 +0100 | [diff] [blame] | 619 | mov x1, x25 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 620 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 621 | bl do_mem_abort |
| 622 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 623 | el0_fpsimd_acc: |
| 624 | /* |
| 625 | * Floating Point or Advanced SIMD access |
| 626 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 627 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 628 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 629 | mov x0, x25 |
| 630 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 631 | bl do_fpsimd_acc |
| 632 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 633 | el0_fpsimd_exc: |
| 634 | /* |
| 635 | * Floating Point or Advanced SIMD exception |
| 636 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 637 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 638 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 639 | mov x0, x25 |
| 640 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 641 | bl do_fpsimd_exc |
| 642 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 643 | el0_sp_pc: |
| 644 | /* |
| 645 | * Stack or PC alignment exception handling |
| 646 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 647 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 648 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 649 | enable_dbg_and_irq |
Mark Rutland | 46b0567 | 2015-06-15 16:40:27 +0100 | [diff] [blame] | 650 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 651 | mov x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 652 | mov x1, x25 |
| 653 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 654 | bl do_sp_pc_abort |
| 655 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 656 | el0_undef: |
| 657 | /* |
| 658 | * Undefined instruction |
| 659 | */ |
Catalin Marinas | 2600e13 | 2013-08-22 11:47:37 +0100 | [diff] [blame] | 660 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 661 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 662 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 663 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 664 | bl do_undefinstr |
| 665 | b ret_to_user |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 666 | el0_sys: |
| 667 | /* |
| 668 | * System instructions, for trapped cache maintenance instructions |
| 669 | */ |
| 670 | enable_dbg_and_irq |
| 671 | ct_user_exit |
| 672 | mov x0, x25 |
| 673 | mov x1, sp |
| 674 | bl do_sysinstr |
| 675 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 676 | el0_dbg: |
| 677 | /* |
| 678 | * Debug exception handling |
| 679 | */ |
| 680 | tbnz x24, #0, el0_inv // EL0 only |
| 681 | mrs x0, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 682 | mov x1, x25 |
| 683 | mov x2, sp |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 684 | bl do_debug_exception |
| 685 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 686 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 687 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 688 | el0_inv: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 689 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 690 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 691 | mov x0, sp |
| 692 | mov x1, #BAD_SYNC |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 693 | mov x2, x25 |
Mark Rutland | de32794 | 2017-01-18 17:23:41 +0000 | [diff] [blame] | 694 | bl bad_el0_sync |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 695 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 696 | ENDPROC(el0_sync) |
| 697 | |
| 698 | .align 6 |
| 699 | el0_irq: |
| 700 | kernel_entry 0 |
| 701 | el0_irq_naked: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 702 | enable_dbg |
| 703 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 704 | bl trace_hardirqs_off |
| 705 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 706 | |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 707 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 708 | irq_handler |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 709 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 710 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 711 | bl trace_hardirqs_on |
| 712 | #endif |
| 713 | b ret_to_user |
| 714 | ENDPROC(el0_irq) |
| 715 | |
| 716 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 717 | * Register switch for AArch64. The callee-saved registers need to be saved |
| 718 | * and restored. On entry: |
| 719 | * x0 = previous task_struct (must be preserved across the switch) |
| 720 | * x1 = next task_struct |
| 721 | * Previous and next are guaranteed not to be the same. |
| 722 | * |
| 723 | */ |
| 724 | ENTRY(cpu_switch_to) |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 725 | mov x10, #THREAD_CPU_CONTEXT |
| 726 | add x8, x0, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 727 | mov x9, sp |
| 728 | stp x19, x20, [x8], #16 // store callee-saved registers |
| 729 | stp x21, x22, [x8], #16 |
| 730 | stp x23, x24, [x8], #16 |
| 731 | stp x25, x26, [x8], #16 |
| 732 | stp x27, x28, [x8], #16 |
| 733 | stp x29, x9, [x8], #16 |
| 734 | str lr, [x8] |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 735 | add x8, x1, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 736 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
| 737 | ldp x21, x22, [x8], #16 |
| 738 | ldp x23, x24, [x8], #16 |
| 739 | ldp x25, x26, [x8], #16 |
| 740 | ldp x27, x28, [x8], #16 |
| 741 | ldp x29, x9, [x8], #16 |
| 742 | ldr lr, [x8] |
| 743 | mov sp, x9 |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 744 | and x9, x9, #~(THREAD_SIZE - 1) |
| 745 | msr sp_el0, x9 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 746 | ret |
| 747 | ENDPROC(cpu_switch_to) |
| 748 | |
| 749 | /* |
| 750 | * This is the fast syscall return path. We do as little as possible here, |
| 751 | * and this includes saving x0 back into the kernel stack. |
| 752 | */ |
| 753 | ret_fast_syscall: |
| 754 | disable_irq // disable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 755 | str x0, [sp, #S_X0] // returned x0 |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 756 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
| 757 | and x2, x1, #_TIF_SYSCALL_WORK |
| 758 | cbnz x2, ret_fast_syscall_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 759 | and x2, x1, #_TIF_WORK_MASK |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 760 | cbnz x2, work_pending |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 761 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 762 | kernel_exit 0 |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 763 | ret_fast_syscall_trace: |
| 764 | enable_irq // enable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 765 | b __sys_trace_return_skipped // we already saved x0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 766 | |
| 767 | /* |
| 768 | * Ok, we need to do extra processing, enter the slow path. |
| 769 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 770 | work_pending: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 771 | mov x0, sp // 'regs' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 772 | bl do_notify_resume |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 773 | #ifdef CONFIG_TRACE_IRQFLAGS |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 774 | bl trace_hardirqs_on // enabled while in userspace |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 775 | #endif |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 776 | ldr x1, [tsk, #TI_FLAGS] // re-check for single-step |
| 777 | b finish_ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 778 | /* |
| 779 | * "slow" syscall return path. |
| 780 | */ |
Catalin Marinas | 59dc67b | 2012-09-10 16:11:46 +0100 | [diff] [blame] | 781 | ret_to_user: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 782 | disable_irq // disable interrupts |
| 783 | ldr x1, [tsk, #TI_FLAGS] |
| 784 | and x2, x1, #_TIF_WORK_MASK |
| 785 | cbnz x2, work_pending |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 786 | finish_ret_to_user: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 787 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 788 | kernel_exit 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 789 | ENDPROC(ret_to_user) |
| 790 | |
| 791 | /* |
| 792 | * This is how we return from a fork. |
| 793 | */ |
| 794 | ENTRY(ret_from_fork) |
| 795 | bl schedule_tail |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 796 | cbz x19, 1f // not a kernel thread |
| 797 | mov x0, x20 |
| 798 | blr x19 |
| 799 | 1: get_thread_info tsk |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 800 | b ret_to_user |
| 801 | ENDPROC(ret_from_fork) |
| 802 | |
| 803 | /* |
| 804 | * SVC handler. |
| 805 | */ |
| 806 | .align 6 |
| 807 | el0_svc: |
| 808 | adrp stbl, sys_call_table // load syscall table pointer |
| 809 | uxtw scno, w8 // syscall number in w8 |
| 810 | mov sc_nr, #__NR_syscalls |
| 811 | el0_svc_naked: // compat entry point |
| 812 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 813 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 814 | ct_user_exit 1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 815 | |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 816 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
| 817 | tst x16, #_TIF_SYSCALL_WORK |
| 818 | b.ne __sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 819 | cmp scno, sc_nr // check upper syscall limit |
| 820 | b.hs ni_sys |
| 821 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 822 | blr x16 // call sys_* routine |
| 823 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 824 | ni_sys: |
| 825 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 826 | bl do_ni_syscall |
| 827 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 828 | ENDPROC(el0_svc) |
| 829 | |
| 830 | /* |
| 831 | * This is the really slow path. We're going to be doing context |
| 832 | * switches, and waiting for our parent to respond. |
| 833 | */ |
| 834 | __sys_trace: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 835 | mov w0, #-1 // set default errno for |
| 836 | cmp scno, x0 // user-issued syscall(-1) |
| 837 | b.ne 1f |
| 838 | mov x0, #-ENOSYS |
| 839 | str x0, [sp, #S_X0] |
| 840 | 1: mov x0, sp |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 841 | bl syscall_trace_enter |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 842 | cmp w0, #-1 // skip the syscall? |
| 843 | b.eq __sys_trace_return_skipped |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 844 | uxtw scno, w0 // syscall number (possibly new) |
| 845 | mov x1, sp // pointer to regs |
| 846 | cmp scno, sc_nr // check upper syscall limit |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 847 | b.hs __ni_sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 848 | ldp x0, x1, [sp] // restore the syscall args |
| 849 | ldp x2, x3, [sp, #S_X2] |
| 850 | ldp x4, x5, [sp, #S_X4] |
| 851 | ldp x6, x7, [sp, #S_X6] |
| 852 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 853 | blr x16 // call sys_* routine |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 854 | |
| 855 | __sys_trace_return: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 856 | str x0, [sp, #S_X0] // save returned x0 |
| 857 | __sys_trace_return_skipped: |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 858 | mov x0, sp |
| 859 | bl syscall_trace_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 860 | b ret_to_user |
| 861 | |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 862 | __ni_sys_trace: |
| 863 | mov x0, sp |
| 864 | bl do_ni_syscall |
| 865 | b __sys_trace_return |
| 866 | |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 867 | .popsection // .entry.text |
| 868 | |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 869 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 870 | /* |
| 871 | * Exception vectors trampoline. |
| 872 | */ |
| 873 | .pushsection ".entry.tramp.text", "ax" |
| 874 | |
| 875 | .macro tramp_map_kernel, tmp |
| 876 | mrs \tmp, ttbr1_el1 |
| 877 | sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
| 878 | bic \tmp, \tmp, #USER_ASID_FLAG |
| 879 | msr ttbr1_el1, \tmp |
| 880 | .endm |
| 881 | |
| 882 | .macro tramp_unmap_kernel, tmp |
| 883 | mrs \tmp, ttbr1_el1 |
| 884 | add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
| 885 | orr \tmp, \tmp, #USER_ASID_FLAG |
| 886 | msr ttbr1_el1, \tmp |
| 887 | /* |
| 888 | * We avoid running the post_ttbr_update_workaround here because the |
| 889 | * user and kernel ASIDs don't have conflicting mappings, so any |
| 890 | * "blessing" as described in: |
| 891 | * |
| 892 | * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com |
| 893 | * |
| 894 | * will not hurt correctness. Whilst this may partially defeat the |
| 895 | * point of using split ASIDs in the first place, it avoids |
| 896 | * the hit of invalidating the entire I-cache on every return to |
| 897 | * userspace. |
| 898 | */ |
| 899 | .endm |
| 900 | |
| 901 | .macro tramp_ventry, regsize = 64 |
| 902 | .align 7 |
| 903 | 1: |
| 904 | .if \regsize == 64 |
| 905 | msr tpidrro_el0, x30 // Restored in kernel_ventry |
| 906 | .endif |
| 907 | tramp_map_kernel x30 |
| 908 | ldr x30, =vectors |
| 909 | prfm plil1strm, [x30, #(1b - tramp_vectors)] |
| 910 | msr vbar_el1, x30 |
| 911 | add x30, x30, #(1b - tramp_vectors) |
| 912 | isb |
| 913 | br x30 |
| 914 | .endm |
| 915 | |
| 916 | .macro tramp_exit, regsize = 64 |
| 917 | adr x30, tramp_vectors |
| 918 | msr vbar_el1, x30 |
| 919 | tramp_unmap_kernel x30 |
| 920 | .if \regsize == 64 |
| 921 | mrs x30, far_el1 |
| 922 | .endif |
| 923 | eret |
| 924 | .endm |
| 925 | |
| 926 | .align 11 |
| 927 | ENTRY(tramp_vectors) |
| 928 | .space 0x400 |
| 929 | |
| 930 | tramp_ventry |
| 931 | tramp_ventry |
| 932 | tramp_ventry |
| 933 | tramp_ventry |
| 934 | |
| 935 | tramp_ventry 32 |
| 936 | tramp_ventry 32 |
| 937 | tramp_ventry 32 |
| 938 | tramp_ventry 32 |
| 939 | END(tramp_vectors) |
| 940 | |
| 941 | ENTRY(tramp_exit_native) |
| 942 | tramp_exit |
| 943 | END(tramp_exit_native) |
| 944 | |
| 945 | ENTRY(tramp_exit_compat) |
| 946 | tramp_exit 32 |
| 947 | END(tramp_exit_compat) |
| 948 | |
| 949 | .ltorg |
| 950 | .popsection // .entry.tramp.text |
| 951 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
| 952 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 953 | /* |
| 954 | * Special system call wrappers. |
| 955 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 956 | ENTRY(sys_rt_sigreturn_wrapper) |
| 957 | mov x0, sp |
| 958 | b sys_rt_sigreturn |
| 959 | ENDPROC(sys_rt_sigreturn_wrapper) |