Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 30 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 32 | #include <linux/export.h> |
Daniel Vetter | 4518f61 | 2013-01-23 16:16:35 +0100 | [diff] [blame] | 33 | #include <generated/utsrelease.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 36 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 38 | #include "i915_drv.h" |
| 39 | |
| 40 | #define DRM_I915_RING_DEBUG 1 |
| 41 | |
| 42 | |
| 43 | #if defined(CONFIG_DEBUG_FS) |
| 44 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 46 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 48 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 49 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 50 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 51 | static const char *yesno(int v) |
| 52 | { |
| 53 | return v ? "yes" : "no"; |
| 54 | } |
| 55 | |
| 56 | static int i915_capabilities(struct seq_file *m, void *data) |
| 57 | { |
| 58 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 59 | struct drm_device *dev = node->minor->dev; |
| 60 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 61 | |
| 62 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 63 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 64 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 65 | #define SEP_SEMICOLON ; |
| 66 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 67 | #undef PRINT_FLAG |
| 68 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 69 | |
| 70 | return 0; |
| 71 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 72 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 73 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 74 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 75 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 76 | return "P"; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 77 | else if (obj->pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 78 | return "p"; |
| 79 | else |
| 80 | return " "; |
| 81 | } |
| 82 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 83 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 84 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 85 | switch (obj->tiling_mode) { |
| 86 | default: |
| 87 | case I915_TILING_NONE: return " "; |
| 88 | case I915_TILING_X: return "X"; |
| 89 | case I915_TILING_Y: return "Y"; |
| 90 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 91 | } |
| 92 | |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 93 | static const char *cache_level_str(int type) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 94 | { |
| 95 | switch (type) { |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 96 | case I915_CACHE_NONE: return " uncached"; |
| 97 | case I915_CACHE_LLC: return " snooped (LLC)"; |
| 98 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 99 | default: return ""; |
| 100 | } |
| 101 | } |
| 102 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 103 | static void |
| 104 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 105 | { |
Kees Cook | 2563a45 | 2013-03-11 12:25:19 -0700 | [diff] [blame] | 106 | seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 107 | &obj->base, |
| 108 | get_pin_flag(obj), |
| 109 | get_tiling_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 110 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 111 | obj->base.read_domains, |
| 112 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 113 | obj->last_read_seqno, |
| 114 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 115 | obj->last_fenced_seqno, |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 116 | cache_level_str(obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 117 | obj->dirty ? " dirty" : "", |
| 118 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 119 | if (obj->base.name) |
| 120 | seq_printf(m, " (name: %d)", obj->base.name); |
Chris Wilson | c110a6d | 2012-08-11 15:41:02 +0100 | [diff] [blame] | 121 | if (obj->pin_count) |
| 122 | seq_printf(m, " (pinned x %d)", obj->pin_count); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 124 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
| 125 | if (obj->gtt_space != NULL) |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 126 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
| 127 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 128 | if (obj->stolen) |
| 129 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 130 | if (obj->pin_mappable || obj->fault_mappable) { |
| 131 | char s[3], *t = s; |
| 132 | if (obj->pin_mappable) |
| 133 | *t++ = 'p'; |
| 134 | if (obj->fault_mappable) |
| 135 | *t++ = 'f'; |
| 136 | *t = '\0'; |
| 137 | seq_printf(m, " (%s mappable)", s); |
| 138 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 139 | if (obj->ring != NULL) |
| 140 | seq_printf(m, " (%s)", obj->ring->name); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 141 | } |
| 142 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 143 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 144 | { |
| 145 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 146 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 147 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 148 | struct drm_device *dev = node->minor->dev; |
| 149 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 150 | struct drm_i915_gem_object *obj; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 151 | size_t total_obj_size, total_gtt_size; |
| 152 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 153 | |
| 154 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 155 | if (ret) |
| 156 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 157 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 158 | switch (list) { |
| 159 | case ACTIVE_LIST: |
| 160 | seq_printf(m, "Active:\n"); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 161 | head = &dev_priv->mm.active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 162 | break; |
| 163 | case INACTIVE_LIST: |
Ben Gamari | a17458f | 2009-07-01 15:01:36 -0400 | [diff] [blame] | 164 | seq_printf(m, "Inactive:\n"); |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 165 | head = &dev_priv->mm.inactive_list; |
| 166 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 167 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 168 | mutex_unlock(&dev->struct_mutex); |
| 169 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 170 | } |
| 171 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 172 | total_obj_size = total_gtt_size = count = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 173 | list_for_each_entry(obj, head, mm_list) { |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 174 | seq_printf(m, " "); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 175 | describe_obj(m, obj); |
Eric Anholt | f4ceda8 | 2009-02-17 23:53:41 -0800 | [diff] [blame] | 176 | seq_printf(m, "\n"); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 177 | total_obj_size += obj->base.size; |
| 178 | total_gtt_size += obj->gtt_space->size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 179 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 180 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 181 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 182 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 183 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 184 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 185 | return 0; |
| 186 | } |
| 187 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 188 | #define count_objects(list, member) do { \ |
| 189 | list_for_each_entry(obj, list, member) { \ |
| 190 | size += obj->gtt_space->size; \ |
| 191 | ++count; \ |
| 192 | if (obj->map_and_fenceable) { \ |
| 193 | mappable_size += obj->gtt_space->size; \ |
| 194 | ++mappable_count; \ |
| 195 | } \ |
| 196 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 197 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 198 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 199 | static int i915_gem_object_info(struct seq_file *m, void* data) |
| 200 | { |
| 201 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 202 | struct drm_device *dev = node->minor->dev; |
| 203 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 204 | u32 count, mappable_count, purgeable_count; |
| 205 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 206 | struct drm_i915_gem_object *obj; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 207 | int ret; |
| 208 | |
| 209 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 210 | if (ret) |
| 211 | return ret; |
| 212 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 213 | seq_printf(m, "%u objects, %zu bytes\n", |
| 214 | dev_priv->mm.object_count, |
| 215 | dev_priv->mm.object_memory); |
| 216 | |
| 217 | size = count = mappable_size = mappable_count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 218 | count_objects(&dev_priv->mm.bound_list, gtt_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 219 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 220 | count, mappable_count, size, mappable_size); |
| 221 | |
| 222 | size = count = mappable_size = mappable_count = 0; |
| 223 | count_objects(&dev_priv->mm.active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 224 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 225 | count, mappable_count, size, mappable_size); |
| 226 | |
| 227 | size = count = mappable_size = mappable_count = 0; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 228 | count_objects(&dev_priv->mm.inactive_list, mm_list); |
| 229 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 230 | count, mappable_count, size, mappable_size); |
| 231 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 232 | size = count = purgeable_size = purgeable_count = 0; |
| 233 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 234 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 235 | if (obj->madv == I915_MADV_DONTNEED) |
| 236 | purgeable_size += obj->base.size, ++purgeable_count; |
| 237 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 238 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 239 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 240 | size = count = mappable_size = mappable_count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 241 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 242 | if (obj->fault_mappable) { |
| 243 | size += obj->gtt_space->size; |
| 244 | ++count; |
| 245 | } |
| 246 | if (obj->pin_mappable) { |
| 247 | mappable_size += obj->gtt_space->size; |
| 248 | ++mappable_count; |
| 249 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 250 | if (obj->madv == I915_MADV_DONTNEED) { |
| 251 | purgeable_size += obj->base.size; |
| 252 | ++purgeable_count; |
| 253 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 254 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 255 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 256 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 257 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 258 | mappable_count, mappable_size); |
| 259 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 260 | count, size); |
| 261 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 262 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 263 | dev_priv->gtt.total, |
| 264 | dev_priv->gtt.mappable_end - dev_priv->gtt.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 265 | |
| 266 | mutex_unlock(&dev->struct_mutex); |
| 267 | |
| 268 | return 0; |
| 269 | } |
| 270 | |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 271 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
| 272 | { |
| 273 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 274 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 275 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 276 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 277 | struct drm_i915_gem_object *obj; |
| 278 | size_t total_obj_size, total_gtt_size; |
| 279 | int count, ret; |
| 280 | |
| 281 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 282 | if (ret) |
| 283 | return ret; |
| 284 | |
| 285 | total_obj_size = total_gtt_size = count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 286 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 287 | if (list == PINNED_LIST && obj->pin_count == 0) |
| 288 | continue; |
| 289 | |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 290 | seq_printf(m, " "); |
| 291 | describe_obj(m, obj); |
| 292 | seq_printf(m, "\n"); |
| 293 | total_obj_size += obj->base.size; |
| 294 | total_gtt_size += obj->gtt_space->size; |
| 295 | count++; |
| 296 | } |
| 297 | |
| 298 | mutex_unlock(&dev->struct_mutex); |
| 299 | |
| 300 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 301 | count, total_obj_size, total_gtt_size); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 306 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 307 | { |
| 308 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 309 | struct drm_device *dev = node->minor->dev; |
| 310 | unsigned long flags; |
| 311 | struct intel_crtc *crtc; |
| 312 | |
| 313 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 314 | const char pipe = pipe_name(crtc->pipe); |
| 315 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 316 | struct intel_unpin_work *work; |
| 317 | |
| 318 | spin_lock_irqsave(&dev->event_lock, flags); |
| 319 | work = crtc->unpin_work; |
| 320 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 321 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 322 | pipe, plane); |
| 323 | } else { |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 324 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 325 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 326 | pipe, plane); |
| 327 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 328 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 329 | pipe, plane); |
| 330 | } |
| 331 | if (work->enable_stall_check) |
| 332 | seq_printf(m, "Stall check enabled, "); |
| 333 | else |
| 334 | seq_printf(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 335 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 336 | |
| 337 | if (work->old_fb_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 338 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
| 339 | if (obj) |
| 340 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 341 | } |
| 342 | if (work->pending_flip_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 343 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
| 344 | if (obj) |
| 345 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 349 | } |
| 350 | |
| 351 | return 0; |
| 352 | } |
| 353 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 354 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 355 | { |
| 356 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 357 | struct drm_device *dev = node->minor->dev; |
| 358 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 359 | struct intel_ring_buffer *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 360 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 361 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 362 | |
| 363 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 364 | if (ret) |
| 365 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 366 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 367 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 368 | for_each_ring(ring, dev_priv, i) { |
| 369 | if (list_empty(&ring->request_list)) |
| 370 | continue; |
| 371 | |
| 372 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 373 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 374 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 375 | list) { |
| 376 | seq_printf(m, " %d @ %d\n", |
| 377 | gem_request->seqno, |
| 378 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 379 | } |
| 380 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 381 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 382 | mutex_unlock(&dev->struct_mutex); |
| 383 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 384 | if (count == 0) |
| 385 | seq_printf(m, "No requests\n"); |
| 386 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 387 | return 0; |
| 388 | } |
| 389 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 390 | static void i915_ring_seqno_info(struct seq_file *m, |
| 391 | struct intel_ring_buffer *ring) |
| 392 | { |
| 393 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 394 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 395 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 396 | } |
| 397 | } |
| 398 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 399 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 400 | { |
| 401 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 402 | struct drm_device *dev = node->minor->dev; |
| 403 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 404 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 405 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 406 | |
| 407 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 408 | if (ret) |
| 409 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 410 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 411 | for_each_ring(ring, dev_priv, i) |
| 412 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 413 | |
| 414 | mutex_unlock(&dev->struct_mutex); |
| 415 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | |
| 420 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 421 | { |
| 422 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 423 | struct drm_device *dev = node->minor->dev; |
| 424 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 425 | struct intel_ring_buffer *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 426 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 427 | |
| 428 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 429 | if (ret) |
| 430 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 431 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 432 | if (IS_VALLEYVIEW(dev)) { |
| 433 | seq_printf(m, "Display IER:\t%08x\n", |
| 434 | I915_READ(VLV_IER)); |
| 435 | seq_printf(m, "Display IIR:\t%08x\n", |
| 436 | I915_READ(VLV_IIR)); |
| 437 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 438 | I915_READ(VLV_IIR_RW)); |
| 439 | seq_printf(m, "Display IMR:\t%08x\n", |
| 440 | I915_READ(VLV_IMR)); |
| 441 | for_each_pipe(pipe) |
| 442 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 443 | pipe_name(pipe), |
| 444 | I915_READ(PIPESTAT(pipe))); |
| 445 | |
| 446 | seq_printf(m, "Master IER:\t%08x\n", |
| 447 | I915_READ(VLV_MASTER_IER)); |
| 448 | |
| 449 | seq_printf(m, "Render IER:\t%08x\n", |
| 450 | I915_READ(GTIER)); |
| 451 | seq_printf(m, "Render IIR:\t%08x\n", |
| 452 | I915_READ(GTIIR)); |
| 453 | seq_printf(m, "Render IMR:\t%08x\n", |
| 454 | I915_READ(GTIMR)); |
| 455 | |
| 456 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 457 | I915_READ(GEN6_PMIER)); |
| 458 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 459 | I915_READ(GEN6_PMIIR)); |
| 460 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 461 | I915_READ(GEN6_PMIMR)); |
| 462 | |
| 463 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 464 | I915_READ(PORT_HOTPLUG_EN)); |
| 465 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 466 | I915_READ(VLV_DPFLIPSTAT)); |
| 467 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 468 | I915_READ(DPINVGTT)); |
| 469 | |
| 470 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 471 | seq_printf(m, "Interrupt enable: %08x\n", |
| 472 | I915_READ(IER)); |
| 473 | seq_printf(m, "Interrupt identity: %08x\n", |
| 474 | I915_READ(IIR)); |
| 475 | seq_printf(m, "Interrupt mask: %08x\n", |
| 476 | I915_READ(IMR)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 477 | for_each_pipe(pipe) |
| 478 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 479 | pipe_name(pipe), |
| 480 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 481 | } else { |
| 482 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 483 | I915_READ(DEIER)); |
| 484 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 485 | I915_READ(DEIIR)); |
| 486 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 487 | I915_READ(DEIMR)); |
| 488 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 489 | I915_READ(SDEIER)); |
| 490 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 491 | I915_READ(SDEIIR)); |
| 492 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 493 | I915_READ(SDEIMR)); |
| 494 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 495 | I915_READ(GTIER)); |
| 496 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 497 | I915_READ(GTIIR)); |
| 498 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 499 | I915_READ(GTIMR)); |
| 500 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 501 | seq_printf(m, "Interrupts received: %d\n", |
| 502 | atomic_read(&dev_priv->irq_received)); |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 503 | for_each_ring(ring, dev_priv, i) { |
Jesse Barnes | da64c6f | 2011-08-09 09:17:46 -0700 | [diff] [blame] | 504 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 505 | seq_printf(m, |
| 506 | "Graphics Interrupt mask (%s): %08x\n", |
| 507 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 508 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 509 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 510 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 511 | mutex_unlock(&dev->struct_mutex); |
| 512 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 513 | return 0; |
| 514 | } |
| 515 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 516 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 517 | { |
| 518 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 519 | struct drm_device *dev = node->minor->dev; |
| 520 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 521 | int i, ret; |
| 522 | |
| 523 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 524 | if (ret) |
| 525 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 526 | |
| 527 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 528 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 529 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 530 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 531 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 532 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 533 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 534 | if (obj == NULL) |
| 535 | seq_printf(m, "unused"); |
| 536 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 537 | describe_obj(m, obj); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 538 | seq_printf(m, "\n"); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 539 | } |
| 540 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 541 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 542 | return 0; |
| 543 | } |
| 544 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 545 | static int i915_hws_info(struct seq_file *m, void *data) |
| 546 | { |
| 547 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 548 | struct drm_device *dev = node->minor->dev; |
| 549 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 550 | struct intel_ring_buffer *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 551 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 552 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 553 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 554 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 555 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 556 | if (hws == NULL) |
| 557 | return 0; |
| 558 | |
| 559 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 560 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 561 | i * 4, |
| 562 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 563 | } |
| 564 | return 0; |
| 565 | } |
| 566 | |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 567 | static const char *ring_str(int ring) |
| 568 | { |
| 569 | switch (ring) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 570 | case RCS: return "render"; |
| 571 | case VCS: return "bsd"; |
| 572 | case BCS: return "blt"; |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame^] | 573 | case VECS: return "vebox"; |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 574 | default: return ""; |
| 575 | } |
| 576 | } |
| 577 | |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 578 | static const char *pin_flag(int pinned) |
| 579 | { |
| 580 | if (pinned > 0) |
| 581 | return " P"; |
| 582 | else if (pinned < 0) |
| 583 | return " p"; |
| 584 | else |
| 585 | return ""; |
| 586 | } |
| 587 | |
| 588 | static const char *tiling_flag(int tiling) |
| 589 | { |
| 590 | switch (tiling) { |
| 591 | default: |
| 592 | case I915_TILING_NONE: return ""; |
| 593 | case I915_TILING_X: return " X"; |
| 594 | case I915_TILING_Y: return " Y"; |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | static const char *dirty_flag(int dirty) |
| 599 | { |
| 600 | return dirty ? " dirty" : ""; |
| 601 | } |
| 602 | |
| 603 | static const char *purgeable_flag(int purgeable) |
| 604 | { |
| 605 | return purgeable ? " purgeable" : ""; |
| 606 | } |
| 607 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 608 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, |
| 609 | const char *f, va_list args) |
| 610 | { |
| 611 | unsigned len; |
| 612 | |
| 613 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { |
| 614 | e->err = -ENOSPC; |
| 615 | return; |
| 616 | } |
| 617 | |
| 618 | if (e->bytes == e->size - 1 || e->err) |
| 619 | return; |
| 620 | |
| 621 | /* Seek the first printf which is hits start position */ |
| 622 | if (e->pos < e->start) { |
| 623 | len = vsnprintf(NULL, 0, f, args); |
| 624 | if (e->pos + len <= e->start) { |
| 625 | e->pos += len; |
| 626 | return; |
| 627 | } |
| 628 | |
| 629 | /* First vsnprintf needs to fit in full for memmove*/ |
| 630 | if (len >= e->size) { |
| 631 | e->err = -EIO; |
| 632 | return; |
| 633 | } |
| 634 | } |
| 635 | |
| 636 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); |
| 637 | if (len >= e->size - e->bytes) |
| 638 | len = e->size - e->bytes - 1; |
| 639 | |
| 640 | /* If this is first printf in this window, adjust it so that |
| 641 | * start position matches start of the buffer |
| 642 | */ |
| 643 | if (e->pos < e->start) { |
| 644 | const size_t off = e->start - e->pos; |
| 645 | |
| 646 | /* Should not happen but be paranoid */ |
| 647 | if (off > len || e->bytes) { |
| 648 | e->err = -EIO; |
| 649 | return; |
| 650 | } |
| 651 | |
| 652 | memmove(e->buf, e->buf + off, len - off); |
| 653 | e->bytes = len - off; |
| 654 | e->pos = e->start; |
| 655 | return; |
| 656 | } |
| 657 | |
| 658 | e->bytes += len; |
| 659 | e->pos += len; |
| 660 | } |
| 661 | |
| 662 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) |
| 663 | { |
| 664 | va_list args; |
| 665 | |
| 666 | va_start(args, f); |
| 667 | i915_error_vprintf(e, f, args); |
| 668 | va_end(args); |
| 669 | } |
| 670 | |
| 671 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 672 | |
| 673 | static void print_error_buffers(struct drm_i915_error_state_buf *m, |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 674 | const char *name, |
| 675 | struct drm_i915_error_buffer *err, |
| 676 | int count) |
| 677 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 678 | err_printf(m, "%s [%d]:\n", name, count); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 679 | |
| 680 | while (count--) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 681 | err_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s", |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 682 | err->gtt_offset, |
| 683 | err->size, |
| 684 | err->read_domains, |
| 685 | err->write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 686 | err->rseqno, err->wseqno, |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 687 | pin_flag(err->pinned), |
| 688 | tiling_flag(err->tiling), |
| 689 | dirty_flag(err->dirty), |
| 690 | purgeable_flag(err->purgeable), |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 691 | err->ring != -1 ? " " : "", |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 692 | ring_str(err->ring), |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 693 | cache_level_str(err->cache_level)); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 694 | |
| 695 | if (err->name) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 696 | err_printf(m, " (name: %d)", err->name); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 697 | if (err->fence_reg != I915_FENCE_REG_NONE) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 698 | err_printf(m, " (fence: %d)", err->fence_reg); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 699 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 700 | err_printf(m, "\n"); |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 701 | err++; |
| 702 | } |
| 703 | } |
| 704 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 705 | static void i915_ring_error_state(struct drm_i915_error_state_buf *m, |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 706 | struct drm_device *dev, |
| 707 | struct drm_i915_error_state *error, |
| 708 | unsigned ring) |
| 709 | { |
Ben Widawsky | ec34a01 | 2012-04-03 23:03:00 -0700 | [diff] [blame] | 710 | BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 711 | err_printf(m, "%s command stream:\n", ring_str(ring)); |
| 712 | err_printf(m, " HEAD: 0x%08x\n", error->head[ring]); |
| 713 | err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); |
| 714 | err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); |
| 715 | err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); |
| 716 | err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); |
| 717 | err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); |
| 718 | err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 719 | if (ring == RCS && INTEL_INFO(dev)->gen >= 4) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 720 | err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 721 | |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 722 | if (INTEL_INFO(dev)->gen >= 4) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 723 | err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); |
| 724 | err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); |
| 725 | err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 726 | if (INTEL_INFO(dev)->gen >= 6) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 727 | err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); |
| 728 | err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); |
| 729 | err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
Chris Wilson | df2b23d | 2012-11-27 17:06:54 +0000 | [diff] [blame] | 730 | error->semaphore_mboxes[ring][0], |
| 731 | error->semaphore_seqno[ring][0]); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 732 | err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", |
Chris Wilson | df2b23d | 2012-11-27 17:06:54 +0000 | [diff] [blame] | 733 | error->semaphore_mboxes[ring][1], |
| 734 | error->semaphore_seqno[ring][1]); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 735 | } |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 736 | err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); |
| 737 | err_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); |
| 738 | err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); |
| 739 | err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 740 | } |
| 741 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 742 | struct i915_error_state_file_priv { |
| 743 | struct drm_device *dev; |
| 744 | struct drm_i915_error_state *error; |
| 745 | }; |
| 746 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 747 | |
| 748 | static int i915_error_state(struct i915_error_state_file_priv *error_priv, |
| 749 | struct drm_i915_error_state_buf *m) |
| 750 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 751 | { |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 752 | struct drm_device *dev = error_priv->dev; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 753 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 754 | struct drm_i915_error_state *error = error_priv->error; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 755 | struct intel_ring_buffer *ring; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 756 | int i, j, page, offset, elt; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 757 | |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 758 | if (!error) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 759 | err_printf(m, "no error state collected\n"); |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 760 | return 0; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 761 | } |
| 762 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 763 | err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 764 | error->time.tv_usec); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 765 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); |
| 766 | err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
| 767 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
| 768 | err_printf(m, "IER: 0x%08x\n", error->ier); |
| 769 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
| 770 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); |
| 771 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); |
| 772 | err_printf(m, "CCID: 0x%08x\n", error->ccid); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 773 | |
Daniel Vetter | bf3301a | 2011-05-12 22:17:12 +0100 | [diff] [blame] | 774 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 775 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
Chris Wilson | 748ebc6 | 2010-10-24 10:28:47 +0100 | [diff] [blame] | 776 | |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 777 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 778 | err_printf(m, " INSTDONE_%d: 0x%08x\n", i, |
| 779 | error->extra_instdone[i]); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 780 | |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 781 | if (INTEL_INFO(dev)->gen >= 6) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 782 | err_printf(m, "ERROR: 0x%08x\n", error->error); |
| 783 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 784 | } |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 785 | |
Ben Widawsky | 71e172e | 2012-08-20 16:15:13 -0700 | [diff] [blame] | 786 | if (INTEL_INFO(dev)->gen == 7) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 787 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); |
Ben Widawsky | 71e172e | 2012-08-20 16:15:13 -0700 | [diff] [blame] | 788 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 789 | for_each_ring(ring, dev_priv, i) |
| 790 | i915_ring_error_state(m, dev, error, i); |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 791 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 792 | if (error->active_bo) |
| 793 | print_error_buffers(m, "Active", |
| 794 | error->active_bo, |
| 795 | error->active_bo_count); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 796 | |
Chris Wilson | c724e8a | 2010-11-22 08:07:02 +0000 | [diff] [blame] | 797 | if (error->pinned_bo) |
| 798 | print_error_buffers(m, "Pinned", |
| 799 | error->pinned_bo, |
| 800 | error->pinned_bo_count); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 801 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 802 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
| 803 | struct drm_i915_error_object *obj; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 804 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 805 | if ((obj = error->ring[i].batchbuffer)) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 806 | err_printf(m, "%s --- gtt_offset = 0x%08x\n", |
Chris Wilson | bcfb2e2 | 2011-01-07 21:06:07 +0000 | [diff] [blame] | 807 | dev_priv->ring[i].name, |
| 808 | obj->gtt_offset); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 809 | offset = 0; |
| 810 | for (page = 0; page < obj->page_count; page++) { |
| 811 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 812 | err_printf(m, "%08x : %08x\n", offset, |
| 813 | obj->pages[page][elt]); |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 814 | offset += 4; |
| 815 | } |
| 816 | } |
| 817 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 818 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 819 | if (error->ring[i].num_requests) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 820 | err_printf(m, "%s --- %d requests\n", |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 821 | dev_priv->ring[i].name, |
| 822 | error->ring[i].num_requests); |
| 823 | for (j = 0; j < error->ring[i].num_requests; j++) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 824 | err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 825 | error->ring[i].requests[j].seqno, |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 826 | error->ring[i].requests[j].jiffies, |
| 827 | error->ring[i].requests[j].tail); |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 828 | } |
| 829 | } |
| 830 | |
| 831 | if ((obj = error->ring[i].ringbuffer)) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 832 | err_printf(m, "%s --- ringbuffer = 0x%08x\n", |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 833 | dev_priv->ring[i].name, |
| 834 | obj->gtt_offset); |
| 835 | offset = 0; |
| 836 | for (page = 0; page < obj->page_count; page++) { |
| 837 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 838 | err_printf(m, "%08x : %08x\n", |
Chris Wilson | e2f973d | 2011-01-27 19:15:11 +0000 | [diff] [blame] | 839 | offset, |
| 840 | obj->pages[page][elt]); |
| 841 | offset += 4; |
| 842 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 843 | } |
| 844 | } |
Ben Widawsky | 8c123e5 | 2013-03-04 17:00:29 -0800 | [diff] [blame] | 845 | |
| 846 | obj = error->ring[i].ctx; |
| 847 | if (obj) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 848 | err_printf(m, "%s --- HW Context = 0x%08x\n", |
Ben Widawsky | 8c123e5 | 2013-03-04 17:00:29 -0800 | [diff] [blame] | 849 | dev_priv->ring[i].name, |
| 850 | obj->gtt_offset); |
| 851 | offset = 0; |
| 852 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 853 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", |
Ben Widawsky | 8c123e5 | 2013-03-04 17:00:29 -0800 | [diff] [blame] | 854 | offset, |
| 855 | obj->pages[0][elt], |
| 856 | obj->pages[0][elt+1], |
| 857 | obj->pages[0][elt+2], |
| 858 | obj->pages[0][elt+3]); |
| 859 | offset += 16; |
| 860 | } |
| 861 | } |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 862 | } |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 863 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 864 | if (error->overlay) |
| 865 | intel_overlay_print_error_state(m, error->overlay); |
| 866 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 867 | if (error->display) |
| 868 | intel_display_print_error_state(m, dev, error->display); |
| 869 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 870 | return 0; |
| 871 | } |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 872 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 873 | static ssize_t |
| 874 | i915_error_state_write(struct file *filp, |
| 875 | const char __user *ubuf, |
| 876 | size_t cnt, |
| 877 | loff_t *ppos) |
| 878 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 879 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 880 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 881 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 882 | |
| 883 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 884 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 885 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 886 | if (ret) |
| 887 | return ret; |
| 888 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 889 | i915_destroy_error_state(dev); |
| 890 | mutex_unlock(&dev->struct_mutex); |
| 891 | |
| 892 | return cnt; |
| 893 | } |
| 894 | |
| 895 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 896 | { |
| 897 | struct drm_device *dev = inode->i_private; |
| 898 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 899 | struct i915_error_state_file_priv *error_priv; |
| 900 | unsigned long flags; |
| 901 | |
| 902 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 903 | if (!error_priv) |
| 904 | return -ENOMEM; |
| 905 | |
| 906 | error_priv->dev = dev; |
| 907 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 908 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
| 909 | error_priv->error = dev_priv->gpu_error.first_error; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 910 | if (error_priv->error) |
| 911 | kref_get(&error_priv->error->ref); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 912 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 913 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 914 | file->private_data = error_priv; |
| 915 | |
| 916 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 920 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 921 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 922 | |
| 923 | if (error_priv->error) |
| 924 | kref_put(&error_priv->error->ref, i915_error_state_free); |
| 925 | kfree(error_priv); |
| 926 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 927 | return 0; |
| 928 | } |
| 929 | |
| 930 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 931 | size_t count, loff_t *pos) |
| 932 | { |
| 933 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 934 | struct drm_i915_error_state_buf error_str; |
| 935 | loff_t tmp_pos = 0; |
| 936 | ssize_t ret_count = 0; |
| 937 | int ret = 0; |
| 938 | |
| 939 | memset(&error_str, 0, sizeof(error_str)); |
| 940 | |
| 941 | /* We need to have enough room to store any i915_error_state printf |
| 942 | * so that we can move it to start position. |
| 943 | */ |
| 944 | error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; |
| 945 | error_str.buf = kmalloc(error_str.size, |
| 946 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); |
| 947 | |
| 948 | if (error_str.buf == NULL) { |
| 949 | error_str.size = PAGE_SIZE; |
| 950 | error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY); |
| 951 | } |
| 952 | |
| 953 | if (error_str.buf == NULL) { |
| 954 | error_str.size = 128; |
| 955 | error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY); |
| 956 | } |
| 957 | |
| 958 | if (error_str.buf == NULL) |
| 959 | return -ENOMEM; |
| 960 | |
| 961 | error_str.start = *pos; |
| 962 | |
| 963 | ret = i915_error_state(error_priv, &error_str); |
| 964 | if (ret) |
| 965 | goto out; |
| 966 | |
| 967 | if (error_str.bytes == 0 && error_str.err) { |
| 968 | ret = error_str.err; |
| 969 | goto out; |
| 970 | } |
| 971 | |
| 972 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 973 | error_str.buf, |
| 974 | error_str.bytes); |
| 975 | |
| 976 | if (ret_count < 0) |
| 977 | ret = ret_count; |
| 978 | else |
| 979 | *pos = error_str.start + ret_count; |
| 980 | out: |
| 981 | kfree(error_str.buf); |
| 982 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 983 | } |
| 984 | |
| 985 | static const struct file_operations i915_error_state_fops = { |
| 986 | .owner = THIS_MODULE, |
| 987 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 988 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 989 | .write = i915_error_state_write, |
| 990 | .llseek = default_llseek, |
| 991 | .release = i915_error_state_release, |
| 992 | }; |
| 993 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 994 | static int |
| 995 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 996 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 997 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 998 | drm_i915_private_t *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 999 | int ret; |
| 1000 | |
| 1001 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1002 | if (ret) |
| 1003 | return ret; |
| 1004 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1005 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1006 | mutex_unlock(&dev->struct_mutex); |
| 1007 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1008 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1009 | } |
| 1010 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1011 | static int |
| 1012 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1013 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1014 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1015 | int ret; |
| 1016 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1017 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1018 | if (ret) |
| 1019 | return ret; |
| 1020 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 1021 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1022 | mutex_unlock(&dev->struct_mutex); |
| 1023 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1024 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1025 | } |
| 1026 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1027 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 1028 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1029 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1030 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1031 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
| 1032 | { |
| 1033 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1034 | struct drm_device *dev = node->minor->dev; |
| 1035 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1036 | u16 crstanddelay; |
| 1037 | int ret; |
| 1038 | |
| 1039 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1040 | if (ret) |
| 1041 | return ret; |
| 1042 | |
| 1043 | crstanddelay = I915_READ16(CRSTANDVID); |
| 1044 | |
| 1045 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1046 | |
| 1047 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); |
| 1048 | |
| 1049 | return 0; |
| 1050 | } |
| 1051 | |
| 1052 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) |
| 1053 | { |
| 1054 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1055 | struct drm_device *dev = node->minor->dev; |
| 1056 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1057 | int ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1058 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1059 | if (IS_GEN5(dev)) { |
| 1060 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1061 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1062 | |
| 1063 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1064 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1065 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1066 | MEMSTAT_VID_SHIFT); |
| 1067 | seq_printf(m, "Current P-state: %d\n", |
| 1068 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1069 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1070 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1071 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1072 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1073 | u32 rpstat, cagf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1074 | u32 rpupei, rpcurup, rpprevup; |
| 1075 | u32 rpdownei, rpcurdown, rpprevdown; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1076 | int max_freq; |
| 1077 | |
| 1078 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1079 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1080 | if (ret) |
| 1081 | return ret; |
| 1082 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 1083 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1084 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1085 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 1086 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 1087 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 1088 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 1089 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 1090 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 1091 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1092 | if (IS_HASWELL(dev)) |
| 1093 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1094 | else |
| 1095 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 1096 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1097 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1098 | gen6_gt_force_wake_put(dev_priv); |
| 1099 | mutex_unlock(&dev->struct_mutex); |
| 1100 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1101 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1102 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1103 | seq_printf(m, "Render p-state ratio: %d\n", |
| 1104 | (gt_perf_status & 0xff00) >> 8); |
| 1105 | seq_printf(m, "Render p-state VID: %d\n", |
| 1106 | gt_perf_status & 0xff); |
| 1107 | seq_printf(m, "Render p-state limit: %d\n", |
| 1108 | rp_state_limits & 0xff); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1109 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1110 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 1111 | GEN6_CURICONT_MASK); |
| 1112 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 1113 | GEN6_CURBSYTAVG_MASK); |
| 1114 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 1115 | GEN6_CURBSYTAVG_MASK); |
| 1116 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 1117 | GEN6_CURIAVG_MASK); |
| 1118 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 1119 | GEN6_CURBSYTAVG_MASK); |
| 1120 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 1121 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1122 | |
| 1123 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1124 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1125 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1126 | |
| 1127 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1128 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1129 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1130 | |
| 1131 | max_freq = rp_state_cap & 0xff; |
| 1132 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1133 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1134 | |
| 1135 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
| 1136 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1137 | } else if (IS_VALLEYVIEW(dev)) { |
| 1138 | u32 freq_sts, val; |
| 1139 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1140 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1141 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1142 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1143 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1144 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1145 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1146 | seq_printf(m, "max GPU freq: %d MHz\n", |
| 1147 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 1148 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1149 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1150 | seq_printf(m, "min GPU freq: %d MHz\n", |
| 1151 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 1152 | |
| 1153 | seq_printf(m, "current GPU freq: %d MHz\n", |
| 1154 | vlv_gpu_freq(dev_priv->mem_freq, |
| 1155 | (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1156 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1157 | } else { |
| 1158 | seq_printf(m, "no P-state info available\n"); |
| 1159 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1160 | |
| 1161 | return 0; |
| 1162 | } |
| 1163 | |
| 1164 | static int i915_delayfreq_table(struct seq_file *m, void *unused) |
| 1165 | { |
| 1166 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1167 | struct drm_device *dev = node->minor->dev; |
| 1168 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1169 | u32 delayfreq; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1170 | int ret, i; |
| 1171 | |
| 1172 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1173 | if (ret) |
| 1174 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1175 | |
| 1176 | for (i = 0; i < 16; i++) { |
| 1177 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1178 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
| 1179 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1180 | } |
| 1181 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1182 | mutex_unlock(&dev->struct_mutex); |
| 1183 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1184 | return 0; |
| 1185 | } |
| 1186 | |
| 1187 | static inline int MAP_TO_MV(int map) |
| 1188 | { |
| 1189 | return 1250 - (map * 25); |
| 1190 | } |
| 1191 | |
| 1192 | static int i915_inttoext_table(struct seq_file *m, void *unused) |
| 1193 | { |
| 1194 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1195 | struct drm_device *dev = node->minor->dev; |
| 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1197 | u32 inttoext; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1198 | int ret, i; |
| 1199 | |
| 1200 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1201 | if (ret) |
| 1202 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1203 | |
| 1204 | for (i = 1; i <= 32; i++) { |
| 1205 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); |
| 1206 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); |
| 1207 | } |
| 1208 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1209 | mutex_unlock(&dev->struct_mutex); |
| 1210 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1211 | return 0; |
| 1212 | } |
| 1213 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1214 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1215 | { |
| 1216 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1217 | struct drm_device *dev = node->minor->dev; |
| 1218 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1219 | u32 rgvmodectl, rstdbyctl; |
| 1220 | u16 crstandvid; |
| 1221 | int ret; |
| 1222 | |
| 1223 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1224 | if (ret) |
| 1225 | return ret; |
| 1226 | |
| 1227 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1228 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1229 | crstandvid = I915_READ16(CRSTANDVID); |
| 1230 | |
| 1231 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1232 | |
| 1233 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1234 | "yes" : "no"); |
| 1235 | seq_printf(m, "Boost freq: %d\n", |
| 1236 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1237 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1238 | seq_printf(m, "HW control enabled: %s\n", |
| 1239 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1240 | seq_printf(m, "SW control enabled: %s\n", |
| 1241 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1242 | seq_printf(m, "Gated voltage change: %s\n", |
| 1243 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1244 | seq_printf(m, "Starting frequency: P%d\n", |
| 1245 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1246 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1247 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1248 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1249 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1250 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1251 | seq_printf(m, "Render standby enabled: %s\n", |
| 1252 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1253 | seq_printf(m, "Current RS state: "); |
| 1254 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1255 | case RSX_STATUS_ON: |
| 1256 | seq_printf(m, "on\n"); |
| 1257 | break; |
| 1258 | case RSX_STATUS_RC1: |
| 1259 | seq_printf(m, "RC1\n"); |
| 1260 | break; |
| 1261 | case RSX_STATUS_RC1E: |
| 1262 | seq_printf(m, "RC1E\n"); |
| 1263 | break; |
| 1264 | case RSX_STATUS_RS1: |
| 1265 | seq_printf(m, "RS1\n"); |
| 1266 | break; |
| 1267 | case RSX_STATUS_RS2: |
| 1268 | seq_printf(m, "RS2 (RC6)\n"); |
| 1269 | break; |
| 1270 | case RSX_STATUS_RS3: |
| 1271 | seq_printf(m, "RC3 (RC6+)\n"); |
| 1272 | break; |
| 1273 | default: |
| 1274 | seq_printf(m, "unknown\n"); |
| 1275 | break; |
| 1276 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1277 | |
| 1278 | return 0; |
| 1279 | } |
| 1280 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1281 | static int gen6_drpc_info(struct seq_file *m) |
| 1282 | { |
| 1283 | |
| 1284 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1285 | struct drm_device *dev = node->minor->dev; |
| 1286 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1287 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1288 | unsigned forcewake_count; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1289 | int count=0, ret; |
| 1290 | |
| 1291 | |
| 1292 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1293 | if (ret) |
| 1294 | return ret; |
| 1295 | |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1296 | spin_lock_irq(&dev_priv->gt_lock); |
| 1297 | forcewake_count = dev_priv->forcewake_count; |
| 1298 | spin_unlock_irq(&dev_priv->gt_lock); |
| 1299 | |
| 1300 | if (forcewake_count) { |
| 1301 | seq_printf(m, "RC information inaccurate because somebody " |
| 1302 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1303 | } else { |
| 1304 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1305 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1306 | udelay(10); |
| 1307 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1308 | } |
| 1309 | |
| 1310 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
| 1311 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); |
| 1312 | |
| 1313 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1314 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1315 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1316 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1317 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1318 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1319 | |
| 1320 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1321 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1322 | seq_printf(m, "HW control enabled: %s\n", |
| 1323 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1324 | seq_printf(m, "SW control enabled: %s\n", |
| 1325 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1326 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1327 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1328 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1329 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1330 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1331 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1332 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1333 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1334 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
| 1335 | seq_printf(m, "Current RC state: "); |
| 1336 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1337 | case GEN6_RC0: |
| 1338 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
| 1339 | seq_printf(m, "Core Power Down\n"); |
| 1340 | else |
| 1341 | seq_printf(m, "on\n"); |
| 1342 | break; |
| 1343 | case GEN6_RC3: |
| 1344 | seq_printf(m, "RC3\n"); |
| 1345 | break; |
| 1346 | case GEN6_RC6: |
| 1347 | seq_printf(m, "RC6\n"); |
| 1348 | break; |
| 1349 | case GEN6_RC7: |
| 1350 | seq_printf(m, "RC7\n"); |
| 1351 | break; |
| 1352 | default: |
| 1353 | seq_printf(m, "Unknown\n"); |
| 1354 | break; |
| 1355 | } |
| 1356 | |
| 1357 | seq_printf(m, "Core Power Down: %s\n", |
| 1358 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1359 | |
| 1360 | /* Not exactly sure what this is */ |
| 1361 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1362 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1363 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1364 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1365 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1366 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1367 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1368 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1369 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1370 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1371 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1372 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1373 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1374 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1375 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1380 | { |
| 1381 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1382 | struct drm_device *dev = node->minor->dev; |
| 1383 | |
| 1384 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 1385 | return gen6_drpc_info(m); |
| 1386 | else |
| 1387 | return ironlake_drpc_info(m); |
| 1388 | } |
| 1389 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1390 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1391 | { |
| 1392 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1393 | struct drm_device *dev = node->minor->dev; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1394 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1395 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1396 | if (!I915_HAS_FBC(dev)) { |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1397 | seq_printf(m, "FBC unsupported on this chipset\n"); |
| 1398 | return 0; |
| 1399 | } |
| 1400 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1401 | if (intel_fbc_enabled(dev)) { |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1402 | seq_printf(m, "FBC enabled\n"); |
| 1403 | } else { |
| 1404 | seq_printf(m, "FBC disabled: "); |
| 1405 | switch (dev_priv->no_fbc_reason) { |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1406 | case FBC_NO_OUTPUT: |
| 1407 | seq_printf(m, "no outputs"); |
| 1408 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1409 | case FBC_STOLEN_TOO_SMALL: |
| 1410 | seq_printf(m, "not enough stolen memory"); |
| 1411 | break; |
| 1412 | case FBC_UNSUPPORTED_MODE: |
| 1413 | seq_printf(m, "mode not supported"); |
| 1414 | break; |
| 1415 | case FBC_MODE_TOO_LARGE: |
| 1416 | seq_printf(m, "mode too large"); |
| 1417 | break; |
| 1418 | case FBC_BAD_PLANE: |
| 1419 | seq_printf(m, "FBC unsupported on plane"); |
| 1420 | break; |
| 1421 | case FBC_NOT_TILED: |
| 1422 | seq_printf(m, "scanout buffer not tiled"); |
| 1423 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1424 | case FBC_MULTIPLE_PIPES: |
| 1425 | seq_printf(m, "multiple pipes are enabled"); |
| 1426 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1427 | case FBC_MODULE_PARAM: |
| 1428 | seq_printf(m, "disabled per module param (default off)"); |
| 1429 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1430 | default: |
| 1431 | seq_printf(m, "unknown reason"); |
| 1432 | } |
| 1433 | seq_printf(m, "\n"); |
| 1434 | } |
| 1435 | return 0; |
| 1436 | } |
| 1437 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1438 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1439 | { |
| 1440 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1441 | struct drm_device *dev = node->minor->dev; |
| 1442 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1443 | bool sr_enabled = false; |
| 1444 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1445 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1446 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1447 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1448 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1449 | else if (IS_I915GM(dev)) |
| 1450 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1451 | else if (IS_PINEVIEW(dev)) |
| 1452 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1453 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1454 | seq_printf(m, "self-refresh: %s\n", |
| 1455 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1456 | |
| 1457 | return 0; |
| 1458 | } |
| 1459 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1460 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1461 | { |
| 1462 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1463 | struct drm_device *dev = node->minor->dev; |
| 1464 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1465 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1466 | int ret; |
| 1467 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1468 | if (!IS_GEN5(dev)) |
| 1469 | return -ENODEV; |
| 1470 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1471 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1472 | if (ret) |
| 1473 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1474 | |
| 1475 | temp = i915_mch_val(dev_priv); |
| 1476 | chipset = i915_chipset_val(dev_priv); |
| 1477 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1478 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1479 | |
| 1480 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1481 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1482 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1483 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1484 | |
| 1485 | return 0; |
| 1486 | } |
| 1487 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1488 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1489 | { |
| 1490 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1491 | struct drm_device *dev = node->minor->dev; |
| 1492 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1493 | int ret; |
| 1494 | int gpu_freq, ia_freq; |
| 1495 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1496 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1497 | seq_printf(m, "unsupported on this chipset\n"); |
| 1498 | return 0; |
| 1499 | } |
| 1500 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1501 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1502 | if (ret) |
| 1503 | return ret; |
| 1504 | |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1505 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1506 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1507 | for (gpu_freq = dev_priv->rps.min_delay; |
| 1508 | gpu_freq <= dev_priv->rps.max_delay; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1509 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1510 | ia_freq = gpu_freq; |
| 1511 | sandybridge_pcode_read(dev_priv, |
| 1512 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1513 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1514 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1515 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1516 | ((ia_freq >> 0) & 0xff) * 100, |
| 1517 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1518 | } |
| 1519 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1520 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1521 | |
| 1522 | return 0; |
| 1523 | } |
| 1524 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1525 | static int i915_gfxec(struct seq_file *m, void *unused) |
| 1526 | { |
| 1527 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1528 | struct drm_device *dev = node->minor->dev; |
| 1529 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1530 | int ret; |
| 1531 | |
| 1532 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1533 | if (ret) |
| 1534 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1535 | |
| 1536 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); |
| 1537 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1538 | mutex_unlock(&dev->struct_mutex); |
| 1539 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1540 | return 0; |
| 1541 | } |
| 1542 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1543 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1544 | { |
| 1545 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1546 | struct drm_device *dev = node->minor->dev; |
| 1547 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1548 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1549 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1550 | int ret; |
| 1551 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1552 | if (data == NULL) |
| 1553 | return -ENOMEM; |
| 1554 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1555 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1556 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1557 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1558 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1559 | if (opregion->header) { |
| 1560 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1561 | seq_write(m, data, OPREGION_SIZE); |
| 1562 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1563 | |
| 1564 | mutex_unlock(&dev->struct_mutex); |
| 1565 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1566 | out: |
| 1567 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1568 | return 0; |
| 1569 | } |
| 1570 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1571 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1572 | { |
| 1573 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1574 | struct drm_device *dev = node->minor->dev; |
| 1575 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1576 | struct intel_fbdev *ifbdev; |
| 1577 | struct intel_framebuffer *fb; |
| 1578 | int ret; |
| 1579 | |
| 1580 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1581 | if (ret) |
| 1582 | return ret; |
| 1583 | |
| 1584 | ifbdev = dev_priv->fbdev; |
| 1585 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1586 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1587 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1588 | fb->base.width, |
| 1589 | fb->base.height, |
| 1590 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1591 | fb->base.bits_per_pixel, |
| 1592 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1593 | describe_obj(m, fb->obj); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1594 | seq_printf(m, "\n"); |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1595 | mutex_unlock(&dev->mode_config.mutex); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1596 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1597 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1598 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
| 1599 | if (&fb->base == ifbdev->helper.fb) |
| 1600 | continue; |
| 1601 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1602 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1603 | fb->base.width, |
| 1604 | fb->base.height, |
| 1605 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1606 | fb->base.bits_per_pixel, |
| 1607 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1608 | describe_obj(m, fb->obj); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1609 | seq_printf(m, "\n"); |
| 1610 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1611 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1612 | |
| 1613 | return 0; |
| 1614 | } |
| 1615 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1616 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1617 | { |
| 1618 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1619 | struct drm_device *dev = node->minor->dev; |
| 1620 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1621 | struct intel_ring_buffer *ring; |
| 1622 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1623 | |
| 1624 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1625 | if (ret) |
| 1626 | return ret; |
| 1627 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1628 | if (dev_priv->ips.pwrctx) { |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1629 | seq_printf(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1630 | describe_obj(m, dev_priv->ips.pwrctx); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1631 | seq_printf(m, "\n"); |
| 1632 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1633 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1634 | if (dev_priv->ips.renderctx) { |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1635 | seq_printf(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1636 | describe_obj(m, dev_priv->ips.renderctx); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1637 | seq_printf(m, "\n"); |
| 1638 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1639 | |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1640 | for_each_ring(ring, dev_priv, i) { |
| 1641 | if (ring->default_context) { |
| 1642 | seq_printf(m, "HW default context %s ring ", ring->name); |
| 1643 | describe_obj(m, ring->default_context->obj); |
| 1644 | seq_printf(m, "\n"); |
| 1645 | } |
| 1646 | } |
| 1647 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1648 | mutex_unlock(&dev->mode_config.mutex); |
| 1649 | |
| 1650 | return 0; |
| 1651 | } |
| 1652 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1653 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1654 | { |
| 1655 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1656 | struct drm_device *dev = node->minor->dev; |
| 1657 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1658 | unsigned forcewake_count; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1659 | |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1660 | spin_lock_irq(&dev_priv->gt_lock); |
| 1661 | forcewake_count = dev_priv->forcewake_count; |
| 1662 | spin_unlock_irq(&dev_priv->gt_lock); |
| 1663 | |
| 1664 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1665 | |
| 1666 | return 0; |
| 1667 | } |
| 1668 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1669 | static const char *swizzle_string(unsigned swizzle) |
| 1670 | { |
| 1671 | switch(swizzle) { |
| 1672 | case I915_BIT_6_SWIZZLE_NONE: |
| 1673 | return "none"; |
| 1674 | case I915_BIT_6_SWIZZLE_9: |
| 1675 | return "bit9"; |
| 1676 | case I915_BIT_6_SWIZZLE_9_10: |
| 1677 | return "bit9/bit10"; |
| 1678 | case I915_BIT_6_SWIZZLE_9_11: |
| 1679 | return "bit9/bit11"; |
| 1680 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1681 | return "bit9/bit10/bit11"; |
| 1682 | case I915_BIT_6_SWIZZLE_9_17: |
| 1683 | return "bit9/bit17"; |
| 1684 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1685 | return "bit9/bit10/bit17"; |
| 1686 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1687 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1688 | } |
| 1689 | |
| 1690 | return "bug"; |
| 1691 | } |
| 1692 | |
| 1693 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1694 | { |
| 1695 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1696 | struct drm_device *dev = node->minor->dev; |
| 1697 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1698 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1699 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1700 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1701 | if (ret) |
| 1702 | return ret; |
| 1703 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1704 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1705 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1706 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1707 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1708 | |
| 1709 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1710 | seq_printf(m, "DDC = 0x%08x\n", |
| 1711 | I915_READ(DCC)); |
| 1712 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1713 | I915_READ16(C0DRB3)); |
| 1714 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1715 | I915_READ16(C1DRB3)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1716 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1717 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1718 | I915_READ(MAD_DIMM_C0)); |
| 1719 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1720 | I915_READ(MAD_DIMM_C1)); |
| 1721 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1722 | I915_READ(MAD_DIMM_C2)); |
| 1723 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1724 | I915_READ(TILECTL)); |
| 1725 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1726 | I915_READ(ARB_MODE)); |
| 1727 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1728 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1729 | } |
| 1730 | mutex_unlock(&dev->struct_mutex); |
| 1731 | |
| 1732 | return 0; |
| 1733 | } |
| 1734 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1735 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 1736 | { |
| 1737 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1738 | struct drm_device *dev = node->minor->dev; |
| 1739 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1740 | struct intel_ring_buffer *ring; |
| 1741 | int i, ret; |
| 1742 | |
| 1743 | |
| 1744 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1745 | if (ret) |
| 1746 | return ret; |
| 1747 | if (INTEL_INFO(dev)->gen == 6) |
| 1748 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 1749 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 1750 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1751 | seq_printf(m, "%s\n", ring->name); |
| 1752 | if (INTEL_INFO(dev)->gen == 7) |
| 1753 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 1754 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 1755 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 1756 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 1757 | } |
| 1758 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1759 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1760 | |
| 1761 | seq_printf(m, "aliasing PPGTT:\n"); |
| 1762 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
| 1763 | } |
| 1764 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
| 1765 | mutex_unlock(&dev->struct_mutex); |
| 1766 | |
| 1767 | return 0; |
| 1768 | } |
| 1769 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1770 | static int i915_dpio_info(struct seq_file *m, void *data) |
| 1771 | { |
| 1772 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1773 | struct drm_device *dev = node->minor->dev; |
| 1774 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1775 | int ret; |
| 1776 | |
| 1777 | |
| 1778 | if (!IS_VALLEYVIEW(dev)) { |
| 1779 | seq_printf(m, "unsupported\n"); |
| 1780 | return 0; |
| 1781 | } |
| 1782 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1783 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1784 | if (ret) |
| 1785 | return ret; |
| 1786 | |
| 1787 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); |
| 1788 | |
| 1789 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1790 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1791 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1792 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1793 | |
| 1794 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1795 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1796 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1797 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1798 | |
| 1799 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1800 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1801 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1802 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1803 | |
| 1804 | seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1805 | vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1806 | seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1807 | vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1808 | |
| 1809 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1810 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1811 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1812 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1813 | |
| 1814 | return 0; |
| 1815 | } |
| 1816 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1817 | static int |
| 1818 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1819 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1820 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1821 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1822 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1823 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1824 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1825 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1826 | } |
| 1827 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1828 | static int |
| 1829 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1830 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1831 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1832 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1833 | DRM_INFO("Manually setting wedged to %llu\n", val); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1834 | i915_handle_error(dev, val); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1835 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1836 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1837 | } |
| 1838 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1839 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 1840 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1841 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 1842 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1843 | static int |
| 1844 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1845 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1846 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1847 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1848 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1849 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1850 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1851 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1852 | } |
| 1853 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1854 | static int |
| 1855 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1856 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1857 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1858 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1859 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1860 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1861 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1862 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1863 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1864 | if (ret) |
| 1865 | return ret; |
| 1866 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1867 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1868 | mutex_unlock(&dev->struct_mutex); |
| 1869 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1870 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1871 | } |
| 1872 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1873 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 1874 | i915_ring_stop_get, i915_ring_stop_set, |
| 1875 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 1876 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1877 | #define DROP_UNBOUND 0x1 |
| 1878 | #define DROP_BOUND 0x2 |
| 1879 | #define DROP_RETIRE 0x4 |
| 1880 | #define DROP_ACTIVE 0x8 |
| 1881 | #define DROP_ALL (DROP_UNBOUND | \ |
| 1882 | DROP_BOUND | \ |
| 1883 | DROP_RETIRE | \ |
| 1884 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1885 | static int |
| 1886 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1887 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1888 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1889 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1890 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1891 | } |
| 1892 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1893 | static int |
| 1894 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1895 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1896 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1897 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1898 | struct drm_i915_gem_object *obj, *next; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1899 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1900 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1901 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1902 | |
| 1903 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 1904 | * on ioctls on -EAGAIN. */ |
| 1905 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1906 | if (ret) |
| 1907 | return ret; |
| 1908 | |
| 1909 | if (val & DROP_ACTIVE) { |
| 1910 | ret = i915_gpu_idle(dev); |
| 1911 | if (ret) |
| 1912 | goto unlock; |
| 1913 | } |
| 1914 | |
| 1915 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 1916 | i915_gem_retire_requests(dev); |
| 1917 | |
| 1918 | if (val & DROP_BOUND) { |
| 1919 | list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list) |
| 1920 | if (obj->pin_count == 0) { |
| 1921 | ret = i915_gem_object_unbind(obj); |
| 1922 | if (ret) |
| 1923 | goto unlock; |
| 1924 | } |
| 1925 | } |
| 1926 | |
| 1927 | if (val & DROP_UNBOUND) { |
| 1928 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) |
| 1929 | if (obj->pages_pin_count == 0) { |
| 1930 | ret = i915_gem_object_put_pages(obj); |
| 1931 | if (ret) |
| 1932 | goto unlock; |
| 1933 | } |
| 1934 | } |
| 1935 | |
| 1936 | unlock: |
| 1937 | mutex_unlock(&dev->struct_mutex); |
| 1938 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1939 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1940 | } |
| 1941 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1942 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 1943 | i915_drop_caches_get, i915_drop_caches_set, |
| 1944 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1945 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1946 | static int |
| 1947 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1948 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1949 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1950 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1951 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1952 | |
| 1953 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1954 | return -ENODEV; |
| 1955 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1956 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1957 | if (ret) |
| 1958 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1959 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1960 | if (IS_VALLEYVIEW(dev)) |
| 1961 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 1962 | dev_priv->rps.max_delay); |
| 1963 | else |
| 1964 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1965 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1966 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1967 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1968 | } |
| 1969 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1970 | static int |
| 1971 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1972 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1973 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1974 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1975 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1976 | |
| 1977 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 1978 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1979 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1980 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1981 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1982 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 1983 | if (ret) |
| 1984 | return ret; |
| 1985 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 1986 | /* |
| 1987 | * Turbo will still be enabled, but won't go above the set value. |
| 1988 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1989 | if (IS_VALLEYVIEW(dev)) { |
| 1990 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 1991 | dev_priv->rps.max_delay = val; |
| 1992 | gen6_set_rps(dev, val); |
| 1993 | } else { |
| 1994 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 1995 | dev_priv->rps.max_delay = val; |
| 1996 | gen6_set_rps(dev, val); |
| 1997 | } |
| 1998 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1999 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2000 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2001 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2002 | } |
| 2003 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2004 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 2005 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2006 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2007 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2008 | static int |
| 2009 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2010 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2011 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2012 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2013 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2014 | |
| 2015 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2016 | return -ENODEV; |
| 2017 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2018 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2019 | if (ret) |
| 2020 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2021 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2022 | if (IS_VALLEYVIEW(dev)) |
| 2023 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 2024 | dev_priv->rps.min_delay); |
| 2025 | else |
| 2026 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2027 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2028 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2029 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2030 | } |
| 2031 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2032 | static int |
| 2033 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2034 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2035 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2036 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2037 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2038 | |
| 2039 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2040 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2041 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2042 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2043 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2044 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2045 | if (ret) |
| 2046 | return ret; |
| 2047 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2048 | /* |
| 2049 | * Turbo will still be enabled, but won't go below the set value. |
| 2050 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2051 | if (IS_VALLEYVIEW(dev)) { |
| 2052 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 2053 | dev_priv->rps.min_delay = val; |
| 2054 | valleyview_set_rps(dev, val); |
| 2055 | } else { |
| 2056 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 2057 | dev_priv->rps.min_delay = val; |
| 2058 | gen6_set_rps(dev, val); |
| 2059 | } |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2060 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2061 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2062 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2063 | } |
| 2064 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2065 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 2066 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2067 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2068 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2069 | static int |
| 2070 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2071 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2072 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2073 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2074 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2075 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2076 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2077 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2078 | return -ENODEV; |
| 2079 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2080 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2081 | if (ret) |
| 2082 | return ret; |
| 2083 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2084 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2085 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 2086 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2087 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2088 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2089 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2090 | } |
| 2091 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2092 | static int |
| 2093 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2094 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2095 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2096 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2097 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2098 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2099 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2100 | return -ENODEV; |
| 2101 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2102 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2103 | return -EINVAL; |
| 2104 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2105 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2106 | |
| 2107 | /* Update the cache sharing policy here as well */ |
| 2108 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2109 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 2110 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 2111 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 2112 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2113 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2114 | } |
| 2115 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2116 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 2117 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 2118 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2119 | |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2120 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 2121 | * allocated we need to hook into the minor for release. */ |
| 2122 | static int |
| 2123 | drm_add_fake_info_node(struct drm_minor *minor, |
| 2124 | struct dentry *ent, |
| 2125 | const void *key) |
| 2126 | { |
| 2127 | struct drm_info_node *node; |
| 2128 | |
| 2129 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); |
| 2130 | if (node == NULL) { |
| 2131 | debugfs_remove(ent); |
| 2132 | return -ENOMEM; |
| 2133 | } |
| 2134 | |
| 2135 | node->minor = minor; |
| 2136 | node->dent = ent; |
| 2137 | node->info_ent = (void *) key; |
Marcin Slusarz | b3e067c | 2011-11-09 22:20:35 +0100 | [diff] [blame] | 2138 | |
| 2139 | mutex_lock(&minor->debugfs_lock); |
| 2140 | list_add(&node->list, &minor->debugfs_list); |
| 2141 | mutex_unlock(&minor->debugfs_lock); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2146 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 2147 | { |
| 2148 | struct drm_device *dev = inode->i_private; |
| 2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2150 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2151 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2152 | return 0; |
| 2153 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2154 | gen6_gt_force_wake_get(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2155 | |
| 2156 | return 0; |
| 2157 | } |
| 2158 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2159 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2160 | { |
| 2161 | struct drm_device *dev = inode->i_private; |
| 2162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2163 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2164 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2165 | return 0; |
| 2166 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2167 | gen6_gt_force_wake_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2168 | |
| 2169 | return 0; |
| 2170 | } |
| 2171 | |
| 2172 | static const struct file_operations i915_forcewake_fops = { |
| 2173 | .owner = THIS_MODULE, |
| 2174 | .open = i915_forcewake_open, |
| 2175 | .release = i915_forcewake_release, |
| 2176 | }; |
| 2177 | |
| 2178 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 2179 | { |
| 2180 | struct drm_device *dev = minor->dev; |
| 2181 | struct dentry *ent; |
| 2182 | |
| 2183 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2184 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2185 | root, dev, |
| 2186 | &i915_forcewake_fops); |
| 2187 | if (IS_ERR(ent)) |
| 2188 | return PTR_ERR(ent); |
| 2189 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2190 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2191 | } |
| 2192 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2193 | static int i915_debugfs_create(struct dentry *root, |
| 2194 | struct drm_minor *minor, |
| 2195 | const char *name, |
| 2196 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2197 | { |
| 2198 | struct drm_device *dev = minor->dev; |
| 2199 | struct dentry *ent; |
| 2200 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2201 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2202 | S_IRUGO | S_IWUSR, |
| 2203 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2204 | fops); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2205 | if (IS_ERR(ent)) |
| 2206 | return PTR_ERR(ent); |
| 2207 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2208 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2209 | } |
| 2210 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2211 | static struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 2212 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2213 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 2214 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 2215 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2216 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 2217 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2218 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2219 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 2220 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 2221 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2222 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2223 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 2224 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 2225 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame^] | 2226 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2227 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
| 2228 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, |
| 2229 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
| 2230 | {"i915_inttoext_table", i915_inttoext_table, 0}, |
| 2231 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2232 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 2233 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2234 | {"i915_gfxec", i915_gfxec, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 2235 | {"i915_fbc_status", i915_fbc_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 2236 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2237 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 2238 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 2239 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2240 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2241 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2242 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 2243 | {"i915_dpio", i915_dpio_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2244 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2245 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2246 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2247 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2248 | { |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2249 | int ret; |
| 2250 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2251 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2252 | "i915_wedged", |
| 2253 | &i915_wedged_fops); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2254 | if (ret) |
| 2255 | return ret; |
| 2256 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2257 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 2258 | if (ret) |
| 2259 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2260 | |
| 2261 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2262 | "i915_max_freq", |
| 2263 | &i915_max_freq_fops); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2264 | if (ret) |
| 2265 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2266 | |
| 2267 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2268 | "i915_min_freq", |
| 2269 | &i915_min_freq_fops); |
| 2270 | if (ret) |
| 2271 | return ret; |
| 2272 | |
| 2273 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2274 | "i915_cache_sharing", |
| 2275 | &i915_cache_sharing_fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2276 | if (ret) |
| 2277 | return ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2278 | |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2279 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2280 | "i915_ring_stop", |
| 2281 | &i915_ring_stop_fops); |
| 2282 | if (ret) |
| 2283 | return ret; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2284 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 2285 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2286 | "i915_gem_drop_caches", |
| 2287 | &i915_drop_caches_fops); |
| 2288 | if (ret) |
| 2289 | return ret; |
| 2290 | |
| 2291 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 2292 | "i915_error_state", |
| 2293 | &i915_error_state_fops); |
| 2294 | if (ret) |
| 2295 | return ret; |
| 2296 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 2297 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 2298 | "i915_next_seqno", |
| 2299 | &i915_next_seqno_fops); |
| 2300 | if (ret) |
| 2301 | return ret; |
| 2302 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2303 | return drm_debugfs_create_files(i915_debugfs_list, |
| 2304 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2305 | minor->debugfs_root, minor); |
| 2306 | } |
| 2307 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2308 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2309 | { |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2310 | drm_debugfs_remove_files(i915_debugfs_list, |
| 2311 | I915_DEBUGFS_ENTRIES, minor); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2312 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 2313 | 1, minor); |
Kristian Høgsberg | 33db679 | 2009-11-11 12:19:16 -0500 | [diff] [blame] | 2314 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
| 2315 | 1, minor); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2316 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
| 2317 | 1, minor); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2318 | drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops, |
| 2319 | 1, minor); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2320 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
| 2321 | 1, minor); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2322 | drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops, |
| 2323 | 1, minor); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2324 | drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, |
| 2325 | 1, minor); |
Daniel Vetter | 6bd459d | 2012-05-21 19:56:52 +0200 | [diff] [blame] | 2326 | drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops, |
| 2327 | 1, minor); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 2328 | drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops, |
| 2329 | 1, minor); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2330 | } |
| 2331 | |
| 2332 | #endif /* CONFIG_DEBUG_FS */ |