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Tejun Heoedb33662005-07-28 10:36:22 +09001/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
Tejun Heoedb33662005-07-28 10:36:22 +09008 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090022#include <linux/gfp.h>
Tejun Heoedb33662005-07-28 10:36:22 +090023#include <linux/pci.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050028#include <linux/device.h>
Tejun Heoedb33662005-07-28 10:36:22 +090029#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050030#include <scsi/scsi_cmnd.h>
Tejun Heoedb33662005-07-28 10:36:22 +090031#include <linux/libata.h>
Tejun Heoedb33662005-07-28 10:36:22 +090032
33#define DRV_NAME "sata_sil24"
Tejun Heo3454dc62007-09-23 13:19:54 +090034#define DRV_VERSION "1.1"
Tejun Heoedb33662005-07-28 10:36:22 +090035
Tejun Heoedb33662005-07-28 10:36:22 +090036/*
37 * Port request block (PRB) 32 bytes
38 */
39struct sil24_prb {
Alexey Dobriyanb4772572006-06-06 07:31:14 +040040 __le16 ctrl;
41 __le16 prot;
42 __le32 rx_cnt;
Tejun Heoedb33662005-07-28 10:36:22 +090043 u8 fis[6 * 4];
44};
45
46/*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49struct sil24_sge {
Alexey Dobriyanb4772572006-06-06 07:31:14 +040050 __le64 addr;
51 __le32 cnt;
52 __le32 flags;
Tejun Heoedb33662005-07-28 10:36:22 +090053};
54
Tejun Heoedb33662005-07-28 10:36:22 +090055
56enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090057 SIL24_HOST_BAR = 0,
58 SIL24_PORT_BAR = 2,
59
Tejun Heo93e26182007-11-22 18:46:57 +090060 /* sil24 fetches in chunks of 64bytes. The first block
61 * contains the PRB and two SGEs. From the second block, it's
62 * consisted of four SGEs and called SGT. Calculate the
63 * number of SGTs that fit into one page.
64 */
65 SIL24_PRB_SZ = sizeof(struct sil24_prb)
66 + 2 * sizeof(struct sil24_sge),
67 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
68 / (4 * sizeof(struct sil24_sge)),
69
70 /* This will give us one unused SGEs for ATA. This extra SGE
71 * will be used to store CDB for ATAPI devices.
72 */
73 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
74
Tejun Heoedb33662005-07-28 10:36:22 +090075 /*
76 * Global controller registers (128 bytes @ BAR0)
77 */
78 /* 32 bit regs */
79 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
80 HOST_CTRL = 0x40,
81 HOST_IRQ_STAT = 0x44,
82 HOST_PHY_CFG = 0x48,
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
88 /* 8 bit regs */
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78, /* 32 bit */
93 HOST_I2C_DATA = 0x7c,
94 HOST_I2C_XFER_CNT = 0x7e,
95 HOST_I2C_CTRL = 0x7f,
96
97 /* HOST_SLOT_STAT bits */
98 HOST_SSTAT_ATTN = (1 << 31),
99
Tejun Heo7dafc3f2006-04-11 22:32:18 +0900100 /* HOST_CTRL bits */
101 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
102 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
103 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
104 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
105 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
Tejun Heod2298dc2006-07-03 16:07:27 +0900106 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
Tejun Heo7dafc3f2006-04-11 22:32:18 +0900107
Tejun Heoedb33662005-07-28 10:36:22 +0900108 /*
109 * Port registers
110 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
111 */
112 PORT_REGS_SIZE = 0x2000,
Tejun Heo135da342006-05-31 18:27:57 +0900113
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900114 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
Tejun Heo135da342006-05-31 18:27:57 +0900115 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
Tejun Heoedb33662005-07-28 10:36:22 +0900116
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900117 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
Tejun Heoc0c55902006-10-16 08:47:18 +0900118 PORT_PMP_STATUS = 0x0000, /* port device status offset */
119 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
120 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
121
Tejun Heoedb33662005-07-28 10:36:22 +0900122 /* 32 bit regs */
Tejun Heo83bbecc2005-08-17 13:09:18 +0900123 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
124 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
125 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
126 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
127 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
Tejun Heoedb33662005-07-28 10:36:22 +0900128 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
Tejun Heo83bbecc2005-08-17 13:09:18 +0900129 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
130 PORT_CMD_ERR = 0x1024, /* command error number */
Tejun Heoedb33662005-07-28 10:36:22 +0900131 PORT_FIS_CFG = 0x1028,
132 PORT_FIFO_THRES = 0x102c,
133 /* 16 bit regs */
134 PORT_DECODE_ERR_CNT = 0x1040,
135 PORT_DECODE_ERR_THRESH = 0x1042,
136 PORT_CRC_ERR_CNT = 0x1044,
137 PORT_CRC_ERR_THRESH = 0x1046,
138 PORT_HSHK_ERR_CNT = 0x1048,
139 PORT_HSHK_ERR_THRESH = 0x104a,
140 /* 32 bit regs */
141 PORT_PHY_CFG = 0x1050,
142 PORT_SLOT_STAT = 0x1800,
143 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
Tejun Heoc0c55902006-10-16 08:47:18 +0900144 PORT_CONTEXT = 0x1e04,
Tejun Heoedb33662005-07-28 10:36:22 +0900145 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
146 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
147 PORT_SCONTROL = 0x1f00,
148 PORT_SSTATUS = 0x1f04,
149 PORT_SERROR = 0x1f08,
150 PORT_SACTIVE = 0x1f0c,
151
152 /* PORT_CTRL_STAT bits */
153 PORT_CS_PORT_RST = (1 << 0), /* port reset */
154 PORT_CS_DEV_RST = (1 << 1), /* device reset */
155 PORT_CS_INIT = (1 << 2), /* port initialize */
156 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
Tejun Heod10cb352005-11-16 16:56:49 +0900157 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900158 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
Tejun Heoe382eb12005-08-17 13:09:13 +0900159 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900160 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
Tejun Heoe382eb12005-08-17 13:09:13 +0900161 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
Tejun Heoedb33662005-07-28 10:36:22 +0900162
163 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
164 /* bits[11:0] are masked */
165 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
166 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
167 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
168 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
169 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
170 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
Tejun Heo7dafc3f2006-04-11 22:32:18 +0900171 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
172 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
173 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
174 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
175 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
Tejun Heo3b9f1d02006-04-11 22:32:18 +0900176 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
Tejun Heoedb33662005-07-28 10:36:22 +0900177
Tejun Heo88ce7552006-05-15 20:58:32 +0900178 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
Tejun Heo05429252006-05-31 18:28:20 +0900179 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
Tejun Heo854c73a2007-09-23 13:14:11 +0900180 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
Tejun Heo88ce7552006-05-15 20:58:32 +0900181
Tejun Heoedb33662005-07-28 10:36:22 +0900182 /* bits[27:16] are unmasked (raw) */
183 PORT_IRQ_RAW_SHIFT = 16,
184 PORT_IRQ_MASKED_MASK = 0x7ff,
185 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
186
187 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
188 PORT_IRQ_STEER_SHIFT = 30,
189 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
190
191 /* PORT_CMD_ERR constants */
192 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
193 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
194 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
195 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
196 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
197 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
198 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
199 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
200 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
201 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
202 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
203 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
204 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
205 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
206 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
207 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
208 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
209 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
210 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
Tejun Heo64008802006-04-11 22:32:18 +0900211 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
Tejun Heoedb33662005-07-28 10:36:22 +0900212 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
Tejun Heo83bbecc2005-08-17 13:09:18 +0900213 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
Tejun Heoedb33662005-07-28 10:36:22 +0900214
Tejun Heod10cb352005-11-16 16:56:49 +0900215 /* bits of PRB control field */
216 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
217 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
218 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
219 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
220 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
221
222 /* PRB protocol field */
223 PRB_PROT_PACKET = (1 << 0),
224 PRB_PROT_TCQ = (1 << 1),
225 PRB_PROT_NCQ = (1 << 2),
226 PRB_PROT_READ = (1 << 3),
227 PRB_PROT_WRITE = (1 << 4),
228 PRB_PROT_TRANSPARENT = (1 << 5),
229
Tejun Heoedb33662005-07-28 10:36:22 +0900230 /*
231 * Other constants
232 */
233 SGE_TRM = (1 << 31), /* Last SGE in chain */
Tejun Heod10cb352005-11-16 16:56:49 +0900234 SGE_LNK = (1 << 30), /* linked list
235 Points to SGT, not SGE */
236 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
237 data address ignored */
Tejun Heoedb33662005-07-28 10:36:22 +0900238
Tejun Heoaee10a02006-05-15 21:03:56 +0900239 SIL24_MAX_CMDS = 31,
240
Tejun Heoedb33662005-07-28 10:36:22 +0900241 /* board id */
242 BID_SIL3124 = 0,
243 BID_SIL3132 = 1,
Tejun Heo042c21f2005-10-09 09:35:46 -0400244 BID_SIL3131 = 2,
Tejun Heoedb33662005-07-28 10:36:22 +0900245
Tejun Heo9466d852006-04-11 22:32:18 +0900246 /* host flags */
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300247 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
248 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
249 ATA_FLAG_AN | ATA_FLAG_PMP,
Tejun Heo37024e82006-04-11 22:32:19 +0900250 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
Tejun Heo9466d852006-04-11 22:32:18 +0900251
Tejun Heoedb33662005-07-28 10:36:22 +0900252 IRQ_STAT_4PORTS = 0xf,
253};
254
Tejun Heo69ad1852005-11-18 14:16:45 +0900255struct sil24_ata_block {
Tejun Heoedb33662005-07-28 10:36:22 +0900256 struct sil24_prb prb;
Tejun Heo93e26182007-11-22 18:46:57 +0900257 struct sil24_sge sge[SIL24_MAX_SGE];
Tejun Heoedb33662005-07-28 10:36:22 +0900258};
259
Tejun Heo69ad1852005-11-18 14:16:45 +0900260struct sil24_atapi_block {
261 struct sil24_prb prb;
262 u8 cdb[16];
Tejun Heo93e26182007-11-22 18:46:57 +0900263 struct sil24_sge sge[SIL24_MAX_SGE];
Tejun Heo69ad1852005-11-18 14:16:45 +0900264};
265
266union sil24_cmd_block {
267 struct sil24_ata_block ata;
268 struct sil24_atapi_block atapi;
269};
270
Joe Perchesfc8cc1d2011-08-05 19:38:17 -0700271static const struct sil24_cerr_info {
Tejun Heo88ce7552006-05-15 20:58:32 +0900272 unsigned int err_mask, action;
273 const char *desc;
274} sil24_cerr_db[] = {
Tejun Heof90f0822007-10-26 16:12:41 +0900275 [0] = { AC_ERR_DEV, 0,
Tejun Heo88ce7552006-05-15 20:58:32 +0900276 "device error" },
Tejun Heof90f0822007-10-26 16:12:41 +0900277 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
Tejun Heo88ce7552006-05-15 20:58:32 +0900278 "device error via D2H FIS" },
Tejun Heof90f0822007-10-26 16:12:41 +0900279 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
Tejun Heo88ce7552006-05-15 20:58:32 +0900280 "device error via SDB FIS" },
Tejun Heocf480622008-01-24 00:05:14 +0900281 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900282 "error in data FIS" },
Tejun Heocf480622008-01-24 00:05:14 +0900283 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900284 "failed to transmit command FIS" },
Tejun Heocf480622008-01-24 00:05:14 +0900285 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900286 "protocol mismatch" },
Tejun Heocf480622008-01-24 00:05:14 +0900287 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900288 "data directon mismatch" },
Tejun Heocf480622008-01-24 00:05:14 +0900289 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900290 "ran out of SGEs while writing" },
Tejun Heocf480622008-01-24 00:05:14 +0900291 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900292 "ran out of SGEs while reading" },
Tejun Heocf480622008-01-24 00:05:14 +0900293 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900294 "invalid data directon for ATAPI CDB" },
Tejun Heocf480622008-01-24 00:05:14 +0900295 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
Tejun Heo7293fa82008-01-13 13:49:22 +0900296 "SGT not on qword boundary" },
Tejun Heocf480622008-01-24 00:05:14 +0900297 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900298 "PCI target abort while fetching SGT" },
Tejun Heocf480622008-01-24 00:05:14 +0900299 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900300 "PCI master abort while fetching SGT" },
Tejun Heocf480622008-01-24 00:05:14 +0900301 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900302 "PCI parity error while fetching SGT" },
Tejun Heocf480622008-01-24 00:05:14 +0900303 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900304 "PRB not on qword boundary" },
Tejun Heocf480622008-01-24 00:05:14 +0900305 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900306 "PCI target abort while fetching PRB" },
Tejun Heocf480622008-01-24 00:05:14 +0900307 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900308 "PCI master abort while fetching PRB" },
Tejun Heocf480622008-01-24 00:05:14 +0900309 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900310 "PCI parity error while fetching PRB" },
Tejun Heocf480622008-01-24 00:05:14 +0900311 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900312 "undefined error while transferring data" },
Tejun Heocf480622008-01-24 00:05:14 +0900313 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900314 "PCI target abort while transferring data" },
Tejun Heocf480622008-01-24 00:05:14 +0900315 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900316 "PCI master abort while transferring data" },
Tejun Heocf480622008-01-24 00:05:14 +0900317 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900318 "PCI parity error while transferring data" },
Tejun Heocf480622008-01-24 00:05:14 +0900319 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
Tejun Heo88ce7552006-05-15 20:58:32 +0900320 "FIS received while sending service FIS" },
321};
322
Tejun Heoedb33662005-07-28 10:36:22 +0900323/*
324 * ap->private_data
325 *
326 * The preview driver always returned 0 for status. We emulate it
327 * here from the previous interrupt.
328 */
329struct sil24_port_priv {
Tejun Heo69ad1852005-11-18 14:16:45 +0900330 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
Tejun Heoedb33662005-07-28 10:36:22 +0900331 dma_addr_t cmd_block_dma; /* DMA base addr for them */
Tejun Heo23818032007-09-23 13:19:54 +0900332 int do_port_rst;
Tejun Heoedb33662005-07-28 10:36:22 +0900333};
334
Alancd0d3bb2007-03-02 00:56:15 +0000335static void sil24_dev_config(struct ata_device *dev);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900336static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
337static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
Tejun Heo3454dc62007-09-23 13:19:54 +0900338static int sil24_qc_defer(struct ata_queued_cmd *qc);
Tejun Heoedb33662005-07-28 10:36:22 +0900339static void sil24_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900340static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo79f97da2008-04-07 22:47:20 +0900341static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
Tejun Heo3454dc62007-09-23 13:19:54 +0900342static void sil24_pmp_attach(struct ata_port *ap);
343static void sil24_pmp_detach(struct ata_port *ap);
Tejun Heo88ce7552006-05-15 20:58:32 +0900344static void sil24_freeze(struct ata_port *ap);
345static void sil24_thaw(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900346static int sil24_softreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348static int sil24_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900350static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
Tejun Heo88ce7552006-05-15 20:58:32 +0900352static void sil24_error_handler(struct ata_port *ap);
353static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
Tejun Heoedb33662005-07-28 10:36:22 +0900354static int sil24_port_start(struct ata_port *ap);
Tejun Heoedb33662005-07-28 10:36:22 +0900355static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700356#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +0900357static int sil24_pci_device_resume(struct pci_dev *pdev);
Tejun Heo3454dc62007-09-23 13:19:54 +0900358static int sil24_port_resume(struct ata_port *ap);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700359#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900360
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500361static const struct pci_device_id sil24_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400362 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
363 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
364 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
Jamie Clark722d67b2007-03-13 12:48:00 +0800365 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
Tejun Heo464b3282008-07-02 17:50:23 +0900366 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400367 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
368 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
369
Tejun Heo1fcce8392005-10-09 09:31:33 -0400370 { } /* terminate list */
Tejun Heoedb33662005-07-28 10:36:22 +0900371};
372
373static struct pci_driver sil24_pci_driver = {
374 .name = DRV_NAME,
375 .id_table = sil24_pci_tbl,
376 .probe = sil24_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900377 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700378#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +0900379 .suspend = ata_pci_device_suspend,
380 .resume = sil24_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700381#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900382};
383
Jeff Garzik193515d2005-11-07 00:59:37 -0500384static struct scsi_host_template sil24_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900385 ATA_NCQ_SHT(DRV_NAME),
Tejun Heoaee10a02006-05-15 21:03:56 +0900386 .can_queue = SIL24_MAX_CMDS,
Tejun Heo93e26182007-11-22 18:46:57 +0900387 .sg_tablesize = SIL24_MAX_SGE,
Tejun Heoedb33662005-07-28 10:36:22 +0900388 .dma_boundary = ATA_DMA_BOUNDARY,
Tejun Heoedb33662005-07-28 10:36:22 +0900389};
390
Tejun Heo029cfd62008-03-25 12:22:49 +0900391static struct ata_port_operations sil24_ops = {
392 .inherits = &sata_pmp_port_ops,
Tejun Heo69ad1852005-11-18 14:16:45 +0900393
Tejun Heo3454dc62007-09-23 13:19:54 +0900394 .qc_defer = sil24_qc_defer,
Tejun Heoedb33662005-07-28 10:36:22 +0900395 .qc_prep = sil24_qc_prep,
396 .qc_issue = sil24_qc_issue,
Tejun Heo79f97da2008-04-07 22:47:20 +0900397 .qc_fill_rtf = sil24_qc_fill_rtf,
Tejun Heoedb33662005-07-28 10:36:22 +0900398
Tejun Heo88ce7552006-05-15 20:58:32 +0900399 .freeze = sil24_freeze,
400 .thaw = sil24_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900401 .softreset = sil24_softreset,
402 .hardreset = sil24_hardreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900403 .pmp_softreset = sil24_softreset,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900404 .pmp_hardreset = sil24_pmp_hardreset,
Tejun Heo88ce7552006-05-15 20:58:32 +0900405 .error_handler = sil24_error_handler,
406 .post_internal_cmd = sil24_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900407 .dev_config = sil24_dev_config,
408
409 .scr_read = sil24_scr_read,
410 .scr_write = sil24_scr_write,
411 .pmp_attach = sil24_pmp_attach,
412 .pmp_detach = sil24_pmp_detach,
Tejun Heo88ce7552006-05-15 20:58:32 +0900413
Tejun Heoedb33662005-07-28 10:36:22 +0900414 .port_start = sil24_port_start,
Tejun Heo3454dc62007-09-23 13:19:54 +0900415#ifdef CONFIG_PM
416 .port_resume = sil24_port_resume,
417#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900418};
419
Rusty Russell90ab5ee2012-01-13 09:32:20 +1030420static bool sata_sil24_msi; /* Disable MSI */
Vivek Mahajandae77212009-11-16 11:49:22 +0530421module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
422MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
423
Tejun Heo042c21f2005-10-09 09:35:46 -0400424/*
Jeff Garzikcca39742006-08-24 03:19:22 -0400425 * Use bits 30-31 of port_flags to encode available port numbers.
Tejun Heo042c21f2005-10-09 09:35:46 -0400426 * Current maxium is 4.
427 */
428#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
429#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
430
Tejun Heo4447d352007-04-17 23:44:08 +0900431static const struct ata_port_info sil24_port_info[] = {
Tejun Heoedb33662005-07-28 10:36:22 +0900432 /* sil_3124 */
433 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
Tejun Heo37024e82006-04-11 22:32:19 +0900435 SIL24_FLAG_PCIX_IRQ_WOC,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100436 .pio_mask = ATA_PIO4,
437 .mwdma_mask = ATA_MWDMA2,
438 .udma_mask = ATA_UDMA5,
Tejun Heoedb33662005-07-28 10:36:22 +0900439 .port_ops = &sil24_ops,
440 },
Jeff Garzik2e9edbf2006-03-24 09:56:57 -0500441 /* sil_3132 */
Tejun Heoedb33662005-07-28 10:36:22 +0900442 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400443 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100444 .pio_mask = ATA_PIO4,
445 .mwdma_mask = ATA_MWDMA2,
446 .udma_mask = ATA_UDMA5,
Tejun Heo042c21f2005-10-09 09:35:46 -0400447 .port_ops = &sil24_ops,
448 },
449 /* sil_3131/sil_3531 */
450 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400451 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100452 .pio_mask = ATA_PIO4,
453 .mwdma_mask = ATA_MWDMA2,
454 .udma_mask = ATA_UDMA5,
Tejun Heoedb33662005-07-28 10:36:22 +0900455 .port_ops = &sil24_ops,
456 },
457};
458
Tejun Heoaee10a02006-05-15 21:03:56 +0900459static int sil24_tag(int tag)
460{
461 if (unlikely(ata_tag_internal(tag)))
462 return 0;
463 return tag;
464}
465
Tejun Heo350756f2008-04-07 22:47:21 +0900466static unsigned long sil24_port_offset(struct ata_port *ap)
467{
468 return ap->port_no * PORT_REGS_SIZE;
469}
470
471static void __iomem *sil24_port_base(struct ata_port *ap)
472{
473 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
474}
475
Alancd0d3bb2007-03-02 00:56:15 +0000476static void sil24_dev_config(struct ata_device *dev)
Tejun Heo69ad1852005-11-18 14:16:45 +0900477{
Tejun Heo350756f2008-04-07 22:47:21 +0900478 void __iomem *port = sil24_port_base(dev->link->ap);
Tejun Heo69ad1852005-11-18 14:16:45 +0900479
Tejun Heo6e7846e2006-02-12 23:32:58 +0900480 if (dev->cdb_len == 16)
Tejun Heo69ad1852005-11-18 14:16:45 +0900481 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
482 else
483 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
484}
485
Tejun Heoe59f0da2007-07-16 14:29:39 +0900486static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
Tejun Heo6a575fa2005-10-06 11:43:39 +0900487{
Tejun Heo350756f2008-04-07 22:47:21 +0900488 void __iomem *port = sil24_port_base(ap);
Tejun Heoe59f0da2007-07-16 14:29:39 +0900489 struct sil24_prb __iomem *prb;
Al Viro4b4a5ea2005-10-29 06:38:44 +0100490 u8 fis[6 * 4];
Tejun Heo6a575fa2005-10-06 11:43:39 +0900491
Tejun Heoe59f0da2007-07-16 14:29:39 +0900492 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
493 memcpy_fromio(fis, prb->fis, sizeof(fis));
494 ata_tf_from_fis(fis, tf);
Tejun Heo6a575fa2005-10-06 11:43:39 +0900495}
496
Tejun Heoedb33662005-07-28 10:36:22 +0900497static int sil24_scr_map[] = {
498 [SCR_CONTROL] = 0,
499 [SCR_STATUS] = 1,
500 [SCR_ERROR] = 2,
501 [SCR_ACTIVE] = 3,
502};
503
Tejun Heo82ef04f2008-07-31 17:02:40 +0900504static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
Tejun Heoedb33662005-07-28 10:36:22 +0900505{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900506 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
Tejun Heoda3dbb12007-07-16 14:29:40 +0900507
Tejun Heoedb33662005-07-28 10:36:22 +0900508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
Al Viro4b4a5ea2005-10-29 06:38:44 +0100509 void __iomem *addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
Tejun Heoda3dbb12007-07-16 14:29:40 +0900511 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
512 return 0;
Tejun Heoedb33662005-07-28 10:36:22 +0900513 }
Tejun Heoda3dbb12007-07-16 14:29:40 +0900514 return -EINVAL;
Tejun Heoedb33662005-07-28 10:36:22 +0900515}
516
Tejun Heo82ef04f2008-07-31 17:02:40 +0900517static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
Tejun Heoedb33662005-07-28 10:36:22 +0900518{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900519 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
Tejun Heoda3dbb12007-07-16 14:29:40 +0900520
Tejun Heoedb33662005-07-28 10:36:22 +0900521 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
Al Viro4b4a5ea2005-10-29 06:38:44 +0100522 void __iomem *addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900523 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
524 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900525 return 0;
Tejun Heoedb33662005-07-28 10:36:22 +0900526 }
Tejun Heoda3dbb12007-07-16 14:29:40 +0900527 return -EINVAL;
Tejun Heoedb33662005-07-28 10:36:22 +0900528}
529
Tejun Heo23818032007-09-23 13:19:54 +0900530static void sil24_config_port(struct ata_port *ap)
531{
Tejun Heo350756f2008-04-07 22:47:21 +0900532 void __iomem *port = sil24_port_base(ap);
Tejun Heo23818032007-09-23 13:19:54 +0900533
534 /* configure IRQ WoC */
535 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
536 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
537 else
538 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
539
540 /* zero error counters. */
Colin Tuckley7a4f8762010-06-04 16:19:51 +0200541 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
542 writew(0x8000, port + PORT_CRC_ERR_THRESH);
543 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
544 writew(0x0000, port + PORT_DECODE_ERR_CNT);
545 writew(0x0000, port + PORT_CRC_ERR_CNT);
546 writew(0x0000, port + PORT_HSHK_ERR_CNT);
Tejun Heo23818032007-09-23 13:19:54 +0900547
548 /* always use 64bit activation */
549 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
550
551 /* clear port multiplier enable and resume bits */
552 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
553}
554
Tejun Heo3454dc62007-09-23 13:19:54 +0900555static void sil24_config_pmp(struct ata_port *ap, int attached)
556{
Tejun Heo350756f2008-04-07 22:47:21 +0900557 void __iomem *port = sil24_port_base(ap);
Tejun Heo3454dc62007-09-23 13:19:54 +0900558
559 if (attached)
560 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
561 else
562 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
563}
564
565static void sil24_clear_pmp(struct ata_port *ap)
566{
Tejun Heo350756f2008-04-07 22:47:21 +0900567 void __iomem *port = sil24_port_base(ap);
Tejun Heo3454dc62007-09-23 13:19:54 +0900568 int i;
569
570 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
571
572 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
573 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
574
575 writel(0, pmp_base + PORT_PMP_STATUS);
576 writel(0, pmp_base + PORT_PMP_QACTIVE);
577 }
578}
579
Tejun Heob5bc4212006-04-11 22:32:19 +0900580static int sil24_init_port(struct ata_port *ap)
581{
Tejun Heo350756f2008-04-07 22:47:21 +0900582 void __iomem *port = sil24_port_base(ap);
Tejun Heo23818032007-09-23 13:19:54 +0900583 struct sil24_port_priv *pp = ap->private_data;
Tejun Heob5bc4212006-04-11 22:32:19 +0900584 u32 tmp;
585
Tejun Heo3454dc62007-09-23 13:19:54 +0900586 /* clear PMP error status */
Tejun Heo071f44b2008-04-07 22:47:22 +0900587 if (sata_pmp_attached(ap))
Tejun Heo3454dc62007-09-23 13:19:54 +0900588 sil24_clear_pmp(ap);
589
Tejun Heob5bc4212006-04-11 22:32:19 +0900590 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
Tejun Heo97750ce2010-09-06 17:56:29 +0200591 ata_wait_register(ap, port + PORT_CTRL_STAT,
Tejun Heob5bc4212006-04-11 22:32:19 +0900592 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
Tejun Heo97750ce2010-09-06 17:56:29 +0200593 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
Tejun Heob5bc4212006-04-11 22:32:19 +0900594 PORT_CS_RDY, 0, 10, 100);
595
Tejun Heo23818032007-09-23 13:19:54 +0900596 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
597 pp->do_port_rst = 1;
Tejun Heocf480622008-01-24 00:05:14 +0900598 ap->link.eh_context.i.action |= ATA_EH_RESET;
Tejun Heob5bc4212006-04-11 22:32:19 +0900599 return -EIO;
Tejun Heo23818032007-09-23 13:19:54 +0900600 }
601
Tejun Heob5bc4212006-04-11 22:32:19 +0900602 return 0;
603}
604
Tejun Heo37b99cb2007-07-16 14:29:39 +0900605static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
606 const struct ata_taskfile *tf,
607 int is_cmd, u32 ctrl,
608 unsigned long timeout_msec)
Tejun Heoca451602005-11-18 14:14:01 +0900609{
Tejun Heo350756f2008-04-07 22:47:21 +0900610 void __iomem *port = sil24_port_base(ap);
Tejun Heoca451602005-11-18 14:14:01 +0900611 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo69ad1852005-11-18 14:16:45 +0900612 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
Tejun Heoca451602005-11-18 14:14:01 +0900613 dma_addr_t paddr = pp->cmd_block_dma;
Tejun Heo37b99cb2007-07-16 14:29:39 +0900614 u32 irq_enabled, irq_mask, irq_stat;
615 int rc;
616
617 prb->ctrl = cpu_to_le16(ctrl);
618 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
619
620 /* temporarily plug completion and error interrupts */
621 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
622 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
623
Catalin Marinas10823452010-06-10 17:02:12 +0100624 /*
625 * The barrier is required to ensure that writes to cmd_block reach
626 * the memory before the write to PORT_CMD_ACTIVATE.
627 */
628 wmb();
Tejun Heo37b99cb2007-07-16 14:29:39 +0900629 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
630 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
631
632 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
Tejun Heo97750ce2010-09-06 17:56:29 +0200633 irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
Tejun Heo37b99cb2007-07-16 14:29:39 +0900634 10, timeout_msec);
635
636 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
637 irq_stat >>= PORT_IRQ_RAW_SHIFT;
638
639 if (irq_stat & PORT_IRQ_COMPLETE)
640 rc = 0;
641 else {
642 /* force port into known state */
643 sil24_init_port(ap);
644
645 if (irq_stat & PORT_IRQ_ERROR)
646 rc = -EIO;
647 else
648 rc = -EBUSY;
649 }
650
651 /* restore IRQ enabled */
652 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
653
654 return rc;
655}
656
Tejun Heo071f44b2008-04-07 22:47:22 +0900657static int sil24_softreset(struct ata_link *link, unsigned int *class,
658 unsigned long deadline)
Tejun Heo37b99cb2007-07-16 14:29:39 +0900659{
Tejun Heocc0680a2007-08-06 18:36:23 +0900660 struct ata_port *ap = link->ap;
Tejun Heo071f44b2008-04-07 22:47:22 +0900661 int pmp = sata_srst_pmp(link);
Tejun Heo37b99cb2007-07-16 14:29:39 +0900662 unsigned long timeout_msec = 0;
Tejun Heoe59f0da2007-07-16 14:29:39 +0900663 struct ata_taskfile tf;
Tejun Heo643be972006-04-11 22:22:29 +0900664 const char *reason;
Tejun Heo37b99cb2007-07-16 14:29:39 +0900665 int rc;
Tejun Heoca451602005-11-18 14:14:01 +0900666
Tejun Heo07b73472006-02-10 23:58:48 +0900667 DPRINTK("ENTER\n");
668
Tejun Heo2555d6c2006-04-11 22:32:19 +0900669 /* put the port into known state */
670 if (sil24_init_port(ap)) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400671 reason = "port not ready";
Tejun Heo2555d6c2006-04-11 22:32:19 +0900672 goto err;
673 }
674
Tejun Heo0eaa6052006-04-11 22:32:19 +0900675 /* do SRST */
Tejun Heo37b99cb2007-07-16 14:29:39 +0900676 if (time_after(deadline, jiffies))
677 timeout_msec = jiffies_to_msecs(deadline - jiffies);
Tejun Heoca451602005-11-18 14:14:01 +0900678
Tejun Heocc0680a2007-08-06 18:36:23 +0900679 ata_tf_init(link->device, &tf); /* doesn't really matter */
Tejun Heo975530e2007-07-16 14:29:39 +0900680 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
681 timeout_msec);
Tejun Heo37b99cb2007-07-16 14:29:39 +0900682 if (rc == -EBUSY) {
683 reason = "timeout";
684 goto err;
685 } else if (rc) {
686 reason = "SRST command error";
Tejun Heo643be972006-04-11 22:22:29 +0900687 goto err;
Tejun Heo07b73472006-02-10 23:58:48 +0900688 }
Tejun Heo10d996a2006-03-11 11:42:34 +0900689
Tejun Heoe59f0da2007-07-16 14:29:39 +0900690 sil24_read_tf(ap, 0, &tf);
691 *class = ata_dev_classify(&tf);
Tejun Heo10d996a2006-03-11 11:42:34 +0900692
Tejun Heo07b73472006-02-10 23:58:48 +0900693 DPRINTK("EXIT, class=%u\n", *class);
Tejun Heoca451602005-11-18 14:14:01 +0900694 return 0;
Tejun Heo643be972006-04-11 22:22:29 +0900695
696 err:
Joe Perchesa9a79df2011-04-15 15:51:59 -0700697 ata_link_err(link, "softreset failed (%s)\n", reason);
Tejun Heo643be972006-04-11 22:22:29 +0900698 return -EIO;
Tejun Heoca451602005-11-18 14:14:01 +0900699}
700
Tejun Heocc0680a2007-08-06 18:36:23 +0900701static int sil24_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900702 unsigned long deadline)
Tejun Heo489ff4c2006-02-10 23:58:48 +0900703{
Tejun Heocc0680a2007-08-06 18:36:23 +0900704 struct ata_port *ap = link->ap;
Tejun Heo350756f2008-04-07 22:47:21 +0900705 void __iomem *port = sil24_port_base(ap);
Tejun Heo23818032007-09-23 13:19:54 +0900706 struct sil24_port_priv *pp = ap->private_data;
707 int did_port_rst = 0;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900708 const char *reason;
Tejun Heoe8e008e2006-05-31 18:27:59 +0900709 int tout_msec, rc;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900710 u32 tmp;
Tejun Heo489ff4c2006-02-10 23:58:48 +0900711
Tejun Heo23818032007-09-23 13:19:54 +0900712 retry:
713 /* Sometimes, DEV_RST is not enough to recover the controller.
714 * This happens often after PM DMA CS errata.
715 */
716 if (pp->do_port_rst) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700717 ata_port_warn(ap,
718 "controller in dubious state, performing PORT_RST\n");
Tejun Heo23818032007-09-23 13:19:54 +0900719
720 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
Tejun Heo97750ce2010-09-06 17:56:29 +0200721 ata_msleep(ap, 10);
Tejun Heo23818032007-09-23 13:19:54 +0900722 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
Tejun Heo97750ce2010-09-06 17:56:29 +0200723 ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
Tejun Heo23818032007-09-23 13:19:54 +0900724 10, 5000);
725
726 /* restore port configuration */
727 sil24_config_port(ap);
728 sil24_config_pmp(ap, ap->nr_pmp_links);
729
730 pp->do_port_rst = 0;
731 did_port_rst = 1;
732 }
733
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900734 /* sil24 does the right thing(tm) without any protection */
Tejun Heocc0680a2007-08-06 18:36:23 +0900735 sata_set_spd(link);
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900736
737 tout_msec = 100;
Tejun Heocc0680a2007-08-06 18:36:23 +0900738 if (ata_link_online(link))
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900739 tout_msec = 5000;
740
741 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
Tejun Heo97750ce2010-09-06 17:56:29 +0200742 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400743 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
744 tout_msec);
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900745
Tejun Heoe8e008e2006-05-31 18:27:59 +0900746 /* SStatus oscillates between zero and valid status after
747 * DEV_RST, debounce it.
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900748 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900749 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
Tejun Heoe8e008e2006-05-31 18:27:59 +0900750 if (rc) {
751 reason = "PHY debouncing failed";
752 goto err;
753 }
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900754
755 if (tmp & PORT_CS_DEV_RST) {
Tejun Heocc0680a2007-08-06 18:36:23 +0900756 if (ata_link_offline(link))
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900757 return 0;
758 reason = "link not ready";
759 goto err;
760 }
761
Tejun Heoe8e008e2006-05-31 18:27:59 +0900762 /* Sil24 doesn't store signature FIS after hardreset, so we
763 * can't wait for BSY to clear. Some devices take a long time
764 * to get ready and those devices will choke if we don't wait
765 * for BSY clearance here. Tell libata to perform follow-up
766 * softreset.
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900767 */
Tejun Heoe8e008e2006-05-31 18:27:59 +0900768 return -EAGAIN;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900769
770 err:
Tejun Heo23818032007-09-23 13:19:54 +0900771 if (!did_port_rst) {
772 pp->do_port_rst = 1;
773 goto retry;
774 }
775
Joe Perchesa9a79df2011-04-15 15:51:59 -0700776 ata_link_err(link, "hardreset failed (%s)\n", reason);
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900777 return -EIO;
Tejun Heo489ff4c2006-02-10 23:58:48 +0900778}
779
Tejun Heoedb33662005-07-28 10:36:22 +0900780static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
Tejun Heo69ad1852005-11-18 14:16:45 +0900781 struct sil24_sge *sge)
Tejun Heoedb33662005-07-28 10:36:22 +0900782{
Jeff Garzik972c26b2005-10-18 22:14:54 -0400783 struct scatterlist *sg;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400784 struct sil24_sge *last_sge = NULL;
Tejun Heoff2aeb12007-12-05 16:43:11 +0900785 unsigned int si;
Tejun Heoedb33662005-07-28 10:36:22 +0900786
Tejun Heoff2aeb12007-12-05 16:43:11 +0900787 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Tejun Heoedb33662005-07-28 10:36:22 +0900788 sge->addr = cpu_to_le64(sg_dma_address(sg));
789 sge->cnt = cpu_to_le32(sg_dma_len(sg));
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400790 sge->flags = 0;
791
792 last_sge = sge;
Jeff Garzik972c26b2005-10-18 22:14:54 -0400793 sge++;
Tejun Heoedb33662005-07-28 10:36:22 +0900794 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400795
Tejun Heoff2aeb12007-12-05 16:43:11 +0900796 last_sge->flags = cpu_to_le32(SGE_TRM);
Tejun Heoedb33662005-07-28 10:36:22 +0900797}
798
Tejun Heo3454dc62007-09-23 13:19:54 +0900799static int sil24_qc_defer(struct ata_queued_cmd *qc)
800{
801 struct ata_link *link = qc->dev->link;
802 struct ata_port *ap = link->ap;
803 u8 prot = qc->tf.protocol;
Tejun Heo3454dc62007-09-23 13:19:54 +0900804
Gwendal Grignou13cc5462008-01-10 15:47:56 +0900805 /*
806 * There is a bug in the chip:
807 * Port LRAM Causes the PRB/SGT Data to be Corrupted
808 * If the host issues a read request for LRAM and SActive registers
809 * while active commands are available in the port, PRB/SGT data in
810 * the LRAM can become corrupted. This issue applies only when
811 * reading from, but not writing to, the LRAM.
812 *
813 * Therefore, reading LRAM when there is no particular error [and
814 * other commands may be outstanding] is prohibited.
815 *
816 * To avoid this bug there are two situations where a command must run
817 * exclusive of any other commands on the port:
818 *
819 * - ATAPI commands which check the sense data
820 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
821 * set.
822 *
823 */
Tejun Heo405e66b2007-11-27 19:28:53 +0900824 int is_excl = (ata_is_atapi(prot) ||
Gwendal Grignou13cc5462008-01-10 15:47:56 +0900825 (qc->flags & ATA_QCFLAG_RESULT_TF));
826
Tejun Heo3454dc62007-09-23 13:19:54 +0900827 if (unlikely(ap->excl_link)) {
828 if (link == ap->excl_link) {
829 if (ap->nr_active_links)
830 return ATA_DEFER_PORT;
831 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
832 } else
833 return ATA_DEFER_PORT;
Gwendal Grignou13cc5462008-01-10 15:47:56 +0900834 } else if (unlikely(is_excl)) {
Tejun Heo3454dc62007-09-23 13:19:54 +0900835 ap->excl_link = link;
836 if (ap->nr_active_links)
837 return ATA_DEFER_PORT;
838 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
839 }
840
841 return ata_std_qc_defer(qc);
842}
843
Tejun Heoedb33662005-07-28 10:36:22 +0900844static void sil24_qc_prep(struct ata_queued_cmd *qc)
845{
846 struct ata_port *ap = qc->ap;
847 struct sil24_port_priv *pp = ap->private_data;
Tejun Heoaee10a02006-05-15 21:03:56 +0900848 union sil24_cmd_block *cb;
Tejun Heo69ad1852005-11-18 14:16:45 +0900849 struct sil24_prb *prb;
850 struct sil24_sge *sge;
Tejun Heobad28a32006-04-11 22:32:19 +0900851 u16 ctrl = 0;
Tejun Heoedb33662005-07-28 10:36:22 +0900852
Tejun Heoaee10a02006-05-15 21:03:56 +0900853 cb = &pp->cmd_block[sil24_tag(qc->tag)];
854
Tejun Heo405e66b2007-11-27 19:28:53 +0900855 if (!ata_is_atapi(qc->tf.protocol)) {
Tejun Heo69ad1852005-11-18 14:16:45 +0900856 prb = &cb->ata.prb;
857 sge = cb->ata.sge;
Robert Hancock4f1a0ee2009-07-30 14:11:29 -0600858 if (ata_is_data(qc->tf.protocol)) {
859 u16 prot = 0;
860 ctrl = PRB_CTRL_PROTOCOL;
861 if (ata_is_ncq(qc->tf.protocol))
862 prot |= PRB_PROT_NCQ;
863 if (qc->tf.flags & ATA_TFLAG_WRITE)
864 prot |= PRB_PROT_WRITE;
865 else
866 prot |= PRB_PROT_READ;
867 prb->prot = cpu_to_le16(prot);
868 }
Tejun Heo405e66b2007-11-27 19:28:53 +0900869 } else {
Tejun Heo69ad1852005-11-18 14:16:45 +0900870 prb = &cb->atapi.prb;
871 sge = cb->atapi.sge;
Dan Carpenter14e45c12010-06-09 14:01:54 +0200872 memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
Tejun Heo6e7846e2006-02-12 23:32:58 +0900873 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
Tejun Heo69ad1852005-11-18 14:16:45 +0900874
Tejun Heo405e66b2007-11-27 19:28:53 +0900875 if (ata_is_data(qc->tf.protocol)) {
Tejun Heo69ad1852005-11-18 14:16:45 +0900876 if (qc->tf.flags & ATA_TFLAG_WRITE)
Tejun Heobad28a32006-04-11 22:32:19 +0900877 ctrl = PRB_CTRL_PACKET_WRITE;
Tejun Heo69ad1852005-11-18 14:16:45 +0900878 else
Tejun Heobad28a32006-04-11 22:32:19 +0900879 ctrl = PRB_CTRL_PACKET_READ;
880 }
Tejun Heoedb33662005-07-28 10:36:22 +0900881 }
882
Tejun Heobad28a32006-04-11 22:32:19 +0900883 prb->ctrl = cpu_to_le16(ctrl);
Tejun Heo3454dc62007-09-23 13:19:54 +0900884 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
Tejun Heoedb33662005-07-28 10:36:22 +0900885
886 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo69ad1852005-11-18 14:16:45 +0900887 sil24_fill_sg(qc, sge);
Tejun Heoedb33662005-07-28 10:36:22 +0900888}
889
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900890static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
Tejun Heoedb33662005-07-28 10:36:22 +0900891{
892 struct ata_port *ap = qc->ap;
893 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo350756f2008-04-07 22:47:21 +0900894 void __iomem *port = sil24_port_base(ap);
Tejun Heoaee10a02006-05-15 21:03:56 +0900895 unsigned int tag = sil24_tag(qc->tag);
896 dma_addr_t paddr;
897 void __iomem *activate;
Tejun Heoedb33662005-07-28 10:36:22 +0900898
Tejun Heoaee10a02006-05-15 21:03:56 +0900899 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
900 activate = port + PORT_CMD_ACTIVATE + tag * 8;
901
Catalin Marinas10823452010-06-10 17:02:12 +0100902 /*
903 * The barrier is required to ensure that writes to cmd_block reach
904 * the memory before the write to PORT_CMD_ACTIVATE.
905 */
906 wmb();
Tejun Heoaee10a02006-05-15 21:03:56 +0900907 writel((u32)paddr, activate);
908 writel((u64)paddr >> 32, activate + 4);
Tejun Heo26ec6342006-04-11 22:32:19 +0900909
Tejun Heoedb33662005-07-28 10:36:22 +0900910 return 0;
911}
912
Tejun Heo79f97da2008-04-07 22:47:20 +0900913static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
914{
915 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
916 return true;
917}
918
Tejun Heo3454dc62007-09-23 13:19:54 +0900919static void sil24_pmp_attach(struct ata_port *ap)
920{
Tejun Heo906c1ff2008-05-19 01:15:13 +0900921 u32 *gscr = ap->link.device->gscr;
922
Tejun Heo3454dc62007-09-23 13:19:54 +0900923 sil24_config_pmp(ap, 1);
924 sil24_init_port(ap);
Tejun Heo906c1ff2008-05-19 01:15:13 +0900925
926 if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
927 sata_pmp_gscr_devid(gscr) == 0x4140) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700928 ata_port_info(ap,
Tejun Heo906c1ff2008-05-19 01:15:13 +0900929 "disabling NCQ support due to sil24-mv4140 quirk\n");
930 ap->flags &= ~ATA_FLAG_NCQ;
931 }
Tejun Heo3454dc62007-09-23 13:19:54 +0900932}
933
934static void sil24_pmp_detach(struct ata_port *ap)
935{
936 sil24_init_port(ap);
937 sil24_config_pmp(ap, 0);
Tejun Heo906c1ff2008-05-19 01:15:13 +0900938
939 ap->flags |= ATA_FLAG_NCQ;
Tejun Heo3454dc62007-09-23 13:19:54 +0900940}
941
Tejun Heo3454dc62007-09-23 13:19:54 +0900942static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
943 unsigned long deadline)
944{
945 int rc;
946
947 rc = sil24_init_port(link->ap);
948 if (rc) {
Joe Perchesa9a79df2011-04-15 15:51:59 -0700949 ata_link_err(link, "hardreset failed (port not ready)\n");
Tejun Heo3454dc62007-09-23 13:19:54 +0900950 return rc;
951 }
952
Tejun Heo5958e302008-04-07 22:47:20 +0900953 return sata_std_hardreset(link, class, deadline);
Tejun Heo3454dc62007-09-23 13:19:54 +0900954}
955
Tejun Heo88ce7552006-05-15 20:58:32 +0900956static void sil24_freeze(struct ata_port *ap)
Tejun Heo7d1ce682005-11-18 14:09:05 +0900957{
Tejun Heo350756f2008-04-07 22:47:21 +0900958 void __iomem *port = sil24_port_base(ap);
Tejun Heo87466182005-08-17 13:08:57 +0900959
Tejun Heo88ce7552006-05-15 20:58:32 +0900960 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
961 * PORT_IRQ_ENABLE instead.
Tejun Heoc0ab4242005-11-18 14:22:03 +0900962 */
Tejun Heo88ce7552006-05-15 20:58:32 +0900963 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
964}
Tejun Heo87466182005-08-17 13:08:57 +0900965
Tejun Heo88ce7552006-05-15 20:58:32 +0900966static void sil24_thaw(struct ata_port *ap)
967{
Tejun Heo350756f2008-04-07 22:47:21 +0900968 void __iomem *port = sil24_port_base(ap);
Tejun Heo88ce7552006-05-15 20:58:32 +0900969 u32 tmp;
970
971 /* clear IRQ */
972 tmp = readl(port + PORT_IRQ_STAT);
973 writel(tmp, port + PORT_IRQ_STAT);
974
975 /* turn IRQ back on */
976 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
977}
978
979static void sil24_error_intr(struct ata_port *ap)
980{
Tejun Heo350756f2008-04-07 22:47:21 +0900981 void __iomem *port = sil24_port_base(ap);
Tejun Heoe59f0da2007-07-16 14:29:39 +0900982 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo3454dc62007-09-23 13:19:54 +0900983 struct ata_queued_cmd *qc = NULL;
984 struct ata_link *link;
985 struct ata_eh_info *ehi;
986 int abort = 0, freeze = 0;
Tejun Heo88ce7552006-05-15 20:58:32 +0900987 u32 irq_stat;
988
989 /* on error, we need to clear IRQ explicitly */
990 irq_stat = readl(port + PORT_IRQ_STAT);
991 writel(irq_stat, port + PORT_IRQ_STAT);
992
993 /* first, analyze and record host port events */
Tejun Heo3454dc62007-09-23 13:19:54 +0900994 link = &ap->link;
995 ehi = &link->eh_info;
Tejun Heo88ce7552006-05-15 20:58:32 +0900996 ata_ehi_clear_desc(ehi);
997
998 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
999
Tejun Heo854c73a2007-09-23 13:14:11 +09001000 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
Tejun Heo854c73a2007-09-23 13:14:11 +09001001 ata_ehi_push_desc(ehi, "SDB notify");
Tejun Heo7d77b242007-09-23 13:14:13 +09001002 sata_async_notification(ap);
Tejun Heo854c73a2007-09-23 13:14:11 +09001003 }
1004
Tejun Heo05429252006-05-31 18:28:20 +09001005 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1006 ata_ehi_hotplugged(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +09001007 ata_ehi_push_desc(ehi, "%s",
1008 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1009 "PHY RDY changed" : "device exchanged");
Tejun Heo88ce7552006-05-15 20:58:32 +09001010 freeze = 1;
Tejun Heo6a575fa2005-10-06 11:43:39 +09001011 }
1012
Tejun Heo88ce7552006-05-15 20:58:32 +09001013 if (irq_stat & PORT_IRQ_UNK_FIS) {
1014 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001015 ehi->action |= ATA_EH_RESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001016 ata_ehi_push_desc(ehi, "unknown FIS");
Tejun Heo88ce7552006-05-15 20:58:32 +09001017 freeze = 1;
Albert Leea22e2eb2005-12-05 15:38:02 +08001018 }
Tejun Heo88ce7552006-05-15 20:58:32 +09001019
1020 /* deal with command error */
1021 if (irq_stat & PORT_IRQ_ERROR) {
Joe Perchesfc8cc1d2011-08-05 19:38:17 -07001022 const struct sil24_cerr_info *ci = NULL;
Tejun Heo88ce7552006-05-15 20:58:32 +09001023 unsigned int err_mask = 0, action = 0;
Tejun Heo3454dc62007-09-23 13:19:54 +09001024 u32 context, cerr;
1025 int pmp;
1026
1027 abort = 1;
1028
1029 /* DMA Context Switch Failure in Port Multiplier Mode
1030 * errata. If we have active commands to 3 or more
1031 * devices, any error condition on active devices can
1032 * corrupt DMA context switching.
1033 */
1034 if (ap->nr_active_links >= 3) {
1035 ehi->err_mask |= AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09001036 ehi->action |= ATA_EH_RESET;
Tejun Heo3454dc62007-09-23 13:19:54 +09001037 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
Tejun Heo23818032007-09-23 13:19:54 +09001038 pp->do_port_rst = 1;
Tejun Heo3454dc62007-09-23 13:19:54 +09001039 freeze = 1;
1040 }
1041
1042 /* find out the offending link and qc */
Tejun Heo071f44b2008-04-07 22:47:22 +09001043 if (sata_pmp_attached(ap)) {
Tejun Heo3454dc62007-09-23 13:19:54 +09001044 context = readl(port + PORT_CONTEXT);
1045 pmp = (context >> 5) & 0xf;
1046
1047 if (pmp < ap->nr_pmp_links) {
1048 link = &ap->pmp_link[pmp];
1049 ehi = &link->eh_info;
1050 qc = ata_qc_from_tag(ap, link->active_tag);
1051
1052 ata_ehi_clear_desc(ehi);
1053 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1054 irq_stat);
1055 } else {
1056 err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001057 action |= ATA_EH_RESET;
Tejun Heo3454dc62007-09-23 13:19:54 +09001058 freeze = 1;
1059 }
1060 } else
1061 qc = ata_qc_from_tag(ap, link->active_tag);
Tejun Heo88ce7552006-05-15 20:58:32 +09001062
1063 /* analyze CMD_ERR */
1064 cerr = readl(port + PORT_CMD_ERR);
1065 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1066 ci = &sil24_cerr_db[cerr];
1067
1068 if (ci && ci->desc) {
1069 err_mask |= ci->err_mask;
1070 action |= ci->action;
Tejun Heocf480622008-01-24 00:05:14 +09001071 if (action & ATA_EH_RESET)
Tejun Heoc2e14f12008-01-13 14:04:16 +09001072 freeze = 1;
Tejun Heob64bbc32007-07-16 14:29:39 +09001073 ata_ehi_push_desc(ehi, "%s", ci->desc);
Tejun Heo88ce7552006-05-15 20:58:32 +09001074 } else {
1075 err_mask |= AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09001076 action |= ATA_EH_RESET;
Tejun Heoc2e14f12008-01-13 14:04:16 +09001077 freeze = 1;
Tejun Heob64bbc32007-07-16 14:29:39 +09001078 ata_ehi_push_desc(ehi, "unknown command error %d",
Tejun Heo88ce7552006-05-15 20:58:32 +09001079 cerr);
1080 }
1081
1082 /* record error info */
Tejun Heo520d06f2008-04-07 22:47:21 +09001083 if (qc)
Tejun Heo88ce7552006-05-15 20:58:32 +09001084 qc->err_mask |= err_mask;
Tejun Heo520d06f2008-04-07 22:47:21 +09001085 else
Tejun Heo88ce7552006-05-15 20:58:32 +09001086 ehi->err_mask |= err_mask;
1087
1088 ehi->action |= action;
Tejun Heo3454dc62007-09-23 13:19:54 +09001089
1090 /* if PMP, resume */
Tejun Heo071f44b2008-04-07 22:47:22 +09001091 if (sata_pmp_attached(ap))
Tejun Heo3454dc62007-09-23 13:19:54 +09001092 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
Tejun Heo88ce7552006-05-15 20:58:32 +09001093 }
1094
1095 /* freeze or abort */
1096 if (freeze)
1097 ata_port_freeze(ap);
Tejun Heo3454dc62007-09-23 13:19:54 +09001098 else if (abort) {
1099 if (qc)
1100 ata_link_abort(qc->dev->link);
1101 else
1102 ata_port_abort(ap);
1103 }
Tejun Heo87466182005-08-17 13:08:57 +09001104}
1105
Tejun Heoedb33662005-07-28 10:36:22 +09001106static inline void sil24_host_intr(struct ata_port *ap)
1107{
Tejun Heo350756f2008-04-07 22:47:21 +09001108 void __iomem *port = sil24_port_base(ap);
Tejun Heoaee10a02006-05-15 21:03:56 +09001109 u32 slot_stat, qc_active;
1110 int rc;
Tejun Heoedb33662005-07-28 10:36:22 +09001111
Tejun Heo228f47b2007-09-23 12:37:05 +09001112 /* If PCIX_IRQ_WOC, there's an inherent race window between
1113 * clearing IRQ pending status and reading PORT_SLOT_STAT
1114 * which may cause spurious interrupts afterwards. This is
1115 * unavoidable and much better than losing interrupts which
1116 * happens if IRQ pending is cleared after reading
1117 * PORT_SLOT_STAT.
1118 */
1119 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1120 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1121
Tejun Heoedb33662005-07-28 10:36:22 +09001122 slot_stat = readl(port + PORT_SLOT_STAT);
Tejun Heo37024e82006-04-11 22:32:19 +09001123
Tejun Heo88ce7552006-05-15 20:58:32 +09001124 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1125 sil24_error_intr(ap);
1126 return;
1127 }
Tejun Heo37024e82006-04-11 22:32:19 +09001128
Tejun Heoaee10a02006-05-15 21:03:56 +09001129 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
Tejun Heo79f97da2008-04-07 22:47:20 +09001130 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heoaee10a02006-05-15 21:03:56 +09001131 if (rc > 0)
1132 return;
1133 if (rc < 0) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001134 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heoaee10a02006-05-15 21:03:56 +09001135 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001136 ehi->action |= ATA_EH_RESET;
Tejun Heoaee10a02006-05-15 21:03:56 +09001137 ata_port_freeze(ap);
Tejun Heo88ce7552006-05-15 20:58:32 +09001138 return;
1139 }
1140
Tejun Heo228f47b2007-09-23 12:37:05 +09001141 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1142 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
Joe Perchesa9a79df2011-04-15 15:51:59 -07001143 ata_port_info(ap,
1144 "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001145 slot_stat, ap->link.active_tag, ap->link.sactive);
Tejun Heoedb33662005-07-28 10:36:22 +09001146}
1147
David Howells7d12e782006-10-05 14:55:46 +01001148static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
Tejun Heoedb33662005-07-28 10:36:22 +09001149{
Jeff Garzikcca39742006-08-24 03:19:22 -04001150 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001151 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
Tejun Heoedb33662005-07-28 10:36:22 +09001152 unsigned handled = 0;
1153 u32 status;
1154 int i;
1155
Tejun Heo0d5ff562007-02-01 15:06:36 +09001156 status = readl(host_base + HOST_IRQ_STAT);
Tejun Heoedb33662005-07-28 10:36:22 +09001157
Tejun Heo06460ae2005-08-17 13:08:52 +09001158 if (status == 0xffffffff) {
1159 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1160 "PCI fault or device removal?\n");
1161 goto out;
1162 }
1163
Tejun Heoedb33662005-07-28 10:36:22 +09001164 if (!(status & IRQ_STAT_4PORTS))
1165 goto out;
1166
Jeff Garzikcca39742006-08-24 03:19:22 -04001167 spin_lock(&host->lock);
Tejun Heoedb33662005-07-28 10:36:22 +09001168
Jeff Garzikcca39742006-08-24 03:19:22 -04001169 for (i = 0; i < host->n_ports; i++)
Tejun Heoedb33662005-07-28 10:36:22 +09001170 if (status & (1 << i)) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001171 sil24_host_intr(host->ports[i]);
1172 handled++;
Tejun Heoedb33662005-07-28 10:36:22 +09001173 }
1174
Jeff Garzikcca39742006-08-24 03:19:22 -04001175 spin_unlock(&host->lock);
Tejun Heoedb33662005-07-28 10:36:22 +09001176 out:
1177 return IRQ_RETVAL(handled);
1178}
1179
Tejun Heo88ce7552006-05-15 20:58:32 +09001180static void sil24_error_handler(struct ata_port *ap)
1181{
Tejun Heo23818032007-09-23 13:19:54 +09001182 struct sil24_port_priv *pp = ap->private_data;
1183
Tejun Heo3454dc62007-09-23 13:19:54 +09001184 if (sil24_init_port(ap))
Tejun Heo88ce7552006-05-15 20:58:32 +09001185 ata_eh_freeze_port(ap);
Tejun Heo88ce7552006-05-15 20:58:32 +09001186
Tejun Heoa1efdab2008-03-25 12:22:50 +09001187 sata_pmp_error_handler(ap);
Tejun Heo23818032007-09-23 13:19:54 +09001188
1189 pp->do_port_rst = 0;
Tejun Heo88ce7552006-05-15 20:58:32 +09001190}
1191
1192static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1193{
1194 struct ata_port *ap = qc->ap;
1195
Tejun Heo88ce7552006-05-15 20:58:32 +09001196 /* make DMA engine forget about the failed command */
Tejun Heo3454dc62007-09-23 13:19:54 +09001197 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1198 ata_eh_freeze_port(ap);
Tejun Heo88ce7552006-05-15 20:58:32 +09001199}
1200
Tejun Heoedb33662005-07-28 10:36:22 +09001201static int sil24_port_start(struct ata_port *ap)
1202{
Jeff Garzikcca39742006-08-24 03:19:22 -04001203 struct device *dev = ap->host->dev;
Tejun Heoedb33662005-07-28 10:36:22 +09001204 struct sil24_port_priv *pp;
Tejun Heo69ad1852005-11-18 14:16:45 +09001205 union sil24_cmd_block *cb;
Tejun Heoaee10a02006-05-15 21:03:56 +09001206 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
Tejun Heoedb33662005-07-28 10:36:22 +09001207 dma_addr_t cb_dma;
1208
Tejun Heo24dc5f32007-01-20 16:00:28 +09001209 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heoedb33662005-07-28 10:36:22 +09001210 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001211 return -ENOMEM;
Tejun Heoedb33662005-07-28 10:36:22 +09001212
Tejun Heo24dc5f32007-01-20 16:00:28 +09001213 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -05001214 if (!cb)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001215 return -ENOMEM;
Tejun Heoedb33662005-07-28 10:36:22 +09001216 memset(cb, 0, cb_size);
1217
Tejun Heoedb33662005-07-28 10:36:22 +09001218 pp->cmd_block = cb;
1219 pp->cmd_block_dma = cb_dma;
1220
1221 ap->private_data = pp;
1222
Tejun Heo350756f2008-04-07 22:47:21 +09001223 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1224 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1225
Tejun Heoedb33662005-07-28 10:36:22 +09001226 return 0;
Tejun Heoedb33662005-07-28 10:36:22 +09001227}
1228
Tejun Heo4447d352007-04-17 23:44:08 +09001229static void sil24_init_controller(struct ata_host *host)
Tejun Heo2a41a612006-07-03 16:07:27 +09001230{
Tejun Heo4447d352007-04-17 23:44:08 +09001231 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
Tejun Heo2a41a612006-07-03 16:07:27 +09001232 u32 tmp;
1233 int i;
1234
1235 /* GPIO off */
1236 writel(0, host_base + HOST_FLASH_CMD);
1237
1238 /* clear global reset & mask interrupts during initialization */
1239 writel(0, host_base + HOST_CTRL);
1240
1241 /* init ports */
Tejun Heo4447d352007-04-17 23:44:08 +09001242 for (i = 0; i < host->n_ports; i++) {
Tejun Heo23818032007-09-23 13:19:54 +09001243 struct ata_port *ap = host->ports[i];
Tejun Heo350756f2008-04-07 22:47:21 +09001244 void __iomem *port = sil24_port_base(ap);
1245
Tejun Heo2a41a612006-07-03 16:07:27 +09001246
1247 /* Initial PHY setting */
1248 writel(0x20c, port + PORT_PHY_CFG);
1249
1250 /* Clear port RST */
1251 tmp = readl(port + PORT_CTRL_STAT);
1252 if (tmp & PORT_CS_PORT_RST) {
1253 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
Tejun Heo97750ce2010-09-06 17:56:29 +02001254 tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
Tejun Heo2a41a612006-07-03 16:07:27 +09001255 PORT_CS_PORT_RST,
1256 PORT_CS_PORT_RST, 10, 100);
1257 if (tmp & PORT_CS_PORT_RST)
Joe Perchesa44fec12011-04-15 15:51:58 -07001258 dev_err(host->dev,
1259 "failed to clear port RST\n");
Tejun Heo2a41a612006-07-03 16:07:27 +09001260 }
1261
Tejun Heo23818032007-09-23 13:19:54 +09001262 /* configure port */
1263 sil24_config_port(ap);
Tejun Heo2a41a612006-07-03 16:07:27 +09001264 }
1265
1266 /* Turn on interrupts */
1267 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1268}
1269
Tejun Heoedb33662005-07-28 10:36:22 +09001270static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1271{
Tejun Heo93e26182007-11-22 18:46:57 +09001272 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
Tejun Heo4447d352007-04-17 23:44:08 +09001273 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1274 const struct ata_port_info *ppi[] = { &pi, NULL };
1275 void __iomem * const *iomap;
1276 struct ata_host *host;
Tejun Heo350756f2008-04-07 22:47:21 +09001277 int rc;
Tejun Heo37024e82006-04-11 22:32:19 +09001278 u32 tmp;
Tejun Heoedb33662005-07-28 10:36:22 +09001279
Tejun Heo93e26182007-11-22 18:46:57 +09001280 /* cause link error if sil24_cmd_block is sized wrongly */
1281 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1282 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1283
Joe Perches06296a12011-04-15 15:52:00 -07001284 ata_print_version_once(&pdev->dev, DRV_VERSION);
Tejun Heoedb33662005-07-28 10:36:22 +09001285
Tejun Heo4447d352007-04-17 23:44:08 +09001286 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001287 rc = pcim_enable_device(pdev);
Tejun Heoedb33662005-07-28 10:36:22 +09001288 if (rc)
1289 return rc;
1290
Tejun Heo0d5ff562007-02-01 15:06:36 +09001291 rc = pcim_iomap_regions(pdev,
1292 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1293 DRV_NAME);
Tejun Heoedb33662005-07-28 10:36:22 +09001294 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001295 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09001296 iomap = pcim_iomap_table(pdev);
Tejun Heoedb33662005-07-28 10:36:22 +09001297
Tejun Heo4447d352007-04-17 23:44:08 +09001298 /* apply workaround for completion IRQ loss on PCI-X errata */
1299 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1300 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1301 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
Joe Perchesa44fec12011-04-15 15:51:58 -07001302 dev_info(&pdev->dev,
1303 "Applying completion IRQ loss on PCI-X errata fix\n");
Tejun Heo4447d352007-04-17 23:44:08 +09001304 else
1305 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1306 }
1307
1308 /* allocate and fill host */
1309 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1310 SIL24_FLAG2NPORTS(ppi[0]->flags));
1311 if (!host)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001312 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001313 host->iomap = iomap;
Tejun Heoedb33662005-07-28 10:36:22 +09001314
Tejun Heo4447d352007-04-17 23:44:08 +09001315 /* configure and activate the device */
Yang Hongyang6a355282009-04-06 19:01:13 -07001316 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1317 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Tejun Heo26ec6342006-04-11 22:32:19 +09001318 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07001319 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Tejun Heo26ec6342006-04-11 22:32:19 +09001320 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001321 dev_err(&pdev->dev,
1322 "64-bit DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001323 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001324 }
1325 }
1326 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07001327 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Tejun Heo26ec6342006-04-11 22:32:19 +09001328 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001329 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001330 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001331 }
Yang Hongyang284901a2009-04-06 19:01:15 -07001332 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Tejun Heo26ec6342006-04-11 22:32:19 +09001333 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001334 dev_err(&pdev->dev,
1335 "32-bit consistent DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001336 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001337 }
Tejun Heoedb33662005-07-28 10:36:22 +09001338 }
1339
Tejun Heoe8b3b5e2008-10-25 14:26:54 +09001340 /* Set max read request size to 4096. This slightly increases
1341 * write throughput for pci-e variants.
1342 */
1343 pcie_set_readrq(pdev, 4096);
1344
Tejun Heo4447d352007-04-17 23:44:08 +09001345 sil24_init_controller(host);
Tejun Heoedb33662005-07-28 10:36:22 +09001346
Vivek Mahajandae77212009-11-16 11:49:22 +05301347 if (sata_sil24_msi && !pci_enable_msi(pdev)) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001348 dev_info(&pdev->dev, "Using MSI\n");
Vivek Mahajandae77212009-11-16 11:49:22 +05301349 pci_intx(pdev, 0);
1350 }
1351
Tejun Heoedb33662005-07-28 10:36:22 +09001352 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09001353 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1354 &sil24_sht);
Tejun Heoedb33662005-07-28 10:36:22 +09001355}
1356
Alexey Dobriyan281d4262006-08-14 22:49:30 -07001357#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +09001358static int sil24_pci_device_resume(struct pci_dev *pdev)
1359{
Jeff Garzikcca39742006-08-24 03:19:22 -04001360 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001361 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
Tejun Heo553c4aa2006-12-26 19:39:50 +09001362 int rc;
Tejun Heod2298dc2006-07-03 16:07:27 +09001363
Tejun Heo553c4aa2006-12-26 19:39:50 +09001364 rc = ata_pci_device_do_resume(pdev);
1365 if (rc)
1366 return rc;
Tejun Heod2298dc2006-07-03 16:07:27 +09001367
1368 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
Tejun Heo0d5ff562007-02-01 15:06:36 +09001369 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
Tejun Heod2298dc2006-07-03 16:07:27 +09001370
Tejun Heo4447d352007-04-17 23:44:08 +09001371 sil24_init_controller(host);
Tejun Heod2298dc2006-07-03 16:07:27 +09001372
Jeff Garzikcca39742006-08-24 03:19:22 -04001373 ata_host_resume(host);
Tejun Heod2298dc2006-07-03 16:07:27 +09001374
1375 return 0;
1376}
Tejun Heo3454dc62007-09-23 13:19:54 +09001377
1378static int sil24_port_resume(struct ata_port *ap)
1379{
1380 sil24_config_pmp(ap, ap->nr_pmp_links);
1381 return 0;
1382}
Alexey Dobriyan281d4262006-08-14 22:49:30 -07001383#endif
Tejun Heod2298dc2006-07-03 16:07:27 +09001384
Tejun Heoedb33662005-07-28 10:36:22 +09001385static int __init sil24_init(void)
1386{
Pavel Roskinb7887192006-08-10 18:13:18 +09001387 return pci_register_driver(&sil24_pci_driver);
Tejun Heoedb33662005-07-28 10:36:22 +09001388}
1389
1390static void __exit sil24_exit(void)
1391{
1392 pci_unregister_driver(&sil24_pci_driver);
1393}
1394
1395MODULE_AUTHOR("Tejun Heo");
1396MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1397MODULE_LICENSE("GPL");
1398MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1399
1400module_init(sil24_init);
1401module_exit(sil24_exit);