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SAN People73a59c12006-01-09 17:05:41 +00001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * linux/arch/arm/mach-at91/at91rm9200_time.c
SAN People73a59c12006-01-09 17:05:41 +00003 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
David Brownell5e802df2007-07-31 01:41:26 +010022#include <linux/kernel.h>
SAN People73a59c12006-01-09 17:05:41 +000023#include <linux/interrupt.h>
Thomas Gleixner07d265d2006-07-01 23:01:50 +010024#include <linux/irq.h>
David Brownell5e802df2007-07-31 01:41:26 +010025#include <linux/clockchips.h>
SAN People73a59c12006-01-09 17:05:41 +000026
SAN People73a59c12006-01-09 17:05:41 +000027#include <asm/mach/time.h>
28
Russell Kinga09e64f2008-08-05 16:14:15 +010029#include <mach/at91_st.h>
Andrew Victor55d8bae2006-11-30 17:16:43 +010030
Andrew Victor963151f2006-06-19 15:23:41 +010031static unsigned long last_crtr;
David Brownell5e802df2007-07-31 01:41:26 +010032static u32 irqmask;
33static struct clock_event_device clkevt;
Andrew Victor963151f2006-06-19 15:23:41 +010034
SAN People73a59c12006-01-09 17:05:41 +000035/*
David Brownell5e802df2007-07-31 01:41:26 +010036 * The ST_CRTR is updated asynchronously to the master clock ... but
37 * the updates as seen by the CPU don't seem to be strictly monotonic.
38 * Waiting until we read the same value twice avoids glitching.
SAN People73a59c12006-01-09 17:05:41 +000039 */
David Brownell5e802df2007-07-31 01:41:26 +010040static inline unsigned long read_CRTR(void)
41{
SAN People73a59c12006-01-09 17:05:41 +000042 unsigned long x1, x2;
43
David Brownell5e802df2007-07-31 01:41:26 +010044 x1 = at91_sys_read(AT91_ST_CRTR);
SAN People73a59c12006-01-09 17:05:41 +000045 do {
SAN People73a59c12006-01-09 17:05:41 +000046 x2 = at91_sys_read(AT91_ST_CRTR);
David Brownell5e802df2007-07-31 01:41:26 +010047 if (x1 == x2)
48 break;
49 x1 = x2;
50 } while (1);
SAN People73a59c12006-01-09 17:05:41 +000051 return x1;
52}
53
54/*
SAN People73a59c12006-01-09 17:05:41 +000055 * IRQ handler for the timer.
56 */
Linus Torvalds0cd61b62006-10-06 10:53:39 -070057static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
SAN People73a59c12006-01-09 17:05:41 +000058{
David Brownell5e802df2007-07-31 01:41:26 +010059 u32 sr = at91_sys_read(AT91_ST_SR) & irqmask;
SAN People73a59c12006-01-09 17:05:41 +000060
David Brownell5e802df2007-07-31 01:41:26 +010061 /* simulate "oneshot" timer with alarm */
62 if (sr & AT91_ST_ALMS) {
63 clkevt.event_handler(&clkevt);
SAN People73a59c12006-01-09 17:05:41 +000064 return IRQ_HANDLED;
65 }
David Brownell5e802df2007-07-31 01:41:26 +010066
67 /* periodic mode should handle delayed ticks */
68 if (sr & AT91_ST_PITS) {
69 u32 crtr = read_CRTR();
70
71 while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
72 last_crtr += LATCH;
73 clkevt.event_handler(&clkevt);
74 }
75 return IRQ_HANDLED;
76 }
77
78 /* this irq is shared ... */
79 return IRQ_NONE;
SAN People73a59c12006-01-09 17:05:41 +000080}
81
82static struct irqaction at91rm9200_timer_irq = {
83 .name = "at91_tick",
Bernhard Walleb30faba2007-05-08 00:35:39 -070084 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
SAN People73a59c12006-01-09 17:05:41 +000085 .handler = at91rm9200_timer_interrupt
86};
87
David Brownell5e802df2007-07-31 01:41:26 +010088static cycle_t read_clk32k(void)
Andrew Victor2a6f9902006-06-19 15:26:50 +010089{
David Brownell5e802df2007-07-31 01:41:26 +010090 return read_CRTR();
Andrew Victor2a6f9902006-06-19 15:26:50 +010091}
92
David Brownell5e802df2007-07-31 01:41:26 +010093static struct clocksource clk32k = {
94 .name = "32k_counter",
95 .rating = 150,
96 .read = read_clk32k,
97 .mask = CLOCKSOURCE_MASK(20),
98 .shift = 10,
99 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
100};
101
102static void
103clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
104{
105 /* Disable and flush pending timer interrupts */
106 at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
107 (void) at91_sys_read(AT91_ST_SR);
108
109 last_crtr = read_CRTR();
110 switch (mode) {
111 case CLOCK_EVT_MODE_PERIODIC:
112 /* PIT for periodic irqs; fixed rate of 1/HZ */
113 irqmask = AT91_ST_PITS;
114 at91_sys_write(AT91_ST_PIMR, LATCH);
115 break;
116 case CLOCK_EVT_MODE_ONESHOT:
117 /* ALM for oneshot irqs, set by next_event()
118 * before 32 seconds have passed
119 */
120 irqmask = AT91_ST_ALMS;
121 at91_sys_write(AT91_ST_RTAR, last_crtr);
122 break;
123 case CLOCK_EVT_MODE_SHUTDOWN:
124 case CLOCK_EVT_MODE_UNUSED:
125 case CLOCK_EVT_MODE_RESUME:
126 irqmask = 0;
127 break;
128 }
129 at91_sys_write(AT91_ST_IER, irqmask);
130}
131
132static int
133clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
134{
135 unsigned long flags;
136 u32 alm;
137 int status = 0;
138
139 BUG_ON(delta < 2);
140
141 /* Use "raw" primitives so we behave correctly on RT kernels. */
142 raw_local_irq_save(flags);
143
Uwe Kleine-Königc4edfce2008-11-20 11:58:36 +0100144 /*
145 * According to Thomas Gleixner irqs are already disabled here. Simply
146 * removing raw_local_irq_save above (and the matching
147 * raw_local_irq_restore) was not accepted. See
148 * http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174
149 * So for now (2008-11-20) just warn once if irqs were not disabled ...
150 */
151 WARN_ON_ONCE(!raw_irqs_disabled_flags(flags));
152
David Brownell5e802df2007-07-31 01:41:26 +0100153 /* The alarm IRQ uses absolute time (now+delta), not the relative
154 * time (delta) in our calling convention. Like all clockevents
155 * using such "match" hardware, we have a race to defend against.
156 *
157 * Our defense here is to have set up the clockevent device so the
158 * delta is at least two. That way we never end up writing RTAR
159 * with the value then held in CRTR ... which would mean the match
160 * wouldn't trigger until 32 seconds later, after CRTR wraps.
161 */
162 alm = read_CRTR();
163
164 /* Cancel any pending alarm; flush any pending IRQ */
165 at91_sys_write(AT91_ST_RTAR, alm);
166 (void) at91_sys_read(AT91_ST_SR);
167
168 /* Schedule alarm by writing RTAR. */
169 alm += delta;
170 at91_sys_write(AT91_ST_RTAR, alm);
171
172 raw_local_irq_restore(flags);
173 return status;
174}
175
176static struct clock_event_device clkevt = {
177 .name = "at91_tick",
178 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
179 .shift = 32,
180 .rating = 150,
David Brownell5e802df2007-07-31 01:41:26 +0100181 .set_next_event = clkevt32k_next_event,
182 .set_mode = clkevt32k_mode,
183};
184
SAN People73a59c12006-01-09 17:05:41 +0000185/*
David Brownell5e802df2007-07-31 01:41:26 +0100186 * ST (system timer) module supports both clockevents and clocksource.
SAN People73a59c12006-01-09 17:05:41 +0000187 */
188void __init at91rm9200_timer_init(void)
189{
David Brownell5e802df2007-07-31 01:41:26 +0100190 /* Disable all timer interrupts, and clear any pending ones */
191 at91_sys_write(AT91_ST_IDR,
192 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
193 (void) at91_sys_read(AT91_ST_SR);
SAN People73a59c12006-01-09 17:05:41 +0000194
Andrew Victor2a6f9902006-06-19 15:26:50 +0100195 /* Make IRQs happen for the system timer */
SAN People73a59c12006-01-09 17:05:41 +0000196 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
197
David Brownell5e802df2007-07-31 01:41:26 +0100198 /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
199 * directly for the clocksource and all clockevents, after adjusting
200 * its prescaler from the 1 Hz default.
201 */
202 at91_sys_write(AT91_ST_RTMR, 1);
SAN People73a59c12006-01-09 17:05:41 +0000203
David Brownell5e802df2007-07-31 01:41:26 +0100204 /* Setup timer clockevent, with minimum of two ticks (important!!) */
205 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
206 clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
207 clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
Rusty Russell320ab2b2008-12-13 21:20:26 +1030208 clkevt.cpumask = cpumask_of(0);
David Brownell5e802df2007-07-31 01:41:26 +0100209 clockevents_register_device(&clkevt);
SAN People73a59c12006-01-09 17:05:41 +0000210
David Brownell5e802df2007-07-31 01:41:26 +0100211 /* register clocksource */
212 clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
213 clocksource_register(&clk32k);
Andrew Victor2a6f9902006-06-19 15:26:50 +0100214}
Andrew Victor2a6f9902006-06-19 15:26:50 +0100215
SAN People73a59c12006-01-09 17:05:41 +0000216struct sys_timer at91rm9200_timer = {
217 .init = at91rm9200_timer_init,
SAN People73a59c12006-01-09 17:05:41 +0000218};
Andrew Victor2a6f9902006-06-19 15:26:50 +0100219