blob: 6ae31fcfb6295c2585ae7fc206023a70bc3dda52 [file] [log] [blame]
Auke Kokbc7f75f2007-09-17 12:30:59 -07001/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allan0d6057e2011-01-04 01:16:44 +00004 Copyright(c) 1999 - 2011 Intel Corporation.
Auke Kokbc7f75f2007-09-17 12:30:59 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/delay.h>
30
31#include "e1000.h"
32
33static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36static s32 e1000_wait_autoneg(struct e1000_hw *hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -070037static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
Bruce Allana4f58f52009-06-02 11:29:18 +000040static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
Auke Kokbc7f75f2007-09-17 12:30:59 -070043
44/* Cable length tables */
Bruce Allan64806412010-12-11 05:53:42 +000045static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
Bruce Allaneb656d42009-12-01 15:47:02 +000047#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
Auke Kokbc7f75f2007-09-17 12:30:59 -070049
Bruce Allan64806412010-12-11 05:53:42 +000050static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58 124};
Auke Kokbc7f75f2007-09-17 12:30:59 -070059#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
Alejandro Martinez Ruizc00acf42007-10-18 10:16:33 +020060 ARRAY_SIZE(e1000_igp_2_cable_length_table)
Auke Kokbc7f75f2007-09-17 12:30:59 -070061
Bruce Allana4f58f52009-06-02 11:29:18 +000062#define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64#define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
68
69#define HV_INTC_FC_PAGE_START 768
70#define I82578_ADDR_REG 29
71#define I82577_ADDR_REG 16
72#define I82577_CFG_REG 22
73#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75#define I82577_CTRL_REG 23
Bruce Allana4f58f52009-06-02 11:29:18 +000076
77/* 82577 specific PHY registers */
78#define I82577_PHY_CTRL_2 18
79#define I82577_PHY_STATUS_2 26
80#define I82577_PHY_DIAG_STATUS 31
81
82/* I82577 PHY Status 2 */
83#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84#define I82577_PHY_STATUS2_MDIX 0x0800
85#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
87
88/* I82577 PHY Control 2 */
89#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
91
92/* I82577 PHY Diagnostics Status */
93#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95
96/* BM PHY Copper Specific Control 1 */
97#define BM_CS_CTRL1 16
98
Bruce Allana4f58f52009-06-02 11:29:18 +000099#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
102
Auke Kokbc7f75f2007-09-17 12:30:59 -0700103/**
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
106 *
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
110 **/
111s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
112{
113 u32 manc;
114
115 manc = er32(MANC);
116
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
119}
120
121/**
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
124 *
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
127 **/
128s32 e1000e_get_phy_id(struct e1000_hw *hw)
129{
130 struct e1000_phy_info *phy = &hw->phy;
Bruce Allana4f58f52009-06-02 11:29:18 +0000131 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700132 u16 phy_id;
Bruce Allana4f58f52009-06-02 11:29:18 +0000133 u16 retry_count = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700134
Bruce Allan94d81862009-11-20 23:25:26 +0000135 if (!(phy->ops.read_reg))
Bruce Allana4f58f52009-06-02 11:29:18 +0000136 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700137
Bruce Allana4f58f52009-06-02 11:29:18 +0000138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
140 if (ret_val)
141 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700142
Bruce Allana4f58f52009-06-02 11:29:18 +0000143 phy->id = (u32)(phy_id << 16);
144 udelay(20);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
146 if (ret_val)
147 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700148
Bruce Allana4f58f52009-06-02 11:29:18 +0000149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
151
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
153 goto out;
154
Bruce Allana4f58f52009-06-02 11:29:18 +0000155 retry_count++;
156 }
157out:
Bruce Allana4f58f52009-06-02 11:29:18 +0000158 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700159}
160
161/**
162 * e1000e_phy_reset_dsp - Reset PHY DSP
163 * @hw: pointer to the HW structure
164 *
165 * Reset the digital signal processor.
166 **/
167s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
168{
169 s32 ret_val;
170
171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
172 if (ret_val)
173 return ret_val;
174
175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
176}
177
178/**
David Graham2d9498f2008-04-23 11:09:14 -0700179 * e1000e_read_phy_reg_mdic - Read MDI control register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700180 * @hw: pointer to the HW structure
181 * @offset: register offset to be read
182 * @data: pointer to the read data
183 *
Auke Kok489815c2008-02-21 15:11:07 -0800184 * Reads the MDI control register in the PHY at offset and stores the
Auke Kokbc7f75f2007-09-17 12:30:59 -0700185 * information read to data.
186 **/
David Graham2d9498f2008-04-23 11:09:14 -0700187s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700188{
189 struct e1000_phy_info *phy = &hw->phy;
190 u32 i, mdic = 0;
191
192 if (offset > MAX_PHY_REG_ADDRESS) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000193 e_dbg("PHY Address %d is out of range\n", offset);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700194 return -E1000_ERR_PARAM;
195 }
196
Bruce Allanad680762008-03-28 09:15:03 -0700197 /*
198 * Set up Op-code, Phy Address, and register offset in the MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -0700199 * Control register. The MAC will take care of interfacing with the
200 * PHY to retrieve the desired data.
201 */
202 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_READ));
205
206 ew32(MDIC, mdic);
207
Bruce Allanad680762008-03-28 09:15:03 -0700208 /*
209 * Poll the ready bit to see if the MDI read completed
210 * Increasing the time out as testing showed failures with
211 * the lower time out
212 */
David Graham2d9498f2008-04-23 11:09:14 -0700213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700214 udelay(50);
215 mdic = er32(MDIC);
216 if (mdic & E1000_MDIC_READY)
217 break;
218 }
219 if (!(mdic & E1000_MDIC_READY)) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000220 e_dbg("MDI Read did not complete\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700221 return -E1000_ERR_PHY;
222 }
223 if (mdic & E1000_MDIC_ERROR) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000224 e_dbg("MDI Error\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700225 return -E1000_ERR_PHY;
226 }
227 *data = (u16) mdic;
228
Bruce Allan664dc872010-11-24 06:01:46 +0000229 /*
230 * Allow some time after each MDIC transaction to avoid
231 * reading duplicate data in the next MDIC transaction.
232 */
233 if (hw->mac.type == e1000_pch2lan)
234 udelay(100);
235
Auke Kokbc7f75f2007-09-17 12:30:59 -0700236 return 0;
237}
238
239/**
David Graham2d9498f2008-04-23 11:09:14 -0700240 * e1000e_write_phy_reg_mdic - Write MDI control register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700241 * @hw: pointer to the HW structure
242 * @offset: register offset to write to
243 * @data: data to write to register at offset
244 *
245 * Writes data to MDI control register in the PHY at offset.
246 **/
David Graham2d9498f2008-04-23 11:09:14 -0700247s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700248{
249 struct e1000_phy_info *phy = &hw->phy;
250 u32 i, mdic = 0;
251
252 if (offset > MAX_PHY_REG_ADDRESS) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000253 e_dbg("PHY Address %d is out of range\n", offset);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700254 return -E1000_ERR_PARAM;
255 }
256
Bruce Allanad680762008-03-28 09:15:03 -0700257 /*
258 * Set up Op-code, Phy Address, and register offset in the MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -0700259 * Control register. The MAC will take care of interfacing with the
260 * PHY to retrieve the desired data.
261 */
262 mdic = (((u32)data) |
263 (offset << E1000_MDIC_REG_SHIFT) |
264 (phy->addr << E1000_MDIC_PHY_SHIFT) |
265 (E1000_MDIC_OP_WRITE));
266
267 ew32(MDIC, mdic);
268
David Graham2d9498f2008-04-23 11:09:14 -0700269 /*
270 * Poll the ready bit to see if the MDI read completed
271 * Increasing the time out as testing showed failures with
272 * the lower time out
273 */
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
275 udelay(50);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700276 mdic = er32(MDIC);
277 if (mdic & E1000_MDIC_READY)
278 break;
279 }
280 if (!(mdic & E1000_MDIC_READY)) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000281 e_dbg("MDI Write did not complete\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700282 return -E1000_ERR_PHY;
283 }
David Graham2d9498f2008-04-23 11:09:14 -0700284 if (mdic & E1000_MDIC_ERROR) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000285 e_dbg("MDI Error\n");
David Graham2d9498f2008-04-23 11:09:14 -0700286 return -E1000_ERR_PHY;
287 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700288
Bruce Allan664dc872010-11-24 06:01:46 +0000289 /*
290 * Allow some time after each MDIC transaction to avoid
291 * reading duplicate data in the next MDIC transaction.
292 */
293 if (hw->mac.type == e1000_pch2lan)
294 udelay(100);
295
Auke Kokbc7f75f2007-09-17 12:30:59 -0700296 return 0;
297}
298
299/**
300 * e1000e_read_phy_reg_m88 - Read m88 PHY register
301 * @hw: pointer to the HW structure
302 * @offset: register offset to be read
303 * @data: pointer to the read data
304 *
305 * Acquires semaphore, if necessary, then reads the PHY register at offset
306 * and storing the retrieved information in data. Release any acquired
307 * semaphores before exiting.
308 **/
309s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
310{
311 s32 ret_val;
312
Bruce Allan94d81862009-11-20 23:25:26 +0000313 ret_val = hw->phy.ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700314 if (ret_val)
315 return ret_val;
316
David Graham2d9498f2008-04-23 11:09:14 -0700317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
318 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700319
Bruce Allan94d81862009-11-20 23:25:26 +0000320 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700321
322 return ret_val;
323}
324
325/**
326 * e1000e_write_phy_reg_m88 - Write m88 PHY register
327 * @hw: pointer to the HW structure
328 * @offset: register offset to write to
329 * @data: data to write at register offset
330 *
331 * Acquires semaphore, if necessary, then writes the data to PHY register
332 * at the offset. Release any acquired semaphores before exiting.
333 **/
334s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
335{
336 s32 ret_val;
337
Bruce Allan94d81862009-11-20 23:25:26 +0000338 ret_val = hw->phy.ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700339 if (ret_val)
340 return ret_val;
341
David Graham2d9498f2008-04-23 11:09:14 -0700342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
343 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700344
Bruce Allan94d81862009-11-20 23:25:26 +0000345 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700346
347 return ret_val;
348}
349
350/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000351 * __e1000e_read_phy_reg_igp - Read igp PHY register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700352 * @hw: pointer to the HW structure
353 * @offset: register offset to be read
354 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000355 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700356 *
357 * Acquires semaphore, if necessary, then reads the PHY register at offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000358 * and stores the retrieved information in data. Release any acquired
Auke Kokbc7f75f2007-09-17 12:30:59 -0700359 * semaphores before exiting.
360 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000361static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
362 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700363{
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000364 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700365
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000366 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +0000367 if (!(hw->phy.ops.acquire))
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000368 goto out;
369
Bruce Allan94d81862009-11-20 23:25:26 +0000370 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000371 if (ret_val)
372 goto out;
373 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700374
375 if (offset > MAX_PHY_MULTI_PAGE_REG) {
David Graham2d9498f2008-04-23 11:09:14 -0700376 ret_val = e1000e_write_phy_reg_mdic(hw,
377 IGP01E1000_PHY_PAGE_SELECT,
378 (u16)offset);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000379 if (ret_val)
380 goto release;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700381 }
382
David Graham2d9498f2008-04-23 11:09:14 -0700383 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000384 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700385
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000386release:
387 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000388 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000389out:
390 return ret_val;
391}
Auke Kokbc7f75f2007-09-17 12:30:59 -0700392
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000393/**
394 * e1000e_read_phy_reg_igp - Read igp PHY register
395 * @hw: pointer to the HW structure
396 * @offset: register offset to be read
397 * @data: pointer to the read data
398 *
399 * Acquires semaphore then reads the PHY register at offset and stores the
400 * retrieved information in data.
401 * Release the acquired semaphore before exiting.
402 **/
403s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
404{
405 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
406}
407
408/**
409 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
410 * @hw: pointer to the HW structure
411 * @offset: register offset to be read
412 * @data: pointer to the read data
413 *
414 * Reads the PHY register at offset and stores the retrieved information
415 * in data. Assumes semaphore already acquired.
416 **/
417s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
418{
419 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
420}
421
422/**
423 * e1000e_write_phy_reg_igp - Write igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
427 * @locked: semaphore has already been acquired or not
428 *
429 * Acquires semaphore, if necessary, then writes the data to PHY register
430 * at the offset. Release any acquired semaphores before exiting.
431 **/
432static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
433 bool locked)
434{
435 s32 ret_val = 0;
436
437 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +0000438 if (!(hw->phy.ops.acquire))
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000439 goto out;
440
Bruce Allan94d81862009-11-20 23:25:26 +0000441 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000442 if (ret_val)
443 goto out;
444 }
445
446 if (offset > MAX_PHY_MULTI_PAGE_REG) {
447 ret_val = e1000e_write_phy_reg_mdic(hw,
448 IGP01E1000_PHY_PAGE_SELECT,
449 (u16)offset);
450 if (ret_val)
451 goto release;
452 }
453
454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
455 data);
456
457release:
458 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000459 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000460
461out:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700462 return ret_val;
463}
464
465/**
466 * e1000e_write_phy_reg_igp - Write igp PHY register
467 * @hw: pointer to the HW structure
468 * @offset: register offset to write to
469 * @data: data to write at register offset
470 *
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000471 * Acquires semaphore then writes the data to PHY register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700472 * at the offset. Release any acquired semaphores before exiting.
473 **/
474s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
475{
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000476 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700477}
478
479/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000480 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to write to
483 * @data: data to write at register offset
484 *
485 * Writes the data to PHY register at the offset.
486 * Assumes semaphore already acquired.
487 **/
488s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
489{
490 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
491}
492
493/**
494 * __e1000_read_kmrn_reg - Read kumeran register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700495 * @hw: pointer to the HW structure
496 * @offset: register offset to be read
497 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000498 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700499 *
500 * Acquires semaphore, if necessary. Then reads the PHY register at offset
501 * using the kumeran interface. The information retrieved is stored in data.
502 * Release any acquired semaphores before exiting.
503 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000504static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
505 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700506{
507 u32 kmrnctrlsta;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000508 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700509
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000510 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +0000511 if (!(hw->phy.ops.acquire))
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000512 goto out;
513
Bruce Allan94d81862009-11-20 23:25:26 +0000514 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000515 if (ret_val)
516 goto out;
517 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700518
519 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
520 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
521 ew32(KMRNCTRLSTA, kmrnctrlsta);
522
523 udelay(2);
524
525 kmrnctrlsta = er32(KMRNCTRLSTA);
526 *data = (u16)kmrnctrlsta;
527
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000528 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000529 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700530
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000531out:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700532 return ret_val;
533}
534
535/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000536 * e1000e_read_kmrn_reg - Read kumeran register
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be read
539 * @data: pointer to the read data
540 *
541 * Acquires semaphore then reads the PHY register at offset using the
542 * kumeran interface. The information retrieved is stored in data.
543 * Release the acquired semaphore before exiting.
544 **/
545s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
546{
547 return __e1000_read_kmrn_reg(hw, offset, data, false);
548}
549
550/**
Bruce Allan1d5846b2009-10-29 13:46:05 +0000551 * e1000e_read_kmrn_reg_locked - Read kumeran register
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000552 * @hw: pointer to the HW structure
553 * @offset: register offset to be read
554 * @data: pointer to the read data
555 *
556 * Reads the PHY register at offset using the kumeran interface. The
557 * information retrieved is stored in data.
558 * Assumes semaphore already acquired.
559 **/
Bruce Allan1d5846b2009-10-29 13:46:05 +0000560s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000561{
562 return __e1000_read_kmrn_reg(hw, offset, data, true);
563}
564
565/**
566 * __e1000_write_kmrn_reg - Write kumeran register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000570 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700571 *
572 * Acquires semaphore, if necessary. Then write the data to PHY register
573 * at the offset using the kumeran interface. Release any acquired semaphores
574 * before exiting.
575 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000576static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
577 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700578{
579 u32 kmrnctrlsta;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000580 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700581
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000582 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +0000583 if (!(hw->phy.ops.acquire))
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000584 goto out;
585
Bruce Allan94d81862009-11-20 23:25:26 +0000586 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000587 if (ret_val)
588 goto out;
589 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700590
591 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
592 E1000_KMRNCTRLSTA_OFFSET) | data;
593 ew32(KMRNCTRLSTA, kmrnctrlsta);
594
595 udelay(2);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700596
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000597 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000598 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000599
600out:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700601 return ret_val;
602}
603
604/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000605 * e1000e_write_kmrn_reg - Write kumeran register
606 * @hw: pointer to the HW structure
607 * @offset: register offset to write to
608 * @data: data to write at register offset
609 *
610 * Acquires semaphore then writes the data to the PHY register at the offset
611 * using the kumeran interface. Release the acquired semaphore before exiting.
612 **/
613s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
614{
615 return __e1000_write_kmrn_reg(hw, offset, data, false);
616}
617
618/**
Bruce Allan1d5846b2009-10-29 13:46:05 +0000619 * e1000e_write_kmrn_reg_locked - Write kumeran register
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000620 * @hw: pointer to the HW structure
621 * @offset: register offset to write to
622 * @data: data to write at register offset
623 *
624 * Write the data to PHY register at the offset using the kumeran interface.
625 * Assumes semaphore already acquired.
626 **/
Bruce Allan1d5846b2009-10-29 13:46:05 +0000627s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000628{
629 return __e1000_write_kmrn_reg(hw, offset, data, true);
630}
631
632/**
Bruce Allana4f58f52009-06-02 11:29:18 +0000633 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
634 * @hw: pointer to the HW structure
635 *
636 * Sets up Carrier-sense on Transmit and downshift values.
637 **/
638s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
639{
Bruce Allana4f58f52009-06-02 11:29:18 +0000640 s32 ret_val;
641 u16 phy_data;
642
Bruce Allanaf667a22010-12-31 06:10:01 +0000643 /* Enable CRS on Tx. This must be set for half-duplex operation. */
Bruce Allan482fed82011-01-06 14:29:49 +0000644 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000645 if (ret_val)
646 goto out;
647
648 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
649
650 /* Enable downshift */
651 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
652
Bruce Allan482fed82011-01-06 14:29:49 +0000653 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000654
655out:
656 return ret_val;
657}
658
659/**
Auke Kokbc7f75f2007-09-17 12:30:59 -0700660 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
661 * @hw: pointer to the HW structure
662 *
663 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
664 * and downshift values are set also.
665 **/
666s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
667{
668 struct e1000_phy_info *phy = &hw->phy;
669 s32 ret_val;
670 u16 phy_data;
671
Bruce Allanad680762008-03-28 09:15:03 -0700672 /* Enable CRS on Tx. This must be set for half-duplex operation. */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700673 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
674 if (ret_val)
675 return ret_val;
676
Bruce Allana4f58f52009-06-02 11:29:18 +0000677 /* For BM PHY this bit is downshift enable */
678 if (phy->type != e1000_phy_bm)
David Graham2d9498f2008-04-23 11:09:14 -0700679 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700680
Bruce Allanad680762008-03-28 09:15:03 -0700681 /*
682 * Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700683 * MDI/MDI-X = 0 (default)
684 * 0 - Auto for all speeds
685 * 1 - MDI mode
686 * 2 - MDI-X mode
687 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
688 */
689 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
690
691 switch (phy->mdix) {
692 case 1:
693 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
694 break;
695 case 2:
696 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
697 break;
698 case 3:
699 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
700 break;
701 case 0:
702 default:
703 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
704 break;
705 }
706
Bruce Allanad680762008-03-28 09:15:03 -0700707 /*
708 * Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700709 * disable_polarity_correction = 0 (default)
710 * Automatic Correction for Reversed Cable Polarity
711 * 0 - Disabled
712 * 1 - Enabled
713 */
714 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
715 if (phy->disable_polarity_correction == 1)
716 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
717
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700718 /* Enable downshift on BM (disabled by default) */
719 if (phy->type == e1000_phy_bm)
720 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
721
Auke Kokbc7f75f2007-09-17 12:30:59 -0700722 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
723 if (ret_val)
724 return ret_val;
725
Bruce Allan4662e822008-08-26 18:37:06 -0700726 if ((phy->type == e1000_phy_m88) &&
727 (phy->revision < E1000_REVISION_4) &&
728 (phy->id != BME1000_E_PHY_ID_R2)) {
Bruce Allanad680762008-03-28 09:15:03 -0700729 /*
730 * Force TX_CLK in the Extended PHY Specific Control Register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700731 * to 25MHz clock.
732 */
733 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
734 if (ret_val)
735 return ret_val;
736
737 phy_data |= M88E1000_EPSCR_TX_CLK_25;
738
739 if ((phy->revision == 2) &&
740 (phy->id == M88E1111_I_PHY_ID)) {
741 /* 82573L PHY - set the downshift counter to 5x. */
742 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
743 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
744 } else {
745 /* Configure Master and Slave downshift values */
746 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
747 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
748 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
749 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
750 }
751 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
752 if (ret_val)
753 return ret_val;
754 }
755
Bruce Allan4662e822008-08-26 18:37:06 -0700756 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
757 /* Set PHY page 0, register 29 to 0x0003 */
758 ret_val = e1e_wphy(hw, 29, 0x0003);
759 if (ret_val)
760 return ret_val;
761
762 /* Set PHY page 0, register 30 to 0x0000 */
763 ret_val = e1e_wphy(hw, 30, 0x0000);
764 if (ret_val)
765 return ret_val;
766 }
767
Auke Kokbc7f75f2007-09-17 12:30:59 -0700768 /* Commit the changes. */
769 ret_val = e1000e_commit_phy(hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000770 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000771 e_dbg("Error committing the PHY changes\n");
Bruce Allana4f58f52009-06-02 11:29:18 +0000772 return ret_val;
773 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700774
Bruce Allana4f58f52009-06-02 11:29:18 +0000775 if (phy->type == e1000_phy_82578) {
Bruce Allan482fed82011-01-06 14:29:49 +0000776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000777 if (ret_val)
778 return ret_val;
779
780 /* 82578 PHY - set the downshift count to 1x. */
781 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
782 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
Bruce Allan482fed82011-01-06 14:29:49 +0000783 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000784 if (ret_val)
785 return ret_val;
786 }
787
788 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700789}
790
791/**
792 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
793 * @hw: pointer to the HW structure
794 *
795 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
796 * igp PHY's.
797 **/
798s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
799{
800 struct e1000_phy_info *phy = &hw->phy;
801 s32 ret_val;
802 u16 data;
803
804 ret_val = e1000_phy_hw_reset(hw);
805 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000806 e_dbg("Error resetting the PHY.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700807 return ret_val;
808 }
809
David Graham2d9498f2008-04-23 11:09:14 -0700810 /*
811 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
812 * timeout issues when LFS is enabled.
813 */
814 msleep(100);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700815
816 /* disable lplu d0 during driver init */
Bruce Allan564ea9b2009-11-20 23:26:44 +0000817 ret_val = e1000_set_d0_lplu_state(hw, false);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700818 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000819 e_dbg("Error Disabling LPLU D0\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700820 return ret_val;
821 }
822 /* Configure mdi-mdix settings */
823 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
824 if (ret_val)
825 return ret_val;
826
827 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
828
829 switch (phy->mdix) {
830 case 1:
831 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
832 break;
833 case 2:
834 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
835 break;
836 case 0:
837 default:
838 data |= IGP01E1000_PSCR_AUTO_MDIX;
839 break;
840 }
841 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
842 if (ret_val)
843 return ret_val;
844
845 /* set auto-master slave resolution settings */
846 if (hw->mac.autoneg) {
Bruce Allanad680762008-03-28 09:15:03 -0700847 /*
848 * when autonegotiation advertisement is only 1000Mbps then we
Auke Kokbc7f75f2007-09-17 12:30:59 -0700849 * should disable SmartSpeed and enable Auto MasterSlave
Bruce Allanad680762008-03-28 09:15:03 -0700850 * resolution as hardware default.
851 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700852 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
853 /* Disable SmartSpeed */
854 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700855 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700856 if (ret_val)
857 return ret_val;
858
859 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
860 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700861 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700862 if (ret_val)
863 return ret_val;
864
865 /* Set auto Master/Slave resolution process */
866 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
867 if (ret_val)
868 return ret_val;
869
870 data &= ~CR_1000T_MS_ENABLE;
871 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
872 if (ret_val)
873 return ret_val;
874 }
875
876 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
877 if (ret_val)
878 return ret_val;
879
880 /* load defaults for future use */
881 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
882 ((data & CR_1000T_MS_VALUE) ?
883 e1000_ms_force_master :
884 e1000_ms_force_slave) :
885 e1000_ms_auto;
886
887 switch (phy->ms_type) {
888 case e1000_ms_force_master:
889 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
890 break;
891 case e1000_ms_force_slave:
892 data |= CR_1000T_MS_ENABLE;
893 data &= ~(CR_1000T_MS_VALUE);
894 break;
895 case e1000_ms_auto:
896 data &= ~CR_1000T_MS_ENABLE;
897 default:
898 break;
899 }
900 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
901 }
902
903 return ret_val;
904}
905
906/**
907 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
908 * @hw: pointer to the HW structure
909 *
910 * Reads the MII auto-neg advertisement register and/or the 1000T control
911 * register and if the PHY is already setup for auto-negotiation, then
912 * return successful. Otherwise, setup advertisement and flow control to
913 * the appropriate values for the wanted auto-negotiation.
914 **/
915static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
916{
917 struct e1000_phy_info *phy = &hw->phy;
918 s32 ret_val;
919 u16 mii_autoneg_adv_reg;
920 u16 mii_1000t_ctrl_reg = 0;
921
922 phy->autoneg_advertised &= phy->autoneg_mask;
923
924 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
925 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
926 if (ret_val)
927 return ret_val;
928
929 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
930 /* Read the MII 1000Base-T Control Register (Address 9). */
931 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
932 if (ret_val)
933 return ret_val;
934 }
935
Bruce Allanad680762008-03-28 09:15:03 -0700936 /*
937 * Need to parse both autoneg_advertised and fc and set up
Auke Kokbc7f75f2007-09-17 12:30:59 -0700938 * the appropriate PHY registers. First we will parse for
939 * autoneg_advertised software override. Since we can advertise
940 * a plethora of combinations, we need to check each bit
941 * individually.
942 */
943
Bruce Allanad680762008-03-28 09:15:03 -0700944 /*
945 * First we clear all the 10/100 mb speed bits in the Auto-Neg
Auke Kokbc7f75f2007-09-17 12:30:59 -0700946 * Advertisement Register (Address 4) and the 1000 mb speed bits in
947 * the 1000Base-T Control Register (Address 9).
948 */
949 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
950 NWAY_AR_100TX_HD_CAPS |
951 NWAY_AR_10T_FD_CAPS |
952 NWAY_AR_10T_HD_CAPS);
953 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
954
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000955 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700956
957 /* Do we want to advertise 10 Mb Half Duplex? */
958 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000959 e_dbg("Advertise 10mb Half duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700960 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
961 }
962
963 /* Do we want to advertise 10 Mb Full Duplex? */
964 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000965 e_dbg("Advertise 10mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700966 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
967 }
968
969 /* Do we want to advertise 100 Mb Half Duplex? */
970 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000971 e_dbg("Advertise 100mb Half duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700972 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
973 }
974
975 /* Do we want to advertise 100 Mb Full Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000977 e_dbg("Advertise 100mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700978 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
979 }
980
981 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
982 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000983 e_dbg("Advertise 1000mb Half duplex request denied!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700984
985 /* Do we want to advertise 1000 Mb Full Duplex? */
986 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000987 e_dbg("Advertise 1000mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700988 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
989 }
990
Bruce Allanad680762008-03-28 09:15:03 -0700991 /*
992 * Check for a software override of the flow control settings, and
Auke Kokbc7f75f2007-09-17 12:30:59 -0700993 * setup the PHY advertisement registers accordingly. If
994 * auto-negotiation is enabled, then software will have to set the
995 * "PAUSE" bits to the correct value in the Auto-Negotiation
996 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
997 * negotiation.
998 *
999 * The possible values of the "fc" parameter are:
1000 * 0: Flow control is completely disabled
1001 * 1: Rx flow control is enabled (we can receive pause frames
1002 * but not send pause frames).
1003 * 2: Tx flow control is enabled (we can send pause frames
1004 * but we do not support receiving pause frames).
Bruce Allanad680762008-03-28 09:15:03 -07001005 * 3: Both Rx and Tx flow control (symmetric) are enabled.
Auke Kokbc7f75f2007-09-17 12:30:59 -07001006 * other: No software override. The flow control configuration
1007 * in the EEPROM is used.
1008 */
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08001009 switch (hw->fc.current_mode) {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001010 case e1000_fc_none:
Bruce Allanad680762008-03-28 09:15:03 -07001011 /*
1012 * Flow control (Rx & Tx) is completely disabled by a
Auke Kokbc7f75f2007-09-17 12:30:59 -07001013 * software over-ride.
1014 */
1015 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1016 break;
1017 case e1000_fc_rx_pause:
Bruce Allanad680762008-03-28 09:15:03 -07001018 /*
1019 * Rx Flow control is enabled, and Tx Flow control is
Auke Kokbc7f75f2007-09-17 12:30:59 -07001020 * disabled, by a software over-ride.
Bruce Allanad680762008-03-28 09:15:03 -07001021 *
1022 * Since there really isn't a way to advertise that we are
1023 * capable of Rx Pause ONLY, we will advertise that we
1024 * support both symmetric and asymmetric Rx PAUSE. Later
Auke Kokbc7f75f2007-09-17 12:30:59 -07001025 * (in e1000e_config_fc_after_link_up) we will disable the
1026 * hw's ability to send PAUSE frames.
1027 */
1028 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1029 break;
1030 case e1000_fc_tx_pause:
Bruce Allanad680762008-03-28 09:15:03 -07001031 /*
1032 * Tx Flow control is enabled, and Rx Flow control is
Auke Kokbc7f75f2007-09-17 12:30:59 -07001033 * disabled, by a software over-ride.
1034 */
1035 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1036 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1037 break;
1038 case e1000_fc_full:
Bruce Allanad680762008-03-28 09:15:03 -07001039 /*
1040 * Flow control (both Rx and Tx) is enabled by a software
Auke Kokbc7f75f2007-09-17 12:30:59 -07001041 * over-ride.
1042 */
1043 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1044 break;
1045 default:
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001046 e_dbg("Flow control param set incorrectly\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001047 ret_val = -E1000_ERR_CONFIG;
1048 return ret_val;
1049 }
1050
1051 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1052 if (ret_val)
1053 return ret_val;
1054
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001055 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001056
Bruce Allanb1cdfea2010-12-11 05:53:47 +00001057 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001058 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001059
1060 return ret_val;
1061}
1062
1063/**
1064 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1065 * @hw: pointer to the HW structure
1066 *
1067 * Performs initial bounds checking on autoneg advertisement parameter, then
1068 * configure to advertise the full capability. Setup the PHY to autoneg
1069 * and restart the negotiation process between the link partner. If
Bruce Allanad680762008-03-28 09:15:03 -07001070 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
Auke Kokbc7f75f2007-09-17 12:30:59 -07001071 **/
1072static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1073{
1074 struct e1000_phy_info *phy = &hw->phy;
1075 s32 ret_val;
1076 u16 phy_ctrl;
1077
Bruce Allanad680762008-03-28 09:15:03 -07001078 /*
1079 * Perform some bounds checking on the autoneg advertisement
Auke Kokbc7f75f2007-09-17 12:30:59 -07001080 * parameter.
1081 */
1082 phy->autoneg_advertised &= phy->autoneg_mask;
1083
Bruce Allanad680762008-03-28 09:15:03 -07001084 /*
1085 * If autoneg_advertised is zero, we assume it was not defaulted
Auke Kokbc7f75f2007-09-17 12:30:59 -07001086 * by the calling code so we set to advertise full capability.
1087 */
1088 if (phy->autoneg_advertised == 0)
1089 phy->autoneg_advertised = phy->autoneg_mask;
1090
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001091 e_dbg("Reconfiguring auto-neg advertisement params\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001092 ret_val = e1000_phy_setup_autoneg(hw);
1093 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001094 e_dbg("Error Setting up Auto-Negotiation\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001095 return ret_val;
1096 }
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001097 e_dbg("Restarting Auto-Neg\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001098
Bruce Allanad680762008-03-28 09:15:03 -07001099 /*
1100 * Restart auto-negotiation by setting the Auto Neg Enable bit and
Auke Kokbc7f75f2007-09-17 12:30:59 -07001101 * the Auto Neg Restart bit in the PHY control register.
1102 */
1103 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1104 if (ret_val)
1105 return ret_val;
1106
1107 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1108 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1109 if (ret_val)
1110 return ret_val;
1111
Bruce Allanad680762008-03-28 09:15:03 -07001112 /*
1113 * Does the user want to wait for Auto-Neg to complete here, or
Auke Kokbc7f75f2007-09-17 12:30:59 -07001114 * check at a later time (for example, callback routine).
1115 */
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001116 if (phy->autoneg_wait_to_complete) {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001117 ret_val = e1000_wait_autoneg(hw);
1118 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001119 e_dbg("Error while waiting for "
Auke Kokbc7f75f2007-09-17 12:30:59 -07001120 "autoneg to complete\n");
1121 return ret_val;
1122 }
1123 }
1124
1125 hw->mac.get_link_status = 1;
1126
1127 return ret_val;
1128}
1129
1130/**
1131 * e1000e_setup_copper_link - Configure copper link settings
1132 * @hw: pointer to the HW structure
1133 *
1134 * Calls the appropriate function to configure the link for auto-neg or forced
1135 * speed and duplex. Then we check for link, once link is established calls
1136 * to configure collision distance and flow control are called. If link is
1137 * not established, we return -E1000_ERR_PHY (-2).
1138 **/
1139s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1140{
1141 s32 ret_val;
1142 bool link;
1143
1144 if (hw->mac.autoneg) {
Bruce Allanad680762008-03-28 09:15:03 -07001145 /*
1146 * Setup autoneg and flow control advertisement and perform
1147 * autonegotiation.
1148 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001149 ret_val = e1000_copper_link_autoneg(hw);
1150 if (ret_val)
1151 return ret_val;
1152 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001153 /*
1154 * PHY will be set to 10H, 10F, 100H or 100F
1155 * depending on user settings.
1156 */
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001157 e_dbg("Forcing Speed and Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001158 ret_val = e1000_phy_force_speed_duplex(hw);
1159 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001160 e_dbg("Error Forcing Speed and Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001161 return ret_val;
1162 }
1163 }
1164
Bruce Allanad680762008-03-28 09:15:03 -07001165 /*
1166 * Check link status. Wait up to 100 microseconds for link to become
Auke Kokbc7f75f2007-09-17 12:30:59 -07001167 * valid.
1168 */
1169 ret_val = e1000e_phy_has_link_generic(hw,
1170 COPPER_LINK_UP_LIMIT,
1171 10,
1172 &link);
1173 if (ret_val)
1174 return ret_val;
1175
1176 if (link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001177 e_dbg("Valid link established!!!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001178 e1000e_config_collision_dist(hw);
1179 ret_val = e1000e_config_fc_after_link_up(hw);
1180 } else {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001181 e_dbg("Unable to establish link!!!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001182 }
1183
1184 return ret_val;
1185}
1186
1187/**
1188 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1189 * @hw: pointer to the HW structure
1190 *
1191 * Calls the PHY setup function to force speed and duplex. Clears the
1192 * auto-crossover to force MDI manually. Waits for link and returns
1193 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1194 **/
1195s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1196{
1197 struct e1000_phy_info *phy = &hw->phy;
1198 s32 ret_val;
1199 u16 phy_data;
1200 bool link;
1201
1202 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1203 if (ret_val)
1204 return ret_val;
1205
1206 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1207
1208 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
Bruce Allanad680762008-03-28 09:15:03 -07001212 /*
1213 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -07001214 * forced whenever speed and duplex are forced.
1215 */
1216 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1217 if (ret_val)
1218 return ret_val;
1219
1220 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1221 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1222
1223 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1224 if (ret_val)
1225 return ret_val;
1226
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001227 e_dbg("IGP PSCR: %X\n", phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001228
1229 udelay(1);
1230
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001231 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001232 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001233
1234 ret_val = e1000e_phy_has_link_generic(hw,
1235 PHY_FORCE_LIMIT,
1236 100000,
1237 &link);
1238 if (ret_val)
1239 return ret_val;
1240
1241 if (!link)
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001242 e_dbg("Link taking longer than expected.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001243
1244 /* Try once more */
1245 ret_val = e1000e_phy_has_link_generic(hw,
1246 PHY_FORCE_LIMIT,
1247 100000,
1248 &link);
1249 if (ret_val)
1250 return ret_val;
1251 }
1252
1253 return ret_val;
1254}
1255
1256/**
1257 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1258 * @hw: pointer to the HW structure
1259 *
1260 * Calls the PHY setup function to force speed and duplex. Clears the
1261 * auto-crossover to force MDI manually. Resets the PHY to commit the
1262 * changes. If time expires while waiting for link up, we reset the DSP.
Bruce Allanad680762008-03-28 09:15:03 -07001263 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
Auke Kokbc7f75f2007-09-17 12:30:59 -07001264 * successful completion, else return corresponding error code.
1265 **/
1266s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1267{
1268 struct e1000_phy_info *phy = &hw->phy;
1269 s32 ret_val;
1270 u16 phy_data;
1271 bool link;
1272
Bruce Allanad680762008-03-28 09:15:03 -07001273 /*
1274 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -07001275 * forced whenever speed and duplex are forced.
1276 */
1277 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1278 if (ret_val)
1279 return ret_val;
1280
1281 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1282 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1283 if (ret_val)
1284 return ret_val;
1285
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001286 e_dbg("M88E1000 PSCR: %X\n", phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001287
1288 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1289 if (ret_val)
1290 return ret_val;
1291
1292 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1293
Auke Kokbc7f75f2007-09-17 12:30:59 -07001294 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1295 if (ret_val)
1296 return ret_val;
1297
Bruce Allan5aa49c82008-11-21 16:49:53 -08001298 /* Reset the phy to commit changes. */
1299 ret_val = e1000e_commit_phy(hw);
1300 if (ret_val)
1301 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001302
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001303 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001304 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001305
1306 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1307 100000, &link);
1308 if (ret_val)
1309 return ret_val;
1310
1311 if (!link) {
Bruce Allan0be84012009-12-02 17:03:18 +00001312 if (hw->phy.type != e1000_phy_m88) {
1313 e_dbg("Link taking longer than expected.\n");
1314 } else {
1315 /*
1316 * We didn't get link.
1317 * Reset the DSP and cross our fingers.
1318 */
Bruce Allan482fed82011-01-06 14:29:49 +00001319 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1320 0x001d);
Bruce Allan0be84012009-12-02 17:03:18 +00001321 if (ret_val)
1322 return ret_val;
1323 ret_val = e1000e_phy_reset_dsp(hw);
1324 if (ret_val)
1325 return ret_val;
1326 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07001327 }
1328
1329 /* Try once more */
1330 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1331 100000, &link);
1332 if (ret_val)
1333 return ret_val;
1334 }
1335
Bruce Allan0be84012009-12-02 17:03:18 +00001336 if (hw->phy.type != e1000_phy_m88)
1337 return 0;
1338
Auke Kokbc7f75f2007-09-17 12:30:59 -07001339 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
Bruce Allanad680762008-03-28 09:15:03 -07001343 /*
1344 * Resetting the phy means we need to re-force TX_CLK in the
Auke Kokbc7f75f2007-09-17 12:30:59 -07001345 * Extended PHY Specific Control Register to 25MHz clock from
1346 * the reset value of 2.5MHz.
1347 */
1348 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1349 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1350 if (ret_val)
1351 return ret_val;
1352
Bruce Allanad680762008-03-28 09:15:03 -07001353 /*
1354 * In addition, we must re-enable CRS on Tx for both half and full
Auke Kokbc7f75f2007-09-17 12:30:59 -07001355 * duplex.
1356 */
1357 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1358 if (ret_val)
1359 return ret_val;
1360
1361 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1362 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1363
1364 return ret_val;
1365}
1366
1367/**
Bruce Allan0be84012009-12-02 17:03:18 +00001368 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1369 * @hw: pointer to the HW structure
1370 *
1371 * Forces the speed and duplex settings of the PHY.
1372 * This is a function pointer entry point only called by
1373 * PHY setup routines.
1374 **/
1375s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1376{
1377 struct e1000_phy_info *phy = &hw->phy;
1378 s32 ret_val;
1379 u16 data;
1380 bool link;
1381
1382 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1383 if (ret_val)
1384 goto out;
1385
1386 e1000e_phy_force_speed_duplex_setup(hw, &data);
1387
1388 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1389 if (ret_val)
1390 goto out;
1391
1392 /* Disable MDI-X support for 10/100 */
1393 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1394 if (ret_val)
1395 goto out;
1396
1397 data &= ~IFE_PMC_AUTO_MDIX;
1398 data &= ~IFE_PMC_FORCE_MDIX;
1399
1400 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1401 if (ret_val)
1402 goto out;
1403
1404 e_dbg("IFE PMC: %X\n", data);
1405
1406 udelay(1);
1407
1408 if (phy->autoneg_wait_to_complete) {
1409 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1410
1411 ret_val = e1000e_phy_has_link_generic(hw,
1412 PHY_FORCE_LIMIT,
1413 100000,
1414 &link);
1415 if (ret_val)
1416 goto out;
1417
1418 if (!link)
1419 e_dbg("Link taking longer than expected.\n");
1420
1421 /* Try once more */
1422 ret_val = e1000e_phy_has_link_generic(hw,
1423 PHY_FORCE_LIMIT,
1424 100000,
1425 &link);
1426 if (ret_val)
1427 goto out;
1428 }
1429
1430out:
1431 return ret_val;
1432}
1433
1434/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001435 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1436 * @hw: pointer to the HW structure
1437 * @phy_ctrl: pointer to current value of PHY_CONTROL
1438 *
1439 * Forces speed and duplex on the PHY by doing the following: disable flow
1440 * control, force speed/duplex on the MAC, disable auto speed detection,
1441 * disable auto-negotiation, configure duplex, configure speed, configure
1442 * the collision distance, write configuration to CTRL register. The
1443 * caller must write to the PHY_CONTROL register for these settings to
1444 * take affect.
1445 **/
1446void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1447{
1448 struct e1000_mac_info *mac = &hw->mac;
1449 u32 ctrl;
1450
1451 /* Turn off flow control when forcing speed/duplex */
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08001452 hw->fc.current_mode = e1000_fc_none;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001453
1454 /* Force speed/duplex on the mac */
1455 ctrl = er32(CTRL);
1456 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1457 ctrl &= ~E1000_CTRL_SPD_SEL;
1458
1459 /* Disable Auto Speed Detection */
1460 ctrl &= ~E1000_CTRL_ASDE;
1461
1462 /* Disable autoneg on the phy */
1463 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1464
1465 /* Forcing Full or Half Duplex? */
1466 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1467 ctrl &= ~E1000_CTRL_FD;
1468 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001469 e_dbg("Half Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001470 } else {
1471 ctrl |= E1000_CTRL_FD;
1472 *phy_ctrl |= MII_CR_FULL_DUPLEX;
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001473 e_dbg("Full Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001474 }
1475
1476 /* Forcing 10mb or 100mb? */
1477 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1478 ctrl |= E1000_CTRL_SPD_100;
1479 *phy_ctrl |= MII_CR_SPEED_100;
1480 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001481 e_dbg("Forcing 100mb\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001482 } else {
1483 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1484 *phy_ctrl |= MII_CR_SPEED_10;
1485 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001486 e_dbg("Forcing 10mb\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001487 }
1488
1489 e1000e_config_collision_dist(hw);
1490
1491 ew32(CTRL, ctrl);
1492}
1493
1494/**
1495 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1496 * @hw: pointer to the HW structure
1497 * @active: boolean used to enable/disable lplu
1498 *
1499 * Success returns 0, Failure returns 1
1500 *
1501 * The low power link up (lplu) state is set to the power management level D3
1502 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1503 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1504 * is used during Dx states where the power conservation is most important.
1505 * During driver activity, SmartSpeed should be enabled so performance is
1506 * maintained.
1507 **/
1508s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1509{
1510 struct e1000_phy_info *phy = &hw->phy;
1511 s32 ret_val;
1512 u16 data;
1513
1514 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1515 if (ret_val)
1516 return ret_val;
1517
1518 if (!active) {
1519 data &= ~IGP02E1000_PM_D3_LPLU;
David Graham2d9498f2008-04-23 11:09:14 -07001520 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001521 if (ret_val)
1522 return ret_val;
Bruce Allanad680762008-03-28 09:15:03 -07001523 /*
1524 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
Auke Kokbc7f75f2007-09-17 12:30:59 -07001525 * during Dx states where the power conservation is most
1526 * important. During driver activity we should enable
Bruce Allanad680762008-03-28 09:15:03 -07001527 * SmartSpeed, so performance is maintained.
1528 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001529 if (phy->smart_speed == e1000_smart_speed_on) {
1530 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001531 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001532 if (ret_val)
1533 return ret_val;
1534
1535 data |= IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001537 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001538 if (ret_val)
1539 return ret_val;
1540 } else if (phy->smart_speed == e1000_smart_speed_off) {
1541 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001542 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001543 if (ret_val)
1544 return ret_val;
1545
1546 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1547 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001548 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001549 if (ret_val)
1550 return ret_val;
1551 }
1552 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1553 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1554 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1555 data |= IGP02E1000_PM_D3_LPLU;
1556 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1557 if (ret_val)
1558 return ret_val;
1559
1560 /* When LPLU is enabled, we should disable SmartSpeed */
1561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1562 if (ret_val)
1563 return ret_val;
1564
1565 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1566 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1567 }
1568
1569 return ret_val;
1570}
1571
1572/**
Auke Kok489815c2008-02-21 15:11:07 -08001573 * e1000e_check_downshift - Checks whether a downshift in speed occurred
Auke Kokbc7f75f2007-09-17 12:30:59 -07001574 * @hw: pointer to the HW structure
1575 *
1576 * Success returns 0, Failure returns 1
1577 *
1578 * A downshift is detected by querying the PHY link health.
1579 **/
1580s32 e1000e_check_downshift(struct e1000_hw *hw)
1581{
1582 struct e1000_phy_info *phy = &hw->phy;
1583 s32 ret_val;
1584 u16 phy_data, offset, mask;
1585
1586 switch (phy->type) {
1587 case e1000_phy_m88:
1588 case e1000_phy_gg82563:
Bruce Allan07f025e2009-12-01 15:53:48 +00001589 case e1000_phy_bm:
Bruce Allana4f58f52009-06-02 11:29:18 +00001590 case e1000_phy_82578:
Auke Kokbc7f75f2007-09-17 12:30:59 -07001591 offset = M88E1000_PHY_SPEC_STATUS;
1592 mask = M88E1000_PSSR_DOWNSHIFT;
1593 break;
1594 case e1000_phy_igp_2:
1595 case e1000_phy_igp_3:
1596 offset = IGP01E1000_PHY_LINK_HEALTH;
1597 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1598 break;
1599 default:
1600 /* speed downshift not supported */
Bruce Allan564ea9b2009-11-20 23:26:44 +00001601 phy->speed_downgraded = false;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001602 return 0;
1603 }
1604
1605 ret_val = e1e_rphy(hw, offset, &phy_data);
1606
1607 if (!ret_val)
1608 phy->speed_downgraded = (phy_data & mask);
1609
1610 return ret_val;
1611}
1612
1613/**
1614 * e1000_check_polarity_m88 - Checks the polarity.
1615 * @hw: pointer to the HW structure
1616 *
1617 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1618 *
1619 * Polarity is determined based on the PHY specific status register.
1620 **/
Bruce Allan0be84012009-12-02 17:03:18 +00001621s32 e1000_check_polarity_m88(struct e1000_hw *hw)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001622{
1623 struct e1000_phy_info *phy = &hw->phy;
1624 s32 ret_val;
1625 u16 data;
1626
1627 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1628
1629 if (!ret_val)
1630 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1631 ? e1000_rev_polarity_reversed
1632 : e1000_rev_polarity_normal;
1633
1634 return ret_val;
1635}
1636
1637/**
1638 * e1000_check_polarity_igp - Checks the polarity.
1639 * @hw: pointer to the HW structure
1640 *
1641 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1642 *
1643 * Polarity is determined based on the PHY port status register, and the
1644 * current speed (since there is no polarity at 100Mbps).
1645 **/
Bruce Allan0be84012009-12-02 17:03:18 +00001646s32 e1000_check_polarity_igp(struct e1000_hw *hw)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001647{
1648 struct e1000_phy_info *phy = &hw->phy;
1649 s32 ret_val;
1650 u16 data, offset, mask;
1651
Bruce Allanad680762008-03-28 09:15:03 -07001652 /*
1653 * Polarity is determined based on the speed of
1654 * our connection.
1655 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001656 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1657 if (ret_val)
1658 return ret_val;
1659
1660 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1661 IGP01E1000_PSSR_SPEED_1000MBPS) {
1662 offset = IGP01E1000_PHY_PCS_INIT_REG;
1663 mask = IGP01E1000_PHY_POLARITY_MASK;
1664 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001665 /*
1666 * This really only applies to 10Mbps since
Auke Kokbc7f75f2007-09-17 12:30:59 -07001667 * there is no polarity for 100Mbps (always 0).
1668 */
1669 offset = IGP01E1000_PHY_PORT_STATUS;
1670 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1671 }
1672
1673 ret_val = e1e_rphy(hw, offset, &data);
1674
1675 if (!ret_val)
1676 phy->cable_polarity = (data & mask)
1677 ? e1000_rev_polarity_reversed
1678 : e1000_rev_polarity_normal;
1679
1680 return ret_val;
1681}
1682
1683/**
Bruce Allan0be84012009-12-02 17:03:18 +00001684 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1685 * @hw: pointer to the HW structure
1686 *
1687 * Polarity is determined on the polarity reversal feature being enabled.
1688 **/
1689s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1690{
1691 struct e1000_phy_info *phy = &hw->phy;
1692 s32 ret_val;
1693 u16 phy_data, offset, mask;
1694
1695 /*
1696 * Polarity is determined based on the reversal feature being enabled.
1697 */
1698 if (phy->polarity_correction) {
1699 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1700 mask = IFE_PESC_POLARITY_REVERSED;
1701 } else {
1702 offset = IFE_PHY_SPECIAL_CONTROL;
1703 mask = IFE_PSC_FORCE_POLARITY;
1704 }
1705
1706 ret_val = e1e_rphy(hw, offset, &phy_data);
1707
1708 if (!ret_val)
1709 phy->cable_polarity = (phy_data & mask)
1710 ? e1000_rev_polarity_reversed
1711 : e1000_rev_polarity_normal;
1712
1713 return ret_val;
1714}
1715
1716/**
Bruce Allanad680762008-03-28 09:15:03 -07001717 * e1000_wait_autoneg - Wait for auto-neg completion
Auke Kokbc7f75f2007-09-17 12:30:59 -07001718 * @hw: pointer to the HW structure
1719 *
1720 * Waits for auto-negotiation to complete or for the auto-negotiation time
1721 * limit to expire, which ever happens first.
1722 **/
1723static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1724{
1725 s32 ret_val = 0;
1726 u16 i, phy_status;
1727
1728 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1729 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1730 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1731 if (ret_val)
1732 break;
1733 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1734 if (ret_val)
1735 break;
1736 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1737 break;
1738 msleep(100);
1739 }
1740
Bruce Allanad680762008-03-28 09:15:03 -07001741 /*
1742 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
Auke Kokbc7f75f2007-09-17 12:30:59 -07001743 * has completed.
1744 */
1745 return ret_val;
1746}
1747
1748/**
1749 * e1000e_phy_has_link_generic - Polls PHY for link
1750 * @hw: pointer to the HW structure
1751 * @iterations: number of times to poll for link
1752 * @usec_interval: delay between polling attempts
1753 * @success: pointer to whether polling was successful or not
1754 *
1755 * Polls the PHY status register for link, 'iterations' number of times.
1756 **/
1757s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1758 u32 usec_interval, bool *success)
1759{
1760 s32 ret_val = 0;
1761 u16 i, phy_status;
1762
1763 for (i = 0; i < iterations; i++) {
Bruce Allanad680762008-03-28 09:15:03 -07001764 /*
1765 * Some PHYs require the PHY_STATUS register to be read
Auke Kokbc7f75f2007-09-17 12:30:59 -07001766 * twice due to the link bit being sticky. No harm doing
1767 * it across the board.
1768 */
1769 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1770 if (ret_val)
Bruce Allan906e8d92009-07-01 13:28:50 +00001771 /*
1772 * If the first read fails, another entity may have
1773 * ownership of the resources, wait and try again to
1774 * see if they have relinquished the resources yet.
1775 */
1776 udelay(usec_interval);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001777 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1778 if (ret_val)
1779 break;
1780 if (phy_status & MII_SR_LINK_STATUS)
1781 break;
1782 if (usec_interval >= 1000)
1783 mdelay(usec_interval/1000);
1784 else
1785 udelay(usec_interval);
1786 }
1787
1788 *success = (i < iterations);
1789
1790 return ret_val;
1791}
1792
1793/**
1794 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1795 * @hw: pointer to the HW structure
1796 *
1797 * Reads the PHY specific status register to retrieve the cable length
1798 * information. The cable length is determined by averaging the minimum and
1799 * maximum values to get the "average" cable length. The m88 PHY has four
1800 * possible cable length values, which are:
1801 * Register Value Cable Length
1802 * 0 < 50 meters
1803 * 1 50 - 80 meters
1804 * 2 80 - 110 meters
1805 * 3 110 - 140 meters
1806 * 4 > 140 meters
1807 **/
1808s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1809{
1810 struct e1000_phy_info *phy = &hw->phy;
1811 s32 ret_val;
1812 u16 phy_data, index;
1813
1814 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1815 if (ret_val)
Bruce Allaneb656d42009-12-01 15:47:02 +00001816 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001817
1818 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
Bruce Allaneb656d42009-12-01 15:47:02 +00001819 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1820 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1821 ret_val = -E1000_ERR_PHY;
1822 goto out;
1823 }
1824
Auke Kokbc7f75f2007-09-17 12:30:59 -07001825 phy->min_cable_length = e1000_m88_cable_length_table[index];
Bruce Allaneb656d42009-12-01 15:47:02 +00001826 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
Auke Kokbc7f75f2007-09-17 12:30:59 -07001827
1828 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1829
Bruce Allaneb656d42009-12-01 15:47:02 +00001830out:
Auke Kokbc7f75f2007-09-17 12:30:59 -07001831 return ret_val;
1832}
1833
1834/**
1835 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1836 * @hw: pointer to the HW structure
1837 *
1838 * The automatic gain control (agc) normalizes the amplitude of the
1839 * received signal, adjusting for the attenuation produced by the
Auke Kok489815c2008-02-21 15:11:07 -08001840 * cable. By reading the AGC registers, which represent the
Bruce Allan5ff5b662009-12-01 15:51:11 +00001841 * combination of coarse and fine gain value, the value can be put
Auke Kokbc7f75f2007-09-17 12:30:59 -07001842 * into a lookup table to obtain the approximate cable length
1843 * for each channel.
1844 **/
1845s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1846{
1847 struct e1000_phy_info *phy = &hw->phy;
1848 s32 ret_val;
1849 u16 phy_data, i, agc_value = 0;
1850 u16 cur_agc_index, max_agc_index = 0;
1851 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
Jeff Kirsher66744502010-12-01 19:59:50 +00001852 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1853 IGP02E1000_PHY_AGC_A,
1854 IGP02E1000_PHY_AGC_B,
1855 IGP02E1000_PHY_AGC_C,
1856 IGP02E1000_PHY_AGC_D
1857 };
Auke Kokbc7f75f2007-09-17 12:30:59 -07001858
1859 /* Read the AGC registers for all channels */
1860 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1861 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1862 if (ret_val)
1863 return ret_val;
1864
Bruce Allanad680762008-03-28 09:15:03 -07001865 /*
1866 * Getting bits 15:9, which represent the combination of
Bruce Allan5ff5b662009-12-01 15:51:11 +00001867 * coarse and fine gain values. The result is a number
Auke Kokbc7f75f2007-09-17 12:30:59 -07001868 * that can be put into the lookup table to obtain the
Bruce Allanad680762008-03-28 09:15:03 -07001869 * approximate cable length.
1870 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001871 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1872 IGP02E1000_AGC_LENGTH_MASK;
1873
1874 /* Array index bound check. */
1875 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1876 (cur_agc_index == 0))
1877 return -E1000_ERR_PHY;
1878
1879 /* Remove min & max AGC values from calculation. */
1880 if (e1000_igp_2_cable_length_table[min_agc_index] >
1881 e1000_igp_2_cable_length_table[cur_agc_index])
1882 min_agc_index = cur_agc_index;
1883 if (e1000_igp_2_cable_length_table[max_agc_index] <
1884 e1000_igp_2_cable_length_table[cur_agc_index])
1885 max_agc_index = cur_agc_index;
1886
1887 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1888 }
1889
1890 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1891 e1000_igp_2_cable_length_table[max_agc_index]);
1892 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1893
1894 /* Calculate cable length with the error range of +/- 10 meters. */
1895 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1896 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1897 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1898
1899 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1900
1901 return ret_val;
1902}
1903
1904/**
1905 * e1000e_get_phy_info_m88 - Retrieve PHY information
1906 * @hw: pointer to the HW structure
1907 *
1908 * Valid for only copper links. Read the PHY status register (sticky read)
1909 * to verify that link is up. Read the PHY special control register to
1910 * determine the polarity and 10base-T extended distance. Read the PHY
1911 * special status register to determine MDI/MDIx and current speed. If
1912 * speed is 1000, then determine cable length, local and remote receiver.
1913 **/
1914s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1915{
1916 struct e1000_phy_info *phy = &hw->phy;
1917 s32 ret_val;
1918 u16 phy_data;
1919 bool link;
1920
Bruce Allan0be84012009-12-02 17:03:18 +00001921 if (phy->media_type != e1000_media_type_copper) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001922 e_dbg("Phy info is only valid for copper media\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001923 return -E1000_ERR_CONFIG;
1924 }
1925
1926 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1927 if (ret_val)
1928 return ret_val;
1929
1930 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001931 e_dbg("Phy info is only valid if link is up\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001932 return -E1000_ERR_CONFIG;
1933 }
1934
1935 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1936 if (ret_val)
1937 return ret_val;
1938
1939 phy->polarity_correction = (phy_data &
1940 M88E1000_PSCR_POLARITY_REVERSAL);
1941
1942 ret_val = e1000_check_polarity_m88(hw);
1943 if (ret_val)
1944 return ret_val;
1945
1946 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1951
1952 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1953 ret_val = e1000_get_cable_length(hw);
1954 if (ret_val)
1955 return ret_val;
1956
1957 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1958 if (ret_val)
1959 return ret_val;
1960
1961 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1964
1965 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1968 } else {
1969 /* Set values to "undefined" */
1970 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1971 phy->local_rx = e1000_1000t_rx_status_undefined;
1972 phy->remote_rx = e1000_1000t_rx_status_undefined;
1973 }
1974
1975 return ret_val;
1976}
1977
1978/**
1979 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1980 * @hw: pointer to the HW structure
1981 *
1982 * Read PHY status to determine if link is up. If link is up, then
1983 * set/determine 10base-T extended distance and polarity correction. Read
1984 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1985 * determine on the cable length, local and remote receiver.
1986 **/
1987s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1988{
1989 struct e1000_phy_info *phy = &hw->phy;
1990 s32 ret_val;
1991 u16 data;
1992 bool link;
1993
1994 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1995 if (ret_val)
1996 return ret_val;
1997
1998 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001999 e_dbg("Phy info is only valid if link is up\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07002000 return -E1000_ERR_CONFIG;
2001 }
2002
Bruce Allan564ea9b2009-11-20 23:26:44 +00002003 phy->polarity_correction = true;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002004
2005 ret_val = e1000_check_polarity_igp(hw);
2006 if (ret_val)
2007 return ret_val;
2008
2009 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2010 if (ret_val)
2011 return ret_val;
2012
2013 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2014
2015 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2016 IGP01E1000_PSSR_SPEED_1000MBPS) {
2017 ret_val = e1000_get_cable_length(hw);
2018 if (ret_val)
2019 return ret_val;
2020
2021 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2022 if (ret_val)
2023 return ret_val;
2024
2025 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2026 ? e1000_1000t_rx_status_ok
2027 : e1000_1000t_rx_status_not_ok;
2028
2029 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2030 ? e1000_1000t_rx_status_ok
2031 : e1000_1000t_rx_status_not_ok;
2032 } else {
2033 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2034 phy->local_rx = e1000_1000t_rx_status_undefined;
2035 phy->remote_rx = e1000_1000t_rx_status_undefined;
2036 }
2037
2038 return ret_val;
2039}
2040
2041/**
Bruce Allan0be84012009-12-02 17:03:18 +00002042 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2043 * @hw: pointer to the HW structure
2044 *
2045 * Populates "phy" structure with various feature states.
2046 **/
2047s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2048{
2049 struct e1000_phy_info *phy = &hw->phy;
2050 s32 ret_val;
2051 u16 data;
2052 bool link;
2053
2054 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2055 if (ret_val)
2056 goto out;
2057
2058 if (!link) {
2059 e_dbg("Phy info is only valid if link is up\n");
2060 ret_val = -E1000_ERR_CONFIG;
2061 goto out;
2062 }
2063
2064 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2065 if (ret_val)
2066 goto out;
2067 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2068 ? false : true;
2069
2070 if (phy->polarity_correction) {
2071 ret_val = e1000_check_polarity_ife(hw);
2072 if (ret_val)
2073 goto out;
2074 } else {
2075 /* Polarity is forced */
2076 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2077 ? e1000_rev_polarity_reversed
2078 : e1000_rev_polarity_normal;
2079 }
2080
2081 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2082 if (ret_val)
2083 goto out;
2084
2085 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2086
2087 /* The following parameters are undefined for 10/100 operation. */
2088 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2089 phy->local_rx = e1000_1000t_rx_status_undefined;
2090 phy->remote_rx = e1000_1000t_rx_status_undefined;
2091
2092out:
2093 return ret_val;
2094}
2095
2096/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002097 * e1000e_phy_sw_reset - PHY software reset
2098 * @hw: pointer to the HW structure
2099 *
2100 * Does a software reset of the PHY by reading the PHY control register and
2101 * setting/write the control register reset bit to the PHY.
2102 **/
2103s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2104{
2105 s32 ret_val;
2106 u16 phy_ctrl;
2107
2108 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2109 if (ret_val)
2110 return ret_val;
2111
2112 phy_ctrl |= MII_CR_RESET;
2113 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2114 if (ret_val)
2115 return ret_val;
2116
2117 udelay(1);
2118
2119 return ret_val;
2120}
2121
2122/**
2123 * e1000e_phy_hw_reset_generic - PHY hardware reset
2124 * @hw: pointer to the HW structure
2125 *
2126 * Verify the reset block is not blocking us from resetting. Acquire
2127 * semaphore (if necessary) and read/set/write the device control reset
2128 * bit in the PHY. Wait the appropriate delay time for the device to
Auke Kok489815c2008-02-21 15:11:07 -08002129 * reset and release the semaphore (if necessary).
Auke Kokbc7f75f2007-09-17 12:30:59 -07002130 **/
2131s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2132{
2133 struct e1000_phy_info *phy = &hw->phy;
2134 s32 ret_val;
2135 u32 ctrl;
2136
2137 ret_val = e1000_check_reset_block(hw);
2138 if (ret_val)
2139 return 0;
2140
Bruce Allan94d81862009-11-20 23:25:26 +00002141 ret_val = phy->ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002142 if (ret_val)
2143 return ret_val;
2144
2145 ctrl = er32(CTRL);
2146 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2147 e1e_flush();
2148
2149 udelay(phy->reset_delay_us);
2150
2151 ew32(CTRL, ctrl);
2152 e1e_flush();
2153
2154 udelay(150);
2155
Bruce Allan94d81862009-11-20 23:25:26 +00002156 phy->ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002157
2158 return e1000_get_phy_cfg_done(hw);
2159}
2160
2161/**
2162 * e1000e_get_cfg_done - Generic configuration done
2163 * @hw: pointer to the HW structure
2164 *
2165 * Generic function to wait 10 milli-seconds for configuration to complete
2166 * and return success.
2167 **/
2168s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2169{
2170 mdelay(10);
2171 return 0;
2172}
2173
Bruce Allanf4187b52008-08-26 18:36:50 -07002174/**
2175 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2176 * @hw: pointer to the HW structure
2177 *
2178 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2179 **/
2180s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2181{
Bruce Allan3bb99fe2009-11-20 23:25:07 +00002182 e_dbg("Running IGP 3 PHY init script\n");
Bruce Allanf4187b52008-08-26 18:36:50 -07002183
2184 /* PHY init IGP 3 */
2185 /* Enable rise/fall, 10-mode work in class-A */
2186 e1e_wphy(hw, 0x2F5B, 0x9018);
2187 /* Remove all caps from Replica path filter */
2188 e1e_wphy(hw, 0x2F52, 0x0000);
2189 /* Bias trimming for ADC, AFE and Driver (Default) */
2190 e1e_wphy(hw, 0x2FB1, 0x8B24);
2191 /* Increase Hybrid poly bias */
2192 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2193 /* Add 4% to Tx amplitude in Gig mode */
2194 e1e_wphy(hw, 0x2010, 0x10B0);
2195 /* Disable trimming (TTT) */
2196 e1e_wphy(hw, 0x2011, 0x0000);
2197 /* Poly DC correction to 94.6% + 2% for all channels */
2198 e1e_wphy(hw, 0x20DD, 0x249A);
2199 /* ABS DC correction to 95.9% */
2200 e1e_wphy(hw, 0x20DE, 0x00D3);
2201 /* BG temp curve trim */
2202 e1e_wphy(hw, 0x28B4, 0x04CE);
2203 /* Increasing ADC OPAMP stage 1 currents to max */
2204 e1e_wphy(hw, 0x2F70, 0x29E4);
2205 /* Force 1000 ( required for enabling PHY regs configuration) */
2206 e1e_wphy(hw, 0x0000, 0x0140);
2207 /* Set upd_freq to 6 */
2208 e1e_wphy(hw, 0x1F30, 0x1606);
2209 /* Disable NPDFE */
2210 e1e_wphy(hw, 0x1F31, 0xB814);
2211 /* Disable adaptive fixed FFE (Default) */
2212 e1e_wphy(hw, 0x1F35, 0x002A);
2213 /* Enable FFE hysteresis */
2214 e1e_wphy(hw, 0x1F3E, 0x0067);
2215 /* Fixed FFE for short cable lengths */
2216 e1e_wphy(hw, 0x1F54, 0x0065);
2217 /* Fixed FFE for medium cable lengths */
2218 e1e_wphy(hw, 0x1F55, 0x002A);
2219 /* Fixed FFE for long cable lengths */
2220 e1e_wphy(hw, 0x1F56, 0x002A);
2221 /* Enable Adaptive Clip Threshold */
2222 e1e_wphy(hw, 0x1F72, 0x3FB0);
2223 /* AHT reset limit to 1 */
2224 e1e_wphy(hw, 0x1F76, 0xC0FF);
2225 /* Set AHT master delay to 127 msec */
2226 e1e_wphy(hw, 0x1F77, 0x1DEC);
2227 /* Set scan bits for AHT */
2228 e1e_wphy(hw, 0x1F78, 0xF9EF);
2229 /* Set AHT Preset bits */
2230 e1e_wphy(hw, 0x1F79, 0x0210);
2231 /* Change integ_factor of channel A to 3 */
2232 e1e_wphy(hw, 0x1895, 0x0003);
2233 /* Change prop_factor of channels BCD to 8 */
2234 e1e_wphy(hw, 0x1796, 0x0008);
2235 /* Change cg_icount + enable integbp for channels BCD */
2236 e1e_wphy(hw, 0x1798, 0xD008);
2237 /*
2238 * Change cg_icount + enable integbp + change prop_factor_master
2239 * to 8 for channel A
2240 */
2241 e1e_wphy(hw, 0x1898, 0xD918);
2242 /* Disable AHT in Slave mode on channel A */
2243 e1e_wphy(hw, 0x187A, 0x0800);
2244 /*
2245 * Enable LPLU and disable AN to 1000 in non-D0a states,
2246 * Enable SPD+B2B
2247 */
2248 e1e_wphy(hw, 0x0019, 0x008D);
2249 /* Enable restart AN on an1000_dis change */
2250 e1e_wphy(hw, 0x001B, 0x2080);
2251 /* Enable wh_fifo read clock in 10/100 modes */
2252 e1e_wphy(hw, 0x0014, 0x0045);
2253 /* Restart AN, Speed selection is 1000 */
2254 e1e_wphy(hw, 0x0000, 0x1340);
2255
2256 return 0;
2257}
2258
Auke Kokbc7f75f2007-09-17 12:30:59 -07002259/* Internal function pointers */
2260
2261/**
2262 * e1000_get_phy_cfg_done - Generic PHY configuration done
2263 * @hw: pointer to the HW structure
2264 *
2265 * Return success if silicon family did not implement a family specific
2266 * get_cfg_done function.
2267 **/
2268static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2269{
2270 if (hw->phy.ops.get_cfg_done)
2271 return hw->phy.ops.get_cfg_done(hw);
2272
2273 return 0;
2274}
2275
2276/**
2277 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2278 * @hw: pointer to the HW structure
2279 *
2280 * When the silicon family has not implemented a forced speed/duplex
2281 * function for the PHY, simply return 0.
2282 **/
2283static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2284{
2285 if (hw->phy.ops.force_speed_duplex)
2286 return hw->phy.ops.force_speed_duplex(hw);
2287
2288 return 0;
2289}
2290
2291/**
2292 * e1000e_get_phy_type_from_id - Get PHY type from id
2293 * @phy_id: phy_id read from the phy
2294 *
2295 * Returns the phy type from the id.
2296 **/
2297enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2298{
2299 enum e1000_phy_type phy_type = e1000_phy_unknown;
2300
2301 switch (phy_id) {
2302 case M88E1000_I_PHY_ID:
2303 case M88E1000_E_PHY_ID:
2304 case M88E1111_I_PHY_ID:
2305 case M88E1011_I_PHY_ID:
2306 phy_type = e1000_phy_m88;
2307 break;
2308 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2309 phy_type = e1000_phy_igp_2;
2310 break;
2311 case GG82563_E_PHY_ID:
2312 phy_type = e1000_phy_gg82563;
2313 break;
2314 case IGP03E1000_E_PHY_ID:
2315 phy_type = e1000_phy_igp_3;
2316 break;
2317 case IFE_E_PHY_ID:
2318 case IFE_PLUS_E_PHY_ID:
2319 case IFE_C_E_PHY_ID:
2320 phy_type = e1000_phy_ife;
2321 break;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002322 case BME1000_E_PHY_ID:
2323 case BME1000_E_PHY_ID_R2:
2324 phy_type = e1000_phy_bm;
2325 break;
Bruce Allana4f58f52009-06-02 11:29:18 +00002326 case I82578_E_PHY_ID:
2327 phy_type = e1000_phy_82578;
2328 break;
2329 case I82577_E_PHY_ID:
2330 phy_type = e1000_phy_82577;
2331 break;
Bruce Alland3738bb2010-06-16 13:27:28 +00002332 case I82579_E_PHY_ID:
2333 phy_type = e1000_phy_82579;
2334 break;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002335 default:
2336 phy_type = e1000_phy_unknown;
2337 break;
2338 }
2339 return phy_type;
2340}
2341
2342/**
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002343 * e1000e_determine_phy_address - Determines PHY address.
2344 * @hw: pointer to the HW structure
2345 *
2346 * This uses a trial and error method to loop through possible PHY
2347 * addresses. It tests each by reading the PHY ID registers and
2348 * checking for a match.
2349 **/
2350s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2351{
2352 s32 ret_val = -E1000_ERR_PHY_TYPE;
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002353 u32 phy_addr = 0;
2354 u32 i;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002355 enum e1000_phy_type phy_type = e1000_phy_unknown;
2356
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002357 hw->phy.id = phy_type;
2358
2359 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2360 hw->phy.addr = phy_addr;
2361 i = 0;
2362
2363 do {
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002364 e1000e_get_phy_id(hw);
2365 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2366
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002367 /*
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002368 * If phy_type is valid, break - we found our
2369 * PHY address
2370 */
2371 if (phy_type != e1000_phy_unknown) {
2372 ret_val = 0;
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002373 goto out;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002374 }
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002375 msleep(1);
2376 i++;
2377 } while (i < 10);
2378 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002379
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002380out:
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002381 return ret_val;
2382}
2383
2384/**
2385 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2386 * @page: page to access
2387 *
2388 * Returns the phy address for the page requested.
2389 **/
2390static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2391{
2392 u32 phy_addr = 2;
2393
2394 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2395 phy_addr = 1;
2396
2397 return phy_addr;
2398}
2399
2400/**
2401 * e1000e_write_phy_reg_bm - Write BM PHY register
2402 * @hw: pointer to the HW structure
2403 * @offset: register offset to write to
2404 * @data: data to write at register offset
2405 *
2406 * Acquires semaphore, if necessary, then writes the data to PHY register
2407 * at the offset. Release any acquired semaphores before exiting.
2408 **/
2409s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2410{
2411 s32 ret_val;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002412 u32 page = offset >> IGP_PAGE_SHIFT;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002413
Bruce Allan94d81862009-11-20 23:25:26 +00002414 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002415 if (ret_val)
2416 return ret_val;
2417
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002418 /* Page 800 works differently than the rest so it has its own func */
2419 if (page == BM_WUC_PAGE) {
2420 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2421 false);
2422 goto out;
2423 }
2424
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002425 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2426
2427 if (offset > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan90da0662011-01-06 07:02:53 +00002428 u32 page_shift, page_select;
2429
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002430 /*
2431 * Page select is register 31 for phy address 1 and 22 for
2432 * phy address 2 and 3. Page select is shifted only for
2433 * phy address 1.
2434 */
2435 if (hw->phy.addr == 1) {
2436 page_shift = IGP_PAGE_SHIFT;
2437 page_select = IGP01E1000_PHY_PAGE_SELECT;
2438 } else {
2439 page_shift = 0;
2440 page_select = BM_PHY_PAGE_SELECT;
2441 }
2442
2443 /* Page is shifted left, PHY expects (page x 32) */
2444 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2445 (page << page_shift));
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002446 if (ret_val)
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002447 goto out;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002448 }
2449
2450 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2451 data);
2452
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002453out:
Bruce Allan94d81862009-11-20 23:25:26 +00002454 hw->phy.ops.release(hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002455 return ret_val;
2456}
2457
2458/**
2459 * e1000e_read_phy_reg_bm - Read BM PHY register
2460 * @hw: pointer to the HW structure
2461 * @offset: register offset to be read
2462 * @data: pointer to the read data
2463 *
2464 * Acquires semaphore, if necessary, then reads the PHY register at offset
2465 * and storing the retrieved information in data. Release any acquired
2466 * semaphores before exiting.
2467 **/
2468s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2469{
2470 s32 ret_val;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002471 u32 page = offset >> IGP_PAGE_SHIFT;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002472
Bruce Allan94d81862009-11-20 23:25:26 +00002473 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002474 if (ret_val)
2475 return ret_val;
2476
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002477 /* Page 800 works differently than the rest so it has its own func */
2478 if (page == BM_WUC_PAGE) {
2479 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2480 true);
2481 goto out;
2482 }
2483
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002484 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2485
2486 if (offset > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan90da0662011-01-06 07:02:53 +00002487 u32 page_shift, page_select;
2488
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002489 /*
2490 * Page select is register 31 for phy address 1 and 22 for
2491 * phy address 2 and 3. Page select is shifted only for
2492 * phy address 1.
2493 */
2494 if (hw->phy.addr == 1) {
2495 page_shift = IGP_PAGE_SHIFT;
2496 page_select = IGP01E1000_PHY_PAGE_SELECT;
2497 } else {
2498 page_shift = 0;
2499 page_select = BM_PHY_PAGE_SELECT;
2500 }
2501
2502 /* Page is shifted left, PHY expects (page x 32) */
2503 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2504 (page << page_shift));
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002505 if (ret_val)
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002506 goto out;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002507 }
2508
2509 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2510 data);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002511out:
Bruce Allan94d81862009-11-20 23:25:26 +00002512 hw->phy.ops.release(hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002513 return ret_val;
2514}
2515
2516/**
Bruce Allan4662e822008-08-26 18:37:06 -07002517 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2518 * @hw: pointer to the HW structure
2519 * @offset: register offset to be read
2520 * @data: pointer to the read data
2521 *
2522 * Acquires semaphore, if necessary, then reads the PHY register at offset
2523 * and storing the retrieved information in data. Release any acquired
2524 * semaphores before exiting.
2525 **/
2526s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2527{
2528 s32 ret_val;
2529 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2530
Bruce Allan94d81862009-11-20 23:25:26 +00002531 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002532 if (ret_val)
2533 return ret_val;
2534
Bruce Allan4662e822008-08-26 18:37:06 -07002535 /* Page 800 works differently than the rest so it has its own func */
2536 if (page == BM_WUC_PAGE) {
2537 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2538 true);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002539 goto out;
Bruce Allan4662e822008-08-26 18:37:06 -07002540 }
2541
Bruce Allan4662e822008-08-26 18:37:06 -07002542 hw->phy.addr = 1;
2543
2544 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2545
2546 /* Page is shifted left, PHY expects (page x 32) */
2547 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2548 page);
2549
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002550 if (ret_val)
2551 goto out;
Bruce Allan4662e822008-08-26 18:37:06 -07002552 }
2553
2554 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2555 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002556out:
Bruce Allan94d81862009-11-20 23:25:26 +00002557 hw->phy.ops.release(hw);
Bruce Allan4662e822008-08-26 18:37:06 -07002558 return ret_val;
2559}
2560
2561/**
2562 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2563 * @hw: pointer to the HW structure
2564 * @offset: register offset to write to
2565 * @data: data to write at register offset
2566 *
2567 * Acquires semaphore, if necessary, then writes the data to PHY register
2568 * at the offset. Release any acquired semaphores before exiting.
2569 **/
2570s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2571{
2572 s32 ret_val;
2573 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2574
Bruce Allan94d81862009-11-20 23:25:26 +00002575 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002576 if (ret_val)
2577 return ret_val;
2578
Bruce Allan4662e822008-08-26 18:37:06 -07002579 /* Page 800 works differently than the rest so it has its own func */
2580 if (page == BM_WUC_PAGE) {
2581 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2582 false);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002583 goto out;
Bruce Allan4662e822008-08-26 18:37:06 -07002584 }
2585
Bruce Allan4662e822008-08-26 18:37:06 -07002586 hw->phy.addr = 1;
2587
2588 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2589 /* Page is shifted left, PHY expects (page x 32) */
2590 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2591 page);
2592
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002593 if (ret_val)
2594 goto out;
Bruce Allan4662e822008-08-26 18:37:06 -07002595 }
2596
2597 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2598 data);
2599
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002600out:
Bruce Allan94d81862009-11-20 23:25:26 +00002601 hw->phy.ops.release(hw);
Bruce Allan4662e822008-08-26 18:37:06 -07002602 return ret_val;
2603}
2604
2605/**
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002606 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2607 * @hw: pointer to the HW structure
2608 * @offset: register offset to be read or written
2609 * @data: pointer to the data to read or write
2610 * @read: determines if operation is read or write
2611 *
2612 * Acquires semaphore, if necessary, then reads the PHY register at offset
2613 * and storing the retrieved information in data. Release any acquired
2614 * semaphores before exiting. Note that procedure to read the wakeup
2615 * registers are different. It works as such:
2616 * 1) Set page 769, register 17, bit 2 = 1
2617 * 2) Set page to 800 for host (801 if we were manageability)
2618 * 3) Write the address using the address opcode (0x11)
2619 * 4) Read or write the data using the data opcode (0x12)
2620 * 5) Restore 769_17.2 to its original value
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002621 *
2622 * Assumes semaphore already acquired.
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002623 **/
2624static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2625 u16 *data, bool read)
2626{
2627 s32 ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00002628 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002629 u16 phy_reg = 0;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002630
Bruce Allana4f58f52009-06-02 11:29:18 +00002631 /* Gig must be disabled for MDIO accesses to page 800 */
2632 if ((hw->mac.type == e1000_pchlan) &&
2633 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
Bruce Allan9b71b412009-12-01 15:53:07 +00002634 e_dbg("Attempting to access page 800 while gig enabled.\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00002635
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002636 /* All operations in this function are phy address 1 */
2637 hw->phy.addr = 1;
2638
2639 /* Set page 769 */
2640 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2641 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2642
2643 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
Bruce Allan9b71b412009-12-01 15:53:07 +00002644 if (ret_val) {
2645 e_dbg("Could not read PHY page 769\n");
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002646 goto out;
Bruce Allan9b71b412009-12-01 15:53:07 +00002647 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002648
2649 /* First clear bit 4 to avoid a power state change */
2650 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2651 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
Bruce Allan9b71b412009-12-01 15:53:07 +00002652 if (ret_val) {
2653 e_dbg("Could not clear PHY page 769 bit 4\n");
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002654 goto out;
Bruce Allan9b71b412009-12-01 15:53:07 +00002655 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002656
2657 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2658 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2659 phy_reg | BM_WUC_ENABLE_BIT);
Bruce Allan9b71b412009-12-01 15:53:07 +00002660 if (ret_val) {
2661 e_dbg("Could not write PHY page 769 bit 2\n");
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002662 goto out;
Bruce Allan9b71b412009-12-01 15:53:07 +00002663 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002664
2665 /* Select page 800 */
2666 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2667 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2668
2669 /* Write the page 800 offset value using opcode 0x11 */
2670 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
Bruce Allan9b71b412009-12-01 15:53:07 +00002671 if (ret_val) {
2672 e_dbg("Could not write address opcode to page 800\n");
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002673 goto out;
Bruce Allan9b71b412009-12-01 15:53:07 +00002674 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002675
2676 if (read) {
2677 /* Read the page 800 value using opcode 0x12 */
2678 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2679 data);
2680 } else {
Bruce Allan5ff5b662009-12-01 15:51:11 +00002681 /* Write the page 800 value using opcode 0x12 */
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002682 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2683 *data);
2684 }
2685
Bruce Allan9b71b412009-12-01 15:53:07 +00002686 if (ret_val) {
2687 e_dbg("Could not access data value from page 800\n");
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002688 goto out;
Bruce Allan9b71b412009-12-01 15:53:07 +00002689 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002690
2691 /*
2692 * Restore 769_17.2 to its original value
2693 * Set page 769
2694 */
2695 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2696 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2697
2698 /* Clear 769_17.2 */
2699 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
Bruce Allan9b71b412009-12-01 15:53:07 +00002700 if (ret_val) {
2701 e_dbg("Could not clear PHY page 769 bit 2\n");
2702 goto out;
2703 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002704
2705out:
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002706 return ret_val;
2707}
2708
2709/**
Bruce Allan17f208d2009-12-01 15:47:22 +00002710 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2711 * @hw: pointer to the HW structure
2712 *
2713 * In the case of a PHY power down to save power, or to turn off link during a
2714 * driver unload, or wake on lan is not enabled, restore the link to previous
2715 * settings.
2716 **/
2717void e1000_power_up_phy_copper(struct e1000_hw *hw)
2718{
2719 u16 mii_reg = 0;
2720
2721 /* The PHY will retain its settings across a power down/up cycle */
2722 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2723 mii_reg &= ~MII_CR_POWER_DOWN;
2724 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2725}
2726
2727/**
2728 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2729 * @hw: pointer to the HW structure
2730 *
2731 * In the case of a PHY power down to save power, or to turn off link during a
2732 * driver unload, or wake on lan is not enabled, restore the link to previous
2733 * settings.
2734 **/
2735void e1000_power_down_phy_copper(struct e1000_hw *hw)
2736{
2737 u16 mii_reg = 0;
2738
2739 /* The PHY will retain its settings across a power down/up cycle */
2740 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2741 mii_reg |= MII_CR_POWER_DOWN;
2742 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2743 msleep(1);
2744}
2745
2746/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002747 * e1000e_commit_phy - Soft PHY reset
2748 * @hw: pointer to the HW structure
2749 *
2750 * Performs a soft PHY reset on those that apply. This is a function pointer
2751 * entry point called by drivers.
2752 **/
2753s32 e1000e_commit_phy(struct e1000_hw *hw)
2754{
Bruce Allan94d81862009-11-20 23:25:26 +00002755 if (hw->phy.ops.commit)
2756 return hw->phy.ops.commit(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002757
2758 return 0;
2759}
2760
2761/**
2762 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2763 * @hw: pointer to the HW structure
2764 * @active: boolean used to enable/disable lplu
2765 *
2766 * Success returns 0, Failure returns 1
2767 *
2768 * The low power link up (lplu) state is set to the power management level D0
2769 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2770 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2771 * is used during Dx states where the power conservation is most important.
2772 * During driver activity, SmartSpeed should be enabled so performance is
2773 * maintained. This is a function pointer entry point called by drivers.
2774 **/
2775static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2776{
2777 if (hw->phy.ops.set_d0_lplu_state)
2778 return hw->phy.ops.set_d0_lplu_state(hw, active);
2779
2780 return 0;
2781}
Bruce Allana4f58f52009-06-02 11:29:18 +00002782
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002783/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002784 * __e1000_read_phy_reg_hv - Read HV PHY register
Bruce Allana4f58f52009-06-02 11:29:18 +00002785 * @hw: pointer to the HW structure
2786 * @offset: register offset to be read
2787 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002788 * @locked: semaphore has already been acquired or not
Bruce Allana4f58f52009-06-02 11:29:18 +00002789 *
2790 * Acquires semaphore, if necessary, then reads the PHY register at offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002791 * and stores the retrieved information in data. Release any acquired
Bruce Allana4f58f52009-06-02 11:29:18 +00002792 * semaphore before exiting.
2793 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002794static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2795 bool locked)
Bruce Allana4f58f52009-06-02 11:29:18 +00002796{
2797 s32 ret_val;
2798 u16 page = BM_PHY_REG_PAGE(offset);
2799 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allana4f58f52009-06-02 11:29:18 +00002800
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002801 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +00002802 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002803 if (ret_val)
2804 return ret_val;
2805 }
2806
Bruce Allana4f58f52009-06-02 11:29:18 +00002807 /* Page 800 works differently than the rest so it has its own func */
2808 if (page == BM_WUC_PAGE) {
2809 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2810 data, true);
2811 goto out;
2812 }
2813
2814 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2815 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2816 data, true);
2817 goto out;
2818 }
2819
Bruce Allana4f58f52009-06-02 11:29:18 +00002820 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2821
2822 if (page == HV_INTC_FC_PAGE_START)
2823 page = 0;
2824
2825 if (reg > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan842ec8b2009-11-19 12:34:40 +00002826 u32 phy_addr = hw->phy.addr;
Bruce Allana4f58f52009-06-02 11:29:18 +00002827
Bruce Allan842ec8b2009-11-19 12:34:40 +00002828 hw->phy.addr = 1;
Bruce Allana4f58f52009-06-02 11:29:18 +00002829
Bruce Allan842ec8b2009-11-19 12:34:40 +00002830 /* Page is shifted left, PHY expects (page x 32) */
2831 ret_val = e1000e_write_phy_reg_mdic(hw,
2832 IGP01E1000_PHY_PAGE_SELECT,
2833 (page << IGP_PAGE_SHIFT));
2834 hw->phy.addr = phy_addr;
2835
2836 if (ret_val)
2837 goto out;
Bruce Allana4f58f52009-06-02 11:29:18 +00002838 }
2839
2840 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2841 data);
Bruce Allana4f58f52009-06-02 11:29:18 +00002842out:
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002843 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +00002844 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002845
Bruce Allana4f58f52009-06-02 11:29:18 +00002846 return ret_val;
2847}
2848
2849/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002850 * e1000_read_phy_reg_hv - Read HV PHY register
2851 * @hw: pointer to the HW structure
2852 * @offset: register offset to be read
2853 * @data: pointer to the read data
2854 *
2855 * Acquires semaphore then reads the PHY register at offset and stores
2856 * the retrieved information in data. Release the acquired semaphore
2857 * before exiting.
2858 **/
2859s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2860{
2861 return __e1000_read_phy_reg_hv(hw, offset, data, false);
2862}
2863
2864/**
2865 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2866 * @hw: pointer to the HW structure
2867 * @offset: register offset to be read
2868 * @data: pointer to the read data
2869 *
2870 * Reads the PHY register at offset and stores the retrieved information
2871 * in data. Assumes semaphore already acquired.
2872 **/
2873s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2874{
2875 return __e1000_read_phy_reg_hv(hw, offset, data, true);
2876}
2877
2878/**
2879 * __e1000_write_phy_reg_hv - Write HV PHY register
Bruce Allana4f58f52009-06-02 11:29:18 +00002880 * @hw: pointer to the HW structure
2881 * @offset: register offset to write to
2882 * @data: data to write at register offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002883 * @locked: semaphore has already been acquired or not
Bruce Allana4f58f52009-06-02 11:29:18 +00002884 *
2885 * Acquires semaphore, if necessary, then writes the data to PHY register
2886 * at the offset. Release any acquired semaphores before exiting.
2887 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002888static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2889 bool locked)
Bruce Allana4f58f52009-06-02 11:29:18 +00002890{
2891 s32 ret_val;
2892 u16 page = BM_PHY_REG_PAGE(offset);
2893 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allana4f58f52009-06-02 11:29:18 +00002894
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002895 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +00002896 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002897 if (ret_val)
2898 return ret_val;
2899 }
2900
Bruce Allana4f58f52009-06-02 11:29:18 +00002901 /* Page 800 works differently than the rest so it has its own func */
2902 if (page == BM_WUC_PAGE) {
2903 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2904 &data, false);
2905 goto out;
2906 }
2907
2908 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2909 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2910 &data, false);
2911 goto out;
2912 }
2913
Bruce Allana4f58f52009-06-02 11:29:18 +00002914 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2915
2916 if (page == HV_INTC_FC_PAGE_START)
2917 page = 0;
2918
2919 /*
2920 * Workaround MDIO accesses being disabled after entering IEEE Power
2921 * Down (whenever bit 11 of the PHY Control register is set)
2922 */
2923 if ((hw->phy.type == e1000_phy_82578) &&
2924 (hw->phy.revision >= 1) &&
2925 (hw->phy.addr == 2) &&
2926 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2927 (data & (1 << 11))) {
2928 u16 data2 = 0x7EFF;
Bruce Allana4f58f52009-06-02 11:29:18 +00002929 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
2930 &data2, false);
2931 if (ret_val)
2932 goto out;
Bruce Allana4f58f52009-06-02 11:29:18 +00002933 }
2934
2935 if (reg > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan842ec8b2009-11-19 12:34:40 +00002936 u32 phy_addr = hw->phy.addr;
Bruce Allana4f58f52009-06-02 11:29:18 +00002937
Bruce Allan842ec8b2009-11-19 12:34:40 +00002938 hw->phy.addr = 1;
Bruce Allana4f58f52009-06-02 11:29:18 +00002939
Bruce Allan842ec8b2009-11-19 12:34:40 +00002940 /* Page is shifted left, PHY expects (page x 32) */
2941 ret_val = e1000e_write_phy_reg_mdic(hw,
2942 IGP01E1000_PHY_PAGE_SELECT,
2943 (page << IGP_PAGE_SHIFT));
2944 hw->phy.addr = phy_addr;
2945
2946 if (ret_val)
2947 goto out;
Bruce Allana4f58f52009-06-02 11:29:18 +00002948 }
2949
2950 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2951 data);
Bruce Allana4f58f52009-06-02 11:29:18 +00002952
2953out:
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002954 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +00002955 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002956
Bruce Allana4f58f52009-06-02 11:29:18 +00002957 return ret_val;
2958}
2959
2960/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002961 * e1000_write_phy_reg_hv - Write HV PHY register
2962 * @hw: pointer to the HW structure
2963 * @offset: register offset to write to
2964 * @data: data to write at register offset
2965 *
2966 * Acquires semaphore then writes the data to PHY register at the offset.
2967 * Release the acquired semaphores before exiting.
2968 **/
2969s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2970{
2971 return __e1000_write_phy_reg_hv(hw, offset, data, false);
2972}
2973
2974/**
2975 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2976 * @hw: pointer to the HW structure
2977 * @offset: register offset to write to
2978 * @data: data to write at register offset
2979 *
2980 * Writes the data to PHY register at the offset. Assumes semaphore
2981 * already acquired.
2982 **/
2983s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2984{
2985 return __e1000_write_phy_reg_hv(hw, offset, data, true);
2986}
2987
2988/**
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04002989 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
Bruce Allana4f58f52009-06-02 11:29:18 +00002990 * @page: page to be accessed
2991 **/
2992static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2993{
2994 u32 phy_addr = 2;
2995
2996 if (page >= HV_INTC_FC_PAGE_START)
2997 phy_addr = 1;
2998
2999 return phy_addr;
3000}
3001
3002/**
3003 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3004 * @hw: pointer to the HW structure
3005 * @offset: register offset to be read or written
3006 * @data: pointer to the data to be read or written
3007 * @read: determines if operation is read or written
3008 *
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003009 * Reads the PHY register at offset and stores the retreived information
3010 * in data. Assumes semaphore already acquired. Note that the procedure
3011 * to read these regs uses the address port and data port to read/write.
Bruce Allana4f58f52009-06-02 11:29:18 +00003012 **/
3013static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3014 u16 *data, bool read)
3015{
3016 s32 ret_val;
3017 u32 addr_reg = 0;
3018 u32 data_reg = 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003019
3020 /* This takes care of the difference with desktop vs mobile phy */
3021 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3022 I82578_ADDR_REG : I82577_ADDR_REG;
3023 data_reg = addr_reg + 1;
3024
Bruce Allana4f58f52009-06-02 11:29:18 +00003025 /* All operations in this function are phy address 2 */
3026 hw->phy.addr = 2;
3027
3028 /* masking with 0x3F to remove the page from offset */
3029 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3030 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003031 e_dbg("Could not write PHY the HV address register\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003032 goto out;
3033 }
3034
3035 /* Read or write the data value next */
3036 if (read)
3037 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3038 else
3039 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3040
3041 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003042 e_dbg("Could not read data value from HV data register\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003043 goto out;
3044 }
3045
3046out:
Bruce Allana4f58f52009-06-02 11:29:18 +00003047 return ret_val;
3048}
3049
3050/**
3051 * e1000_link_stall_workaround_hv - Si workaround
3052 * @hw: pointer to the HW structure
3053 *
3054 * This function works around a Si bug where the link partner can get
3055 * a link up indication before the PHY does. If small packets are sent
3056 * by the link partner they can be placed in the packet buffer without
3057 * being properly accounted for by the PHY and will stall preventing
3058 * further packets from being received. The workaround is to clear the
3059 * packet buffer after the PHY detects link up.
3060 **/
3061s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3062{
3063 s32 ret_val = 0;
3064 u16 data;
3065
3066 if (hw->phy.type != e1000_phy_82578)
3067 goto out;
3068
Bruce Allane65fa872009-07-01 13:27:31 +00003069 /* Do not apply workaround if in PHY loopback bit 14 set */
Bruce Allan482fed82011-01-06 14:29:49 +00003070 e1e_rphy(hw, PHY_CONTROL, &data);
Bruce Allane65fa872009-07-01 13:27:31 +00003071 if (data & PHY_CONTROL_LB)
3072 goto out;
3073
Bruce Allana4f58f52009-06-02 11:29:18 +00003074 /* check if link is up and at 1Gbps */
Bruce Allan482fed82011-01-06 14:29:49 +00003075 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003076 if (ret_val)
3077 goto out;
3078
3079 data &= BM_CS_STATUS_LINK_UP |
3080 BM_CS_STATUS_RESOLVED |
3081 BM_CS_STATUS_SPEED_MASK;
3082
3083 if (data != (BM_CS_STATUS_LINK_UP |
3084 BM_CS_STATUS_RESOLVED |
3085 BM_CS_STATUS_SPEED_1000))
3086 goto out;
3087
3088 mdelay(200);
3089
3090 /* flush the packets in the fifo buffer */
Bruce Allan482fed82011-01-06 14:29:49 +00003091 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3092 HV_MUX_DATA_CTRL_FORCE_SPEED);
Bruce Allana4f58f52009-06-02 11:29:18 +00003093 if (ret_val)
3094 goto out;
3095
Bruce Allan482fed82011-01-06 14:29:49 +00003096 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
Bruce Allana4f58f52009-06-02 11:29:18 +00003097
3098out:
3099 return ret_val;
3100}
3101
3102/**
3103 * e1000_check_polarity_82577 - Checks the polarity.
3104 * @hw: pointer to the HW structure
3105 *
3106 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3107 *
3108 * Polarity is determined based on the PHY specific status register.
3109 **/
3110s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3111{
3112 struct e1000_phy_info *phy = &hw->phy;
3113 s32 ret_val;
3114 u16 data;
3115
Bruce Allan482fed82011-01-06 14:29:49 +00003116 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003117
3118 if (!ret_val)
3119 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3120 ? e1000_rev_polarity_reversed
3121 : e1000_rev_polarity_normal;
3122
3123 return ret_val;
3124}
3125
3126/**
3127 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3128 * @hw: pointer to the HW structure
3129 *
Bruce Allaneab50ff2010-05-10 15:01:30 +00003130 * Calls the PHY setup function to force speed and duplex.
Bruce Allana4f58f52009-06-02 11:29:18 +00003131 **/
3132s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3133{
3134 struct e1000_phy_info *phy = &hw->phy;
3135 s32 ret_val;
3136 u16 phy_data;
3137 bool link;
3138
Bruce Allan482fed82011-01-06 14:29:49 +00003139 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003140 if (ret_val)
3141 goto out;
3142
3143 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3144
Bruce Allan482fed82011-01-06 14:29:49 +00003145 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003146 if (ret_val)
3147 goto out;
3148
Bruce Allana4f58f52009-06-02 11:29:18 +00003149 udelay(1);
3150
3151 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003152 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003153
3154 ret_val = e1000e_phy_has_link_generic(hw,
3155 PHY_FORCE_LIMIT,
3156 100000,
3157 &link);
3158 if (ret_val)
3159 goto out;
3160
3161 if (!link)
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003162 e_dbg("Link taking longer than expected.\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003163
3164 /* Try once more */
3165 ret_val = e1000e_phy_has_link_generic(hw,
3166 PHY_FORCE_LIMIT,
3167 100000,
3168 &link);
3169 if (ret_val)
3170 goto out;
3171 }
3172
3173out:
3174 return ret_val;
3175}
3176
3177/**
3178 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3179 * @hw: pointer to the HW structure
3180 *
3181 * Read PHY status to determine if link is up. If link is up, then
3182 * set/determine 10base-T extended distance and polarity correction. Read
3183 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3184 * determine on the cable length, local and remote receiver.
3185 **/
3186s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3187{
3188 struct e1000_phy_info *phy = &hw->phy;
3189 s32 ret_val;
3190 u16 data;
3191 bool link;
3192
3193 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3194 if (ret_val)
3195 goto out;
3196
3197 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003198 e_dbg("Phy info is only valid if link is up\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003199 ret_val = -E1000_ERR_CONFIG;
3200 goto out;
3201 }
3202
3203 phy->polarity_correction = true;
3204
3205 ret_val = e1000_check_polarity_82577(hw);
3206 if (ret_val)
3207 goto out;
3208
Bruce Allan482fed82011-01-06 14:29:49 +00003209 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003210 if (ret_val)
3211 goto out;
3212
3213 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3214
3215 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3216 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3217 ret_val = hw->phy.ops.get_cable_length(hw);
3218 if (ret_val)
3219 goto out;
3220
Bruce Allan482fed82011-01-06 14:29:49 +00003221 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003222 if (ret_val)
3223 goto out;
3224
3225 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3226 ? e1000_1000t_rx_status_ok
3227 : e1000_1000t_rx_status_not_ok;
3228
3229 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3230 ? e1000_1000t_rx_status_ok
3231 : e1000_1000t_rx_status_not_ok;
3232 } else {
3233 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3234 phy->local_rx = e1000_1000t_rx_status_undefined;
3235 phy->remote_rx = e1000_1000t_rx_status_undefined;
3236 }
3237
3238out:
3239 return ret_val;
3240}
3241
3242/**
3243 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3244 * @hw: pointer to the HW structure
3245 *
3246 * Reads the diagnostic status register and verifies result is valid before
3247 * placing it in the phy_cable_length field.
3248 **/
3249s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3250{
3251 struct e1000_phy_info *phy = &hw->phy;
3252 s32 ret_val;
3253 u16 phy_data, length;
3254
Bruce Allan482fed82011-01-06 14:29:49 +00003255 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003256 if (ret_val)
3257 goto out;
3258
3259 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3260 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3261
3262 if (length == E1000_CABLE_LENGTH_UNDEFINED)
Bruce Allan98086a92009-11-20 23:23:53 +00003263 ret_val = -E1000_ERR_PHY;
Bruce Allana4f58f52009-06-02 11:29:18 +00003264
3265 phy->cable_length = length;
3266
3267out:
3268 return ret_val;
3269}