Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.h |
| 3 | * |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2009 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 18 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 19 | #include <plat/clock.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 20 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
| 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 |
| 23 | |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 24 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
| 25 | #define CORE_CLK_SRC_32K 0x0 |
| 26 | #define CORE_CLK_SRC_DPLL 0x1 |
| 27 | #define CORE_CLK_SRC_DPLL_X2 0x2 |
| 28 | |
| 29 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ |
| 30 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 |
| 31 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 |
| 32 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 |
| 33 | |
| 34 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 35 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 |
| 36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 |
| 37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
| 38 | |
Rajendra Nayak | 16975a7 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 39 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 40 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 |
| 41 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 |
| 42 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 |
| 43 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 |
| 44 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 45 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 46 | #define DPLL_LOW_POWER_STOP 0x1 |
| 47 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 48 | #define DPLL_LOCKED 0x7 |
| 49 | |
Tony Lindgren | 646e3ed | 2008-10-06 15:49:36 +0300 | [diff] [blame] | 50 | int omap2_clk_init(void); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 51 | int omap2_clk_enable(struct clk *clk); |
| 52 | void omap2_clk_disable(struct clk *clk); |
| 53 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 54 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 55 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
Paul Walmsley | fecb494 | 2009-01-27 19:12:50 -0700 | [diff] [blame] | 56 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 57 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 58 | unsigned long omap3_dpll_recalc(struct clk *clk); |
| 59 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); |
| 60 | void omap3_dpll_allow_idle(struct clk *clk); |
| 61 | void omap3_dpll_deny_idle(struct clk *clk); |
| 62 | u32 omap3_dpll_autoidle_read(struct clk *clk); |
| 63 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 64 | int omap3_noncore_dpll_enable(struct clk *clk); |
| 65 | void omap3_noncore_dpll_disable(struct clk *clk); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 66 | |
| 67 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 68 | void omap2_clk_disable_unused(struct clk *clk); |
| 69 | #else |
| 70 | #define omap2_clk_disable_unused NULL |
| 71 | #endif |
| 72 | |
Russell King | 8b9dbc1 | 2009-02-12 10:12:59 +0000 | [diff] [blame] | 73 | unsigned long omap2_clksel_recalc(struct clk *clk); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 74 | void omap2_init_clk_clkdm(struct clk *clk); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 75 | void omap2_init_clksel_parent(struct clk *clk); |
| 76 | u32 omap2_clksel_get_divisor(struct clk *clk); |
| 77 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 78 | u32 *new_div); |
| 79 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 80 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
Russell King | 8b9dbc1 | 2009-02-12 10:12:59 +0000 | [diff] [blame] | 81 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 82 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 83 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
| 84 | u32 omap2_get_dpll_rate(struct clk *clk); |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame^] | 85 | void omap2_init_dpll_parent(struct clk *clk); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 86 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
Tony Lindgren | ff00fcc | 2008-07-03 12:24:44 +0300 | [diff] [blame] | 87 | void omap2_clk_prepare_for_reboot(void); |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 88 | int omap2_dflt_clk_enable(struct clk *clk); |
| 89 | void omap2_dflt_clk_disable(struct clk *clk); |
| 90 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
| 91 | u8 *other_bit); |
| 92 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
| 93 | u8 *idlest_bit); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 94 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 95 | extern u8 cpu_mask; |
| 96 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 97 | extern const struct clkops clkops_omap2_dflt_wait; |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 98 | extern const struct clkops clkops_omap2_dflt; |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 99 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 100 | extern struct clk_functions omap2_clk_functions; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 101 | extern struct clk *vclk, *sclk; |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 102 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 103 | extern const struct clksel_rate gpt_32k_rates[]; |
| 104 | extern const struct clksel_rate gpt_sys_rates[]; |
| 105 | extern const struct clksel_rate gfx_l3_rates[]; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 106 | |
| 107 | |
| 108 | #endif |