Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "drm_crtc.h" |
| 33 | #include "drm_crtc_helper.h" |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 34 | #include "drm_edid.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "intel_drv.h" |
| 36 | #include "i915_drm.h" |
| 37 | #include "i915_drv.h" |
| 38 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 39 | /* Here's the desired hotplug mode */ |
| 40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
| 41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
| 42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
| 43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
| 44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
| 45 | ADPA_CRT_HOTPLUG_ENABLE) |
| 46 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 47 | struct intel_crt { |
| 48 | struct intel_encoder base; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 49 | bool force_hotplug_required; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 50 | u32 adpa_reg; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| 54 | { |
| 55 | return container_of(intel_attached_encoder(connector), |
| 56 | struct intel_crt, base); |
| 57 | } |
| 58 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 59 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
| 60 | { |
| 61 | return container_of(encoder, struct intel_crt, base); |
| 62 | } |
| 63 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 64 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
| 65 | enum pipe *pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 66 | { |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 67 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 68 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 69 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 70 | u32 tmp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 71 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 72 | tmp = I915_READ(crt->adpa_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 73 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 74 | if (!(tmp & ADPA_DAC_ENABLE)) |
| 75 | return false; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 76 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 77 | if (HAS_PCH_CPT(dev)) |
| 78 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 79 | else |
| 80 | *pipe = PORT_TO_PIPE(tmp); |
| 81 | |
| 82 | return true; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 83 | } |
| 84 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 85 | static void intel_disable_crt(struct intel_encoder *encoder) |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 86 | { |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 87 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 88 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 89 | u32 temp; |
| 90 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 91 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 92 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
ling.ma@intel.com | febc769 | 2009-06-25 11:55:57 +0800 | [diff] [blame] | 93 | temp &= ~ADPA_DAC_ENABLE; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 94 | I915_WRITE(crt->adpa_reg, temp); |
| 95 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 96 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 97 | static void intel_enable_crt(struct intel_encoder *encoder) |
| 98 | { |
| 99 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 100 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 101 | u32 temp; |
| 102 | |
| 103 | temp = I915_READ(crt->adpa_reg); |
| 104 | temp |= ADPA_DAC_ENABLE; |
| 105 | I915_WRITE(crt->adpa_reg, temp); |
| 106 | } |
| 107 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 108 | /* Note: The caller is required to filter out dpms modes not supported by the |
| 109 | * platform. */ |
| 110 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 111 | { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 112 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 113 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 114 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 115 | u32 temp; |
| 116 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 117 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 118 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
| 119 | temp &= ~ADPA_DAC_ENABLE; |
Jesse Barnes | bd9e841 | 2012-06-15 11:55:18 -0700 | [diff] [blame] | 120 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 121 | switch (mode) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 122 | case DRM_MODE_DPMS_ON: |
| 123 | temp |= ADPA_DAC_ENABLE; |
| 124 | break; |
| 125 | case DRM_MODE_DPMS_STANDBY: |
| 126 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
| 127 | break; |
| 128 | case DRM_MODE_DPMS_SUSPEND: |
| 129 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 130 | break; |
| 131 | case DRM_MODE_DPMS_OFF: |
| 132 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 133 | break; |
| 134 | } |
| 135 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 136 | I915_WRITE(crt->adpa_reg, temp); |
| 137 | } |
| 138 | |
| 139 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
| 140 | { |
| 141 | struct drm_device *dev = connector->dev; |
| 142 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
| 143 | struct drm_crtc *crtc; |
| 144 | int old_dpms; |
| 145 | |
| 146 | /* PCH platforms and VLV only support on/off. */ |
| 147 | if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) |
| 148 | mode = DRM_MODE_DPMS_OFF; |
| 149 | |
| 150 | if (mode == connector->dpms) |
| 151 | return; |
| 152 | |
| 153 | old_dpms = connector->dpms; |
| 154 | connector->dpms = mode; |
| 155 | |
| 156 | /* Only need to change hw state when actually enabled */ |
| 157 | crtc = encoder->base.crtc; |
| 158 | if (!crtc) { |
| 159 | encoder->connectors_active = false; |
| 160 | return; |
| 161 | } |
| 162 | |
| 163 | /* We need the pipe to run for anything but OFF. */ |
| 164 | if (mode == DRM_MODE_DPMS_OFF) |
| 165 | encoder->connectors_active = false; |
| 166 | else |
| 167 | encoder->connectors_active = true; |
| 168 | |
| 169 | if (mode < old_dpms) { |
| 170 | /* From off to on, enable the pipe first. */ |
| 171 | intel_crtc_update_dpms(crtc); |
| 172 | |
| 173 | intel_crt_set_dpms(encoder, mode); |
| 174 | } else { |
| 175 | intel_crt_set_dpms(encoder, mode); |
| 176 | |
| 177 | intel_crtc_update_dpms(crtc); |
| 178 | } |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 179 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 180 | intel_modeset_check_state(connector->dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static int intel_crt_mode_valid(struct drm_connector *connector, |
| 184 | struct drm_display_mode *mode) |
| 185 | { |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 186 | struct drm_device *dev = connector->dev; |
| 187 | |
| 188 | int max_clock = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 189 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 190 | return MODE_NO_DBLESCAN; |
| 191 | |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 192 | if (mode->clock < 25000) |
| 193 | return MODE_CLOCK_LOW; |
| 194 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 195 | if (IS_GEN2(dev)) |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 196 | max_clock = 350000; |
| 197 | else |
| 198 | max_clock = 400000; |
| 199 | if (mode->clock > max_clock) |
| 200 | return MODE_CLOCK_HIGH; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 201 | |
| 202 | return MODE_OK; |
| 203 | } |
| 204 | |
| 205 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 206 | const struct drm_display_mode *mode, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 207 | struct drm_display_mode *adjusted_mode) |
| 208 | { |
| 209 | return true; |
| 210 | } |
| 211 | |
| 212 | static void intel_crt_mode_set(struct drm_encoder *encoder, |
| 213 | struct drm_display_mode *mode, |
| 214 | struct drm_display_mode *adjusted_mode) |
| 215 | { |
| 216 | |
| 217 | struct drm_device *dev = encoder->dev; |
| 218 | struct drm_crtc *crtc = encoder->crtc; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 219 | struct intel_crt *crt = |
| 220 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 222 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 223 | int dpll_md_reg; |
| 224 | u32 adpa, dpll_md; |
| 225 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 226 | dpll_md_reg = DPLL_MD(intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * Disable separate mode multiplier used when cloning SDVO to CRT |
| 230 | * XXX this needs to be adjusted when we really are cloning |
| 231 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 232 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 233 | dpll_md = I915_READ(dpll_md_reg); |
| 234 | I915_WRITE(dpll_md_reg, |
| 235 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); |
| 236 | } |
| 237 | |
Daniel Vetter | 912d812 | 2012-10-11 20:08:23 +0200 | [diff] [blame^] | 238 | if (HAS_PCH_SPLIT(dev)) |
| 239 | adpa = ADPA_HOTPLUG_BITS; |
| 240 | else |
| 241 | adpa = 0; |
| 242 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 243 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 244 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
| 245 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 246 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
| 247 | |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 248 | /* For CPT allow 3 pipe config, for others just use A or B */ |
| 249 | if (HAS_PCH_CPT(dev)) |
| 250 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 251 | else if (intel_crtc->pipe == 0) |
| 252 | adpa |= ADPA_PIPE_A_SELECT; |
| 253 | else |
| 254 | adpa |= ADPA_PIPE_B_SELECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 255 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 256 | if (!HAS_PCH_SPLIT(dev)) |
| 257 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); |
| 258 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 259 | I915_WRITE(crt->adpa_reg, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 260 | } |
| 261 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 262 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 263 | { |
| 264 | struct drm_device *dev = connector->dev; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 265 | struct intel_crt *crt = intel_attached_crt(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 266 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 267 | u32 adpa; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 268 | bool ret; |
| 269 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 270 | /* The first time through, trigger an explicit detection cycle */ |
| 271 | if (crt->force_hotplug_required) { |
| 272 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
| 273 | u32 save_adpa; |
Zhenyu Wang | 67941da | 2009-07-24 01:00:33 +0800 | [diff] [blame] | 274 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 275 | crt->force_hotplug_required = 0; |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 276 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 277 | save_adpa = adpa = I915_READ(PCH_ADPA); |
| 278 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 279 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 280 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 281 | if (turn_off_dac) |
| 282 | adpa &= ~ADPA_DAC_ENABLE; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 283 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 284 | I915_WRITE(PCH_ADPA, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 285 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 286 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 287 | 1000)) |
| 288 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 289 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 290 | if (turn_off_dac) { |
| 291 | I915_WRITE(PCH_ADPA, save_adpa); |
| 292 | POSTING_READ(PCH_ADPA); |
| 293 | } |
Zhenyu Wang | a4a6b90 | 2010-04-07 16:15:55 +0800 | [diff] [blame] | 294 | } |
| 295 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 296 | /* Check the status to see if both blue and green are on now */ |
| 297 | adpa = I915_READ(PCH_ADPA); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 298 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 299 | ret = true; |
| 300 | else |
| 301 | ret = false; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 302 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 303 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 304 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 305 | } |
| 306 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 307 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
| 308 | { |
| 309 | struct drm_device *dev = connector->dev; |
| 310 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 311 | u32 adpa; |
| 312 | bool ret; |
| 313 | u32 save_adpa; |
| 314 | |
| 315 | save_adpa = adpa = I915_READ(ADPA); |
| 316 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
| 317 | |
| 318 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 319 | |
| 320 | I915_WRITE(ADPA, adpa); |
| 321 | |
| 322 | if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 323 | 1000)) { |
| 324 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
| 325 | I915_WRITE(ADPA, save_adpa); |
| 326 | } |
| 327 | |
| 328 | /* Check the status to see if both blue and green are on now */ |
| 329 | adpa = I915_READ(ADPA); |
| 330 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
| 331 | ret = true; |
| 332 | else |
| 333 | ret = false; |
| 334 | |
| 335 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
| 336 | |
| 337 | /* FIXME: debug force function and remove */ |
| 338 | ret = true; |
| 339 | |
| 340 | return ret; |
| 341 | } |
| 342 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 343 | /** |
| 344 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
| 345 | * |
| 346 | * Not for i915G/i915GM |
| 347 | * |
| 348 | * \return true if CRT is connected. |
| 349 | * \return false if CRT is disconnected. |
| 350 | */ |
| 351 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
| 352 | { |
| 353 | struct drm_device *dev = connector->dev; |
| 354 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 355 | u32 hotplug_en, orig, stat; |
| 356 | bool ret = false; |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 357 | int i, tries = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 358 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 359 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 360 | return intel_ironlake_crt_detect_hotplug(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 361 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 362 | if (IS_VALLEYVIEW(dev)) |
| 363 | return valleyview_crt_detect_hotplug(connector); |
| 364 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 365 | /* |
| 366 | * On 4 series desktop, CRT detect sequence need to be done twice |
| 367 | * to get a reliable result. |
| 368 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 369 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 370 | if (IS_G4X(dev) && !IS_GM45(dev)) |
| 371 | tries = 2; |
| 372 | else |
| 373 | tries = 1; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 374 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 375 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 376 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 377 | for (i = 0; i < tries ; i++) { |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 378 | /* turn on the FORCE_DETECT */ |
| 379 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 380 | /* wait for FORCE_DETECT to go off */ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 381 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
| 382 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 383 | 1000)) |
Chris Wilson | 7907731 | 2010-09-12 19:58:04 +0100 | [diff] [blame] | 384 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 385 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 386 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 387 | stat = I915_READ(PORT_HOTPLUG_STAT); |
| 388 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
| 389 | ret = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 390 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 391 | /* clear the interrupt we just generated, if any */ |
| 392 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
| 393 | |
| 394 | /* and put the bits back */ |
| 395 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
| 396 | |
| 397 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 398 | } |
| 399 | |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 400 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
| 401 | struct i2c_adapter *i2c) |
| 402 | { |
| 403 | struct edid *edid; |
| 404 | |
| 405 | edid = drm_get_edid(connector, i2c); |
| 406 | |
| 407 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
| 408 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
| 409 | intel_gmbus_force_bit(i2c, true); |
| 410 | edid = drm_get_edid(connector, i2c); |
| 411 | intel_gmbus_force_bit(i2c, false); |
| 412 | } |
| 413 | |
| 414 | return edid; |
| 415 | } |
| 416 | |
| 417 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
| 418 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
| 419 | struct i2c_adapter *adapter) |
| 420 | { |
| 421 | struct edid *edid; |
| 422 | |
| 423 | edid = intel_crt_get_edid(connector, adapter); |
| 424 | if (!edid) |
| 425 | return 0; |
| 426 | |
| 427 | return intel_connector_update_modes(connector, edid); |
| 428 | } |
| 429 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 430 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 431 | { |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 432 | struct intel_crt *crt = intel_attached_crt(connector); |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 433 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 434 | struct edid *edid; |
| 435 | struct i2c_adapter *i2c; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 436 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 437 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 438 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 439 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 440 | edid = intel_crt_get_edid(connector, i2c); |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 441 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 442 | if (edid) { |
| 443 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
| 444 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 445 | /* |
| 446 | * This may be a DVI-I connector with a shared DDC |
| 447 | * link between analog and digital outputs, so we |
| 448 | * have to check the EDID input spec of the attached device. |
| 449 | */ |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 450 | if (!is_digital) { |
| 451 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
| 452 | return true; |
| 453 | } |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 454 | |
| 455 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
| 456 | } else { |
| 457 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 458 | } |
| 459 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 460 | kfree(edid); |
| 461 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 462 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 463 | } |
| 464 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 465 | static enum drm_connector_status |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 466 | intel_crt_load_detect(struct intel_crt *crt) |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 467 | { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 468 | struct drm_device *dev = crt->base.base.dev; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 469 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 470 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 471 | uint32_t save_bclrpat; |
| 472 | uint32_t save_vtotal; |
| 473 | uint32_t vtotal, vactive; |
| 474 | uint32_t vsample; |
| 475 | uint32_t vblank, vblank_start, vblank_end; |
| 476 | uint32_t dsl; |
| 477 | uint32_t bclrpat_reg; |
| 478 | uint32_t vtotal_reg; |
| 479 | uint32_t vblank_reg; |
| 480 | uint32_t vsync_reg; |
| 481 | uint32_t pipeconf_reg; |
| 482 | uint32_t pipe_dsl_reg; |
| 483 | uint8_t st00; |
| 484 | enum drm_connector_status status; |
| 485 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 486 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
| 487 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 488 | bclrpat_reg = BCLRPAT(pipe); |
| 489 | vtotal_reg = VTOTAL(pipe); |
| 490 | vblank_reg = VBLANK(pipe); |
| 491 | vsync_reg = VSYNC(pipe); |
| 492 | pipeconf_reg = PIPECONF(pipe); |
| 493 | pipe_dsl_reg = PIPEDSL(pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 494 | |
| 495 | save_bclrpat = I915_READ(bclrpat_reg); |
| 496 | save_vtotal = I915_READ(vtotal_reg); |
| 497 | vblank = I915_READ(vblank_reg); |
| 498 | |
| 499 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
| 500 | vactive = (save_vtotal & 0x7ff) + 1; |
| 501 | |
| 502 | vblank_start = (vblank & 0xfff) + 1; |
| 503 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
| 504 | |
| 505 | /* Set the border color to purple. */ |
| 506 | I915_WRITE(bclrpat_reg, 0x500050); |
| 507 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 508 | if (!IS_GEN2(dev)) { |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 509 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
| 510 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
Chris Wilson | 19c55da | 2010-08-09 14:50:53 +0100 | [diff] [blame] | 511 | POSTING_READ(pipeconf_reg); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 512 | /* Wait for next Vblank to substitue |
| 513 | * border color for Color info */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 514 | intel_wait_for_vblank(dev, pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 515 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 516 | status = ((st00 & (1 << 4)) != 0) ? |
| 517 | connector_status_connected : |
| 518 | connector_status_disconnected; |
| 519 | |
| 520 | I915_WRITE(pipeconf_reg, pipeconf); |
| 521 | } else { |
| 522 | bool restore_vblank = false; |
| 523 | int count, detect; |
| 524 | |
| 525 | /* |
| 526 | * If there isn't any border, add some. |
| 527 | * Yes, this will flicker |
| 528 | */ |
| 529 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
| 530 | uint32_t vsync = I915_READ(vsync_reg); |
| 531 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
| 532 | |
| 533 | vblank_start = vsync_start; |
| 534 | I915_WRITE(vblank_reg, |
| 535 | (vblank_start - 1) | |
| 536 | ((vblank_end - 1) << 16)); |
| 537 | restore_vblank = true; |
| 538 | } |
| 539 | /* sample in the vertical border, selecting the larger one */ |
| 540 | if (vblank_start - vactive >= vtotal - vblank_end) |
| 541 | vsample = (vblank_start + vactive) >> 1; |
| 542 | else |
| 543 | vsample = (vtotal + vblank_end) >> 1; |
| 544 | |
| 545 | /* |
| 546 | * Wait for the border to be displayed |
| 547 | */ |
| 548 | while (I915_READ(pipe_dsl_reg) >= vactive) |
| 549 | ; |
| 550 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
| 551 | ; |
| 552 | /* |
| 553 | * Watch ST00 for an entire scanline |
| 554 | */ |
| 555 | detect = 0; |
| 556 | count = 0; |
| 557 | do { |
| 558 | count++; |
| 559 | /* Read the ST00 VGA status register */ |
| 560 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 561 | if (st00 & (1 << 4)) |
| 562 | detect++; |
| 563 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
| 564 | |
| 565 | /* restore vblank if necessary */ |
| 566 | if (restore_vblank) |
| 567 | I915_WRITE(vblank_reg, vblank); |
| 568 | /* |
| 569 | * If more than 3/4 of the scanline detected a monitor, |
| 570 | * then it is assumed to be present. This works even on i830, |
| 571 | * where there isn't any way to force the border color across |
| 572 | * the screen |
| 573 | */ |
| 574 | status = detect * 4 > count * 3 ? |
| 575 | connector_status_connected : |
| 576 | connector_status_disconnected; |
| 577 | } |
| 578 | |
| 579 | /* Restore previous settings */ |
| 580 | I915_WRITE(bclrpat_reg, save_bclrpat); |
| 581 | |
| 582 | return status; |
| 583 | } |
| 584 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 585 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 586 | intel_crt_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 587 | { |
| 588 | struct drm_device *dev = connector->dev; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 589 | struct intel_crt *crt = intel_attached_crt(connector); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 590 | enum drm_connector_status status; |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 591 | struct intel_load_detect_pipe tmp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 592 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 593 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 594 | /* We can not rely on the HPD pin always being correctly wired |
| 595 | * up, for example many KVM do not pass it through, and so |
| 596 | * only trust an assertion that the monitor is connected. |
| 597 | */ |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 598 | if (intel_crt_detect_hotplug(connector)) { |
| 599 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 600 | return connector_status_connected; |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 601 | } else |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 602 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 603 | } |
| 604 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 605 | if (intel_crt_detect_ddc(connector)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 606 | return connector_status_connected; |
| 607 | |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 608 | /* Load detection is broken on HPD capable machines. Whoever wants a |
| 609 | * broken monitor (without edid) to work behind a broken kvm (that fails |
| 610 | * to have the right resistors for HP detection) needs to fix this up. |
| 611 | * For now just bail out. */ |
| 612 | if (I915_HAS_HOTPLUG(dev)) |
| 613 | return connector_status_disconnected; |
| 614 | |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 615 | if (!force) |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 616 | return connector->status; |
| 617 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 618 | /* for pre-945g platforms use load detect */ |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 619 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 620 | if (intel_crt_detect_ddc(connector)) |
| 621 | status = connector_status_connected; |
| 622 | else |
| 623 | status = intel_crt_load_detect(crt); |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 624 | intel_release_load_detect_pipe(connector, &tmp); |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 625 | } else |
| 626 | status = connector_status_unknown; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 627 | |
| 628 | return status; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | static void intel_crt_destroy(struct drm_connector *connector) |
| 632 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 633 | drm_sysfs_connector_remove(connector); |
| 634 | drm_connector_cleanup(connector); |
| 635 | kfree(connector); |
| 636 | } |
| 637 | |
| 638 | static int intel_crt_get_modes(struct drm_connector *connector) |
| 639 | { |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 640 | struct drm_device *dev = connector->dev; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 641 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 642 | int ret; |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 643 | struct i2c_adapter *i2c; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 644 | |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 645 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 646 | ret = intel_crt_ddc_get_modes(connector, i2c); |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 647 | if (ret || !IS_G4X(dev)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 648 | return ret; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 649 | |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 650 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 651 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 652 | return intel_crt_ddc_get_modes(connector, i2c); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 653 | } |
| 654 | |
| 655 | static int intel_crt_set_property(struct drm_connector *connector, |
| 656 | struct drm_property *property, |
| 657 | uint64_t value) |
| 658 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | return 0; |
| 660 | } |
| 661 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 662 | static void intel_crt_reset(struct drm_connector *connector) |
| 663 | { |
| 664 | struct drm_device *dev = connector->dev; |
| 665 | struct intel_crt *crt = intel_attached_crt(connector); |
| 666 | |
| 667 | if (HAS_PCH_SPLIT(dev)) |
| 668 | crt->force_hotplug_required = 1; |
| 669 | } |
| 670 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 671 | /* |
| 672 | * Routines for controlling stuff on the analog port |
| 673 | */ |
| 674 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 675 | static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 676 | .mode_fixup = intel_crt_mode_fixup, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 677 | .mode_set = intel_crt_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame] | 678 | .disable = intel_encoder_noop, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 679 | }; |
| 680 | |
| 681 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 682 | .reset = intel_crt_reset, |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 683 | .dpms = intel_crt_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 684 | .detect = intel_crt_detect, |
| 685 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 686 | .destroy = intel_crt_destroy, |
| 687 | .set_property = intel_crt_set_property, |
| 688 | }; |
| 689 | |
| 690 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
| 691 | .mode_valid = intel_crt_mode_valid, |
| 692 | .get_modes = intel_crt_get_modes, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 693 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 694 | }; |
| 695 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 696 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 697 | .destroy = intel_encoder_destroy, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 698 | }; |
| 699 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 700 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
| 701 | { |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 702 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 703 | return 1; |
| 704 | } |
| 705 | |
| 706 | static const struct dmi_system_id intel_no_crt[] = { |
| 707 | { |
| 708 | .callback = intel_no_crt_dmi_callback, |
| 709 | .ident = "ACER ZGB", |
| 710 | .matches = { |
| 711 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
| 712 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
| 713 | }, |
| 714 | }, |
| 715 | { } |
| 716 | }; |
| 717 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 718 | void intel_crt_init(struct drm_device *dev) |
| 719 | { |
| 720 | struct drm_connector *connector; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 721 | struct intel_crt *crt; |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 722 | struct intel_connector *intel_connector; |
David Müller (ELSOFT AG) | db54501 | 2009-08-29 08:54:45 +0200 | [diff] [blame] | 723 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 724 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 725 | /* Skip machines without VGA that falsely report hotplug events */ |
| 726 | if (dmi_check_system(intel_no_crt)) |
| 727 | return; |
| 728 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 729 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
| 730 | if (!crt) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 731 | return; |
| 732 | |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 733 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 734 | if (!intel_connector) { |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 735 | kfree(crt); |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 736 | return; |
| 737 | } |
| 738 | |
| 739 | connector = &intel_connector->base; |
| 740 | drm_connector_init(dev, &intel_connector->base, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
| 742 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 743 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 744 | DRM_MODE_ENCODER_DAC); |
| 745 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 746 | intel_connector_attach_encoder(intel_connector, &crt->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 747 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 748 | crt->base.type = INTEL_OUTPUT_ANALOG; |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 749 | crt->base.cloneable = true; |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 750 | if (IS_HASWELL(dev)) |
| 751 | crt->base.crtc_mask = (1 << 0); |
| 752 | else |
Keith Packard | 0826874 | 2012-08-13 21:34:45 -0700 | [diff] [blame] | 753 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 754 | |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 755 | if (IS_GEN2(dev)) |
| 756 | connector->interlace_allowed = 0; |
| 757 | else |
| 758 | connector->interlace_allowed = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 759 | connector->doublescan_allowed = 0; |
| 760 | |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 761 | if (HAS_PCH_SPLIT(dev)) |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 762 | crt->adpa_reg = PCH_ADPA; |
| 763 | else if (IS_VALLEYVIEW(dev)) |
| 764 | crt->adpa_reg = VLV_ADPA; |
| 765 | else |
| 766 | crt->adpa_reg = ADPA; |
| 767 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 768 | crt->base.disable = intel_disable_crt; |
| 769 | crt->base.enable = intel_enable_crt; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 770 | crt->base.get_hw_state = intel_crt_get_hw_state; |
| 771 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 772 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 773 | drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 774 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| 775 | |
| 776 | drm_sysfs_connector_add(connector); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 777 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 778 | if (I915_HAS_HOTPLUG(dev)) |
| 779 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 780 | else |
| 781 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 782 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 783 | /* |
| 784 | * Configure the automatic hotplug detection stuff |
| 785 | */ |
| 786 | crt->force_hotplug_required = 0; |
| 787 | if (HAS_PCH_SPLIT(dev)) { |
| 788 | u32 adpa; |
| 789 | |
| 790 | adpa = I915_READ(PCH_ADPA); |
| 791 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
| 792 | adpa |= ADPA_HOTPLUG_BITS; |
| 793 | I915_WRITE(PCH_ADPA, adpa); |
| 794 | POSTING_READ(PCH_ADPA); |
| 795 | |
| 796 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
| 797 | crt->force_hotplug_required = 1; |
| 798 | } |
| 799 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 800 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 801 | } |