blob: 00ffd661368069ab24e4d67ab2abcecd06333ab0 [file] [log] [blame]
James Hogan27bce452014-11-13 15:32:21 -03001/*
2 * I2C adapter for the IMG Serial Control Bus (SCB) IP block.
3 *
4 * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * There are three ways that this I2C controller can be driven:
11 *
12 * - Raw control of the SDA and SCK signals.
13 *
14 * This corresponds to MODE_RAW, which takes control of the signals
15 * directly for a certain number of clock cycles (the INT_TIMING
16 * interrupt can be used for timing).
17 *
18 * - Atomic commands. A low level I2C symbol (such as generate
19 * start/stop/ack/nack bit, generate byte, receive byte, and receive
20 * ACK) is given to the hardware, with detection of completion by bits
21 * in the LINESTAT register.
22 *
23 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
24 * state machine in the interrupt handler to compose/react to I2C
25 * transactions using atomic mode commands, and also by MODE_SEQUENCE,
26 * which emits a simple fixed sequence of atomic mode commands.
27 *
28 * Due to software control, the use of atomic commands usually results
29 * in suboptimal use of the bus, with gaps between the I2C symbols while
30 * the driver decides what to do next.
31 *
32 * - Automatic mode. A bus address, and whether to read/write is
33 * specified, and the hardware takes care of the I2C state machine,
34 * using a FIFO to send/receive bytes of data to an I2C slave. The
35 * driver just has to keep the FIFO drained or filled in response to the
36 * appropriate FIFO interrupts.
37 *
38 * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals
39 * with control of repeated start bits between I2C messages.
40 *
41 * Use of automatic mode and the FIFO can make much more efficient use
42 * of the bus compared to individual atomic commands, with potentially
43 * no wasted time between I2C symbols or I2C messages.
44 *
45 * In most cases MODE_AUTOMATIC is used, however if any of the messages in
46 * a transaction are zero byte writes (e.g. used by i2cdetect for probing
47 * the bus), MODE_ATOMIC must be used since automatic mode is normally
48 * started by the writing of data into the FIFO.
49 *
50 * The other modes are used in specific circumstances where MODE_ATOMIC and
51 * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus
52 * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure
53 * it is in a sane state.
54 *
55 * Notice that the driver implements a timer-based timeout mechanism.
56 * The reason for this mechanism is to reduce the number of interrupts
57 * received in automatic mode.
58 *
59 * The driver would get a slave event and transaction done interrupts for
60 * each atomic mode command that gets completed. However, these events are
61 * not needed in automatic mode, becase those atomic mode commands are
62 * managed automatically by the hardware.
63 *
64 * In practice, normal I2C transactions will be complete well before you
65 * get the timer interrupt, as the timer is re-scheduled during FIFO
66 * maintenance and disabled after the transaction is complete.
67 *
68 * In this way normal automatic mode operation isn't impacted by
69 * unnecessary interrupts, but the exceptional abort condition can still be
70 * detected (with a slight delay).
71 */
72
73#include <linux/bitops.h>
74#include <linux/clk.h>
75#include <linux/completion.h>
76#include <linux/err.h>
77#include <linux/i2c.h>
78#include <linux/init.h>
79#include <linux/interrupt.h>
80#include <linux/io.h>
81#include <linux/kernel.h>
82#include <linux/module.h>
83#include <linux/of_platform.h>
84#include <linux/platform_device.h>
85#include <linux/slab.h>
86#include <linux/timer.h>
87
88/* Register offsets */
89
90#define SCB_STATUS_REG 0x00
91#define SCB_OVERRIDE_REG 0x04
92#define SCB_READ_ADDR_REG 0x08
93#define SCB_READ_COUNT_REG 0x0c
94#define SCB_WRITE_ADDR_REG 0x10
95#define SCB_READ_DATA_REG 0x14
96#define SCB_WRITE_DATA_REG 0x18
97#define SCB_FIFO_STATUS_REG 0x1c
98#define SCB_CONTROL_SOFT_RESET 0x1f
99#define SCB_CLK_SET_REG 0x3c
100#define SCB_INT_STATUS_REG 0x40
101#define SCB_INT_CLEAR_REG 0x44
102#define SCB_INT_MASK_REG 0x48
103#define SCB_CONTROL_REG 0x4c
104#define SCB_TIME_TPL_REG 0x50
105#define SCB_TIME_TPH_REG 0x54
106#define SCB_TIME_TP2S_REG 0x58
107#define SCB_TIME_TBI_REG 0x60
108#define SCB_TIME_TSL_REG 0x64
109#define SCB_TIME_TDL_REG 0x68
110#define SCB_TIME_TSDL_REG 0x6c
111#define SCB_TIME_TSDH_REG 0x70
112#define SCB_READ_XADDR_REG 0x74
113#define SCB_WRITE_XADDR_REG 0x78
114#define SCB_WRITE_COUNT_REG 0x7c
115#define SCB_CORE_REV_REG 0x80
116#define SCB_TIME_TCKH_REG 0x84
117#define SCB_TIME_TCKL_REG 0x88
118#define SCB_FIFO_FLUSH_REG 0x8c
119#define SCB_READ_FIFO_REG 0x94
120#define SCB_CLEAR_REG 0x98
121
122/* SCB_CONTROL_REG bits */
123
124#define SCB_CONTROL_CLK_ENABLE 0x1e0
125#define SCB_CONTROL_TRANSACTION_HALT 0x200
126
127#define FIFO_READ_FULL BIT(0)
128#define FIFO_READ_EMPTY BIT(1)
129#define FIFO_WRITE_FULL BIT(2)
130#define FIFO_WRITE_EMPTY BIT(3)
131
132/* SCB_CLK_SET_REG bits */
133#define SCB_FILT_DISABLE BIT(31)
134#define SCB_FILT_BYPASS BIT(30)
135#define SCB_FILT_INC_MASK 0x7f
136#define SCB_FILT_INC_SHIFT 16
137#define SCB_INC_MASK 0x7f
138#define SCB_INC_SHIFT 8
139
140/* SCB_INT_*_REG bits */
141
142#define INT_BUS_INACTIVE BIT(0)
143#define INT_UNEXPECTED_START BIT(1)
144#define INT_SCLK_LOW_TIMEOUT BIT(2)
145#define INT_SDAT_LOW_TIMEOUT BIT(3)
146#define INT_WRITE_ACK_ERR BIT(4)
147#define INT_ADDR_ACK_ERR BIT(5)
148#define INT_FIFO_FULL BIT(9)
149#define INT_FIFO_FILLING BIT(10)
150#define INT_FIFO_EMPTY BIT(11)
151#define INT_FIFO_EMPTYING BIT(12)
152#define INT_TRANSACTION_DONE BIT(15)
153#define INT_SLAVE_EVENT BIT(16)
154#define INT_TIMING BIT(18)
155
156#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING)
157#define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING)
158
159/* Level interrupts need clearing after handling instead of before */
160#define INT_LEVEL 0x01e00
161
162/* Don't allow any interrupts while the clock may be off */
163#define INT_ENABLE_MASK_INACTIVE 0x00000
164
165/* Interrupt masks for the different driver modes */
166
167#define INT_ENABLE_MASK_RAW INT_TIMING
168
169#define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \
170 INT_SLAVE_EVENT | \
171 INT_ADDR_ACK_ERR | \
172 INT_WRITE_ACK_ERR)
173
174#define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \
175 INT_ADDR_ACK_ERR | \
176 INT_WRITE_ACK_ERR | \
177 INT_FIFO_FULL | \
178 INT_FIFO_FILLING | \
179 INT_FIFO_EMPTY | \
180 INT_FIFO_EMPTYING)
181
182#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
183 INT_ADDR_ACK_ERR | \
184 INT_WRITE_ACK_ERR)
185
186/* SCB_STATUS_REG fields */
187
188#define LINESTAT_SCLK_LINE_STATUS BIT(0)
189#define LINESTAT_SCLK_EN BIT(1)
190#define LINESTAT_SDAT_LINE_STATUS BIT(2)
191#define LINESTAT_SDAT_EN BIT(3)
192#define LINESTAT_DET_START_STATUS BIT(4)
193#define LINESTAT_DET_STOP_STATUS BIT(5)
194#define LINESTAT_DET_ACK_STATUS BIT(6)
195#define LINESTAT_DET_NACK_STATUS BIT(7)
196#define LINESTAT_BUS_IDLE BIT(8)
197#define LINESTAT_T_DONE_STATUS BIT(9)
198#define LINESTAT_SCLK_OUT_STATUS BIT(10)
199#define LINESTAT_SDAT_OUT_STATUS BIT(11)
200#define LINESTAT_GEN_LINE_MASK_STATUS BIT(12)
201#define LINESTAT_START_BIT_DET BIT(13)
202#define LINESTAT_STOP_BIT_DET BIT(14)
203#define LINESTAT_ACK_DET BIT(15)
204#define LINESTAT_NACK_DET BIT(16)
205#define LINESTAT_INPUT_HELD_V BIT(17)
206#define LINESTAT_ABORT_DET BIT(18)
207#define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET)
208#define LINESTAT_INPUT_DATA 0xff000000
209#define LINESTAT_INPUT_DATA_SHIFT 24
210
211#define LINESTAT_CLEAR_SHIFT 13
212#define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT)
213
214/* SCB_OVERRIDE_REG fields */
215
216#define OVERRIDE_SCLK_OVR BIT(0)
217#define OVERRIDE_SCLKEN_OVR BIT(1)
218#define OVERRIDE_SDAT_OVR BIT(2)
219#define OVERRIDE_SDATEN_OVR BIT(3)
220#define OVERRIDE_MASTER BIT(9)
221#define OVERRIDE_LINE_OVR_EN BIT(10)
222#define OVERRIDE_DIRECT BIT(11)
223#define OVERRIDE_CMD_SHIFT 4
224#define OVERRIDE_CMD_MASK 0x1f
225#define OVERRIDE_DATA_SHIFT 24
226
227#define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \
228 OVERRIDE_SCLKEN_OVR)
229#define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \
230 OVERRIDE_SCLKEN_OVR | \
231 OVERRIDE_SCLK_OVR)
232#define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \
233 OVERRIDE_SDATEN_OVR)
234#define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \
235 OVERRIDE_SDATEN_OVR | \
236 OVERRIDE_SDAT_OVR)
237
238/* OVERRIDE_CMD values */
239
240#define CMD_PAUSE 0x00
241#define CMD_GEN_DATA 0x01
242#define CMD_GEN_START 0x02
243#define CMD_GEN_STOP 0x03
244#define CMD_GEN_ACK 0x04
245#define CMD_GEN_NACK 0x05
246#define CMD_RET_DATA 0x08
247#define CMD_RET_ACK 0x09
248
249/* Fixed timing values */
250
251#define TIMEOUT_TBI 0x0
252#define TIMEOUT_TSL 0xffff
253#define TIMEOUT_TDL 0x0
254
255/* Transaction timeout */
256
257#define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000))
258
259/*
260 * Worst incs are 1 (innacurate) and 16*256 (irregular).
261 * So a sensible inc is the logarithmic mean: 64 (2^6), which is
262 * in the middle of the valid range (0-127).
263 */
264#define SCB_OPT_INC 64
265
266/* Setup the clock enable filtering for 25 ns */
267#define SCB_FILT_GLITCH 25
268
269/*
270 * Bits to return from interrupt handler functions for different modes.
271 * This delays completion until we've finished with the registers, so that the
272 * function waiting for completion can safely disable the clock to save power.
273 */
274#define ISR_COMPLETE_M BIT(31)
275#define ISR_FATAL_M BIT(30)
276#define ISR_WAITSTOP BIT(29)
277#define ISR_STATUS_M 0x0000ffff /* contains +ve errno */
278#define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err)))
279#define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M)
280
281#define REL_SOC_IP_SCB_2_2_1 0x00020201
282
283enum img_i2c_mode {
284 MODE_INACTIVE,
285 MODE_RAW,
286 MODE_ATOMIC,
287 MODE_AUTOMATIC,
288 MODE_SEQUENCE,
289 MODE_FATAL,
290 MODE_WAITSTOP,
291 MODE_SUSPEND,
292};
293
294/* Timing parameters for i2c modes (in ns) */
295struct img_i2c_timings {
296 const char *name;
297 unsigned int max_bitrate;
298 unsigned int tckh, tckl, tsdh, tsdl;
299 unsigned int tp2s, tpl, tph;
300};
301
302/* The timings array must be ordered from slower to faster */
303static struct img_i2c_timings timings[] = {
304 /* Standard mode */
305 {
306 .name = "standard",
307 .max_bitrate = 100000,
308 .tckh = 4000,
309 .tckl = 4700,
310 .tsdh = 4700,
311 .tsdl = 8700,
312 .tp2s = 4700,
313 .tpl = 4700,
314 .tph = 4000,
315 },
316 /* Fast mode */
317 {
318 .name = "fast",
319 .max_bitrate = 400000,
320 .tckh = 600,
321 .tckl = 1300,
322 .tsdh = 600,
323 .tsdl = 1200,
324 .tp2s = 1300,
325 .tpl = 600,
326 .tph = 600,
327 },
328};
329
330/* Reset dance */
331static u8 img_i2c_reset_seq[] = { CMD_GEN_START,
332 CMD_GEN_DATA, 0xff,
333 CMD_RET_ACK,
334 CMD_GEN_START,
335 CMD_GEN_STOP,
336 0 };
337/* Just issue a stop (after an abort condition) */
338static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP,
339 0 };
340
341/* We're interested in different interrupts depending on the mode */
342static unsigned int img_i2c_int_enable_by_mode[] = {
343 [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE,
344 [MODE_RAW] = INT_ENABLE_MASK_RAW,
345 [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC,
346 [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC,
347 [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC,
348 [MODE_FATAL] = 0,
349 [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP,
350 [MODE_SUSPEND] = 0,
351};
352
353/* Atomic command names */
354static const char * const img_i2c_atomic_cmd_names[] = {
355 [CMD_PAUSE] = "PAUSE",
356 [CMD_GEN_DATA] = "GEN_DATA",
357 [CMD_GEN_START] = "GEN_START",
358 [CMD_GEN_STOP] = "GEN_STOP",
359 [CMD_GEN_ACK] = "GEN_ACK",
360 [CMD_GEN_NACK] = "GEN_NACK",
361 [CMD_RET_DATA] = "RET_DATA",
362 [CMD_RET_ACK] = "RET_ACK",
363};
364
365struct img_i2c {
366 struct i2c_adapter adap;
367
368 void __iomem *base;
369
370 /*
371 * The scb core clock is used to get the input frequency, and to disable
372 * it after every set of transactions to save some power.
373 */
374 struct clk *scb_clk, *sys_clk;
375 unsigned int bitrate;
376 bool need_wr_rd_fence;
377
378 /* state */
379 struct completion msg_complete;
380 spinlock_t lock; /* lock before doing anything with the state */
381 struct i2c_msg msg;
382
383 /* After the last transaction, wait for a stop bit */
384 bool last_msg;
385 int msg_status;
386
387 enum img_i2c_mode mode;
388 u32 int_enable; /* depends on mode */
389 u32 line_status; /* line status over command */
390
391 /*
392 * To avoid slave event interrupts in automatic mode, use a timer to
393 * poll the abort condition if we don't get an interrupt for too long.
394 */
395 struct timer_list check_timer;
396 bool t_halt;
397
398 /* atomic mode state */
399 bool at_t_done;
400 bool at_slave_event;
401 int at_cur_cmd;
402 u8 at_cur_data;
403
404 /* Sequence: either reset or stop. See img_i2c_sequence. */
405 u8 *seq;
406
407 /* raw mode */
408 unsigned int raw_timeout;
409};
410
411static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value)
412{
413 writel(value, i2c->base + offset);
414}
415
416static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset)
417{
418 return readl(i2c->base + offset);
419}
420
421/*
422 * The code to read from the master read fifo, and write to the master
423 * write fifo, checks a bit in an SCB register before every byte to
424 * ensure that the fifo is not full (write fifo) or empty (read fifo).
425 * Due to clock domain crossing inside the SCB block the updated value
426 * of this bit is only visible after 2 cycles.
427 *
428 * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only
429 * revision register), and it's called after reading from or writing to the
430 * fifos to ensure that subsequent reads of the fifo status bits do not read
431 * stale values.
432 */
433static void img_i2c_wr_rd_fence(struct img_i2c *i2c)
434{
435 if (i2c->need_wr_rd_fence) {
436 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0);
437 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0);
438 }
439}
440
441static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode)
442{
443 i2c->mode = mode;
444 i2c->int_enable = img_i2c_int_enable_by_mode[mode];
445 i2c->line_status = 0;
446}
447
448static void img_i2c_raw_op(struct img_i2c *i2c)
449{
450 i2c->raw_timeout = 0;
451 img_i2c_writel(i2c, SCB_OVERRIDE_REG,
452 OVERRIDE_SCLKEN_OVR |
453 OVERRIDE_SDATEN_OVR |
454 OVERRIDE_MASTER |
455 OVERRIDE_LINE_OVR_EN |
456 OVERRIDE_DIRECT |
457 ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) |
458 (i2c->at_cur_data << OVERRIDE_DATA_SHIFT));
459}
460
461static const char *img_i2c_atomic_op_name(unsigned int cmd)
462{
463 if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names)))
464 return "UNKNOWN";
465 return img_i2c_atomic_cmd_names[cmd];
466}
467
468/* Send a single atomic mode command to the hardware */
469static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data)
470{
471 i2c->at_cur_cmd = cmd;
472 i2c->at_cur_data = data;
473
474 /* work around lack of data setup time when generating data */
475 if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) {
476 u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
477
478 if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) {
479 /* hold the data line down for a moment */
480 img_i2c_switch_mode(i2c, MODE_RAW);
481 img_i2c_raw_op(i2c);
482 return;
483 }
484 }
485
486 dev_dbg(i2c->adap.dev.parent,
487 "atomic cmd=%s (%d) data=%#x\n",
488 img_i2c_atomic_op_name(cmd), cmd, data);
489 i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK);
490 i2c->at_slave_event = false;
491 i2c->line_status = 0;
492
493 img_i2c_writel(i2c, SCB_OVERRIDE_REG,
494 ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) |
495 OVERRIDE_MASTER |
496 OVERRIDE_DIRECT |
497 (data << OVERRIDE_DATA_SHIFT));
498}
499
500/* Start a transaction in atomic mode */
501static void img_i2c_atomic_start(struct img_i2c *i2c)
502{
503 img_i2c_switch_mode(i2c, MODE_ATOMIC);
504 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
505 img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00);
506}
507
508static void img_i2c_soft_reset(struct img_i2c *i2c)
509{
510 i2c->t_halt = false;
511 img_i2c_writel(i2c, SCB_CONTROL_REG, 0);
512 img_i2c_writel(i2c, SCB_CONTROL_REG,
513 SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET);
514}
515
516/* enable or release transaction halt for control of repeated starts */
517static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt)
518{
519 u32 val;
520
521 if (i2c->t_halt == t_halt)
522 return;
523 i2c->t_halt = t_halt;
524 val = img_i2c_readl(i2c, SCB_CONTROL_REG);
525 if (t_halt)
526 val |= SCB_CONTROL_TRANSACTION_HALT;
527 else
528 val &= ~SCB_CONTROL_TRANSACTION_HALT;
529 img_i2c_writel(i2c, SCB_CONTROL_REG, val);
530}
531
532/* Drain data from the FIFO into the buffer (automatic mode) */
533static void img_i2c_read_fifo(struct img_i2c *i2c)
534{
535 while (i2c->msg.len) {
536 u32 fifo_status;
537 u8 data;
538
539 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG);
540 if (fifo_status & FIFO_READ_EMPTY)
541 break;
542
543 data = img_i2c_readl(i2c, SCB_READ_DATA_REG);
544 *i2c->msg.buf = data;
545
546 img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff);
547 img_i2c_wr_rd_fence(i2c);
548 i2c->msg.len--;
549 i2c->msg.buf++;
550 }
551}
552
553/* Fill the FIFO with data from the buffer (automatic mode) */
554static void img_i2c_write_fifo(struct img_i2c *i2c)
555{
556 while (i2c->msg.len) {
557 u32 fifo_status;
558
559 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG);
560 if (fifo_status & FIFO_WRITE_FULL)
561 break;
562
563 img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf);
564 img_i2c_wr_rd_fence(i2c);
565 i2c->msg.len--;
566 i2c->msg.buf++;
567 }
568
569 /* Disable fifo emptying interrupt if nothing more to write */
570 if (!i2c->msg.len)
571 i2c->int_enable &= ~INT_FIFO_EMPTYING;
572}
573
574/* Start a read transaction in automatic mode */
575static void img_i2c_read(struct img_i2c *i2c)
576{
577 img_i2c_switch_mode(i2c, MODE_AUTOMATIC);
578 if (!i2c->last_msg)
579 i2c->int_enable |= INT_SLAVE_EVENT;
580
581 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
582 img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr);
583 img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len);
584
585 img_i2c_transaction_halt(i2c, false);
586 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
587}
588
589/* Start a write transaction in automatic mode */
590static void img_i2c_write(struct img_i2c *i2c)
591{
592 img_i2c_switch_mode(i2c, MODE_AUTOMATIC);
593 if (!i2c->last_msg)
594 i2c->int_enable |= INT_SLAVE_EVENT;
595
596 img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr);
597 img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len);
598
599 img_i2c_transaction_halt(i2c, false);
600 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
601 img_i2c_write_fifo(i2c);
602
603 /* img_i2c_write_fifo() may modify int_enable */
604 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
605}
606
607/*
608 * Indicate that the transaction is complete. This is called from the
609 * ISR to wake up the waiting thread, after which the ISR must not
610 * access any more SCB registers.
611 */
612static void img_i2c_complete_transaction(struct img_i2c *i2c, int status)
613{
614 img_i2c_switch_mode(i2c, MODE_INACTIVE);
615 if (status) {
616 i2c->msg_status = status;
617 img_i2c_transaction_halt(i2c, false);
618 }
619 complete(&i2c->msg_complete);
620}
621
622static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c,
623 u32 int_status, u32 line_status)
624{
625 /* Stay in raw mode for this, so we don't just loop infinitely */
626 img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data);
627 img_i2c_switch_mode(i2c, MODE_ATOMIC);
628 return 0;
629}
630
631static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status,
632 u32 line_status)
633{
634 if (int_status & INT_TIMING) {
635 if (i2c->raw_timeout == 0)
636 return img_i2c_raw_atomic_delay_handler(i2c,
637 int_status, line_status);
638 --i2c->raw_timeout;
639 }
640 return 0;
641}
642
643static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status)
644{
645 static const unsigned int continue_bits[] = {
646 [CMD_GEN_START] = LINESTAT_START_BIT_DET,
647 [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V,
648 [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET,
649 [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V,
650 [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET,
651 };
652 int next_cmd = -1;
653 u8 next_data = 0x00;
654
655 if (int_status & INT_SLAVE_EVENT)
656 i2c->at_slave_event = true;
657 if (int_status & INT_TRANSACTION_DONE)
658 i2c->at_t_done = true;
659
660 if (!i2c->at_slave_event || !i2c->at_t_done)
661 return 0;
662
663 /* wait if no continue bits are set */
664 if (i2c->at_cur_cmd >= 0 &&
665 i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) {
666 unsigned int cont_bits = continue_bits[i2c->at_cur_cmd];
667
668 if (cont_bits) {
669 cont_bits |= LINESTAT_ABORT_DET;
670 if (!(i2c->line_status & cont_bits))
671 return 0;
672 }
673 }
674
675 /* follow the sequence of commands in i2c->seq */
676 next_cmd = *i2c->seq;
677 /* stop on a nil */
678 if (!next_cmd) {
679 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0);
680 return ISR_COMPLETE(0);
681 }
682 /* when generating data, the next byte is the data */
683 if (next_cmd == CMD_GEN_DATA) {
684 ++i2c->seq;
685 next_data = *i2c->seq;
686 }
687 ++i2c->seq;
688 img_i2c_atomic_op(i2c, next_cmd, next_data);
689
690 return 0;
691}
692
693static void img_i2c_reset_start(struct img_i2c *i2c)
694{
695 /* Initiate the magic dance */
696 img_i2c_switch_mode(i2c, MODE_SEQUENCE);
697 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
698 i2c->seq = img_i2c_reset_seq;
699 i2c->at_slave_event = true;
700 i2c->at_t_done = true;
701 i2c->at_cur_cmd = -1;
702
703 /* img_i2c_reset_seq isn't empty so the following won't fail */
704 img_i2c_sequence(i2c, 0);
705}
706
707static void img_i2c_stop_start(struct img_i2c *i2c)
708{
709 /* Initiate a stop bit sequence */
710 img_i2c_switch_mode(i2c, MODE_SEQUENCE);
711 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
712 i2c->seq = img_i2c_stop_seq;
713 i2c->at_slave_event = true;
714 i2c->at_t_done = true;
715 i2c->at_cur_cmd = -1;
716
717 /* img_i2c_stop_seq isn't empty so the following won't fail */
718 img_i2c_sequence(i2c, 0);
719}
720
721static unsigned int img_i2c_atomic(struct img_i2c *i2c,
722 u32 int_status,
723 u32 line_status)
724{
725 int next_cmd = -1;
726 u8 next_data = 0x00;
727
728 if (int_status & INT_SLAVE_EVENT)
729 i2c->at_slave_event = true;
730 if (int_status & INT_TRANSACTION_DONE)
731 i2c->at_t_done = true;
732
733 if (!i2c->at_slave_event || !i2c->at_t_done)
734 goto next_atomic_cmd;
735 if (i2c->line_status & LINESTAT_ABORT_DET) {
736 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n");
737 next_cmd = CMD_GEN_STOP;
738 i2c->msg_status = -EIO;
739 goto next_atomic_cmd;
740 }
741
742 /* i2c->at_cur_cmd may have completed */
743 switch (i2c->at_cur_cmd) {
744 case CMD_GEN_START:
745 next_cmd = CMD_GEN_DATA;
746 next_data = (i2c->msg.addr << 1);
747 if (i2c->msg.flags & I2C_M_RD)
748 next_data |= 0x1;
749 break;
750 case CMD_GEN_DATA:
751 if (i2c->line_status & LINESTAT_INPUT_HELD_V)
752 next_cmd = CMD_RET_ACK;
753 break;
754 case CMD_RET_ACK:
755 if (i2c->line_status & LINESTAT_ACK_DET) {
756 if (i2c->msg.len == 0) {
757 next_cmd = CMD_GEN_STOP;
758 } else if (i2c->msg.flags & I2C_M_RD) {
759 next_cmd = CMD_RET_DATA;
760 } else {
761 next_cmd = CMD_GEN_DATA;
762 next_data = *i2c->msg.buf;
763 --i2c->msg.len;
764 ++i2c->msg.buf;
765 }
766 } else if (i2c->line_status & LINESTAT_NACK_DET) {
767 i2c->msg_status = -EIO;
768 next_cmd = CMD_GEN_STOP;
769 }
770 break;
771 case CMD_RET_DATA:
772 if (i2c->line_status & LINESTAT_INPUT_HELD_V) {
773 *i2c->msg.buf = (i2c->line_status &
774 LINESTAT_INPUT_DATA)
775 >> LINESTAT_INPUT_DATA_SHIFT;
776 --i2c->msg.len;
777 ++i2c->msg.buf;
778 if (i2c->msg.len)
779 next_cmd = CMD_GEN_ACK;
780 else
781 next_cmd = CMD_GEN_NACK;
782 }
783 break;
784 case CMD_GEN_ACK:
785 if (i2c->line_status & LINESTAT_ACK_DET) {
786 next_cmd = CMD_RET_DATA;
787 } else {
788 i2c->msg_status = -EIO;
789 next_cmd = CMD_GEN_STOP;
790 }
791 break;
792 case CMD_GEN_NACK:
793 next_cmd = CMD_GEN_STOP;
794 break;
795 case CMD_GEN_STOP:
796 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0);
797 return ISR_COMPLETE(0);
798 default:
799 dev_err(i2c->adap.dev.parent, "bad atomic command %d\n",
800 i2c->at_cur_cmd);
801 i2c->msg_status = -EIO;
802 next_cmd = CMD_GEN_STOP;
803 break;
804 }
805
806next_atomic_cmd:
807 if (next_cmd != -1) {
808 /* don't actually stop unless we're the last transaction */
809 if (next_cmd == CMD_GEN_STOP && !i2c->msg_status &&
810 !i2c->last_msg)
811 return ISR_COMPLETE(0);
812 img_i2c_atomic_op(i2c, next_cmd, next_data);
813 }
814 return 0;
815}
816
817/*
818 * Timer function to check if something has gone wrong in automatic mode (so we
819 * don't have to handle so many interrupts just to catch an exception).
820 */
821static void img_i2c_check_timer(unsigned long arg)
822{
823 struct img_i2c *i2c = (struct img_i2c *)arg;
824 unsigned long flags;
825 unsigned int line_status;
826
827 spin_lock_irqsave(&i2c->lock, flags);
828 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
829
830 /* check for an abort condition */
831 if (line_status & LINESTAT_ABORT_DET) {
832 dev_dbg(i2c->adap.dev.parent,
833 "abort condition detected by check timer\n");
834 /* enable slave event interrupt mask to trigger irq */
835 img_i2c_writel(i2c, SCB_INT_MASK_REG,
836 i2c->int_enable | INT_SLAVE_EVENT);
837 }
838
839 spin_unlock_irqrestore(&i2c->lock, flags);
840}
841
842static unsigned int img_i2c_auto(struct img_i2c *i2c,
843 unsigned int int_status,
844 unsigned int line_status)
845{
846 if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR))
847 return ISR_COMPLETE(EIO);
848
849 if (line_status & LINESTAT_ABORT_DET) {
850 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n");
851 /* empty the read fifo */
852 if ((i2c->msg.flags & I2C_M_RD) &&
853 (int_status & INT_FIFO_FULL_FILLING))
854 img_i2c_read_fifo(i2c);
855 /* use atomic mode and try to force a stop bit */
856 i2c->msg_status = -EIO;
857 img_i2c_stop_start(i2c);
858 return 0;
859 }
860
861 /* Enable transaction halt on start bit */
862 if (!i2c->last_msg && i2c->line_status & LINESTAT_START_BIT_DET) {
863 img_i2c_transaction_halt(i2c, true);
864 /* we're no longer interested in the slave event */
865 i2c->int_enable &= ~INT_SLAVE_EVENT;
866 }
867
868 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
869
870 if (i2c->msg.flags & I2C_M_RD) {
871 if (int_status & INT_FIFO_FULL_FILLING) {
872 img_i2c_read_fifo(i2c);
873 if (i2c->msg.len == 0)
874 return ISR_WAITSTOP;
875 }
876 } else {
877 if (int_status & INT_FIFO_EMPTY_EMPTYING) {
878 /*
879 * The write fifo empty indicates that we're in the
880 * last byte so it's safe to start a new write
881 * transaction without losing any bytes from the
882 * previous one.
883 * see 2.3.7 Repeated Start Transactions.
884 */
885 if ((int_status & INT_FIFO_EMPTY) &&
886 i2c->msg.len == 0)
887 return ISR_WAITSTOP;
888 img_i2c_write_fifo(i2c);
889 }
890 }
891
892 return 0;
893}
894
895static irqreturn_t img_i2c_isr(int irq, void *dev_id)
896{
897 struct img_i2c *i2c = (struct img_i2c *)dev_id;
898 u32 int_status, line_status;
899 /* We handle transaction completion AFTER accessing registers */
900 unsigned int hret;
901
902 /* Read interrupt status register. */
903 int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG);
904 /* Clear detected interrupts. */
905 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status);
906
907 /*
908 * Read line status and clear it until it actually is clear. We have
909 * to be careful not to lose any line status bits that get latched.
910 */
911 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
912 if (line_status & LINESTAT_LATCHED) {
913 img_i2c_writel(i2c, SCB_CLEAR_REG,
914 (line_status & LINESTAT_LATCHED)
915 >> LINESTAT_CLEAR_SHIFT);
916 img_i2c_wr_rd_fence(i2c);
917 }
918
919 spin_lock(&i2c->lock);
920
921 /* Keep track of line status bits received */
922 i2c->line_status &= ~LINESTAT_INPUT_DATA;
923 i2c->line_status |= line_status;
924
925 /*
926 * Certain interrupts indicate that sclk low timeout is not
927 * a problem. If any of these are set, just continue.
928 */
929 if ((int_status & INT_SCLK_LOW_TIMEOUT) &&
930 !(int_status & (INT_SLAVE_EVENT |
931 INT_FIFO_EMPTY |
932 INT_FIFO_FULL))) {
933 dev_crit(i2c->adap.dev.parent,
934 "fatal: clock low timeout occurred %s addr 0x%02x\n",
935 (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing",
936 i2c->msg.addr);
937 hret = ISR_FATAL(EIO);
938 goto out;
939 }
940
941 if (i2c->mode == MODE_ATOMIC)
942 hret = img_i2c_atomic(i2c, int_status, line_status);
943 else if (i2c->mode == MODE_AUTOMATIC)
944 hret = img_i2c_auto(i2c, int_status, line_status);
945 else if (i2c->mode == MODE_SEQUENCE)
946 hret = img_i2c_sequence(i2c, int_status);
947 else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) &&
948 (line_status & LINESTAT_STOP_BIT_DET))
949 hret = ISR_COMPLETE(0);
950 else if (i2c->mode == MODE_RAW)
951 hret = img_i2c_raw(i2c, int_status, line_status);
952 else
953 hret = 0;
954
955 /* Clear detected level interrupts. */
956 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL);
957
958out:
959 if (hret & ISR_WAITSTOP) {
960 /*
961 * Only wait for stop on last message.
962 * Also we may already have detected the stop bit.
963 */
964 if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET)
965 hret = ISR_COMPLETE(0);
966 else
967 img_i2c_switch_mode(i2c, MODE_WAITSTOP);
968 }
969
970 /* now we've finished using regs, handle transaction completion */
971 if (hret & ISR_COMPLETE_M) {
972 int status = -(hret & ISR_STATUS_M);
973
974 img_i2c_complete_transaction(i2c, status);
975 if (hret & ISR_FATAL_M)
976 img_i2c_switch_mode(i2c, MODE_FATAL);
977 }
978
979 /* Enable interrupts (int_enable may be altered by changing mode) */
980 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
981
982 spin_unlock(&i2c->lock);
983
984 return IRQ_HANDLED;
985}
986
987/* Force a bus reset sequence and wait for it to complete */
988static int img_i2c_reset_bus(struct img_i2c *i2c)
989{
990 unsigned long flags;
Nicholas Mc Guire913b1d82015-02-09 10:15:21 -0500991 unsigned long time_left;
James Hogan27bce452014-11-13 15:32:21 -0300992
993 spin_lock_irqsave(&i2c->lock, flags);
994 reinit_completion(&i2c->msg_complete);
995 img_i2c_reset_start(i2c);
996 spin_unlock_irqrestore(&i2c->lock, flags);
997
Nicholas Mc Guire913b1d82015-02-09 10:15:21 -0500998 time_left = wait_for_completion_timeout(&i2c->msg_complete,
999 IMG_I2C_TIMEOUT);
1000 if (time_left == 0)
James Hogan27bce452014-11-13 15:32:21 -03001001 return -ETIMEDOUT;
1002 return 0;
1003}
1004
1005static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
1006 int num)
1007{
1008 struct img_i2c *i2c = i2c_get_adapdata(adap);
1009 bool atomic = false;
1010 int i, ret;
Nicholas Mc Guire913b1d82015-02-09 10:15:21 -05001011 unsigned long time_left;
James Hogan27bce452014-11-13 15:32:21 -03001012
1013 if (i2c->mode == MODE_SUSPEND) {
1014 WARN(1, "refusing to service transaction in suspended state\n");
1015 return -EIO;
1016 }
1017
1018 if (i2c->mode == MODE_FATAL)
1019 return -EIO;
1020
1021 for (i = 0; i < num; i++) {
1022 if (likely(msgs[i].len))
1023 continue;
1024 /*
1025 * 0 byte reads are not possible because the slave could try
1026 * and pull the data line low, preventing a stop bit.
1027 */
1028 if (unlikely(msgs[i].flags & I2C_M_RD))
1029 return -EIO;
1030 /*
1031 * 0 byte writes are possible and used for probing, but we
1032 * cannot do them in automatic mode, so use atomic mode
1033 * instead.
1034 */
1035 atomic = true;
1036 }
1037
1038 ret = clk_prepare_enable(i2c->scb_clk);
1039 if (ret)
1040 return ret;
1041
1042 for (i = 0; i < num; i++) {
1043 struct i2c_msg *msg = &msgs[i];
1044 unsigned long flags;
1045
1046 spin_lock_irqsave(&i2c->lock, flags);
1047
1048 /*
1049 * Make a copy of the message struct. We mustn't modify the
1050 * original or we'll confuse drivers and i2c-dev.
1051 */
1052 i2c->msg = *msg;
1053 i2c->msg_status = 0;
1054
1055 /*
1056 * After the last message we must have waited for a stop bit.
1057 * Not waiting can cause problems when the clock is disabled
1058 * before the stop bit is sent, and the linux I2C interface
1059 * requires separate transfers not to joined with repeated
1060 * start.
1061 */
1062 i2c->last_msg = (i == num - 1);
1063 reinit_completion(&i2c->msg_complete);
1064
1065 if (atomic)
1066 img_i2c_atomic_start(i2c);
1067 else if (msg->flags & I2C_M_RD)
1068 img_i2c_read(i2c);
1069 else
1070 img_i2c_write(i2c);
1071 spin_unlock_irqrestore(&i2c->lock, flags);
1072
Nicholas Mc Guire913b1d82015-02-09 10:15:21 -05001073 time_left = wait_for_completion_timeout(&i2c->msg_complete,
1074 IMG_I2C_TIMEOUT);
James Hogan27bce452014-11-13 15:32:21 -03001075 del_timer_sync(&i2c->check_timer);
1076
Nicholas Mc Guire913b1d82015-02-09 10:15:21 -05001077 if (time_left == 0) {
James Hogan27bce452014-11-13 15:32:21 -03001078 dev_err(adap->dev.parent, "i2c transfer timed out\n");
1079 i2c->msg_status = -ETIMEDOUT;
1080 break;
1081 }
1082
1083 if (i2c->msg_status)
1084 break;
1085 }
1086
1087 clk_disable_unprepare(i2c->scb_clk);
1088
1089 return i2c->msg_status ? i2c->msg_status : num;
1090}
1091
1092static u32 img_i2c_func(struct i2c_adapter *adap)
1093{
1094 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1095}
1096
1097static const struct i2c_algorithm img_i2c_algo = {
1098 .master_xfer = img_i2c_xfer,
1099 .functionality = img_i2c_func,
1100};
1101
1102static int img_i2c_init(struct img_i2c *i2c)
1103{
1104 unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh;
1105 unsigned int i, ret, data, prescale, inc, int_bitrate, filt;
1106 struct img_i2c_timings timing;
1107 u32 rev;
1108
1109 ret = clk_prepare_enable(i2c->scb_clk);
1110 if (ret)
1111 return ret;
1112
1113 rev = img_i2c_readl(i2c, SCB_CORE_REV_REG);
1114 if ((rev & 0x00ffffff) < 0x00020200) {
1115 dev_info(i2c->adap.dev.parent,
1116 "Unknown hardware revision (%d.%d.%d.%d)\n",
1117 (rev >> 24) & 0xff, (rev >> 16) & 0xff,
1118 (rev >> 8) & 0xff, rev & 0xff);
1119 clk_disable_unprepare(i2c->scb_clk);
1120 return -EINVAL;
1121 }
1122
1123 if (rev == REL_SOC_IP_SCB_2_2_1) {
1124 i2c->need_wr_rd_fence = true;
1125 dev_info(i2c->adap.dev.parent, "fence quirk enabled");
1126 }
1127
1128 bitrate_khz = i2c->bitrate / 1000;
1129 clk_khz = clk_get_rate(i2c->scb_clk) / 1000;
1130
1131 /* Determine what mode we're in from the bitrate */
1132 timing = timings[0];
1133 for (i = 0; i < ARRAY_SIZE(timings); i++) {
1134 if (i2c->bitrate <= timings[i].max_bitrate) {
1135 timing = timings[i];
1136 break;
1137 }
1138 }
1139
1140 /* Find the prescale that would give us that inc (approx delay = 0) */
1141 prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz);
1142 prescale = clamp_t(unsigned int, prescale, 1, 8);
1143 clk_khz /= prescale;
1144
1145 /* Setup the clock increment value */
1146 inc = (256 * 16 * bitrate_khz) / clk_khz;
1147
1148 /*
1149 * The clock generation logic allows to filter glitches on the bus.
1150 * This filter is able to remove bus glitches shorter than 50ns.
1151 * If the clock enable rate is greater than 20 MHz, no filtering
1152 * is required, so we need to disable it.
1153 * If it's between the 20-40 MHz range, there's no need to divide
1154 * the clock to get a filter.
1155 */
1156 if (clk_khz < 20000) {
1157 filt = SCB_FILT_DISABLE;
1158 } else if (clk_khz < 40000) {
1159 filt = SCB_FILT_BYPASS;
1160 } else {
1161 /* Calculate filter clock */
1162 filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH));
1163
1164 /* Scale up if needed */
1165 if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH))
1166 inc++;
1167
1168 if (filt > SCB_FILT_INC_MASK)
1169 filt = SCB_FILT_INC_MASK;
1170
1171 filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT;
1172 }
1173 data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1);
1174 img_i2c_writel(i2c, SCB_CLK_SET_REG, data);
1175
1176 /* Obtain the clock period of the fx16 clock in ns */
1177 clk_period = (256 * 1000000) / (clk_khz * inc);
1178
1179 /* Calculate the bitrate in terms of internal clock pulses */
1180 int_bitrate = 1000000 / (bitrate_khz * clk_period);
1181 if ((1000000 % (bitrate_khz * clk_period)) >=
1182 ((bitrate_khz * clk_period) / 2))
1183 int_bitrate++;
1184
1185 /* Setup TCKH value */
1186 tckh = timing.tckh / clk_period;
1187 if (timing.tckh % clk_period)
1188 tckh++;
1189
1190 if (tckh > 0)
1191 data = tckh - 1;
1192 else
1193 data = 0;
1194
1195 img_i2c_writel(i2c, SCB_TIME_TCKH_REG, data);
1196
1197 /* Setup TCKL value */
1198 tckl = int_bitrate - tckh;
1199
1200 if (tckl > 0)
1201 data = tckl - 1;
1202 else
1203 data = 0;
1204
1205 img_i2c_writel(i2c, SCB_TIME_TCKL_REG, data);
1206
1207 /* Setup TSDH value */
1208 tsdh = timing.tsdh / clk_period;
1209 if (timing.tsdh % clk_period)
1210 tsdh++;
1211
1212 if (tsdh > 1)
1213 data = tsdh - 1;
1214 else
1215 data = 0x01;
1216 img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data);
1217
1218 /* This value is used later */
1219 tsdh = data;
1220
1221 /* Setup TPL value */
1222 data = timing.tpl / clk_period;
1223 if (data > 0)
1224 --data;
1225 img_i2c_writel(i2c, SCB_TIME_TPL_REG, data);
1226
1227 /* Setup TPH value */
1228 data = timing.tph / clk_period;
1229 if (data > 0)
1230 --data;
1231 img_i2c_writel(i2c, SCB_TIME_TPH_REG, data);
1232
1233 /* Setup TSDL value to TPL + TSDH + 2 */
1234 img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2);
1235
1236 /* Setup TP2S value */
1237 data = timing.tp2s / clk_period;
1238 if (data > 0)
1239 --data;
1240 img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data);
1241
1242 img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI);
1243 img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL);
1244 img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL);
1245
1246 /* Take module out of soft reset and enable clocks */
1247 img_i2c_soft_reset(i2c);
1248
1249 /* Disable all interrupts */
1250 img_i2c_writel(i2c, SCB_INT_MASK_REG, 0);
1251
1252 /* Clear all interrupts */
1253 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0);
1254
1255 /* Clear the scb_line_status events */
1256 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0);
1257
1258 /* Enable interrupts */
1259 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
1260
1261 /* Perform a synchronous sequence to reset the bus */
1262 ret = img_i2c_reset_bus(i2c);
1263
1264 clk_disable_unprepare(i2c->scb_clk);
1265
1266 return ret;
1267}
1268
1269static int img_i2c_probe(struct platform_device *pdev)
1270{
1271 struct device_node *node = pdev->dev.of_node;
1272 struct img_i2c *i2c;
1273 struct resource *res;
1274 int irq, ret;
1275 u32 val;
1276
1277 i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL);
1278 if (!i2c)
1279 return -ENOMEM;
1280
1281 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1282 i2c->base = devm_ioremap_resource(&pdev->dev, res);
1283 if (IS_ERR(i2c->base))
1284 return PTR_ERR(i2c->base);
1285
1286 irq = platform_get_irq(pdev, 0);
1287 if (irq < 0) {
1288 dev_err(&pdev->dev, "can't get irq number\n");
1289 return irq;
1290 }
1291
1292 i2c->sys_clk = devm_clk_get(&pdev->dev, "sys");
1293 if (IS_ERR(i2c->sys_clk)) {
1294 dev_err(&pdev->dev, "can't get system clock\n");
1295 return PTR_ERR(i2c->sys_clk);
1296 }
1297
1298 i2c->scb_clk = devm_clk_get(&pdev->dev, "scb");
1299 if (IS_ERR(i2c->scb_clk)) {
1300 dev_err(&pdev->dev, "can't get core clock\n");
1301 return PTR_ERR(i2c->scb_clk);
1302 }
1303
1304 ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0,
1305 pdev->name, i2c);
1306 if (ret) {
1307 dev_err(&pdev->dev, "can't request irq %d\n", irq);
1308 return ret;
1309 }
1310
1311 /* Set up the exception check timer */
1312 init_timer(&i2c->check_timer);
1313 i2c->check_timer.function = img_i2c_check_timer;
1314 i2c->check_timer.data = (unsigned long)i2c;
1315
1316 i2c->bitrate = timings[0].max_bitrate;
1317 if (!of_property_read_u32(node, "clock-frequency", &val))
1318 i2c->bitrate = val;
1319
1320 i2c_set_adapdata(&i2c->adap, i2c);
1321 i2c->adap.dev.parent = &pdev->dev;
1322 i2c->adap.dev.of_node = node;
1323 i2c->adap.owner = THIS_MODULE;
1324 i2c->adap.algo = &img_i2c_algo;
1325 i2c->adap.retries = 5;
1326 i2c->adap.nr = pdev->id;
1327 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C");
1328
1329 img_i2c_switch_mode(i2c, MODE_INACTIVE);
1330 spin_lock_init(&i2c->lock);
1331 init_completion(&i2c->msg_complete);
1332
1333 platform_set_drvdata(pdev, i2c);
1334
1335 ret = clk_prepare_enable(i2c->sys_clk);
1336 if (ret)
1337 return ret;
1338
1339 ret = img_i2c_init(i2c);
1340 if (ret)
1341 goto disable_clk;
1342
1343 ret = i2c_add_numbered_adapter(&i2c->adap);
1344 if (ret < 0) {
1345 dev_err(&pdev->dev, "failed to add adapter\n");
1346 goto disable_clk;
1347 }
1348
1349 return 0;
1350
1351disable_clk:
1352 clk_disable_unprepare(i2c->sys_clk);
1353 return ret;
1354}
1355
1356static int img_i2c_remove(struct platform_device *dev)
1357{
1358 struct img_i2c *i2c = platform_get_drvdata(dev);
1359
1360 i2c_del_adapter(&i2c->adap);
1361 clk_disable_unprepare(i2c->sys_clk);
1362
1363 return 0;
1364}
1365
1366#ifdef CONFIG_PM_SLEEP
1367static int img_i2c_suspend(struct device *dev)
1368{
1369 struct img_i2c *i2c = dev_get_drvdata(dev);
1370
1371 img_i2c_switch_mode(i2c, MODE_SUSPEND);
1372
1373 clk_disable_unprepare(i2c->sys_clk);
1374
1375 return 0;
1376}
1377
1378static int img_i2c_resume(struct device *dev)
1379{
1380 struct img_i2c *i2c = dev_get_drvdata(dev);
1381 int ret;
1382
1383 ret = clk_prepare_enable(i2c->sys_clk);
1384 if (ret)
1385 return ret;
1386
1387 img_i2c_init(i2c);
1388
1389 return 0;
1390}
1391#endif /* CONFIG_PM_SLEEP */
1392
1393static SIMPLE_DEV_PM_OPS(img_i2c_pm, img_i2c_suspend, img_i2c_resume);
1394
1395static const struct of_device_id img_scb_i2c_match[] = {
1396 { .compatible = "img,scb-i2c" },
1397 { }
1398};
1399MODULE_DEVICE_TABLE(of, img_scb_i2c_match);
1400
1401static struct platform_driver img_scb_i2c_driver = {
1402 .driver = {
1403 .name = "img-i2c-scb",
1404 .of_match_table = img_scb_i2c_match,
1405 .pm = &img_i2c_pm,
1406 },
1407 .probe = img_i2c_probe,
1408 .remove = img_i2c_remove,
1409};
1410module_platform_driver(img_scb_i2c_driver);
1411
1412MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>");
1413MODULE_DESCRIPTION("IMG host I2C driver");
1414MODULE_LICENSE("GPL v2");