Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2010 Daniel Vetter |
Ben Widawsky | c4ac524 | 2014-02-19 22:05:47 -0800 | [diff] [blame] | 3 | * Copyright © 2011-2014 Intel Corporation |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 22 | * IN THE SOFTWARE. |
| 23 | * |
| 24 | */ |
| 25 | |
Daniel Vetter | 0e46ce2 | 2014-01-08 16:10:27 +0100 | [diff] [blame] | 26 | #include <linux/seq_file.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/i915_drm.h> |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "i915_trace.h" |
| 31 | #include "intel_drv.h" |
| 32 | |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
| 34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); |
Ben Widawsky | a2319c0 | 2014-03-18 16:09:37 -0700 | [diff] [blame] | 35 | |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 36 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
| 37 | { |
| 38 | if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) |
| 39 | return 0; |
| 40 | |
| 41 | if (enable_ppgtt == 1) |
| 42 | return 1; |
| 43 | |
| 44 | if (enable_ppgtt == 2 && HAS_PPGTT(dev)) |
| 45 | return 2; |
| 46 | |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 47 | #ifdef CONFIG_INTEL_IOMMU |
| 48 | /* Disable ppgtt on SNB if VT-d is on. */ |
| 49 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { |
| 50 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 51 | return 0; |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 52 | } |
| 53 | #endif |
| 54 | |
Jesse Barnes | 62942ed | 2014-06-13 09:28:33 -0700 | [diff] [blame] | 55 | /* Early VLV doesn't have this */ |
Ville Syrjälä | ca2aed6c | 2014-06-28 02:03:56 +0300 | [diff] [blame] | 56 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 57 | dev->pdev->revision < 0xb) { |
Jesse Barnes | 62942ed | 2014-06-13 09:28:33 -0700 | [diff] [blame] | 58 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
| 59 | return 0; |
| 60 | } |
| 61 | |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 62 | return HAS_ALIASING_PPGTT(dev) ? 1 : 0; |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 65 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 66 | static void ppgtt_bind_vma(struct i915_vma *vma, |
| 67 | enum i915_cache_level cache_level, |
| 68 | u32 flags); |
| 69 | static void ppgtt_unbind_vma(struct i915_vma *vma); |
| 70 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 71 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
| 72 | enum i915_cache_level level, |
| 73 | bool valid) |
| 74 | { |
| 75 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
| 76 | pte |= addr; |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 77 | |
| 78 | switch (level) { |
| 79 | case I915_CACHE_NONE: |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 80 | pte |= PPAT_UNCACHED_INDEX; |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 81 | break; |
| 82 | case I915_CACHE_WT: |
| 83 | pte |= PPAT_DISPLAY_ELLC_INDEX; |
| 84 | break; |
| 85 | default: |
| 86 | pte |= PPAT_CACHED_INDEX; |
| 87 | break; |
| 88 | } |
| 89 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 90 | return pte; |
| 91 | } |
| 92 | |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 93 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
| 94 | dma_addr_t addr, |
| 95 | enum i915_cache_level level) |
| 96 | { |
| 97 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
| 98 | pde |= addr; |
| 99 | if (level != I915_CACHE_NONE) |
| 100 | pde |= PPAT_CACHED_PDE_INDEX; |
| 101 | else |
| 102 | pde |= PPAT_UNCACHED_INDEX; |
| 103 | return pde; |
| 104 | } |
| 105 | |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 106 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 107 | enum i915_cache_level level, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 108 | bool valid, u32 unused) |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 109 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 110 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 111 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 112 | |
| 113 | switch (level) { |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 114 | case I915_CACHE_L3_LLC: |
| 115 | case I915_CACHE_LLC: |
| 116 | pte |= GEN6_PTE_CACHE_LLC; |
| 117 | break; |
| 118 | case I915_CACHE_NONE: |
| 119 | pte |= GEN6_PTE_UNCACHED; |
| 120 | break; |
| 121 | default: |
| 122 | WARN_ON(1); |
| 123 | } |
| 124 | |
| 125 | return pte; |
| 126 | } |
| 127 | |
| 128 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 129 | enum i915_cache_level level, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 130 | bool valid, u32 unused) |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 131 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 132 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 133 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 134 | |
| 135 | switch (level) { |
| 136 | case I915_CACHE_L3_LLC: |
| 137 | pte |= GEN7_PTE_CACHE_L3_LLC; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 138 | break; |
| 139 | case I915_CACHE_LLC: |
| 140 | pte |= GEN6_PTE_CACHE_LLC; |
| 141 | break; |
| 142 | case I915_CACHE_NONE: |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 143 | pte |= GEN6_PTE_UNCACHED; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 144 | break; |
| 145 | default: |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 146 | WARN_ON(1); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 147 | } |
| 148 | |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 149 | return pte; |
| 150 | } |
| 151 | |
Ben Widawsky | 80a74f7 | 2013-06-27 16:30:19 -0700 | [diff] [blame] | 152 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 153 | enum i915_cache_level level, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 154 | bool valid, u32 flags) |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 155 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 156 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 157 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 158 | |
| 159 | /* Mark the page as writeable. Other platforms don't have a |
| 160 | * setting for read-only/writable, so this matches that behavior. |
| 161 | */ |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 162 | if (!(flags & PTE_READ_ONLY)) |
| 163 | pte |= BYT_PTE_WRITEABLE; |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 164 | |
| 165 | if (level != I915_CACHE_NONE) |
| 166 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; |
| 167 | |
| 168 | return pte; |
| 169 | } |
| 170 | |
Ben Widawsky | 80a74f7 | 2013-06-27 16:30:19 -0700 | [diff] [blame] | 171 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 172 | enum i915_cache_level level, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 173 | bool valid, u32 unused) |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 174 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 175 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 176 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 177 | |
| 178 | if (level != I915_CACHE_NONE) |
Ben Widawsky | 87a6b68 | 2013-08-04 23:47:29 -0700 | [diff] [blame] | 179 | pte |= HSW_WB_LLC_AGE3; |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 180 | |
| 181 | return pte; |
| 182 | } |
| 183 | |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 184 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 185 | enum i915_cache_level level, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 186 | bool valid, u32 unused) |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 187 | { |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 188 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 189 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
| 190 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 191 | switch (level) { |
| 192 | case I915_CACHE_NONE: |
| 193 | break; |
| 194 | case I915_CACHE_WT: |
Chris Wilson | c51e970 | 2013-11-22 10:37:53 +0000 | [diff] [blame] | 195 | pte |= HSW_WT_ELLC_LLC_AGE3; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 196 | break; |
| 197 | default: |
Chris Wilson | c51e970 | 2013-11-22 10:37:53 +0000 | [diff] [blame] | 198 | pte |= HSW_WB_ELLC_LLC_AGE3; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 199 | break; |
| 200 | } |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 201 | |
| 202 | return pte; |
| 203 | } |
| 204 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 205 | /* Broadwell Page Directory Pointer Descriptors */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 206 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 207 | uint64_t val, bool synchronous) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 208 | { |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 209 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 210 | int ret; |
| 211 | |
| 212 | BUG_ON(entry >= 4); |
| 213 | |
Ben Widawsky | e178f70 | 2013-12-06 14:10:47 -0800 | [diff] [blame] | 214 | if (synchronous) { |
| 215 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); |
| 216 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); |
| 217 | return 0; |
| 218 | } |
| 219 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 220 | ret = intel_ring_begin(ring, 6); |
| 221 | if (ret) |
| 222 | return ret; |
| 223 | |
| 224 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 225 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); |
| 226 | intel_ring_emit(ring, (u32)(val >> 32)); |
| 227 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 228 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); |
| 229 | intel_ring_emit(ring, (u32)(val)); |
| 230 | intel_ring_advance(ring); |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 235 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 236 | struct intel_engine_cs *ring, |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 237 | bool synchronous) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 238 | { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 239 | int i, ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 240 | |
| 241 | /* bit of a hack to find the actual last used pd */ |
| 242 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; |
| 243 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 244 | for (i = used_pd - 1; i >= 0; i--) { |
| 245 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 246 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
| 247 | if (ret) |
| 248 | return ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 249 | } |
Ben Widawsky | d595bd4 | 2013-11-25 09:54:32 -0800 | [diff] [blame] | 250 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 251 | return 0; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 252 | } |
| 253 | |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 254 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 255 | uint64_t start, |
| 256 | uint64_t length, |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 257 | bool use_scratch) |
| 258 | { |
| 259 | struct i915_hw_ppgtt *ppgtt = |
| 260 | container_of(vm, struct i915_hw_ppgtt, base); |
| 261 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 262 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
| 263 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
| 264 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 265 | unsigned num_entries = length >> PAGE_SHIFT; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 266 | unsigned last_pte, i; |
| 267 | |
| 268 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, |
| 269 | I915_CACHE_LLC, use_scratch); |
| 270 | |
| 271 | while (num_entries) { |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 272 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 273 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 274 | last_pte = pte + num_entries; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 275 | if (last_pte > GEN8_PTES_PER_PAGE) |
| 276 | last_pte = GEN8_PTES_PER_PAGE; |
| 277 | |
| 278 | pt_vaddr = kmap_atomic(page_table); |
| 279 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 280 | for (i = pte; i < last_pte; i++) { |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 281 | pt_vaddr[i] = scratch_pte; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 282 | num_entries--; |
| 283 | } |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 284 | |
Rafael Barbalho | fd1ab8f | 2014-04-09 13:28:02 +0300 | [diff] [blame] | 285 | if (!HAS_LLC(ppgtt->base.dev)) |
| 286 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 287 | kunmap_atomic(pt_vaddr); |
| 288 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 289 | pte = 0; |
| 290 | if (++pde == GEN8_PDES_PER_PAGE) { |
| 291 | pdpe++; |
| 292 | pde = 0; |
| 293 | } |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 294 | } |
| 295 | } |
| 296 | |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 297 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
| 298 | struct sg_table *pages, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 299 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 300 | enum i915_cache_level cache_level, u32 unused) |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 301 | { |
| 302 | struct i915_hw_ppgtt *ppgtt = |
| 303 | container_of(vm, struct i915_hw_ppgtt, base); |
| 304 | gen8_gtt_pte_t *pt_vaddr; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 305 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
| 306 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
| 307 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 308 | struct sg_page_iter sg_iter; |
| 309 | |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 310 | pt_vaddr = NULL; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 311 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 312 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
| 313 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
| 314 | break; |
| 315 | |
| 316 | if (pt_vaddr == NULL) |
| 317 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
| 318 | |
| 319 | pt_vaddr[pte] = |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 320 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
| 321 | cache_level, true); |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 322 | if (++pte == GEN8_PTES_PER_PAGE) { |
Rafael Barbalho | fd1ab8f | 2014-04-09 13:28:02 +0300 | [diff] [blame] | 323 | if (!HAS_LLC(ppgtt->base.dev)) |
| 324 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 325 | kunmap_atomic(pt_vaddr); |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 326 | pt_vaddr = NULL; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 327 | if (++pde == GEN8_PDES_PER_PAGE) { |
| 328 | pdpe++; |
| 329 | pde = 0; |
| 330 | } |
| 331 | pte = 0; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 332 | } |
| 333 | } |
Rafael Barbalho | fd1ab8f | 2014-04-09 13:28:02 +0300 | [diff] [blame] | 334 | if (pt_vaddr) { |
| 335 | if (!HAS_LLC(ppgtt->base.dev)) |
| 336 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 337 | kunmap_atomic(pt_vaddr); |
Rafael Barbalho | fd1ab8f | 2014-04-09 13:28:02 +0300 | [diff] [blame] | 338 | } |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 339 | } |
| 340 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 341 | static void gen8_free_page_tables(struct page **pt_pages) |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 342 | { |
| 343 | int i; |
| 344 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 345 | if (pt_pages == NULL) |
| 346 | return; |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 347 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 348 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) |
| 349 | if (pt_pages[i]) |
| 350 | __free_pages(pt_pages[i], 0); |
| 351 | } |
| 352 | |
| 353 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) |
| 354 | { |
| 355 | int i; |
| 356 | |
| 357 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
| 358 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); |
| 359 | kfree(ppgtt->gen8_pt_pages[i]); |
| 360 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
| 361 | } |
| 362 | |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 363 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
| 364 | } |
| 365 | |
| 366 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
| 367 | { |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 368 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 369 | int i, j; |
| 370 | |
| 371 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
| 372 | /* TODO: In the future we'll support sparse mappings, so this |
| 373 | * will have to change. */ |
| 374 | if (!ppgtt->pd_dma_addr[i]) |
| 375 | continue; |
| 376 | |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 377 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
| 378 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 379 | |
| 380 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
| 381 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
| 382 | if (addr) |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 383 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
| 384 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 385 | } |
| 386 | } |
| 387 | } |
| 388 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 389 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
| 390 | { |
| 391 | struct i915_hw_ppgtt *ppgtt = |
| 392 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 393 | |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 394 | gen8_ppgtt_unmap_pages(ppgtt); |
| 395 | gen8_ppgtt_free(ppgtt); |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 396 | } |
| 397 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 398 | static struct page **__gen8_alloc_page_tables(void) |
| 399 | { |
| 400 | struct page **pt_pages; |
| 401 | int i; |
| 402 | |
| 403 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); |
| 404 | if (!pt_pages) |
| 405 | return ERR_PTR(-ENOMEM); |
| 406 | |
| 407 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { |
| 408 | pt_pages[i] = alloc_page(GFP_KERNEL); |
| 409 | if (!pt_pages[i]) |
| 410 | goto bail; |
| 411 | } |
| 412 | |
| 413 | return pt_pages; |
| 414 | |
| 415 | bail: |
| 416 | gen8_free_page_tables(pt_pages); |
| 417 | kfree(pt_pages); |
| 418 | return ERR_PTR(-ENOMEM); |
| 419 | } |
| 420 | |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 421 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
| 422 | const int max_pdp) |
| 423 | { |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 424 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 425 | int i, ret; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 426 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 427 | for (i = 0; i < max_pdp; i++) { |
| 428 | pt_pages[i] = __gen8_alloc_page_tables(); |
| 429 | if (IS_ERR(pt_pages[i])) { |
| 430 | ret = PTR_ERR(pt_pages[i]); |
| 431 | goto unwind_out; |
| 432 | } |
| 433 | } |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 434 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 435 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, |
| 436 | * "atomic" - for cleanup purposes. |
| 437 | */ |
| 438 | for (i = 0; i < max_pdp; i++) |
| 439 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; |
| 440 | |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 441 | return 0; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 442 | |
| 443 | unwind_out: |
| 444 | while (i--) { |
| 445 | gen8_free_page_tables(pt_pages[i]); |
| 446 | kfree(pt_pages[i]); |
| 447 | } |
| 448 | |
| 449 | return ret; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) |
| 453 | { |
| 454 | int i; |
| 455 | |
| 456 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
| 457 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, |
| 458 | sizeof(dma_addr_t), |
| 459 | GFP_KERNEL); |
| 460 | if (!ppgtt->gen8_pt_dma_addr[i]) |
| 461 | return -ENOMEM; |
| 462 | } |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, |
| 468 | const int max_pdp) |
| 469 | { |
| 470 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); |
| 471 | if (!ppgtt->pd_pages) |
| 472 | return -ENOMEM; |
| 473 | |
| 474 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); |
| 475 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); |
| 476 | |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, |
| 481 | const int max_pdp) |
| 482 | { |
| 483 | int ret; |
| 484 | |
| 485 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); |
| 486 | if (ret) |
| 487 | return ret; |
| 488 | |
| 489 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); |
| 490 | if (ret) { |
| 491 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); |
| 492 | return ret; |
| 493 | } |
| 494 | |
| 495 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; |
| 496 | |
| 497 | ret = gen8_ppgtt_allocate_dma(ppgtt); |
| 498 | if (ret) |
| 499 | gen8_ppgtt_free(ppgtt); |
| 500 | |
| 501 | return ret; |
| 502 | } |
| 503 | |
| 504 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, |
| 505 | const int pd) |
| 506 | { |
| 507 | dma_addr_t pd_addr; |
| 508 | int ret; |
| 509 | |
| 510 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, |
| 511 | &ppgtt->pd_pages[pd], 0, |
| 512 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 513 | |
| 514 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); |
| 515 | if (ret) |
| 516 | return ret; |
| 517 | |
| 518 | ppgtt->pd_dma_addr[pd] = pd_addr; |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, |
| 524 | const int pd, |
| 525 | const int pt) |
| 526 | { |
| 527 | dma_addr_t pt_addr; |
| 528 | struct page *p; |
| 529 | int ret; |
| 530 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 531 | p = ppgtt->gen8_pt_pages[pd][pt]; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 532 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
| 533 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 534 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); |
| 535 | if (ret) |
| 536 | return ret; |
| 537 | |
| 538 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 543 | /** |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 544 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
| 545 | * with a net effect resembling a 2-level page table in normal x86 terms. Each |
| 546 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address |
| 547 | * space. |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 548 | * |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 549 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
| 550 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 551 | * TODO: Do something with the size parameter |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 552 | */ |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 553 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
| 554 | { |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 555 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 556 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 557 | int i, j, ret; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 558 | |
| 559 | if (size % (1<<30)) |
| 560 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); |
| 561 | |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 562 | /* 1. Do all our allocations for page directories and page tables. */ |
| 563 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); |
| 564 | if (ret) |
| 565 | return ret; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 566 | |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 567 | /* |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 568 | * 2. Create DMA mappings for the page directories and page tables. |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 569 | */ |
| 570 | for (i = 0; i < max_pdp; i++) { |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 571 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 572 | if (ret) |
| 573 | goto bail; |
| 574 | |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 575 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 576 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 577 | if (ret) |
| 578 | goto bail; |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 579 | } |
| 580 | } |
| 581 | |
| 582 | /* |
| 583 | * 3. Map all the page directory entires to point to the page tables |
| 584 | * we've allocated. |
| 585 | * |
| 586 | * For now, the PPGTT helper functions all require that the PDEs are |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 587 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 588 | * will never need to touch the PDEs again. |
| 589 | */ |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 590 | for (i = 0; i < max_pdp; i++) { |
| 591 | gen8_ppgtt_pde_t *pd_vaddr; |
| 592 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); |
| 593 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
| 594 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; |
| 595 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
| 596 | I915_CACHE_LLC); |
| 597 | } |
Rafael Barbalho | fd1ab8f | 2014-04-09 13:28:02 +0300 | [diff] [blame] | 598 | if (!HAS_LLC(ppgtt->base.dev)) |
| 599 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 600 | kunmap_atomic(pd_vaddr); |
| 601 | } |
| 602 | |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 603 | ppgtt->switch_mm = gen8_mm_switch; |
| 604 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
| 605 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
| 606 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
| 607 | ppgtt->base.start = 0; |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 608 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 609 | |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 610 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 611 | |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 612 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
| 613 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); |
| 614 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 615 | ppgtt->num_pd_entries, |
| 616 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 617 | return 0; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 618 | |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 619 | bail: |
| 620 | gen8_ppgtt_unmap_pages(ppgtt); |
| 621 | gen8_ppgtt_free(ppgtt); |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 622 | return ret; |
| 623 | } |
| 624 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 625 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
| 626 | { |
| 627 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
| 628 | struct i915_address_space *vm = &ppgtt->base; |
| 629 | gen6_gtt_pte_t __iomem *pd_addr; |
| 630 | gen6_gtt_pte_t scratch_pte; |
| 631 | uint32_t pd_entry; |
| 632 | int pte, pde; |
| 633 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 634 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 635 | |
| 636 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + |
| 637 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); |
| 638 | |
| 639 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, |
| 640 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); |
| 641 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { |
| 642 | u32 expected; |
| 643 | gen6_gtt_pte_t *pt_vaddr; |
| 644 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; |
| 645 | pd_entry = readl(pd_addr + pde); |
| 646 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
| 647 | |
| 648 | if (pd_entry != expected) |
| 649 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", |
| 650 | pde, |
| 651 | pd_entry, |
| 652 | expected); |
| 653 | seq_printf(m, "\tPDE: %x\n", pd_entry); |
| 654 | |
| 655 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); |
| 656 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { |
| 657 | unsigned long va = |
| 658 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + |
| 659 | (pte * PAGE_SIZE); |
| 660 | int i; |
| 661 | bool found = false; |
| 662 | for (i = 0; i < 4; i++) |
| 663 | if (pt_vaddr[pte + i] != scratch_pte) |
| 664 | found = true; |
| 665 | if (!found) |
| 666 | continue; |
| 667 | |
| 668 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); |
| 669 | for (i = 0; i < 4; i++) { |
| 670 | if (pt_vaddr[pte + i] != scratch_pte) |
| 671 | seq_printf(m, " %08x", pt_vaddr[pte + i]); |
| 672 | else |
| 673 | seq_puts(m, " SCRATCH "); |
| 674 | } |
| 675 | seq_puts(m, "\n"); |
| 676 | } |
| 677 | kunmap_atomic(pt_vaddr); |
| 678 | } |
| 679 | } |
| 680 | |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 681 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 682 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 683 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 684 | gen6_gtt_pte_t __iomem *pd_addr; |
| 685 | uint32_t pd_entry; |
| 686 | int i; |
| 687 | |
Ben Widawsky | 0a73287 | 2013-04-23 23:15:30 -0700 | [diff] [blame] | 688 | WARN_ON(ppgtt->pd_offset & 0x3f); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 689 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
| 690 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); |
| 691 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 692 | dma_addr_t pt_addr; |
| 693 | |
| 694 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 695 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 696 | pd_entry |= GEN6_PDE_VALID; |
| 697 | |
| 698 | writel(pd_entry, pd_addr + i); |
| 699 | } |
| 700 | readl(pd_addr); |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 701 | } |
| 702 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 703 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 704 | { |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 705 | BUG_ON(ppgtt->pd_offset & 0x3f); |
| 706 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 707 | return (ppgtt->pd_offset / 64) << 16; |
| 708 | } |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 709 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 710 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 711 | struct intel_engine_cs *ring, |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 712 | bool synchronous) |
| 713 | { |
| 714 | struct drm_device *dev = ppgtt->base.dev; |
| 715 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 716 | int ret; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 717 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 718 | /* If we're in reset, we can assume the GPU is sufficiently idle to |
| 719 | * manually frob these bits. Ideally we could use the ring functions, |
| 720 | * except our error handling makes it quite difficult (can't use |
| 721 | * intel_ring_begin, ring->flush, or intel_ring_advance) |
| 722 | * |
| 723 | * FIXME: We should try not to special case reset |
| 724 | */ |
| 725 | if (synchronous || |
| 726 | i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 727 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); |
| 728 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 729 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 730 | POSTING_READ(RING_PP_DIR_BASE(ring)); |
| 731 | return 0; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 732 | } |
| 733 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 734 | /* NB: TLBs must be flushed and invalidated before a switch */ |
| 735 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 736 | if (ret) |
| 737 | return ret; |
| 738 | |
| 739 | ret = intel_ring_begin(ring, 6); |
| 740 | if (ret) |
| 741 | return ret; |
| 742 | |
| 743 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 744 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 745 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 746 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 747 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 748 | intel_ring_emit(ring, MI_NOOP); |
| 749 | intel_ring_advance(ring); |
| 750 | |
| 751 | return 0; |
| 752 | } |
| 753 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 754 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 755 | struct intel_engine_cs *ring, |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 756 | bool synchronous) |
| 757 | { |
| 758 | struct drm_device *dev = ppgtt->base.dev; |
| 759 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 760 | int ret; |
| 761 | |
| 762 | /* If we're in reset, we can assume the GPU is sufficiently idle to |
| 763 | * manually frob these bits. Ideally we could use the ring functions, |
| 764 | * except our error handling makes it quite difficult (can't use |
| 765 | * intel_ring_begin, ring->flush, or intel_ring_advance) |
| 766 | * |
| 767 | * FIXME: We should try not to special case reset |
| 768 | */ |
| 769 | if (synchronous || |
| 770 | i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 771 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); |
| 772 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 773 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 774 | POSTING_READ(RING_PP_DIR_BASE(ring)); |
| 775 | return 0; |
| 776 | } |
| 777 | |
| 778 | /* NB: TLBs must be flushed and invalidated before a switch */ |
| 779 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 780 | if (ret) |
| 781 | return ret; |
| 782 | |
| 783 | ret = intel_ring_begin(ring, 6); |
| 784 | if (ret) |
| 785 | return ret; |
| 786 | |
| 787 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 788 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 789 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 790 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 791 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 792 | intel_ring_emit(ring, MI_NOOP); |
| 793 | intel_ring_advance(ring); |
| 794 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 795 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
| 796 | if (ring->id != RCS) { |
| 797 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 798 | if (ret) |
| 799 | return ret; |
| 800 | } |
| 801 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 802 | return 0; |
| 803 | } |
| 804 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 805 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 806 | struct intel_engine_cs *ring, |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 807 | bool synchronous) |
| 808 | { |
| 809 | struct drm_device *dev = ppgtt->base.dev; |
| 810 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 811 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 812 | if (!synchronous) |
| 813 | return 0; |
| 814 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 815 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 816 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 817 | |
| 818 | POSTING_READ(RING_PP_DIR_DCLV(ring)); |
| 819 | |
| 820 | return 0; |
| 821 | } |
| 822 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 823 | static void gen8_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 824 | { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 825 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 826 | struct intel_engine_cs *ring; |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 827 | int j; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 828 | |
Oscar Mateo | b7c7182 | 2014-08-15 12:01:31 +0100 | [diff] [blame] | 829 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
| 830 | * and the PDPs are contained within the context itself. We don't |
| 831 | * need to do anything here. */ |
| 832 | if (i915.enable_execlists) |
| 833 | return; |
| 834 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 835 | for_each_ring(ring, dev_priv, j) { |
| 836 | I915_WRITE(RING_MODE_GEN7(ring), |
| 837 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 838 | } |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 839 | } |
| 840 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 841 | static void gen7_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 842 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 843 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 844 | struct intel_engine_cs *ring; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 845 | uint32_t ecochk, ecobits; |
| 846 | int i; |
| 847 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 848 | ecobits = I915_READ(GAC_ECO_BITS); |
| 849 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
| 850 | |
| 851 | ecochk = I915_READ(GAM_ECOCHK); |
| 852 | if (IS_HASWELL(dev)) { |
| 853 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
| 854 | } else { |
| 855 | ecochk |= ECOCHK_PPGTT_LLC_IVB; |
| 856 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; |
| 857 | } |
| 858 | I915_WRITE(GAM_ECOCHK, ecochk); |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 859 | |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 860 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 861 | /* GFX_MODE is per-ring on gen7+ */ |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 862 | I915_WRITE(RING_MODE_GEN7(ring), |
| 863 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 864 | } |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 865 | } |
| 866 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 867 | static void gen6_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 868 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 870 | uint32_t ecochk, gab_ctl, ecobits; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 871 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 872 | ecobits = I915_READ(GAC_ECO_BITS); |
| 873 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
| 874 | ECOBITS_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 875 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 876 | gab_ctl = I915_READ(GAB_CTL); |
| 877 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 878 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 879 | ecochk = I915_READ(GAM_ECOCHK); |
| 880 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 881 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 882 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 883 | } |
| 884 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 885 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 886 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 887 | uint64_t start, |
| 888 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 889 | bool use_scratch) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 890 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 891 | struct i915_hw_ppgtt *ppgtt = |
| 892 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 893 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 894 | unsigned first_entry = start >> PAGE_SHIFT; |
| 895 | unsigned num_entries = length >> PAGE_SHIFT; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 896 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 897 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 898 | unsigned last_pte, i; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 899 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 900 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 901 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 902 | while (num_entries) { |
| 903 | last_pte = first_pte + num_entries; |
| 904 | if (last_pte > I915_PPGTT_PT_ENTRIES) |
| 905 | last_pte = I915_PPGTT_PT_ENTRIES; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 906 | |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 907 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 908 | |
| 909 | for (i = first_pte; i < last_pte; i++) |
| 910 | pt_vaddr[i] = scratch_pte; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 911 | |
| 912 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 913 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 914 | num_entries -= last_pte - first_pte; |
| 915 | first_pte = 0; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 916 | act_pt++; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 917 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 918 | } |
| 919 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 920 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 921 | struct sg_table *pages, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 922 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 923 | enum i915_cache_level cache_level, u32 flags) |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 924 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 925 | struct i915_hw_ppgtt *ppgtt = |
| 926 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 927 | gen6_gtt_pte_t *pt_vaddr; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 928 | unsigned first_entry = start >> PAGE_SHIFT; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 929 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 930 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
| 931 | struct sg_page_iter sg_iter; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 932 | |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 933 | pt_vaddr = NULL; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 934 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 935 | if (pt_vaddr == NULL) |
| 936 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 937 | |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 938 | pt_vaddr[act_pte] = |
| 939 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 940 | cache_level, true, flags); |
| 941 | |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 942 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
| 943 | kunmap_atomic(pt_vaddr); |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 944 | pt_vaddr = NULL; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 945 | act_pt++; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 946 | act_pte = 0; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 947 | } |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 948 | } |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 949 | if (pt_vaddr) |
| 950 | kunmap_atomic(pt_vaddr); |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 951 | } |
| 952 | |
Ben Widawsky | a00d825 | 2014-02-19 22:05:48 -0800 | [diff] [blame] | 953 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 954 | { |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 955 | int i; |
| 956 | |
| 957 | if (ppgtt->pt_dma_addr) { |
| 958 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 959 | pci_unmap_page(ppgtt->base.dev->pdev, |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 960 | ppgtt->pt_dma_addr[i], |
| 961 | 4096, PCI_DMA_BIDIRECTIONAL); |
| 962 | } |
Ben Widawsky | a00d825 | 2014-02-19 22:05:48 -0800 | [diff] [blame] | 963 | } |
| 964 | |
| 965 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
| 966 | { |
| 967 | int i; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 968 | |
| 969 | kfree(ppgtt->pt_dma_addr); |
| 970 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
| 971 | __free_page(ppgtt->pt_pages[i]); |
| 972 | kfree(ppgtt->pt_pages); |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 973 | } |
| 974 | |
Ben Widawsky | a00d825 | 2014-02-19 22:05:48 -0800 | [diff] [blame] | 975 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
| 976 | { |
| 977 | struct i915_hw_ppgtt *ppgtt = |
| 978 | container_of(vm, struct i915_hw_ppgtt, base); |
| 979 | |
Ben Widawsky | a00d825 | 2014-02-19 22:05:48 -0800 | [diff] [blame] | 980 | drm_mm_remove_node(&ppgtt->node); |
| 981 | |
| 982 | gen6_ppgtt_unmap_pages(ppgtt); |
| 983 | gen6_ppgtt_free(ppgtt); |
| 984 | } |
| 985 | |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 986 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 987 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 988 | struct drm_device *dev = ppgtt->base.dev; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 989 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 990 | bool retried = false; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 991 | int ret; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 992 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 993 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
| 994 | * allocator works in address space sizes, so it's multiplied by page |
| 995 | * size. We allocate at the top of the GTT to avoid fragmentation. |
| 996 | */ |
| 997 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 998 | alloc: |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 999 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
| 1000 | &ppgtt->node, GEN6_PD_SIZE, |
| 1001 | GEN6_PD_ALIGN, 0, |
| 1002 | 0, dev_priv->gtt.base.total, |
Ben Widawsky | 3e8b5ae | 2014-05-06 22:21:30 -0700 | [diff] [blame] | 1003 | DRM_MM_TOPDOWN); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1004 | if (ret == -ENOSPC && !retried) { |
| 1005 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, |
| 1006 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 1007 | I915_CACHE_NONE, |
| 1008 | 0, dev_priv->gtt.base.total, |
| 1009 | 0); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1010 | if (ret) |
| 1011 | return ret; |
| 1012 | |
| 1013 | retried = true; |
| 1014 | goto alloc; |
| 1015 | } |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1016 | |
| 1017 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
| 1018 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1019 | |
Ben Widawsky | 6670a5a | 2013-06-27 16:30:04 -0700 | [diff] [blame] | 1020 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1021 | return ret; |
| 1022 | } |
| 1023 | |
| 1024 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) |
| 1025 | { |
| 1026 | int i; |
| 1027 | |
| 1028 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
| 1029 | GFP_KERNEL); |
| 1030 | |
| 1031 | if (!ppgtt->pt_pages) |
| 1032 | return -ENOMEM; |
| 1033 | |
| 1034 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 1035 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); |
| 1036 | if (!ppgtt->pt_pages[i]) { |
| 1037 | gen6_ppgtt_free(ppgtt); |
| 1038 | return -ENOMEM; |
| 1039 | } |
| 1040 | } |
| 1041 | |
| 1042 | return 0; |
| 1043 | } |
| 1044 | |
| 1045 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
| 1046 | { |
| 1047 | int ret; |
| 1048 | |
| 1049 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); |
| 1050 | if (ret) |
| 1051 | return ret; |
| 1052 | |
| 1053 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); |
| 1054 | if (ret) { |
| 1055 | drm_mm_remove_node(&ppgtt->node); |
| 1056 | return ret; |
| 1057 | } |
| 1058 | |
| 1059 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
| 1060 | GFP_KERNEL); |
| 1061 | if (!ppgtt->pt_dma_addr) { |
| 1062 | drm_mm_remove_node(&ppgtt->node); |
| 1063 | gen6_ppgtt_free(ppgtt); |
| 1064 | return -ENOMEM; |
| 1065 | } |
| 1066 | |
| 1067 | return 0; |
| 1068 | } |
| 1069 | |
| 1070 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) |
| 1071 | { |
| 1072 | struct drm_device *dev = ppgtt->base.dev; |
| 1073 | int i; |
| 1074 | |
| 1075 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 1076 | dma_addr_t pt_addr; |
| 1077 | |
| 1078 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
| 1079 | PCI_DMA_BIDIRECTIONAL); |
| 1080 | |
| 1081 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
| 1082 | gen6_ppgtt_unmap_pages(ppgtt); |
| 1083 | return -EIO; |
| 1084 | } |
| 1085 | |
| 1086 | ppgtt->pt_dma_addr[i] = pt_addr; |
| 1087 | } |
| 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
| 1093 | { |
| 1094 | struct drm_device *dev = ppgtt->base.dev; |
| 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1096 | int ret; |
| 1097 | |
| 1098 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1099 | if (IS_GEN6(dev)) { |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1100 | ppgtt->switch_mm = gen6_mm_switch; |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1101 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1102 | ppgtt->switch_mm = hsw_mm_switch; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1103 | } else if (IS_GEN7(dev)) { |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1104 | ppgtt->switch_mm = gen7_mm_switch; |
| 1105 | } else |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1106 | BUG(); |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1107 | |
| 1108 | ret = gen6_ppgtt_alloc(ppgtt); |
| 1109 | if (ret) |
| 1110 | return ret; |
| 1111 | |
| 1112 | ret = gen6_ppgtt_setup_page_tables(ppgtt); |
| 1113 | if (ret) { |
| 1114 | gen6_ppgtt_free(ppgtt); |
| 1115 | return ret; |
| 1116 | } |
| 1117 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1118 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
| 1119 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; |
| 1120 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
Ben Widawsky | 686e1f6 | 2013-11-25 09:54:34 -0800 | [diff] [blame] | 1121 | ppgtt->base.start = 0; |
Ben Widawsky | 5a6c93f | 2014-03-08 11:58:17 -0800 | [diff] [blame] | 1122 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1123 | ppgtt->debug_dump = gen6_dump_ppgtt; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1124 | |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1125 | ppgtt->pd_offset = |
| 1126 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1127 | |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1128 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1129 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1130 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
| 1131 | ppgtt->node.size >> 20, |
| 1132 | ppgtt->node.start / PAGE_SIZE); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1133 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1134 | gen6_write_pdes(ppgtt); |
| 1135 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
| 1136 | ppgtt->pd_offset << 10); |
| 1137 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1138 | return 0; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1139 | } |
| 1140 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1141 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1142 | { |
| 1143 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1144 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1145 | ppgtt->base.dev = dev; |
Ben Widawsky | 8407bb9 | 2014-03-08 11:58:16 -0800 | [diff] [blame] | 1146 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1147 | |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1148 | if (INTEL_INFO(dev)->gen < 8) |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1149 | return gen6_ppgtt_init(ppgtt); |
Daniel Vetter | 8fe6bd2 | 2013-11-02 21:07:01 -0700 | [diff] [blame] | 1150 | else if (IS_GEN8(dev)) |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1151 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1152 | else |
| 1153 | BUG(); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1154 | } |
| 1155 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
| 1156 | { |
| 1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1158 | int ret = 0; |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1159 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1160 | ret = __hw_ppgtt_init(dev, ppgtt); |
| 1161 | if (ret == 0) { |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 1162 | kref_init(&ppgtt->ref); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1163 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
| 1164 | ppgtt->base.total); |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 1165 | i915_init_vm(dev_priv, &ppgtt->base); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1166 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1167 | |
| 1168 | return ret; |
| 1169 | } |
| 1170 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1171 | int i915_ppgtt_init_hw(struct drm_device *dev) |
| 1172 | { |
| 1173 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1174 | struct intel_engine_cs *ring; |
| 1175 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1176 | int i, ret = 0; |
| 1177 | |
| 1178 | if (!USES_PPGTT(dev)) |
| 1179 | return 0; |
| 1180 | |
| 1181 | if (IS_GEN6(dev)) |
| 1182 | gen6_ppgtt_enable(dev); |
| 1183 | else if (IS_GEN7(dev)) |
| 1184 | gen7_ppgtt_enable(dev); |
| 1185 | else if (INTEL_INFO(dev)->gen >= 8) |
| 1186 | gen8_ppgtt_enable(dev); |
| 1187 | else |
| 1188 | WARN_ON(1); |
| 1189 | |
| 1190 | if (ppgtt) { |
| 1191 | for_each_ring(ring, dev_priv, i) { |
| 1192 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
| 1193 | if (ret != 0) |
| 1194 | return ret; |
| 1195 | } |
| 1196 | } |
| 1197 | |
| 1198 | return ret; |
| 1199 | } |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 1200 | struct i915_hw_ppgtt * |
| 1201 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) |
| 1202 | { |
| 1203 | struct i915_hw_ppgtt *ppgtt; |
| 1204 | int ret; |
| 1205 | |
| 1206 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 1207 | if (!ppgtt) |
| 1208 | return ERR_PTR(-ENOMEM); |
| 1209 | |
| 1210 | ret = i915_ppgtt_init(dev, ppgtt); |
| 1211 | if (ret) { |
| 1212 | kfree(ppgtt); |
| 1213 | return ERR_PTR(ret); |
| 1214 | } |
| 1215 | |
| 1216 | ppgtt->file_priv = fpriv; |
| 1217 | |
| 1218 | return ppgtt; |
| 1219 | } |
| 1220 | |
Daniel Vetter | ee960be | 2014-08-06 15:04:45 +0200 | [diff] [blame] | 1221 | void i915_ppgtt_release(struct kref *kref) |
| 1222 | { |
| 1223 | struct i915_hw_ppgtt *ppgtt = |
| 1224 | container_of(kref, struct i915_hw_ppgtt, ref); |
| 1225 | |
| 1226 | /* vmas should already be unbound */ |
| 1227 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
| 1228 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); |
| 1229 | |
Daniel Vetter | 19dd120 | 2014-08-06 15:04:55 +0200 | [diff] [blame] | 1230 | list_del(&ppgtt->base.global_link); |
| 1231 | drm_mm_takedown(&ppgtt->base.mm); |
| 1232 | |
Daniel Vetter | ee960be | 2014-08-06 15:04:45 +0200 | [diff] [blame] | 1233 | ppgtt->base.cleanup(&ppgtt->base); |
| 1234 | kfree(ppgtt); |
| 1235 | } |
| 1236 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 1237 | static void |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1238 | ppgtt_bind_vma(struct i915_vma *vma, |
| 1239 | enum i915_cache_level cache_level, |
| 1240 | u32 flags) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1241 | { |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1242 | /* Currently applicable only to VLV */ |
| 1243 | if (vma->obj->gt_ro) |
| 1244 | flags |= PTE_READ_ONLY; |
| 1245 | |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1246 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1247 | cache_level, flags); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1248 | } |
| 1249 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 1250 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1251 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1252 | vma->vm->clear_range(vma->vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1253 | vma->node.start, |
| 1254 | vma->obj->base.size, |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1255 | true); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1256 | } |
| 1257 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1258 | extern int intel_iommu_gfx_mapped; |
| 1259 | /* Certain Gen5 chipsets require require idling the GPU before |
| 1260 | * unmapping anything from the GTT when VT-d is enabled. |
| 1261 | */ |
| 1262 | static inline bool needs_idle_maps(struct drm_device *dev) |
| 1263 | { |
| 1264 | #ifdef CONFIG_INTEL_IOMMU |
| 1265 | /* Query intel_iommu to see if we need the workaround. Presumably that |
| 1266 | * was loaded first. |
| 1267 | */ |
| 1268 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) |
| 1269 | return true; |
| 1270 | #endif |
| 1271 | return false; |
| 1272 | } |
| 1273 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1274 | static bool do_idling(struct drm_i915_private *dev_priv) |
| 1275 | { |
| 1276 | bool ret = dev_priv->mm.interruptible; |
| 1277 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1278 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1279 | dev_priv->mm.interruptible = false; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1280 | if (i915_gpu_idle(dev_priv->dev)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1281 | DRM_ERROR("Couldn't idle GPU\n"); |
| 1282 | /* Wait a bit, in hopes it avoids the hang */ |
| 1283 | udelay(10); |
| 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | return ret; |
| 1288 | } |
| 1289 | |
| 1290 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) |
| 1291 | { |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1292 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1293 | dev_priv->mm.interruptible = interruptible; |
| 1294 | } |
| 1295 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1296 | void i915_check_and_clear_faults(struct drm_device *dev) |
| 1297 | { |
| 1298 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1299 | struct intel_engine_cs *ring; |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1300 | int i; |
| 1301 | |
| 1302 | if (INTEL_INFO(dev)->gen < 6) |
| 1303 | return; |
| 1304 | |
| 1305 | for_each_ring(ring, dev_priv, i) { |
| 1306 | u32 fault_reg; |
| 1307 | fault_reg = I915_READ(RING_FAULT_REG(ring)); |
| 1308 | if (fault_reg & RING_FAULT_VALID) { |
| 1309 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
| 1310 | "\tAddr: 0x%08lx\\n" |
| 1311 | "\tAddress space: %s\n" |
| 1312 | "\tSource ID: %d\n" |
| 1313 | "\tType: %d\n", |
| 1314 | fault_reg & PAGE_MASK, |
| 1315 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", |
| 1316 | RING_FAULT_SRCID(fault_reg), |
| 1317 | RING_FAULT_FAULT_TYPE(fault_reg)); |
| 1318 | I915_WRITE(RING_FAULT_REG(ring), |
| 1319 | fault_reg & ~RING_FAULT_VALID); |
| 1320 | } |
| 1321 | } |
| 1322 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); |
| 1323 | } |
| 1324 | |
| 1325 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
| 1326 | { |
| 1327 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1328 | |
| 1329 | /* Don't bother messing with faults pre GEN6 as we have little |
| 1330 | * documentation supporting that it's a good idea. |
| 1331 | */ |
| 1332 | if (INTEL_INFO(dev)->gen < 6) |
| 1333 | return; |
| 1334 | |
| 1335 | i915_check_and_clear_faults(dev); |
| 1336 | |
| 1337 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1338 | dev_priv->gtt.base.start, |
| 1339 | dev_priv->gtt.base.total, |
Daniel Vetter | e568af1 | 2014-03-26 20:08:20 +0100 | [diff] [blame] | 1340 | true); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1341 | } |
| 1342 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1343 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
| 1344 | { |
| 1345 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1346 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 80da216 | 2013-12-06 14:11:17 -0800 | [diff] [blame] | 1347 | struct i915_address_space *vm; |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1348 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1349 | i915_check_and_clear_faults(dev); |
| 1350 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 1351 | /* First fill our portion of the GTT with scratch pages */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1352 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1353 | dev_priv->gtt.base.start, |
| 1354 | dev_priv->gtt.base.total, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1355 | true); |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 1356 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1357 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1358 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
| 1359 | &dev_priv->gtt.base); |
| 1360 | if (!vma) |
| 1361 | continue; |
| 1362 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1363 | i915_gem_clflush_object(obj, obj->pin_display); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1364 | /* The bind_vma code tries to be smart about tracking mappings. |
| 1365 | * Unfortunately above, we've just wiped out the mappings |
| 1366 | * without telling our object about it. So we need to fake it. |
| 1367 | */ |
| 1368 | obj->has_global_gtt_mapping = 0; |
| 1369 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1370 | } |
| 1371 | |
Ben Widawsky | 80da216 | 2013-12-06 14:11:17 -0800 | [diff] [blame] | 1372 | |
Ben Widawsky | a2319c0 | 2014-03-18 16:09:37 -0700 | [diff] [blame] | 1373 | if (INTEL_INFO(dev)->gen >= 8) { |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 1374 | if (IS_CHERRYVIEW(dev)) |
| 1375 | chv_setup_private_ppat(dev_priv); |
| 1376 | else |
| 1377 | bdw_setup_private_ppat(dev_priv); |
| 1378 | |
Ben Widawsky | 80da216 | 2013-12-06 14:11:17 -0800 | [diff] [blame] | 1379 | return; |
Ben Widawsky | a2319c0 | 2014-03-18 16:09:37 -0700 | [diff] [blame] | 1380 | } |
Ben Widawsky | 80da216 | 2013-12-06 14:11:17 -0800 | [diff] [blame] | 1381 | |
| 1382 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 1383 | /* TODO: Perhaps it shouldn't be gen6 specific */ |
| 1384 | if (i915_is_ggtt(vm)) { |
| 1385 | if (dev_priv->mm.aliasing_ppgtt) |
| 1386 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); |
| 1387 | continue; |
| 1388 | } |
| 1389 | |
| 1390 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1391 | } |
| 1392 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1393 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1394 | } |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1395 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1396 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1397 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1398 | if (obj->has_dma_mapping) |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1399 | return 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1400 | |
| 1401 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
| 1402 | obj->pages->sgl, obj->pages->nents, |
| 1403 | PCI_DMA_BIDIRECTIONAL)) |
| 1404 | return -ENOSPC; |
| 1405 | |
| 1406 | return 0; |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1407 | } |
| 1408 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1409 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
| 1410 | { |
| 1411 | #ifdef writeq |
| 1412 | writeq(pte, addr); |
| 1413 | #else |
| 1414 | iowrite32((u32)pte, addr); |
| 1415 | iowrite32(pte >> 32, addr + 4); |
| 1416 | #endif |
| 1417 | } |
| 1418 | |
| 1419 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
| 1420 | struct sg_table *st, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1421 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1422 | enum i915_cache_level level, u32 unused) |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1423 | { |
| 1424 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1425 | unsigned first_entry = start >> PAGE_SHIFT; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1426 | gen8_gtt_pte_t __iomem *gtt_entries = |
| 1427 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
| 1428 | int i = 0; |
| 1429 | struct sg_page_iter sg_iter; |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1430 | dma_addr_t addr = 0; /* shut up gcc */ |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1431 | |
| 1432 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
| 1433 | addr = sg_dma_address(sg_iter.sg) + |
| 1434 | (sg_iter.sg_pgoffset << PAGE_SHIFT); |
| 1435 | gen8_set_pte(>t_entries[i], |
| 1436 | gen8_pte_encode(addr, level, true)); |
| 1437 | i++; |
| 1438 | } |
| 1439 | |
| 1440 | /* |
| 1441 | * XXX: This serves as a posting read to make sure that the PTE has |
| 1442 | * actually been updated. There is some concern that even though |
| 1443 | * registers and PTEs are within the same BAR that they are potentially |
| 1444 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1445 | * hardware should work, we must keep this posting read for paranoia. |
| 1446 | */ |
| 1447 | if (i != 0) |
| 1448 | WARN_ON(readq(>t_entries[i-1]) |
| 1449 | != gen8_pte_encode(addr, level, true)); |
| 1450 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1451 | /* This next bit makes the above posting read even more important. We |
| 1452 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1453 | * have finished. |
| 1454 | */ |
| 1455 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1456 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1457 | } |
| 1458 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1459 | /* |
| 1460 | * Binds an object into the global gtt with the specified cache level. The object |
| 1461 | * will be accessible to the GPU via commands whose operands reference offsets |
| 1462 | * within the global GTT as well as accessible by the GPU through the GMADR |
| 1463 | * mapped BAR (dev_priv->mm.gtt->gtt). |
| 1464 | */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1465 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1466 | struct sg_table *st, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1467 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1468 | enum i915_cache_level level, u32 flags) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1469 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1470 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1471 | unsigned first_entry = start >> PAGE_SHIFT; |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 1472 | gen6_gtt_pte_t __iomem *gtt_entries = |
| 1473 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1474 | int i = 0; |
| 1475 | struct sg_page_iter sg_iter; |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1476 | dma_addr_t addr = 0; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1477 | |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1478 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1479 | addr = sg_page_iter_dma_address(&sg_iter); |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1480 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1481 | i++; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1482 | } |
| 1483 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1484 | /* XXX: This serves as a posting read to make sure that the PTE has |
| 1485 | * actually been updated. There is some concern that even though |
| 1486 | * registers and PTEs are within the same BAR that they are potentially |
| 1487 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1488 | * hardware should work, we must keep this posting read for paranoia. |
| 1489 | */ |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1490 | if (i != 0) { |
| 1491 | unsigned long gtt = readl(>t_entries[i-1]); |
| 1492 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); |
| 1493 | } |
Ben Widawsky | 0f9b91c | 2012-11-04 09:21:30 -0800 | [diff] [blame] | 1494 | |
| 1495 | /* This next bit makes the above posting read even more important. We |
| 1496 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1497 | * have finished. |
| 1498 | */ |
| 1499 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1500 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1501 | } |
| 1502 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1503 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1504 | uint64_t start, |
| 1505 | uint64_t length, |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1506 | bool use_scratch) |
| 1507 | { |
| 1508 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1509 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1510 | unsigned num_entries = length >> PAGE_SHIFT; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1511 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
| 1512 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
| 1513 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
| 1514 | int i; |
| 1515 | |
| 1516 | if (WARN(num_entries > max_entries, |
| 1517 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1518 | first_entry, num_entries, max_entries)) |
| 1519 | num_entries = max_entries; |
| 1520 | |
| 1521 | scratch_pte = gen8_pte_encode(vm->scratch.addr, |
| 1522 | I915_CACHE_LLC, |
| 1523 | use_scratch); |
| 1524 | for (i = 0; i < num_entries; i++) |
| 1525 | gen8_set_pte(>t_base[i], scratch_pte); |
| 1526 | readl(gtt_base); |
| 1527 | } |
| 1528 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1529 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1530 | uint64_t start, |
| 1531 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1532 | bool use_scratch) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1533 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1534 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1535 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1536 | unsigned num_entries = length >> PAGE_SHIFT; |
Ben Widawsky | e7c2b58 | 2013-04-08 18:43:48 -0700 | [diff] [blame] | 1537 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
| 1538 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 1539 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1540 | int i; |
| 1541 | |
| 1542 | if (WARN(num_entries > max_entries, |
| 1543 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1544 | first_entry, num_entries, max_entries)) |
| 1545 | num_entries = max_entries; |
| 1546 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1547 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1548 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1549 | for (i = 0; i < num_entries; i++) |
| 1550 | iowrite32(scratch_pte, >t_base[i]); |
| 1551 | readl(gtt_base); |
| 1552 | } |
| 1553 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1554 | |
| 1555 | static void i915_ggtt_bind_vma(struct i915_vma *vma, |
| 1556 | enum i915_cache_level cache_level, |
| 1557 | u32 unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1558 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1559 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1560 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
| 1561 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; |
| 1562 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1563 | BUG_ON(!i915_is_ggtt(vma->vm)); |
| 1564 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); |
| 1565 | vma->obj->has_global_gtt_mapping = 1; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1566 | } |
| 1567 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1568 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1569 | uint64_t start, |
| 1570 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1571 | bool unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1572 | { |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1573 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1574 | unsigned num_entries = length >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1575 | intel_gtt_clear_range(first_entry, num_entries); |
| 1576 | } |
| 1577 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1578 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 1579 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1580 | const unsigned int first = vma->node.start >> PAGE_SHIFT; |
| 1581 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1582 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1583 | BUG_ON(!i915_is_ggtt(vma->vm)); |
| 1584 | vma->obj->has_global_gtt_mapping = 0; |
| 1585 | intel_gtt_clear_range(first, size); |
Chris Wilson | d5bd144 | 2011-04-14 06:48:26 +0100 | [diff] [blame] | 1586 | } |
| 1587 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1588 | static void ggtt_bind_vma(struct i915_vma *vma, |
| 1589 | enum i915_cache_level cache_level, |
| 1590 | u32 flags) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1591 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1592 | struct drm_device *dev = vma->vm->dev; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1593 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1594 | struct drm_i915_gem_object *obj = vma->obj; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1595 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1596 | /* Currently applicable only to VLV */ |
| 1597 | if (obj->gt_ro) |
| 1598 | flags |= PTE_READ_ONLY; |
| 1599 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1600 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
| 1601 | * or we have a global mapping already but the cacheability flags have |
| 1602 | * changed, set the global PTEs. |
| 1603 | * |
| 1604 | * If there is an aliasing PPGTT it is anecdotally faster, so use that |
| 1605 | * instead if none of the above hold true. |
| 1606 | * |
| 1607 | * NB: A global mapping should only be needed for special regions like |
| 1608 | * "gtt mappable", SNB errata, or if specified via special execbuf |
| 1609 | * flags. At all other times, the GPU will use the aliasing PPGTT. |
| 1610 | */ |
| 1611 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
| 1612 | if (!obj->has_global_gtt_mapping || |
| 1613 | (cache_level != obj->cache_level)) { |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1614 | vma->vm->insert_entries(vma->vm, obj->pages, |
| 1615 | vma->node.start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1616 | cache_level, flags); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1617 | obj->has_global_gtt_mapping = 1; |
| 1618 | } |
| 1619 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1620 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1621 | if (dev_priv->mm.aliasing_ppgtt && |
| 1622 | (!obj->has_aliasing_ppgtt_mapping || |
| 1623 | (cache_level != obj->cache_level))) { |
| 1624 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
| 1625 | appgtt->base.insert_entries(&appgtt->base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1626 | vma->obj->pages, |
| 1627 | vma->node.start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1628 | cache_level, flags); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1629 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
| 1630 | } |
| 1631 | } |
| 1632 | |
| 1633 | static void ggtt_unbind_vma(struct i915_vma *vma) |
| 1634 | { |
| 1635 | struct drm_device *dev = vma->vm->dev; |
| 1636 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1637 | struct drm_i915_gem_object *obj = vma->obj; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1638 | |
| 1639 | if (obj->has_global_gtt_mapping) { |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1640 | vma->vm->clear_range(vma->vm, |
| 1641 | vma->node.start, |
| 1642 | obj->base.size, |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1643 | true); |
| 1644 | obj->has_global_gtt_mapping = 0; |
| 1645 | } |
| 1646 | |
| 1647 | if (obj->has_aliasing_ppgtt_mapping) { |
| 1648 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
| 1649 | appgtt->base.clear_range(&appgtt->base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1650 | vma->node.start, |
| 1651 | obj->base.size, |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1652 | true); |
| 1653 | obj->has_aliasing_ppgtt_mapping = 0; |
| 1654 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1655 | } |
| 1656 | |
| 1657 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) |
| 1658 | { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1659 | struct drm_device *dev = obj->base.dev; |
| 1660 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1661 | bool interruptible; |
| 1662 | |
| 1663 | interruptible = do_idling(dev_priv); |
| 1664 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1665 | if (!obj->has_dma_mapping) |
| 1666 | dma_unmap_sg(&dev->pdev->dev, |
| 1667 | obj->pages->sgl, obj->pages->nents, |
| 1668 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1669 | |
| 1670 | undo_idling(dev_priv, interruptible); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1671 | } |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1672 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 1673 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
| 1674 | unsigned long color, |
| 1675 | unsigned long *start, |
| 1676 | unsigned long *end) |
| 1677 | { |
| 1678 | if (node->color != color) |
| 1679 | *start += 4096; |
| 1680 | |
| 1681 | if (!list_empty(&node->node_list)) { |
| 1682 | node = list_entry(node->node_list.next, |
| 1683 | struct drm_mm_node, |
| 1684 | node_list); |
| 1685 | if (node->allocated && node->color != color) |
| 1686 | *end -= 4096; |
| 1687 | } |
| 1688 | } |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1689 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 1690 | int i915_gem_setup_global_gtt(struct drm_device *dev, |
| 1691 | unsigned long start, |
| 1692 | unsigned long mappable_end, |
| 1693 | unsigned long end) |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1694 | { |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 1695 | /* Let GEM Manage all of the aperture. |
| 1696 | * |
| 1697 | * However, leave one page at the end still bound to the scratch page. |
| 1698 | * There are a number of places where the hardware apparently prefetches |
| 1699 | * past the end of the object, and we've seen multiple hangs with the |
| 1700 | * GPU head pointer stuck in a batchbuffer bound at the last page of the |
| 1701 | * aperture. One page should be enough to keep any prefetching inside |
| 1702 | * of the aperture. |
| 1703 | */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1704 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1705 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1706 | struct drm_mm_node *entry; |
| 1707 | struct drm_i915_gem_object *obj; |
| 1708 | unsigned long hole_start, hole_end; |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1709 | int ret; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1710 | |
Ben Widawsky | 35451cb | 2013-01-17 12:45:13 -0800 | [diff] [blame] | 1711 | BUG_ON(mappable_end > end); |
| 1712 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1713 | /* Subtract the guard page ... */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1714 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 1715 | if (!HAS_LLC(dev)) |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1716 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1717 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1718 | /* Mark any preallocated objects as occupied */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1719 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1720 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1721 | |
Ben Widawsky | edd41a8 | 2013-07-05 14:41:05 -0700 | [diff] [blame] | 1722 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 1723 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1724 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 1725 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1726 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 1727 | if (ret) { |
| 1728 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); |
| 1729 | return ret; |
| 1730 | } |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1731 | obj->has_global_gtt_mapping = 1; |
| 1732 | } |
| 1733 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1734 | dev_priv->gtt.base.start = start; |
| 1735 | dev_priv->gtt.base.total = end - start; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 1736 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1737 | /* Clear any non-preallocated blocks */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 1738 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1739 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
| 1740 | hole_start, hole_end); |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1741 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
| 1742 | hole_end - hole_start, true); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1743 | } |
| 1744 | |
| 1745 | /* And finally clear the reserved guard page */ |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1746 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 1747 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1748 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
| 1749 | struct i915_hw_ppgtt *ppgtt; |
| 1750 | |
| 1751 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 1752 | if (!ppgtt) |
| 1753 | return -ENOMEM; |
| 1754 | |
| 1755 | ret = __hw_ppgtt_init(dev, ppgtt); |
| 1756 | if (ret != 0) |
| 1757 | return ret; |
| 1758 | |
| 1759 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
| 1760 | } |
| 1761 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 1762 | return 0; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1763 | } |
| 1764 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1765 | void i915_gem_init_global_gtt(struct drm_device *dev) |
| 1766 | { |
| 1767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1768 | unsigned long gtt_size, mappable_size; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1769 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1770 | gtt_size = dev_priv->gtt.base.total; |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 1771 | mappable_size = dev_priv->gtt.mappable_end; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 1772 | |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 1773 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1774 | } |
| 1775 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 1776 | void i915_global_gtt_cleanup(struct drm_device *dev) |
| 1777 | { |
| 1778 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1779 | struct i915_address_space *vm = &dev_priv->gtt.base; |
| 1780 | |
Daniel Vetter | 70e3254 | 2014-08-06 15:04:57 +0200 | [diff] [blame] | 1781 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1782 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1783 | |
| 1784 | ppgtt->base.cleanup(&ppgtt->base); |
| 1785 | } |
| 1786 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 1787 | if (drm_mm_initialized(&vm->mm)) { |
| 1788 | drm_mm_takedown(&vm->mm); |
| 1789 | list_del(&vm->global_link); |
| 1790 | } |
| 1791 | |
| 1792 | vm->cleanup(vm); |
| 1793 | } |
Daniel Vetter | 70e3254 | 2014-08-06 15:04:57 +0200 | [diff] [blame] | 1794 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1795 | static int setup_scratch_page(struct drm_device *dev) |
| 1796 | { |
| 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1798 | struct page *page; |
| 1799 | dma_addr_t dma_addr; |
| 1800 | |
| 1801 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| 1802 | if (page == NULL) |
| 1803 | return -ENOMEM; |
| 1804 | get_page(page); |
| 1805 | set_pages_uc(page, 1); |
| 1806 | |
| 1807 | #ifdef CONFIG_INTEL_IOMMU |
| 1808 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, |
| 1809 | PCI_DMA_BIDIRECTIONAL); |
| 1810 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) |
| 1811 | return -EINVAL; |
| 1812 | #else |
| 1813 | dma_addr = page_to_phys(page); |
| 1814 | #endif |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1815 | dev_priv->gtt.base.scratch.page = page; |
| 1816 | dev_priv->gtt.base.scratch.addr = dma_addr; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1817 | |
| 1818 | return 0; |
| 1819 | } |
| 1820 | |
| 1821 | static void teardown_scratch_page(struct drm_device *dev) |
| 1822 | { |
| 1823 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1824 | struct page *page = dev_priv->gtt.base.scratch.page; |
| 1825 | |
| 1826 | set_pages_wb(page, 1); |
| 1827 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1828 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1829 | put_page(page); |
| 1830 | __free_page(page); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
| 1834 | { |
| 1835 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; |
| 1836 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; |
| 1837 | return snb_gmch_ctl << 20; |
| 1838 | } |
| 1839 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1840 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
| 1841 | { |
| 1842 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; |
| 1843 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; |
| 1844 | if (bdw_gmch_ctl) |
| 1845 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; |
Ben Widawsky | 562d55d | 2014-05-27 16:53:08 -0700 | [diff] [blame] | 1846 | |
| 1847 | #ifdef CONFIG_X86_32 |
| 1848 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ |
| 1849 | if (bdw_gmch_ctl > 4) |
| 1850 | bdw_gmch_ctl = 4; |
| 1851 | #endif |
| 1852 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1853 | return bdw_gmch_ctl << 20; |
| 1854 | } |
| 1855 | |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 1856 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
| 1857 | { |
| 1858 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; |
| 1859 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; |
| 1860 | |
| 1861 | if (gmch_ctrl) |
| 1862 | return 1 << (20 + gmch_ctrl); |
| 1863 | |
| 1864 | return 0; |
| 1865 | } |
| 1866 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 1867 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1868 | { |
| 1869 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; |
| 1870 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; |
| 1871 | return snb_gmch_ctl << 25; /* 32 MB units */ |
| 1872 | } |
| 1873 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 1874 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
| 1875 | { |
| 1876 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
| 1877 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; |
| 1878 | return bdw_gmch_ctl << 25; /* 32 MB units */ |
| 1879 | } |
| 1880 | |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 1881 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
| 1882 | { |
| 1883 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; |
| 1884 | gmch_ctrl &= SNB_GMCH_GMS_MASK; |
| 1885 | |
| 1886 | /* |
| 1887 | * 0x0 to 0x10: 32MB increments starting at 0MB |
| 1888 | * 0x11 to 0x16: 4MB increments starting at 8MB |
| 1889 | * 0x17 to 0x1d: 4MB increments start at 36MB |
| 1890 | */ |
| 1891 | if (gmch_ctrl < 0x11) |
| 1892 | return gmch_ctrl << 25; |
| 1893 | else if (gmch_ctrl < 0x17) |
| 1894 | return (gmch_ctrl - 0x11 + 2) << 22; |
| 1895 | else |
| 1896 | return (gmch_ctrl - 0x17 + 9) << 22; |
| 1897 | } |
| 1898 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1899 | static int ggtt_probe_common(struct drm_device *dev, |
| 1900 | size_t gtt_size) |
| 1901 | { |
| 1902 | struct drm_i915_private *dev_priv = dev->dev_private; |
Bjorn Helgaas | 21c3460 | 2013-12-21 10:52:52 -0700 | [diff] [blame] | 1903 | phys_addr_t gtt_phys_addr; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1904 | int ret; |
| 1905 | |
| 1906 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
Bjorn Helgaas | 21c3460 | 2013-12-21 10:52:52 -0700 | [diff] [blame] | 1907 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1908 | (pci_resource_len(dev->pdev, 0) / 2); |
| 1909 | |
Bjorn Helgaas | 21c3460 | 2013-12-21 10:52:52 -0700 | [diff] [blame] | 1910 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1911 | if (!dev_priv->gtt.gsm) { |
| 1912 | DRM_ERROR("Failed to map the gtt page table\n"); |
| 1913 | return -ENOMEM; |
| 1914 | } |
| 1915 | |
| 1916 | ret = setup_scratch_page(dev); |
| 1917 | if (ret) { |
| 1918 | DRM_ERROR("Scratch setup failed\n"); |
| 1919 | /* iounmap will also get called at remove, but meh */ |
| 1920 | iounmap(dev_priv->gtt.gsm); |
| 1921 | } |
| 1922 | |
| 1923 | return ret; |
| 1924 | } |
| 1925 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1926 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
| 1927 | * bits. When using advanced contexts each context stores its own PAT, but |
| 1928 | * writing this data shouldn't be harmful even in those cases. */ |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 1929 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1930 | { |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 1931 | uint64_t pat; |
| 1932 | |
| 1933 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ |
| 1934 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ |
| 1935 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ |
| 1936 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ |
| 1937 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | |
| 1938 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | |
| 1939 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | |
| 1940 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); |
| 1941 | |
| 1942 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
| 1943 | * write would work. */ |
| 1944 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
| 1945 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
| 1946 | } |
| 1947 | |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 1948 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
| 1949 | { |
| 1950 | uint64_t pat; |
| 1951 | |
| 1952 | /* |
| 1953 | * Map WB on BDW to snooped on CHV. |
| 1954 | * |
| 1955 | * Only the snoop bit has meaning for CHV, the rest is |
| 1956 | * ignored. |
| 1957 | * |
| 1958 | * Note that the harware enforces snooping for all page |
| 1959 | * table accesses. The snoop bit is actually ignored for |
| 1960 | * PDEs. |
| 1961 | */ |
| 1962 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | |
| 1963 | GEN8_PPAT(1, 0) | |
| 1964 | GEN8_PPAT(2, 0) | |
| 1965 | GEN8_PPAT(3, 0) | |
| 1966 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | |
| 1967 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | |
| 1968 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | |
| 1969 | GEN8_PPAT(7, CHV_PPAT_SNOOP); |
| 1970 | |
| 1971 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
| 1972 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
| 1973 | } |
| 1974 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 1975 | static int gen8_gmch_probe(struct drm_device *dev, |
| 1976 | size_t *gtt_total, |
| 1977 | size_t *stolen, |
| 1978 | phys_addr_t *mappable_base, |
| 1979 | unsigned long *mappable_end) |
| 1980 | { |
| 1981 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1982 | unsigned int gtt_size; |
| 1983 | u16 snb_gmch_ctl; |
| 1984 | int ret; |
| 1985 | |
| 1986 | /* TODO: We're not aware of mappable constraints on gen8 yet */ |
| 1987 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 1988 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 1989 | |
| 1990 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) |
| 1991 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); |
| 1992 | |
| 1993 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 1994 | |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 1995 | if (IS_CHERRYVIEW(dev)) { |
| 1996 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
| 1997 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); |
| 1998 | } else { |
| 1999 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); |
| 2000 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
| 2001 | } |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2002 | |
Ben Widawsky | d31eb10 | 2013-11-02 21:07:17 -0700 | [diff] [blame] | 2003 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2004 | |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 2005 | if (IS_CHERRYVIEW(dev)) |
| 2006 | chv_setup_private_ppat(dev_priv); |
| 2007 | else |
| 2008 | bdw_setup_private_ppat(dev_priv); |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2009 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2010 | ret = ggtt_probe_common(dev, gtt_size); |
| 2011 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 2012 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
| 2013 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2014 | |
| 2015 | return ret; |
| 2016 | } |
| 2017 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2018 | static int gen6_gmch_probe(struct drm_device *dev, |
| 2019 | size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2020 | size_t *stolen, |
| 2021 | phys_addr_t *mappable_base, |
| 2022 | unsigned long *mappable_end) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2023 | { |
| 2024 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2025 | unsigned int gtt_size; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2026 | u16 snb_gmch_ctl; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2027 | int ret; |
| 2028 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2029 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 2030 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 2031 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2032 | /* 64/512MB is the current min/max we actually know of, but this is just |
| 2033 | * a coarse sanity check. |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2034 | */ |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2035 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2036 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
| 2037 | dev_priv->gtt.mappable_end); |
| 2038 | return -ENXIO; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2039 | } |
| 2040 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2041 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
| 2042 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2043 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2044 | |
Ben Widawsky | c4ae25e | 2013-05-01 11:00:34 -0700 | [diff] [blame] | 2045 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2046 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2047 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2048 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
| 2049 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2050 | ret = ggtt_probe_common(dev, gtt_size); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2051 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2052 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
| 2053 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2054 | |
| 2055 | return ret; |
| 2056 | } |
| 2057 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2058 | static void gen6_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2059 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2060 | |
| 2061 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); |
Ben Widawsky | 5ed1678 | 2013-11-25 09:54:43 -0800 | [diff] [blame] | 2062 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2063 | iounmap(gtt->gsm); |
| 2064 | teardown_scratch_page(vm->dev); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2065 | } |
| 2066 | |
| 2067 | static int i915_gmch_probe(struct drm_device *dev, |
| 2068 | size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2069 | size_t *stolen, |
| 2070 | phys_addr_t *mappable_base, |
| 2071 | unsigned long *mappable_end) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2072 | { |
| 2073 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2074 | int ret; |
| 2075 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2076 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
| 2077 | if (!ret) { |
| 2078 | DRM_ERROR("failed to set up gmch\n"); |
| 2079 | return -EIO; |
| 2080 | } |
| 2081 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2082 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2083 | |
| 2084 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2085 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2086 | |
Chris Wilson | c0a7f81 | 2013-12-30 12:16:15 +0000 | [diff] [blame] | 2087 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
| 2088 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
| 2089 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2090 | return 0; |
| 2091 | } |
| 2092 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2093 | static void i915_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2094 | { |
| 2095 | intel_gmch_remove(); |
| 2096 | } |
| 2097 | |
| 2098 | int i915_gem_gtt_init(struct drm_device *dev) |
| 2099 | { |
| 2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2101 | struct i915_gtt *gtt = &dev_priv->gtt; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2102 | int ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2103 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2104 | if (INTEL_INFO(dev)->gen <= 5) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2105 | gtt->gtt_probe = i915_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2106 | gtt->base.cleanup = i915_gmch_remove; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2107 | } else if (INTEL_INFO(dev)->gen < 8) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2108 | gtt->gtt_probe = gen6_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2109 | gtt->base.cleanup = gen6_gmch_remove; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 2110 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2111 | gtt->base.pte_encode = iris_pte_encode; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 2112 | else if (IS_HASWELL(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2113 | gtt->base.pte_encode = hsw_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2114 | else if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2115 | gtt->base.pte_encode = byt_pte_encode; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 2116 | else if (INTEL_INFO(dev)->gen >= 7) |
| 2117 | gtt->base.pte_encode = ivb_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2118 | else |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 2119 | gtt->base.pte_encode = snb_pte_encode; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2120 | } else { |
| 2121 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; |
| 2122 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2123 | } |
| 2124 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2125 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2126 | >t->mappable_base, >t->mappable_end); |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 2127 | if (ret) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2128 | return ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2129 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2130 | gtt->base.dev = dev; |
| 2131 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2132 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2133 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
| 2134 | gtt->base.total >> 20); |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2135 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
| 2136 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
Daniel Vetter | 5db6c73 | 2014-03-31 16:23:04 +0200 | [diff] [blame] | 2137 | #ifdef CONFIG_INTEL_IOMMU |
| 2138 | if (intel_iommu_gfx_mapped) |
| 2139 | DRM_INFO("VT-d active for gfx access\n"); |
| 2140 | #endif |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 2141 | /* |
| 2142 | * i915.enable_ppgtt is read-only, so do an early pass to validate the |
| 2143 | * user's requested state against the hardware/driver capabilities. We |
| 2144 | * do this now so that we can print out any log messages once rather |
| 2145 | * than every time we check intel_enable_ppgtt(). |
| 2146 | */ |
| 2147 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); |
| 2148 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 2149 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2150 | return 0; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2151 | } |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2152 | |
| 2153 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, |
| 2154 | struct i915_address_space *vm) |
| 2155 | { |
| 2156 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
| 2157 | if (vma == NULL) |
| 2158 | return ERR_PTR(-ENOMEM); |
| 2159 | |
| 2160 | INIT_LIST_HEAD(&vma->vma_link); |
| 2161 | INIT_LIST_HEAD(&vma->mm_list); |
| 2162 | INIT_LIST_HEAD(&vma->exec_list); |
| 2163 | vma->vm = vm; |
| 2164 | vma->obj = obj; |
| 2165 | |
| 2166 | switch (INTEL_INFO(vm->dev)->gen) { |
| 2167 | case 8: |
| 2168 | case 7: |
| 2169 | case 6: |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 2170 | if (i915_is_ggtt(vm)) { |
| 2171 | vma->unbind_vma = ggtt_unbind_vma; |
| 2172 | vma->bind_vma = ggtt_bind_vma; |
| 2173 | } else { |
| 2174 | vma->unbind_vma = ppgtt_unbind_vma; |
| 2175 | vma->bind_vma = ppgtt_bind_vma; |
| 2176 | } |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2177 | break; |
| 2178 | case 5: |
| 2179 | case 4: |
| 2180 | case 3: |
| 2181 | case 2: |
| 2182 | BUG_ON(!i915_is_ggtt(vm)); |
| 2183 | vma->unbind_vma = i915_ggtt_unbind_vma; |
| 2184 | vma->bind_vma = i915_ggtt_bind_vma; |
| 2185 | break; |
| 2186 | default: |
| 2187 | BUG(); |
| 2188 | } |
| 2189 | |
| 2190 | /* Keep GGTT vmas first to make debug easier */ |
| 2191 | if (i915_is_ggtt(vm)) |
| 2192 | list_add(&vma->vma_link, &obj->vma_list); |
| 2193 | else |
| 2194 | list_add_tail(&vma->vma_link, &obj->vma_list); |
| 2195 | |
| 2196 | return vma; |
| 2197 | } |
| 2198 | |
| 2199 | struct i915_vma * |
| 2200 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 2201 | struct i915_address_space *vm) |
| 2202 | { |
| 2203 | struct i915_vma *vma; |
| 2204 | |
| 2205 | vma = i915_gem_obj_to_vma(obj, vm); |
| 2206 | if (!vma) |
| 2207 | vma = __i915_gem_vma_create(obj, vm); |
| 2208 | |
Daniel Vetter | 841cd77 | 2014-08-06 15:04:48 +0200 | [diff] [blame] | 2209 | if (!i915_is_ggtt(vm)) |
| 2210 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 2211 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2212 | return vma; |
| 2213 | } |