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gerrit-public.fairphone.software / kernel / msm-4.9 / 92b96797118e5836294a6d42a5a8e10b86f50e3f / . / drivers / staging / vt6656 / mac.h
blob: 78ba7fcd9d349f6008d19887cff08ade7d16d39a [file] [log] [blame]
Forest Bond92b96792009-06-13 07:38:31 -0400[diff] [blame^]1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: mac.h
21 *
22 * Purpose: MAC routines
23 *
24 * Author: Tevin Chen
25 *
26 * Date: May 21, 1996
27 *
28 * Revision History:
29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
32 */
33
34#ifndef __MAC_H__
35#define __MAC_H__
36
37#if !defined(__TTYPE_H__)
38#include "ttype.h"
39#endif
40#if !defined(__DEVICE_H__)
41#include "device.h"
42#endif
43#if !defined(__TMACRO_H__)
44#include "tmacro.h"
45#endif
46#if !defined(__UMEM_H__)
47#include "umem.h"
48#endif
49
50/*--------------------- Export Definitions -------------------------*/
51
52#define REV_ID_VT3253_A0 0x00
53#define REV_ID_VT3253_A1 0x01
54#define REV_ID_VT3253_B0 0x08
55#define REV_ID_VT3253_B1 0x09
56
57//
58// Registers in the MAC
59//
60#define MAC_REG_BISTCMD 0x04
61#define MAC_REG_BISTSR0 0x05
62#define MAC_REG_BISTSR1 0x06
63#define MAC_REG_BISTSR2 0x07
64#define MAC_REG_I2MCSR 0x08
65#define MAC_REG_I2MTGID 0x09
66#define MAC_REG_I2MTGAD 0x0A
67#define MAC_REG_I2MCFG 0x0B
68#define MAC_REG_I2MDIPT 0x0C
69#define MAC_REG_I2MDOPT 0x0E
70#define MAC_REG_USBSUS 0x0F
71
72#define MAC_REG_LOCALID 0x14
73#define MAC_REG_TESTCFG 0x15
74#define MAC_REG_JUMPER0 0x16
75#define MAC_REG_JUMPER1 0x17
76#define MAC_REG_TMCTL 0x18
77#define MAC_REG_TMDATA0 0x1C
78#define MAC_REG_TMDATA1 0x1D
79#define MAC_REG_TMDATA2 0x1E
80#define MAC_REG_TMDATA3 0x1F
81
82// MAC Parameter related
83#define MAC_REG_LRT 0x20 //
84#define MAC_REG_SRT 0x21 //
85#define MAC_REG_SIFS 0x22 //
86#define MAC_REG_DIFS 0x23 //
87#define MAC_REG_EIFS 0x24 //
88#define MAC_REG_SLOT 0x25 //
89#define MAC_REG_BI 0x26 //
90#define MAC_REG_CWMAXMIN0 0x28 //
91#define MAC_REG_LINKOFFTOTM 0x2A
92#define MAC_REG_SWTMOT 0x2B
93#define MAC_REG_RTSOKCNT 0x2C
94#define MAC_REG_RTSFAILCNT 0x2D
95#define MAC_REG_ACKFAILCNT 0x2E
96#define MAC_REG_FCSERRCNT 0x2F
97// TSF Related
98#define MAC_REG_TSFCNTR 0x30 //
99#define MAC_REG_NEXTTBTT 0x38 //
100#define MAC_REG_TSFOFST 0x40 //
101#define MAC_REG_TFTCTL 0x48 //
102// WMAC Control/Status Related
103#define MAC_REG_ENCFG0 0x4C //
104#define MAC_REG_ENCFG1 0x4D //
105#define MAC_REG_ENCFG2 0x4E //
106
107#define MAC_REG_CFG 0x50 //
108#define MAC_REG_TEST 0x52 //
109#define MAC_REG_HOSTCR 0x54 //
110#define MAC_REG_MACCR 0x55 //
111#define MAC_REG_RCR 0x56 //
112#define MAC_REG_TCR 0x57 //
113#define MAC_REG_IMR 0x58 //
114#define MAC_REG_ISR 0x5C
115#define MAC_REG_ISR1 0x5D
116// Power Saving Related
117#define MAC_REG_PSCFG 0x60 //
118#define MAC_REG_PSCTL 0x61 //
119#define MAC_REG_PSPWRSIG 0x62 //
120#define MAC_REG_BBCR13 0x63
121#define MAC_REG_AIDATIM 0x64
122#define MAC_REG_PWBT 0x66
123#define MAC_REG_WAKEOKTMR 0x68
124#define MAC_REG_CALTMR 0x69
125#define MAC_REG_SYNSPACCNT 0x6A
126#define MAC_REG_WAKSYNOPT 0x6B
127// Baseband/IF Control Group
128#define MAC_REG_BBREGCTL 0x6C //
129#define MAC_REG_CHANNEL 0x6D
130#define MAC_REG_BBREGADR 0x6E
131#define MAC_REG_BBREGDATA 0x6F
132#define MAC_REG_IFREGCTL 0x70 //
133#define MAC_REG_IFDATA 0x71 //
134#define MAC_REG_ITRTMSET 0x74 //
135#define MAC_REG_PAPEDELAY 0x77
136#define MAC_REG_SOFTPWRCTL 0x78 //
137#define MAC_REG_SOFTPWRCTL2 0x79 //
138#define MAC_REG_GPIOCTL0 0x7A //
139#define MAC_REG_GPIOCTL1 0x7B //
140
141// MiscFF PIO related
142#define MAC_REG_MISCFFNDEX 0xBC
143#define MAC_REG_MISCFFCTL 0xBE
144#define MAC_REG_MISCFFDATA 0xC0
145
146// MAC Configuration Group
147#define MAC_REG_PAR0 0xC4
148#define MAC_REG_PAR4 0xC8
149#define MAC_REG_BSSID0 0xCC
150#define MAC_REG_BSSID4 0xD0
151#define MAC_REG_MAR0 0xD4
152#define MAC_REG_MAR4 0xD8
153// MAC RSPPKT INFO Group
154#define MAC_REG_RSPINF_B_1 0xDC
155#define MAC_REG_RSPINF_B_2 0xE0
156#define MAC_REG_RSPINF_B_5 0xE4
157#define MAC_REG_RSPINF_B_11 0xE8
158#define MAC_REG_RSPINF_A_6 0xEC
159#define MAC_REG_RSPINF_A_9 0xEE
160#define MAC_REG_RSPINF_A_12 0xF0
161#define MAC_REG_RSPINF_A_18 0xF2
162#define MAC_REG_RSPINF_A_24 0xF4
163#define MAC_REG_RSPINF_A_36 0xF6
164#define MAC_REG_RSPINF_A_48 0xF8
165#define MAC_REG_RSPINF_A_54 0xFA
166#define MAC_REG_RSPINF_A_72 0xFC
167
168
169//
170// Bits in the I2MCFG EEPROM register
171//
172#define I2MCFG_BOUNDCTL 0x80
173#define I2MCFG_WAITCTL 0x20
174#define I2MCFG_SCLOECTL 0x10
175#define I2MCFG_WBUSYCTL 0x08
176#define I2MCFG_NORETRY 0x04
177#define I2MCFG_I2MLDSEQ 0x02
178#define I2MCFG_I2CMFAST 0x01
179
180//
181// Bits in the I2MCSR EEPROM register
182//
183#define I2MCSR_EEMW 0x80
184#define I2MCSR_EEMR 0x40
185#define I2MCSR_AUTOLD 0x08
186#define I2MCSR_NACK 0x02
187#define I2MCSR_DONE 0x01
188
189//
190// Bits in the TMCTL register
191//
192#define TMCTL_TSUSP 0x04
193#define TMCTL_TMD 0x02
194#define TMCTL_TE 0x01
195
196//
197// Bits in the TFTCTL register
198//
199#define TFTCTL_HWUTSF 0x80 //
200#define TFTCTL_TBTTSYNC 0x40
201#define TFTCTL_HWUTSFEN 0x20
202#define TFTCTL_TSFCNTRRD 0x10 //
203#define TFTCTL_TBTTSYNCEN 0x08 //
204#define TFTCTL_TSFSYNCEN 0x04 //
205#define TFTCTL_TSFCNTRST 0x02 //
206#define TFTCTL_TSFCNTREN 0x01 //
207
208//
209// Bits in the EnhanceCFG_0 register
210//
211#define EnCFG_BBType_a 0x00
212#define EnCFG_BBType_b 0x01
213#define EnCFG_BBType_g 0x02
214#define EnCFG_BBType_MASK 0x03
215#define EnCFG_ProtectMd 0x20
216
217//
218// Bits in the EnhanceCFG_1 register
219//
220#define EnCFG_BcnSusInd 0x01
221#define EnCFG_BcnSusClr 0x02
222
223//
224// Bits in the EnhanceCFG_2 register
225//
226#define EnCFG_NXTBTTCFPSTR 0x01
227#define EnCFG_BarkerPream 0x02
228#define EnCFG_PktBurstMode 0x04
229
230//
231// Bits in the CFG register
232//
233#define CFG_TKIPOPT 0x80
234#define CFG_RXDMAOPT 0x40
235#define CFG_TMOT_SW 0x20
236#define CFG_TMOT_HWLONG 0x10
237#define CFG_TMOT_HW 0x00
238#define CFG_CFPENDOPT 0x08
239#define CFG_BCNSUSEN 0x04
240#define CFG_NOTXTIMEOUT 0x02
241#define CFG_NOBUFOPT 0x01
242
243//
244// Bits in the TEST register
245//
246#define TEST_LBEXT 0x80 //
247#define TEST_LBINT 0x40 //
248#define TEST_LBNONE 0x00 //
249#define TEST_SOFTINT 0x20 //
250#define TEST_CONTTX 0x10 //
251#define TEST_TXPE 0x08 //
252#define TEST_NAVDIS 0x04 //
253#define TEST_NOCTS 0x02 //
254#define TEST_NOACK 0x01 //
255
256//
257// Bits in the HOSTCR register
258//
259#define HOSTCR_TXONST 0x80 //
260#define HOSTCR_RXONST 0x40 //
261#define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
262#define HOSTCR_AP 0x10 // Port Type 1 = AP
263#define HOSTCR_TXON 0x08 //0000 1000
264#define HOSTCR_RXON 0x04 //0000 0100
265#define HOSTCR_MACEN 0x02 //0000 0010
266#define HOSTCR_SOFTRST 0x01 //0000 0001
267
268//
269// Bits in the MACCR register
270//
271#define MACCR_SYNCFLUSHOK 0x04 //
272#define MACCR_SYNCFLUSH 0x02 //
273#define MACCR_CLRNAV 0x01 //
274
275//
276// Bits in the RCR register
277//
278#define RCR_SSID 0x80
279#define RCR_RXALLTYPE 0x40 //
280#define RCR_UNICAST 0x20 //
281#define RCR_BROADCAST 0x10 //
282#define RCR_MULTICAST 0x08 //
283#define RCR_WPAERR 0x04 //
284#define RCR_ERRCRC 0x02 //
285#define RCR_BSSID 0x01 //
286
287//
288// Bits in the TCR register
289//
290#define TCR_SYNCDCFOPT 0x02 //
291#define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
292
293
294//ISR1
295#define ISR_GPIO3 0x40
296#define ISR_RXNOBUF 0x08
297#define ISR_MIBNEARFULL 0x04
298#define ISR_SOFTINT 0x02
299#define ISR_FETALERR 0x01
300
301#define LEDSTS_STS 0x06
302#define LEDSTS_TMLEN 0x78
303#define LEDSTS_OFF 0x00
304#define LEDSTS_ON 0x02
305#define LEDSTS_SLOW 0x04
306#define LEDSTS_INTER 0x06
307
308//ISR0
309#define ISR_WATCHDOG 0x80
310#define ISR_SOFTTIMER 0x40
311#define ISR_GPIO0 0x20
312#define ISR_TBTT 0x10
313#define ISR_RXDMA0 0x08
314#define ISR_BNTX 0x04
315#define ISR_ACTX 0x01
316
317//
318// Bits in the PSCFG register
319//
320#define PSCFG_PHILIPMD 0x40 //
321#define PSCFG_WAKECALEN 0x20 //
322#define PSCFG_WAKETMREN 0x10 //
323#define PSCFG_BBPSPROG 0x08 //
324#define PSCFG_WAKESYN 0x04 //
325#define PSCFG_SLEEPSYN 0x02 //
326#define PSCFG_AUTOSLEEP 0x01 //
327
328//
329// Bits in the PSCTL register
330//
331#define PSCTL_WAKEDONE 0x20 //
332#define PSCTL_PS 0x10 //
333#define PSCTL_GO2DOZE 0x08 //
334#define PSCTL_LNBCN 0x04 //
335#define PSCTL_ALBCN 0x02 //
336#define PSCTL_PSEN 0x01 //
337
338//
339// Bits in the PSPWSIG register
340//
341#define PSSIG_WPE3 0x80 //
342#define PSSIG_WPE2 0x40 //
343#define PSSIG_WPE1 0x20 //
344#define PSSIG_WRADIOPE 0x10 //
345#define PSSIG_SPE3 0x08 //
346#define PSSIG_SPE2 0x04 //
347#define PSSIG_SPE1 0x02 //
348#define PSSIG_SRADIOPE 0x01 //
349
350//
351// Bits in the BBREGCTL register
352//
353#define BBREGCTL_DONE 0x04 //
354#define BBREGCTL_REGR 0x02 //
355#define BBREGCTL_REGW 0x01 //
356
357//
358// Bits in the IFREGCTL register
359//
360#define IFREGCTL_DONE 0x04 //
361#define IFREGCTL_IFRF 0x02 //
362#define IFREGCTL_REGW 0x01 //
363
364//
365// Bits in the SOFTPWRCTL register
366//
367#define SOFTPWRCTL_RFLEOPT 0x08 //
368#define SOFTPWRCTL_TXPEINV 0x02 //
369#define SOFTPWRCTL_SWPECTI 0x01 //
370#define SOFTPWRCTL_SWPAPE 0x20 //
371#define SOFTPWRCTL_SWCALEN 0x10 //
372#define SOFTPWRCTL_SWRADIO_PE 0x08 //
373#define SOFTPWRCTL_SWPE2 0x04 //
374#define SOFTPWRCTL_SWPE1 0x02 //
375#define SOFTPWRCTL_SWPE3 0x01 //
376
377//
378// Bits in the GPIOCTL1 register
379//
380#define GPIO3_MD 0x20 //
381#define GPIO3_DATA 0x40 //
382#define GPIO3_INTMD 0x80 //
383
384//
385// Bits in the MISCFFCTL register
386//
387#define MISCFFCTL_WRITE 0x0001 //
388
389
390// Loopback mode
391#define MAC_LB_EXT 0x02 //
392#define MAC_LB_INTERNAL 0x01 //
393#define MAC_LB_NONE 0x00 //
394
395// Ethernet address filter type
396#define PKT_TYPE_NONE 0x00 // turn off receiver
397#define PKT_TYPE_ALL_MULTICAST 0x80
398#define PKT_TYPE_PROMISCUOUS 0x40
399#define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
400#define PKT_TYPE_BROADCAST 0x10
401#define PKT_TYPE_MULTICAST 0x08
402#define PKT_TYPE_ERROR_WPA 0x04
403#define PKT_TYPE_ERROR_CRC 0x02
404#define PKT_TYPE_BSSID 0x01
405
406#define Default_BI 0x200
407
408// MiscFIFO Offset
409#define MISCFIFO_KEYETRY0 32
410#define MISCFIFO_KEYENTRYSIZE 22
411
412// max time out delay time
413#define W_MAX_TIMEOUT 0xFFF0U //
414
415// wait time within loop
416#define CB_DELAY_LOOP_WAIT 10 // 10ms
417
418#define MAC_REVISION_A0 0x00
419#define MAC_REVISION_A1 0x01
420
421
422/*--------------------- Export Types ------------------------------*/
423
424/*--------------------- Export Macros ------------------------------*/
425
426/*--------------------- Export Classes ----------------------------*/
427
428/*--------------------- Export Variables --------------------------*/
429
430/*--------------------- Export Functions --------------------------*/
431#ifdef __cplusplus
432extern "C" { /* Assume C declarations for C++ */
433#endif /* __cplusplus */
434
435void MACvSetMultiAddrByHash (PSDevice pDevice, BYTE byHashIdx);
436VOID MACvWriteMultiAddr (PSDevice pDevice, UINT uByteIdx, BYTE byData);
437BOOL MACbShutdown(PSDevice pDevice);;
438void MACvSetBBType(PSDevice pDevice,BYTE byType);
439void MACvSetMISCFifo (PSDevice pDevice, WORD wOffset, DWORD dwData);
440void MACvDisableKeyEntry(PSDevice pDevice, UINT uEntryIdx);
441void MACvSetKeyEntry(PSDevice pDevice, WORD wKeyCtl, UINT uEntryIdx, UINT uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey);
442
443void MACvRegBitsOff(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
444void MACvRegBitsOn(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
445void MACvWriteWord(PSDevice pDevice, BYTE byRegOfs, WORD wData);
446
447void MACvWriteBSSIDAddress(PSDevice pDevice, PBYTE pbyEtherAddr);
448void MACvEnableProtectMD(PSDevice pDevice);
449void MACvDisableProtectMD(PSDevice pDevice);
450void MACvEnableBarkerPreambleMd(PSDevice pDevice);
451void MACvDisableBarkerPreambleMd(PSDevice pDevice);
452void MACvWriteBeaconInterval(PSDevice pDevice, WORD wInterval);
453
454#ifdef __cplusplus
455} /* End of extern "C" { */
456#endif /* __cplusplus */
457
458#endif // __MAC_H__