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Erik Gilling3c92db92010-03-15 19:40:06 -07001/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
Thierry Reding641d0342013-01-21 11:09:01 +010020#include <linux/err.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070021#include <linux/init.h>
22#include <linux/irq.h>
Colin Cross2e47b8b2010-04-07 12:59:42 -070023#include <linux/interrupt.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070024#include <linux/io.h>
25#include <linux/gpio.h>
Stephen Warren5c1e2c92012-03-16 17:35:08 -060026#include <linux/of_device.h>
Stephen Warren88d89512011-10-11 16:16:14 -060027#include <linux/platform_device.h>
28#include <linux/module.h>
Stephen Warren6f74dc92012-01-04 08:39:37 +000029#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000030#include <linux/irqchip/chained_irq.h>
Stephen Warren3e215d02012-02-18 01:04:55 -070031#include <linux/pinctrl/consumer.h>
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053032#include <linux/pm.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070033
Erik Gilling3c92db92010-03-15 19:40:06 -070034#define GPIO_BANK(x) ((x) >> 5)
35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
36#define GPIO_BIT(x) ((x) & 0x7)
37
Stephen Warren5c1e2c92012-03-16 17:35:08 -060038#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
39 GPIO_PORT(x) * 4)
Erik Gilling3c92db92010-03-15 19:40:06 -070040
41#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
42#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
43#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
44#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
45#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
46#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
47#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
48#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
49
Stephen Warren5c1e2c92012-03-16 17:35:08 -060050#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
51#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
52#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
53#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
54#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
55#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
Erik Gilling3c92db92010-03-15 19:40:06 -070056
57#define GPIO_INT_LVL_MASK 0x010101
58#define GPIO_INT_LVL_EDGE_RISING 0x000101
59#define GPIO_INT_LVL_EDGE_FALLING 0x000100
60#define GPIO_INT_LVL_EDGE_BOTH 0x010100
61#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
62#define GPIO_INT_LVL_LEVEL_LOW 0x000000
63
64struct tegra_gpio_bank {
65 int bank;
66 int irq;
67 spinlock_t lvl_lock[4];
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053068#ifdef CONFIG_PM_SLEEP
Colin Cross2e47b8b2010-04-07 12:59:42 -070069 u32 cnf[4];
70 u32 out[4];
71 u32 oe[4];
72 u32 int_enb[4];
73 u32 int_lvl[4];
Joseph Lo203f31c2013-04-03 19:31:44 +080074 u32 wake_enb[4];
Colin Cross2e47b8b2010-04-07 12:59:42 -070075#endif
Erik Gilling3c92db92010-03-15 19:40:06 -070076};
77
Stephen Warrendf231f22013-10-16 13:25:33 -060078static struct device *dev;
Stephen Warrenbdc93a72012-02-13 16:21:15 -070079static struct irq_domain *irq_domain;
Stephen Warren88d89512011-10-11 16:16:14 -060080static void __iomem *regs;
Stephen Warren33918112012-01-19 08:16:35 +000081static u32 tegra_gpio_bank_count;
Stephen Warren5c1e2c92012-03-16 17:35:08 -060082static u32 tegra_gpio_bank_stride;
83static u32 tegra_gpio_upper_offset;
Stephen Warren33918112012-01-19 08:16:35 +000084static struct tegra_gpio_bank *tegra_gpio_banks;
Stephen Warren88d89512011-10-11 16:16:14 -060085
86static inline void tegra_gpio_writel(u32 val, u32 reg)
87{
88 __raw_writel(val, regs + reg);
89}
90
91static inline u32 tegra_gpio_readl(u32 reg)
92{
93 return __raw_readl(regs + reg);
94}
Erik Gilling3c92db92010-03-15 19:40:06 -070095
96static int tegra_gpio_compose(int bank, int port, int bit)
97{
98 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
99}
100
101static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
102{
103 u32 val;
104
105 val = 0x100 << GPIO_BIT(gpio);
106 if (value)
107 val |= 1 << GPIO_BIT(gpio);
Stephen Warren88d89512011-10-11 16:16:14 -0600108 tegra_gpio_writel(val, reg);
Erik Gilling3c92db92010-03-15 19:40:06 -0700109}
110
Stephen Warren3e215d02012-02-18 01:04:55 -0700111static void tegra_gpio_enable(int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700112{
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
114}
115
Stephen Warren3e215d02012-02-18 01:04:55 -0700116static void tegra_gpio_disable(int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700117{
118 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
119}
120
Axel Lin924a0982012-11-08 10:45:24 +0800121static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700122{
123 return pinctrl_request_gpio(offset);
124}
125
Axel Lin924a0982012-11-08 10:45:24 +0800126static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700127{
128 pinctrl_free_gpio(offset);
129 tegra_gpio_disable(offset);
130}
131
Erik Gilling3c92db92010-03-15 19:40:06 -0700132static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133{
134 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
135}
136
137static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
138{
Laxman Dewangan195812e2012-11-09 11:34:20 +0530139 /* If gpio is in output mode then read from the out value */
140 if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
141 return (tegra_gpio_readl(GPIO_OUT(offset)) >>
142 GPIO_BIT(offset)) & 0x1;
143
Stephen Warren88d89512011-10-11 16:16:14 -0600144 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
Erik Gilling3c92db92010-03-15 19:40:06 -0700145}
146
147static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
148{
149 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
Stephen Warren3e215d02012-02-18 01:04:55 -0700150 tegra_gpio_enable(offset);
Erik Gilling3c92db92010-03-15 19:40:06 -0700151 return 0;
152}
153
154static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
155 int value)
156{
157 tegra_gpio_set(chip, offset, value);
158 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
Stephen Warren3e215d02012-02-18 01:04:55 -0700159 tegra_gpio_enable(offset);
Erik Gilling3c92db92010-03-15 19:40:06 -0700160 return 0;
161}
162
Stephen Warren438a99c2011-08-23 00:39:56 +0100163static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
164{
Stephen Warrenbdc93a72012-02-13 16:21:15 -0700165 return irq_find_mapping(irq_domain, offset);
Stephen Warren438a99c2011-08-23 00:39:56 +0100166}
Erik Gilling3c92db92010-03-15 19:40:06 -0700167
168static struct gpio_chip tegra_gpio_chip = {
169 .label = "tegra-gpio",
Stephen Warren3e215d02012-02-18 01:04:55 -0700170 .request = tegra_gpio_request,
171 .free = tegra_gpio_free,
Erik Gilling3c92db92010-03-15 19:40:06 -0700172 .direction_input = tegra_gpio_direction_input,
173 .get = tegra_gpio_get,
174 .direction_output = tegra_gpio_direction_output,
175 .set = tegra_gpio_set,
Stephen Warren438a99c2011-08-23 00:39:56 +0100176 .to_irq = tegra_gpio_to_irq,
Erik Gilling3c92db92010-03-15 19:40:06 -0700177 .base = 0,
Erik Gilling3c92db92010-03-15 19:40:06 -0700178};
179
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100180static void tegra_gpio_irq_ack(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700181{
Stephen Warren6f74dc92012-01-04 08:39:37 +0000182 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700183
Stephen Warren88d89512011-10-11 16:16:14 -0600184 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700185}
186
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100187static void tegra_gpio_irq_mask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700188{
Stephen Warren6f74dc92012-01-04 08:39:37 +0000189 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700190
191 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
192}
193
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100194static void tegra_gpio_irq_unmask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700195{
Stephen Warren6f74dc92012-01-04 08:39:37 +0000196 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700197
198 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
199}
200
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100201static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Erik Gilling3c92db92010-03-15 19:40:06 -0700202{
Stephen Warren6f74dc92012-01-04 08:39:37 +0000203 int gpio = d->hwirq;
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100204 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Erik Gilling3c92db92010-03-15 19:40:06 -0700205 int port = GPIO_PORT(gpio);
206 int lvl_type;
207 int val;
208 unsigned long flags;
Stephen Warrendf231f22013-10-16 13:25:33 -0600209 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700210
211 switch (type & IRQ_TYPE_SENSE_MASK) {
212 case IRQ_TYPE_EDGE_RISING:
213 lvl_type = GPIO_INT_LVL_EDGE_RISING;
214 break;
215
216 case IRQ_TYPE_EDGE_FALLING:
217 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
218 break;
219
220 case IRQ_TYPE_EDGE_BOTH:
221 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
222 break;
223
224 case IRQ_TYPE_LEVEL_HIGH:
225 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
226 break;
227
228 case IRQ_TYPE_LEVEL_LOW:
229 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
230 break;
231
232 default:
233 return -EINVAL;
234 }
235
Alexandre Courbote3a2e872014-10-23 17:27:07 +0900236 ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600237 if (ret) {
238 dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
239 return ret;
240 }
241
Erik Gilling3c92db92010-03-15 19:40:06 -0700242 spin_lock_irqsave(&bank->lvl_lock[port], flags);
243
Stephen Warren88d89512011-10-11 16:16:14 -0600244 val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700245 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
246 val |= lvl_type << GPIO_BIT(gpio);
Stephen Warren88d89512011-10-11 16:16:14 -0600247 tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700248
249 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
250
Stephen Warrend9411362012-03-19 10:31:58 -0600251 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
252 tegra_gpio_enable(gpio);
253
Erik Gilling3c92db92010-03-15 19:40:06 -0700254 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200255 irq_set_handler_locked(d, handle_level_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700256 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200257 irq_set_handler_locked(d, handle_edge_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700258
259 return 0;
260}
261
Stephen Warrendf231f22013-10-16 13:25:33 -0600262static void tegra_gpio_irq_shutdown(struct irq_data *d)
263{
264 int gpio = d->hwirq;
265
Alexandre Courbote3a2e872014-10-23 17:27:07 +0900266 gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600267}
268
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200269static void tegra_gpio_irq_handler(struct irq_desc *desc)
Erik Gilling3c92db92010-03-15 19:40:06 -0700270{
Erik Gilling3c92db92010-03-15 19:40:06 -0700271 int port;
272 int pin;
273 int unmasked = 0;
Will Deacon98022942011-02-21 13:58:10 +0000274 struct irq_chip *chip = irq_desc_get_chip(desc);
Jiang Liu476f8b42015-06-04 12:13:15 +0800275 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700276
Will Deacon98022942011-02-21 13:58:10 +0000277 chained_irq_enter(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700278
Erik Gilling3c92db92010-03-15 19:40:06 -0700279 for (port = 0; port < 4; port++) {
280 int gpio = tegra_gpio_compose(bank->bank, port, 0);
Stephen Warren88d89512011-10-11 16:16:14 -0600281 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
282 tegra_gpio_readl(GPIO_INT_ENB(gpio));
283 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700284
285 for_each_set_bit(pin, &sta, 8) {
Stephen Warren88d89512011-10-11 16:16:14 -0600286 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700287
288 /* if gpio is edge triggered, clear condition
Colin Cronin20a8a962015-05-18 11:41:43 -0700289 * before executing the handler so that we don't
Erik Gilling3c92db92010-03-15 19:40:06 -0700290 * miss edges
291 */
292 if (lvl & (0x100 << pin)) {
293 unmasked = 1;
Will Deacon98022942011-02-21 13:58:10 +0000294 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700295 }
296
297 generic_handle_irq(gpio_to_irq(gpio + pin));
298 }
299 }
300
301 if (!unmasked)
Will Deacon98022942011-02-21 13:58:10 +0000302 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700303
304}
305
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530306#ifdef CONFIG_PM_SLEEP
307static int tegra_gpio_resume(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700308{
309 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700310 int b;
311 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700312
313 local_irq_save(flags);
314
Stephen Warren33918112012-01-19 08:16:35 +0000315 for (b = 0; b < tegra_gpio_bank_count; b++) {
Colin Cross2e47b8b2010-04-07 12:59:42 -0700316 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
317
318 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
319 unsigned int gpio = (b<<5) | (p<<3);
Stephen Warren88d89512011-10-11 16:16:14 -0600320 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
321 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
322 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
323 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
324 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700325 }
326 }
327
328 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530329 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700330}
331
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530332static int tegra_gpio_suspend(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700333{
334 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700335 int b;
336 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700337
Colin Cross2e47b8b2010-04-07 12:59:42 -0700338 local_irq_save(flags);
Stephen Warren33918112012-01-19 08:16:35 +0000339 for (b = 0; b < tegra_gpio_bank_count; b++) {
Colin Cross2e47b8b2010-04-07 12:59:42 -0700340 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
341
342 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
343 unsigned int gpio = (b<<5) | (p<<3);
Stephen Warren88d89512011-10-11 16:16:14 -0600344 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
345 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
346 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
347 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
348 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Joseph Lo203f31c2013-04-03 19:31:44 +0800349
350 /* Enable gpio irq for wake up source */
351 tegra_gpio_writel(bank->wake_enb[p],
352 GPIO_INT_ENB(gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700353 }
354 }
355 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530356 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700357}
358
Joseph Lo203f31c2013-04-03 19:31:44 +0800359static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700360{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100361 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Joseph Lo203f31c2013-04-03 19:31:44 +0800362 int gpio = d->hwirq;
363 u32 port, bit, mask;
364
365 port = GPIO_PORT(gpio);
366 bit = GPIO_BIT(gpio);
367 mask = BIT(bit);
368
369 if (enable)
370 bank->wake_enb[port] |= mask;
371 else
372 bank->wake_enb[port] &= ~mask;
373
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100374 return irq_set_irq_wake(bank->irq, enable);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700375}
376#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700377
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000378#ifdef CONFIG_DEBUG_FS
379
380#include <linux/debugfs.h>
381#include <linux/seq_file.h>
382
383static int dbg_gpio_show(struct seq_file *s, void *unused)
384{
385 int i;
386 int j;
387
388 for (i = 0; i < tegra_gpio_bank_count; i++) {
389 for (j = 0; j < 4; j++) {
390 int gpio = tegra_gpio_compose(i, j, 0);
391 seq_printf(s,
392 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
393 i, j,
394 tegra_gpio_readl(GPIO_CNF(gpio)),
395 tegra_gpio_readl(GPIO_OE(gpio)),
396 tegra_gpio_readl(GPIO_OUT(gpio)),
397 tegra_gpio_readl(GPIO_IN(gpio)),
398 tegra_gpio_readl(GPIO_INT_STA(gpio)),
399 tegra_gpio_readl(GPIO_INT_ENB(gpio)),
400 tegra_gpio_readl(GPIO_INT_LVL(gpio)));
401 }
402 }
403 return 0;
404}
405
406static int dbg_gpio_open(struct inode *inode, struct file *file)
407{
408 return single_open(file, dbg_gpio_show, &inode->i_private);
409}
410
411static const struct file_operations debug_fops = {
412 .open = dbg_gpio_open,
413 .read = seq_read,
414 .llseek = seq_lseek,
415 .release = single_release,
416};
417
418static void tegra_gpio_debuginit(void)
419{
420 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
421 NULL, NULL, &debug_fops);
422}
423
424#else
425
426static inline void tegra_gpio_debuginit(void)
427{
428}
429
430#endif
431
Erik Gilling3c92db92010-03-15 19:40:06 -0700432static struct irq_chip tegra_gpio_irq_chip = {
433 .name = "GPIO",
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100434 .irq_ack = tegra_gpio_irq_ack,
435 .irq_mask = tegra_gpio_irq_mask,
436 .irq_unmask = tegra_gpio_irq_unmask,
437 .irq_set_type = tegra_gpio_irq_set_type,
Stephen Warrendf231f22013-10-16 13:25:33 -0600438 .irq_shutdown = tegra_gpio_irq_shutdown,
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530439#ifdef CONFIG_PM_SLEEP
Joseph Lo203f31c2013-04-03 19:31:44 +0800440 .irq_set_wake = tegra_gpio_irq_set_wake,
Colin Cross2e47b8b2010-04-07 12:59:42 -0700441#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700442};
443
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530444static const struct dev_pm_ops tegra_gpio_pm_ops = {
445 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
446};
447
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600448struct tegra_gpio_soc_config {
449 u32 bank_stride;
450 u32 upper_offset;
451};
452
453static struct tegra_gpio_soc_config tegra20_gpio_config = {
454 .bank_stride = 0x80,
455 .upper_offset = 0x800,
456};
457
458static struct tegra_gpio_soc_config tegra30_gpio_config = {
459 .bank_stride = 0x100,
460 .upper_offset = 0x80,
461};
462
Jingoo Han30373b62014-05-07 18:07:42 +0900463static const struct of_device_id tegra_gpio_of_match[] = {
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600464 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
465 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
466 { },
467};
Erik Gilling3c92db92010-03-15 19:40:06 -0700468
469/* This lock class tells lockdep that GPIO irqs are in a different
470 * category than their parents, so it won't report false recursion.
471 */
472static struct lock_class_key gpio_lock_class;
473
Bill Pemberton38363092012-11-19 13:22:34 -0500474static int tegra_gpio_probe(struct platform_device *pdev)
Erik Gilling3c92db92010-03-15 19:40:06 -0700475{
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600476 const struct of_device_id *match;
477 struct tegra_gpio_soc_config *config;
Stephen Warren88d89512011-10-11 16:16:14 -0600478 struct resource *res;
Erik Gilling3c92db92010-03-15 19:40:06 -0700479 struct tegra_gpio_bank *bank;
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700480 int ret;
Stephen Warren47008002011-08-23 00:39:55 +0100481 int gpio;
Erik Gilling3c92db92010-03-15 19:40:06 -0700482 int i;
483 int j;
484
Stephen Warrendf231f22013-10-16 13:25:33 -0600485 dev = &pdev->dev;
486
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600487 match = of_match_device(tegra_gpio_of_match, &pdev->dev);
Stephen Warren165b6c22013-02-15 14:54:48 -0700488 if (!match) {
489 dev_err(&pdev->dev, "Error: No device match found\n");
490 return -ENODEV;
491 }
492 config = (struct tegra_gpio_soc_config *)match->data;
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600493
494 tegra_gpio_bank_stride = config->bank_stride;
495 tegra_gpio_upper_offset = config->upper_offset;
496
Stephen Warren33918112012-01-19 08:16:35 +0000497 for (;;) {
498 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
499 if (!res)
500 break;
501 tegra_gpio_bank_count++;
502 }
503 if (!tegra_gpio_bank_count) {
504 dev_err(&pdev->dev, "Missing IRQ resource\n");
505 return -ENODEV;
506 }
507
508 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
509
510 tegra_gpio_banks = devm_kzalloc(&pdev->dev,
511 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
512 GFP_KERNEL);
Jingoo Hanc88a73b2014-04-29 17:44:14 +0900513 if (!tegra_gpio_banks)
Stephen Warren33918112012-01-19 08:16:35 +0000514 return -ENODEV;
Stephen Warren33918112012-01-19 08:16:35 +0000515
Linus Walleijd0235672012-10-16 21:00:09 +0200516 irq_domain = irq_domain_add_linear(pdev->dev.of_node,
517 tegra_gpio_chip.ngpio,
Stephen Warrenbdc93a72012-02-13 16:21:15 -0700518 &irq_domain_simple_ops, NULL);
Linus Walleijd0235672012-10-16 21:00:09 +0200519 if (!irq_domain)
520 return -ENODEV;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000521
Stephen Warren33918112012-01-19 08:16:35 +0000522 for (i = 0; i < tegra_gpio_bank_count; i++) {
Stephen Warren88d89512011-10-11 16:16:14 -0600523 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
524 if (!res) {
525 dev_err(&pdev->dev, "Missing IRQ resource\n");
526 return -ENODEV;
527 }
528
529 bank = &tegra_gpio_banks[i];
530 bank->bank = i;
531 bank->irq = res->start;
532 }
533
534 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding641d0342013-01-21 11:09:01 +0100535 regs = devm_ioremap_resource(&pdev->dev, res);
536 if (IS_ERR(regs))
537 return PTR_ERR(regs);
Stephen Warren88d89512011-10-11 16:16:14 -0600538
Stephen Warren4a3398e2012-03-16 17:37:24 -0600539 for (i = 0; i < tegra_gpio_bank_count; i++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700540 for (j = 0; j < 4; j++) {
541 int gpio = tegra_gpio_compose(i, j, 0);
Stephen Warren88d89512011-10-11 16:16:14 -0600542 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700543 }
544 }
545
Stephen Warren88d89512011-10-11 16:16:14 -0600546 tegra_gpio_chip.of_node = pdev->dev.of_node;
Grant Likelydf221222011-06-15 14:54:14 -0600547
Linus Walleij4eab22e2015-12-08 10:41:44 +0100548 ret = gpiochip_add_data(&tegra_gpio_chip, NULL);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700549 if (ret < 0) {
550 irq_domain_remove(irq_domain);
551 return ret;
552 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700553
Stephen Warren33918112012-01-19 08:16:35 +0000554 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
Linus Walleijd0235672012-10-16 21:00:09 +0200555 int irq = irq_create_mapping(irq_domain, gpio);
Stephen Warren47008002011-08-23 00:39:55 +0100556 /* No validity check; all Tegra GPIOs are valid IRQs */
Erik Gilling3c92db92010-03-15 19:40:06 -0700557
Stephen Warren47008002011-08-23 00:39:55 +0100558 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
559
560 irq_set_lockdep_class(irq, &gpio_lock_class);
561 irq_set_chip_data(irq, bank);
562 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100563 handle_simple_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700564 }
565
Stephen Warren33918112012-01-19 08:16:35 +0000566 for (i = 0; i < tegra_gpio_bank_count; i++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700567 bank = &tegra_gpio_banks[i];
568
Russell Kinge88d2512015-06-16 23:06:50 +0100569 irq_set_chained_handler_and_data(bank->irq,
570 tegra_gpio_irq_handler, bank);
Erik Gilling3c92db92010-03-15 19:40:06 -0700571
572 for (j = 0; j < 4; j++)
573 spin_lock_init(&bank->lvl_lock[j]);
574 }
575
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000576 tegra_gpio_debuginit();
577
Erik Gilling3c92db92010-03-15 19:40:06 -0700578 return 0;
579}
580
Stephen Warren88d89512011-10-11 16:16:14 -0600581static struct platform_driver tegra_gpio_driver = {
582 .driver = {
583 .name = "tegra-gpio",
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530584 .pm = &tegra_gpio_pm_ops,
Stephen Warren88d89512011-10-11 16:16:14 -0600585 .of_match_table = tegra_gpio_of_match,
586 },
587 .probe = tegra_gpio_probe,
588};
589
590static int __init tegra_gpio_init(void)
591{
592 return platform_driver_register(&tegra_gpio_driver);
593}
Erik Gilling3c92db92010-03-15 19:40:06 -0700594postcore_initcall(tegra_gpio_init);