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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
Fabian Godehardtb6e49132009-06-11 14:53:18 +01009 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010039#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
Sascha Hauer38a41fd2008-07-05 10:02:46 +020044#include <linux/clk.h>
Fabian Godehardtb6e49132009-06-11 14:53:18 +010045#include <linux/delay.h>
Oskar Schirmer534fca02009-06-11 14:52:23 +010046#include <linux/rational.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090047#include <linux/slab.h>
Shawn Guo22698aa2011-06-25 02:04:34 +080048#include <linux/of.h>
49#include <linux/of_device.h>
Sachin Kamate32a9f82013-01-07 10:25:03 +053050#include <linux/io.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080051#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020054#include <linux/platform_data/serial-imx.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080055#include <linux/platform_data/dma-imx.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Sascha Hauerff4bfb22007-04-26 08:26:13 +010057/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
Shawn Guofe6b5402011-06-25 02:04:33 +080072#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
Sascha Hauerff4bfb22007-04-26 08:26:13 +010075
76/* UART Control Register Bit Fields.*/
Jiada Wang55d86932014-12-09 18:11:22 +090077#define URXD_DUMMY_READ (1<<16)
Sachin Kamat82313e62013-01-07 10:25:02 +053078#define URXD_CHARRDY (1<<15)
79#define URXD_ERR (1<<14)
80#define URXD_OVRRUN (1<<13)
81#define URXD_FRMERR (1<<12)
82#define URXD_BRK (1<<11)
83#define URXD_PRERR (1<<10)
Dirk Behme26c47412014-09-03 12:33:53 +010084#define URXD_RX_DATA (0xFF<<0)
Sachin Kamat82313e62013-01-07 10:25:02 +053085#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080089#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
Sachin Kamat82313e62013-01-07 10:25:02 +053090#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92#define UCR1_IREN (1<<7) /* Infrared interface enable */
93#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95#define UCR1_SNDBRK (1<<4) /* Send break */
96#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080098#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
Sachin Kamat82313e62013-01-07 10:25:02 +053099#define UCR1_DOZE (1<<1) /* Doze */
100#define UCR1_UARTEN (1<<0) /* UART enabled */
101#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103#define UCR2_CTSC (1<<13) /* CTS pin control */
104#define UCR2_CTS (1<<12) /* Clear to send */
105#define UCR2_ESCEN (1<<11) /* Escape enable */
106#define UCR2_PREN (1<<8) /* Parity enable */
107#define UCR2_PROE (1<<7) /* Parity odd/even */
108#define UCR2_STPB (1<<6) /* Stop */
109#define UCR2_WS (1<<5) /* Word size */
110#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112#define UCR2_TXEN (1<<2) /* Transmitter enabled */
113#define UCR2_RXEN (1<<1) /* Receiver enabled */
114#define UCR2_SRST (1<<0) /* SW reset */
115#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116#define UCR3_PARERREN (1<<12) /* Parity enable */
117#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118#define UCR3_DSR (1<<10) /* Data set ready */
119#define UCR3_DCD (1<<9) /* Data carrier detect */
120#define UCR3_RI (1<<8) /* Ring indicator */
Fabio Estevamb38cb7d2014-05-14 15:55:03 -0300121#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
Sachin Kamat82313e62013-01-07 10:25:02 +0530122#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127#define UCR3_BPEN (1<<0) /* Preset registers enable */
128#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130#define UCR4_INVR (1<<9) /* Inverted infrared reception */
131#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800134#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
Sachin Kamat82313e62013-01-07 10:25:02 +0530135#define UCR4_IRSC (1<<5) /* IR special case */
136#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146#define USR1_RTSS (1<<14) /* RTS pin status */
147#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148#define USR1_RTSD (1<<12) /* RTS delta */
149#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159#define USR2_IDLE (1<<12) /* Idle condition */
160#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161#define USR2_WAKE (1<<7) /* Wake */
162#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163#define USR2_TXDC (1<<3) /* Transmitter complete */
164#define USR2_BRCD (1<<2) /* Break condition */
165#define USR2_ORE (1<<1) /* Overrun error */
166#define USR2_RDR (1<<0) /* Recv data ready */
167#define UTS_FRCPERR (1<<13) /* Force parity error */
168#define UTS_LOOP (1<<12) /* Loop tx and rx */
169#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171#define UTS_TXFULL (1<<4) /* TxFIFO full */
172#define UTS_RXFULL (1<<3) /* RxFIFO full */
173#define UTS_SOFTRST (1<<0) /* Software reset */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100174
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175/* We've been assigned a range on the "Low-density serial ports" major */
Sachin Kamat82313e62013-01-07 10:25:02 +0530176#define SERIAL_IMX_MAJOR 207
177#define MINOR_START 16
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200178#define DEV_NAME "ttymxc"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186#define MCTRL_TIMEOUT (250*HZ/1000)
187
188#define DRIVER_NAME "IMX-uart"
189
Sascha Hauerdbff4e92008-07-05 10:02:45 +0200190#define UART_NR 8
191
Shawn Guofe6b5402011-06-25 02:04:33 +0800192/* i.mx21 type uart runs on all i.mx except i.mx1 */
193enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
Huang Shijiea496e622013-07-08 17:14:17 +0800196 IMX6Q_UART,
Shawn Guofe6b5402011-06-25 02:04:33 +0800197};
198
199/* device type dependent stuff */
200struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203};
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
Sachin Kamat82313e62013-01-07 10:25:02 +0530209 int txirq, rxirq, rtsirq;
Daniel Glöckner26bbb3f2009-06-11 14:36:29 +0100210 unsigned int have_rtscts:1;
Huang Shijie20ff2fe2013-05-30 14:07:12 +0800211 unsigned int dte_mode:1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
Sascha Hauer3a9465f2012-03-07 09:31:43 +0100216 struct clk *clk_ipg;
217 struct clk *clk_per;
Uwe Kleine-König7d0b0662012-05-21 21:57:39 +0200218 const struct imx_uart_data *devdata;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800228 unsigned int tx_bytes;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800229 unsigned int dma_tx_nents;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700230 wait_queue_head_t dma_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231};
232
Dirk Behme0ad5a812011-12-22 09:57:52 +0100233struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237};
238
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100239#ifdef CONFIG_IRDA
240#define USE_IRDA(sport) ((sport)->use_irda)
241#else
242#define USE_IRDA(sport) (0)
243#endif
244
Shawn Guofe6b5402011-06-25 02:04:33 +0800245static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
Huang Shijiea496e622013-07-08 17:14:17 +0800254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
Shawn Guofe6b5402011-06-25 02:04:33 +0800258};
259
260static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
Huang Shijiea496e622013-07-08 17:14:17 +0800268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
Shawn Guofe6b5402011-06-25 02:04:33 +0800271 /* sentinel */
272 }
273};
274MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
Shawn Guo22698aa2011-06-25 02:04:34 +0800276static struct of_device_id imx_uart_dt_ids[] = {
Huang Shijiea496e622013-07-08 17:14:17 +0800277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
Shawn Guo22698aa2011-06-25 02:04:34 +0800278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281};
282MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
Shawn Guofe6b5402011-06-25 02:04:33 +0800284static inline unsigned uts_reg(struct imx_port *sport)
285{
286 return sport->devdata->uts_reg;
287}
288
289static inline int is_imx1_uart(struct imx_port *sport)
290{
291 return sport->devdata->devtype == IMX1_UART;
292}
293
294static inline int is_imx21_uart(struct imx_port *sport)
295{
296 return sport->devdata->devtype == IMX21_UART;
297}
298
Huang Shijiea496e622013-07-08 17:14:17 +0800299static inline int is_imx6q_uart(struct imx_port *sport)
300{
301 return sport->devdata->devtype == IMX6Q_UART;
302}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303/*
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
Fabio Estevam93d94b32014-11-12 15:55:07 -0200306#if defined(CONFIG_SERIAL_IMX_CONSOLE)
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200307static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309{
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314}
315
316static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318{
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323}
Fabio Estevame8bfa762013-06-05 00:58:46 -0300324#endif
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200325
326/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 * Handle any change of modem status signal since we were last called.
328 */
329static void imx_mctrl_check(struct imx_port *sport)
330{
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
Alan Coxbdc04e32009-09-19 13:13:31 -0700350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351}
352
353/*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357static void imx_timeout(unsigned long data)
358{
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
Alan Coxebd2c8f2009-09-19 13:13:28 -0700362 if (sport->port.state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369}
370
371/*
372 * interrupts disabled on entry
373 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100374static void imx_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100377 unsigned long temp;
378
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800427
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430}
431
432/*
433 * interrupts disabled on entry
434 */
435static void imx_stop_rx(struct uart_port *port)
436{
437 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100438 unsigned long temp;
439
Huang Shijie45564a62014-09-19 15:33:12 +0800440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800448
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100449 temp = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +0530450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
Huang Shijie85878392014-05-23 12:32:54 +0800451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455}
456
457/*
458 * Set the modem control timer to fire immediately.
459 */
460static void imx_enable_ms(struct uart_port *port)
461{
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465}
466
Jiada Wang91a1a902014-12-09 18:11:36 +0900467static void imx_dma_tx(struct imx_port *sport);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468static inline void imx_transmit_buffer(struct imx_port *sport)
469{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700470 struct circ_buf *xmit = &sport->port.state->xmit;
Jiada Wang91a1a902014-12-09 18:11:36 +0900471 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400473 if (sport->port.x_char) {
474 /* Send next char */
475 writel(sport->port.x_char, sport->port.membase + URTX0);
Jiada Wang7e2fb5a2014-12-09 18:11:35 +0900476 sport->port.icount.tx++;
477 sport->port.x_char = 0;
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400478 return;
479 }
480
481 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
482 imx_stop_tx(&sport->port);
483 return;
484 }
485
Jiada Wang91a1a902014-12-09 18:11:36 +0900486 if (sport->dma_is_enabled) {
487 /*
488 * We've just sent a X-char Ensure the TX DMA is enabled
489 * and the TX IRQ is disabled.
490 **/
491 temp = readl(sport->port.membase + UCR1);
492 temp &= ~UCR1_TXMPTYEN;
493 if (sport->dma_is_txing) {
494 temp |= UCR1_TDMAEN;
495 writel(temp, sport->port.membase + UCR1);
496 } else {
497 writel(temp, sport->port.membase + UCR1);
498 imx_dma_tx(sport);
499 }
500 }
501
Volker Ernst4e4e6602010-10-13 11:03:57 +0200502 while (!uart_circ_empty(xmit) &&
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400503 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 /* send xmit->buf[xmit->tail]
505 * out the port here */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100506 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100507 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 sport->port.icount.tx++;
Sascha Hauer8c0b2542007-02-05 16:10:16 -0800509 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510
Fabian Godehardt977757312009-06-11 14:37:19 +0100511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
512 uart_write_wakeup(&sport->port);
513
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +0100515 imx_stop_tx(&sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516}
517
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800518static void dma_tx_callback(void *data)
519{
520 struct imx_port *sport = data;
521 struct scatterlist *sgl = &sport->tx_sgl[0];
522 struct circ_buf *xmit = &sport->port.state->xmit;
523 unsigned long flags;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900524 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800525
Dirk Behme42f752b2014-12-09 18:11:28 +0900526 spin_lock_irqsave(&sport->port.lock, flags);
527
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800528 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
529
Dirk Behmea2c718c2014-12-09 18:11:31 +0900530 temp = readl(sport->port.membase + UCR1);
531 temp &= ~UCR1_TDMAEN;
532 writel(temp, sport->port.membase + UCR1);
533
Dirk Behme42f752b2014-12-09 18:11:28 +0900534 /* update the stat */
535 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
536 sport->port.icount.tx += sport->tx_bytes;
537
538 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
539
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800540 sport->dma_is_txing = 0;
541
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800542 spin_unlock_irqrestore(&sport->port.lock, flags);
543
Jiada Wangd64b8602014-12-09 18:11:29 +0900544 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
545 uart_write_wakeup(&sport->port);
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700546
547 if (waitqueue_active(&sport->dma_wait)) {
548 wake_up(&sport->dma_wait);
549 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
550 return;
551 }
Jiada Wang0bbc9b82014-12-09 18:11:30 +0900552
553 spin_lock_irqsave(&sport->port.lock, flags);
554 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
555 imx_dma_tx(sport);
556 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800557}
558
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800559static void imx_dma_tx(struct imx_port *sport)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800560{
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800561 struct circ_buf *xmit = &sport->port.state->xmit;
562 struct scatterlist *sgl = sport->tx_sgl;
563 struct dma_async_tx_descriptor *desc;
564 struct dma_chan *chan = sport->dma_chan_tx;
565 struct device *dev = sport->port.dev;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900566 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800567 int ret;
568
Dirk Behme42f752b2014-12-09 18:11:28 +0900569 if (sport->dma_is_txing)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800570 return;
571
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800572 sport->tx_bytes = uart_circ_chars_pending(xmit);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800573
Dirk Behme7942f852014-12-09 18:11:25 +0900574 if (xmit->tail < xmit->head) {
575 sport->dma_tx_nents = 1;
576 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
577 } else {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800578 sport->dma_tx_nents = 2;
579 sg_init_table(sgl, 2);
580 sg_set_buf(sgl, xmit->buf + xmit->tail,
581 UART_XMIT_SIZE - xmit->tail);
582 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800583 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800584
585 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
586 if (ret == 0) {
587 dev_err(dev, "DMA mapping error for TX.\n");
588 return;
589 }
590 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
591 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
592 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +0900593 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
594 DMA_TO_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800595 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
596 return;
597 }
598 desc->callback = dma_tx_callback;
599 desc->callback_param = sport;
600
601 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
602 uart_circ_chars_pending(xmit));
Dirk Behmea2c718c2014-12-09 18:11:31 +0900603
604 temp = readl(sport->port.membase + UCR1);
605 temp |= UCR1_TDMAEN;
606 writel(temp, sport->port.membase + UCR1);
607
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800608 /* fire it */
609 sport->dma_is_txing = 1;
610 dmaengine_submit(desc);
611 dma_async_issue_pending(chan);
612 return;
613}
614
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615/*
616 * interrupts disabled on entry
617 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100618static void imx_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619{
620 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100621 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100623 if (USE_IRDA(sport)) {
624 /* half duplex in IrDA mode; have to disable receive mode */
625 temp = readl(sport->port.membase + UCR4);
626 temp &= ~(UCR4_DREN);
627 writel(temp, sport->port.membase + UCR4);
628
629 temp = readl(sport->port.membase + UCR1);
630 temp &= ~(UCR1_RRDYEN);
631 writel(temp, sport->port.membase + UCR1);
632 }
633
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800634 if (!sport->dma_is_enabled) {
635 temp = readl(sport->port.membase + UCR1);
636 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
637 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100639 if (USE_IRDA(sport)) {
640 temp = readl(sport->port.membase + UCR1);
641 temp |= UCR1_TRDYEN;
642 writel(temp, sport->port.membase + UCR1);
643
644 temp = readl(sport->port.membase + UCR4);
645 temp |= UCR4_TCEN;
646 writel(temp, sport->port.membase + UCR4);
647 }
648
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800649 if (sport->dma_is_enabled) {
Jiada Wang91a1a902014-12-09 18:11:36 +0900650 if (sport->port.x_char) {
651 /* We have X-char to send, so enable TX IRQ and
652 * disable TX DMA to let TX interrupt to send X-char */
653 temp = readl(sport->port.membase + UCR1);
654 temp &= ~UCR1_TDMAEN;
655 temp |= UCR1_TXMPTYEN;
656 writel(temp, sport->port.membase + UCR1);
657 return;
658 }
659
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400660 if (!uart_circ_empty(&port->state->xmit) &&
661 !uart_tx_stopped(port))
662 imx_dma_tx(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800663 return;
664 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665}
666
David Howells7d12e782006-10-05 14:55:46 +0100667static irqreturn_t imx_rtsint(int irq, void *dev_id)
Sascha Hauerceca6292005-10-12 19:58:08 +0100668{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800669 struct imx_port *sport = dev_id;
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200670 unsigned int val;
Sascha Hauerceca6292005-10-12 19:58:08 +0100671 unsigned long flags;
672
673 spin_lock_irqsave(&sport->port.lock, flags);
674
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100675 writel(USR1_RTSD, sport->port.membase + USR1);
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200676 val = readl(sport->port.membase + USR1) & USR1_RTSS;
Sascha Hauerceca6292005-10-12 19:58:08 +0100677 uart_handle_cts_change(&sport->port, !!val);
Alan Coxbdc04e32009-09-19 13:13:31 -0700678 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Sascha Hauerceca6292005-10-12 19:58:08 +0100679
680 spin_unlock_irqrestore(&sport->port.lock, flags);
681 return IRQ_HANDLED;
682}
683
David Howells7d12e782006-10-05 14:55:46 +0100684static irqreturn_t imx_txint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800686 struct imx_port *sport = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 unsigned long flags;
688
Sachin Kamat82313e62013-01-07 10:25:02 +0530689 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 imx_transmit_buffer(sport);
Sachin Kamat82313e62013-01-07 10:25:02 +0530691 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 return IRQ_HANDLED;
693}
694
David Howells7d12e782006-10-05 14:55:46 +0100695static irqreturn_t imx_rxint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696{
697 struct imx_port *sport = dev_id;
Sachin Kamat82313e62013-01-07 10:25:02 +0530698 unsigned int rx, flg, ignored = 0;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100699 struct tty_port *port = &sport->port.state->port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100700 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701
Sachin Kamat82313e62013-01-07 10:25:02 +0530702 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100704 while (readl(sport->port.membase + USR2) & USR2_RDR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 flg = TTY_NORMAL;
706 sport->port.icount.rx++;
707
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100708 rx = readl(sport->port.membase + URXD0);
709
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100710 temp = readl(sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100711 if (temp & USR2_BRCD) {
Andy Green94d32f92010-02-01 13:28:54 +0100712 writel(USR2_BRCD, sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100713 if (uart_handle_break(&sport->port))
714 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 }
716
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100717 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
Sascha Hauer864eeed2008-04-17 08:39:22 +0100718 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
Hui Wang019dc9e2011-08-24 17:41:47 +0800720 if (unlikely(rx & URXD_ERR)) {
721 if (rx & URXD_BRK)
722 sport->port.icount.brk++;
723 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100724 sport->port.icount.parity++;
725 else if (rx & URXD_FRMERR)
726 sport->port.icount.frame++;
727 if (rx & URXD_OVRRUN)
728 sport->port.icount.overrun++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729
Sascha Hauer864eeed2008-04-17 08:39:22 +0100730 if (rx & sport->port.ignore_status_mask) {
731 if (++ignored > 100)
732 goto out;
733 continue;
734 }
735
Eric Nelson8d267fd2014-12-18 12:37:13 -0700736 rx &= (sport->port.read_status_mask | 0xFF);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100737
Hui Wang019dc9e2011-08-24 17:41:47 +0800738 if (rx & URXD_BRK)
739 flg = TTY_BREAK;
740 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100741 flg = TTY_PARITY;
742 else if (rx & URXD_FRMERR)
743 flg = TTY_FRAME;
744 if (rx & URXD_OVRRUN)
745 flg = TTY_OVERRUN;
746
747#ifdef SUPPORT_SYSRQ
748 sport->port.sysrq = 0;
749#endif
750 }
751
Jiada Wang55d86932014-12-09 18:11:22 +0900752 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
753 goto out;
754
Jiri Slaby92a19f92013-01-03 15:53:03 +0100755 tty_insert_flip_char(port, rx, flg);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100756 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
758out:
Sachin Kamat82313e62013-01-07 10:25:02 +0530759 spin_unlock_irqrestore(&sport->port.lock, flags);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100760 tty_flip_buffer_push(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762}
763
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800764static int start_rx_dma(struct imx_port *sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800765/*
766 * If the RXFIFO is filled with some data, and then we
767 * arise a DMA operation to receive them.
768 */
769static void imx_dma_rxint(struct imx_port *sport)
770{
771 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900772 unsigned long flags;
773
774 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800775
776 temp = readl(sport->port.membase + USR2);
777 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
778 sport->dma_is_rxing = 1;
779
780 /* disable the `Recerver Ready Interrrupt` */
781 temp = readl(sport->port.membase + UCR1);
782 temp &= ~(UCR1_RRDYEN);
783 writel(temp, sport->port.membase + UCR1);
784
785 /* tell the DMA to receive the data. */
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800786 start_rx_dma(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800787 }
Jiada Wang73631812014-12-09 18:11:23 +0900788
789 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800790}
791
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200792static irqreturn_t imx_int(int irq, void *dev_id)
793{
794 struct imx_port *sport = dev_id;
795 unsigned int sts;
Alexander Steinf1f836e2013-05-14 17:06:07 +0200796 unsigned int sts2;
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200797
798 sts = readl(sport->port.membase + USR1);
799
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800800 if (sts & USR1_RRDY) {
801 if (sport->dma_is_enabled)
802 imx_dma_rxint(sport);
803 else
804 imx_rxint(irq, dev_id);
805 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200806
807 if (sts & USR1_TRDY &&
808 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
809 imx_txint(irq, dev_id);
810
Marc Kleine-Budde9fbe6042008-07-28 21:26:01 +0200811 if (sts & USR1_RTSD)
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200812 imx_rtsint(irq, dev_id);
813
Fabio Estevamdb1a9b52011-12-13 01:23:48 -0200814 if (sts & USR1_AWAKE)
815 writel(USR1_AWAKE, sport->port.membase + USR1);
816
Alexander Steinf1f836e2013-05-14 17:06:07 +0200817 sts2 = readl(sport->port.membase + USR2);
818 if (sts2 & USR2_ORE) {
819 dev_err(sport->port.dev, "Rx FIFO overrun\n");
820 sport->port.icount.overrun++;
821 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
822 }
823
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200824 return IRQ_HANDLED;
825}
826
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827/*
828 * Return TIOCSER_TEMT when transmitter is not busy.
829 */
830static unsigned int imx_tx_empty(struct uart_port *port)
831{
832 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie1ce43e52013-10-11 18:30:59 +0800833 unsigned int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834
Huang Shijie1ce43e52013-10-11 18:30:59 +0800835 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
836
837 /* If the TX DMA is working, return 0. */
838 if (sport->dma_is_enabled && sport->dma_is_txing)
839 ret = 0;
840
841 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842}
843
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100844/*
845 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
846 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847static unsigned int imx_get_mctrl(struct uart_port *port)
848{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100849 struct imx_port *sport = (struct imx_port *)port;
850 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100851
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100852 if (readl(sport->port.membase + USR1) & USR1_RTSS)
853 tmp |= TIOCM_CTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100854
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100855 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
856 tmp |= TIOCM_RTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100857
Huang Shijie6b471a92013-11-29 17:29:24 +0800858 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
859 tmp |= TIOCM_LOOP;
860
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100861 return tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862}
863
864static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
865{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100866 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100867 unsigned long temp;
868
Fugang Duanbb2f8612014-09-19 15:26:40 +0800869 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100870 if (mctrl & TIOCM_RTS)
Fugang Duanbb2f8612014-09-19 15:26:40 +0800871 temp |= UCR2_CTS | UCR2_CTSC;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100872
873 writel(temp, sport->port.membase + UCR2);
Huang Shijie6b471a92013-11-29 17:29:24 +0800874
875 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
876 if (mctrl & TIOCM_LOOP)
877 temp |= UTS_LOOP;
878 writel(temp, sport->port.membase + uts_reg(sport));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879}
880
881/*
882 * Interrupts always disabled.
883 */
884static void imx_break_ctl(struct uart_port *port, int break_state)
885{
886 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100887 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888
889 spin_lock_irqsave(&sport->port.lock, flags);
890
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100891 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
892
Sachin Kamat82313e62013-01-07 10:25:02 +0530893 if (break_state != 0)
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100894 temp |= UCR1_SNDBRK;
895
896 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897
898 spin_unlock_irqrestore(&sport->port.lock, flags);
899}
900
901#define TXTL 2 /* reset default */
902#define RXTL 1 /* reset default */
903
Sascha Hauer587897f2005-04-29 22:46:40 +0100904static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
905{
906 unsigned int val;
Sascha Hauer587897f2005-04-29 22:46:40 +0100907
Dirk Behme7be06702012-08-31 10:02:47 +0200908 /* set receiver / transmitter trigger level */
909 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
910 val |= TXTL << UFCR_TXTL_SHF | RXTL;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100911 writel(val, sport->port.membase + UFCR);
Sascha Hauer587897f2005-04-29 22:46:40 +0100912 return 0;
913}
914
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800915#define RX_BUF_SIZE (PAGE_SIZE)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800916static void imx_rx_dma_done(struct imx_port *sport)
917{
918 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900919 unsigned long flags;
920
921 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800922
923 /* Enable this interrupt when the RXFIFO is empty. */
924 temp = readl(sport->port.membase + UCR1);
925 temp |= UCR1_RRDYEN;
926 writel(temp, sport->port.membase + UCR1);
927
928 sport->dma_is_rxing = 0;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700929
930 /* Is the shutdown waiting for us? */
931 if (waitqueue_active(&sport->dma_wait))
932 wake_up(&sport->dma_wait);
Jiada Wang73631812014-12-09 18:11:23 +0900933
934 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800935}
936
937/*
938 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
939 * [1] the RX DMA buffer is full.
940 * [2] the Aging timer expires(wait for 8 bytes long)
941 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
942 *
943 * The [2] is trigger when a character was been sitting in the FIFO
944 * meanwhile [3] can wait for 32 bytes long when the RX line is
945 * on IDLE state and RxFIFO is empty.
946 */
947static void dma_rx_callback(void *data)
948{
949 struct imx_port *sport = data;
950 struct dma_chan *chan = sport->dma_chan_rx;
951 struct scatterlist *sgl = &sport->rx_sgl;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800952 struct tty_port *port = &sport->port.state->port;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800953 struct dma_tx_state state;
954 enum dma_status status;
955 unsigned int count;
956
957 /* unmap it first */
958 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
959
Huang Shijief0ef8832013-10-11 18:31:01 +0800960 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800961 count = RX_BUF_SIZE - state.residue;
962 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
963
964 if (count) {
Jiada Wang55d86932014-12-09 18:11:22 +0900965 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
966 tty_insert_flip_string(port, sport->rx_buf, count);
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800967 tty_flip_buffer_push(port);
968
969 start_rx_dma(sport);
Robin Gongee5e7c12014-12-09 18:11:33 +0900970 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
971 /*
972 * start rx_dma directly once data in RXFIFO, more efficient
973 * than before:
974 * 1. call imx_rx_dma_done to stop dma if no data received
975 * 2. wait next RDR interrupt to start dma transfer.
976 */
977 start_rx_dma(sport);
978 } else {
979 /*
980 * stop dma to prevent too many IDLE event trigged if no data
981 * in RXFIFO
982 */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800983 imx_rx_dma_done(sport);
Robin Gongee5e7c12014-12-09 18:11:33 +0900984 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800985}
986
987static int start_rx_dma(struct imx_port *sport)
988{
989 struct scatterlist *sgl = &sport->rx_sgl;
990 struct dma_chan *chan = sport->dma_chan_rx;
991 struct device *dev = sport->port.dev;
992 struct dma_async_tx_descriptor *desc;
993 int ret;
994
995 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
996 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
997 if (ret == 0) {
998 dev_err(dev, "DMA mapping error for RX.\n");
999 return -EINVAL;
1000 }
1001 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
1002 DMA_PREP_INTERRUPT);
1003 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +09001004 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001005 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1006 return -EINVAL;
1007 }
1008 desc->callback = dma_rx_callback;
1009 desc->callback_param = sport;
1010
1011 dev_dbg(dev, "RX: prepare for the DMA.\n");
1012 dmaengine_submit(desc);
1013 dma_async_issue_pending(chan);
1014 return 0;
1015}
1016
1017static void imx_uart_dma_exit(struct imx_port *sport)
1018{
1019 if (sport->dma_chan_rx) {
1020 dma_release_channel(sport->dma_chan_rx);
1021 sport->dma_chan_rx = NULL;
1022
1023 kfree(sport->rx_buf);
1024 sport->rx_buf = NULL;
1025 }
1026
1027 if (sport->dma_chan_tx) {
1028 dma_release_channel(sport->dma_chan_tx);
1029 sport->dma_chan_tx = NULL;
1030 }
1031
1032 sport->dma_is_inited = 0;
1033}
1034
1035static int imx_uart_dma_init(struct imx_port *sport)
1036{
Huang Shijieb09c74a2013-08-29 16:29:25 +08001037 struct dma_slave_config slave_config = {};
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001038 struct device *dev = sport->port.dev;
1039 int ret;
1040
1041 /* Prepare for RX : */
1042 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1043 if (!sport->dma_chan_rx) {
1044 dev_dbg(dev, "cannot get the DMA channel.\n");
1045 ret = -EINVAL;
1046 goto err;
1047 }
1048
1049 slave_config.direction = DMA_DEV_TO_MEM;
1050 slave_config.src_addr = sport->port.mapbase + URXD0;
1051 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1052 slave_config.src_maxburst = RXTL;
1053 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1054 if (ret) {
1055 dev_err(dev, "error in RX dma configuration.\n");
1056 goto err;
1057 }
1058
1059 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1060 if (!sport->rx_buf) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001061 ret = -ENOMEM;
1062 goto err;
1063 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001064
1065 /* Prepare for TX : */
1066 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1067 if (!sport->dma_chan_tx) {
1068 dev_err(dev, "cannot get the TX DMA channel!\n");
1069 ret = -EINVAL;
1070 goto err;
1071 }
1072
1073 slave_config.direction = DMA_MEM_TO_DEV;
1074 slave_config.dst_addr = sport->port.mapbase + URTX0;
1075 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1076 slave_config.dst_maxburst = TXTL;
1077 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1078 if (ret) {
1079 dev_err(dev, "error in TX dma configuration.");
1080 goto err;
1081 }
1082
1083 sport->dma_is_inited = 1;
1084
1085 return 0;
1086err:
1087 imx_uart_dma_exit(sport);
1088 return ret;
1089}
1090
1091static void imx_enable_dma(struct imx_port *sport)
1092{
1093 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001094
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001095 init_waitqueue_head(&sport->dma_wait);
1096
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001097 /* set UCR1 */
1098 temp = readl(sport->port.membase + UCR1);
1099 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1100 /* wait for 32 idle frames for IDDMA interrupt */
1101 UCR1_ICD_REG(3);
1102 writel(temp, sport->port.membase + UCR1);
1103
1104 /* set UCR4 */
1105 temp = readl(sport->port.membase + UCR4);
1106 temp |= UCR4_IDDMAEN;
1107 writel(temp, sport->port.membase + UCR4);
1108
1109 sport->dma_is_enabled = 1;
1110}
1111
1112static void imx_disable_dma(struct imx_port *sport)
1113{
1114 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001115
1116 /* clear UCR1 */
1117 temp = readl(sport->port.membase + UCR1);
1118 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1119 writel(temp, sport->port.membase + UCR1);
1120
1121 /* clear UCR2 */
1122 temp = readl(sport->port.membase + UCR2);
1123 temp &= ~(UCR2_CTSC | UCR2_CTS);
1124 writel(temp, sport->port.membase + UCR2);
1125
1126 /* clear UCR4 */
1127 temp = readl(sport->port.membase + UCR4);
1128 temp &= ~UCR4_IDDMAEN;
1129 writel(temp, sport->port.membase + UCR4);
1130
1131 sport->dma_is_enabled = 0;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001132}
1133
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001134/* half the RX buffer size */
1135#define CTSTL 16
1136
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137static int imx_startup(struct uart_port *port)
1138{
1139 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie772f8992014-05-21 08:56:28 +08001140 int retval, i;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001141 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Huang Shijie1cf93e02013-06-28 13:39:42 +08001143 retval = clk_prepare_enable(sport->clk_per);
1144 if (retval)
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001145 return retval;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001146 retval = clk_prepare_enable(sport->clk_ipg);
1147 if (retval) {
1148 clk_disable_unprepare(sport->clk_per);
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001149 return retval;
Huang Shijie0c375502013-06-09 10:01:19 +08001150 }
Huang Shijie28eb4272013-06-04 09:59:33 +08001151
Sascha Hauer587897f2005-04-29 22:46:40 +01001152 imx_setup_ufcr(sport, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153
1154 /* disable the DREN bit (Data Ready interrupt enable) before
1155 * requesting IRQs
1156 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001157 temp = readl(sport->port.membase + UCR4);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001158
1159 if (USE_IRDA(sport))
1160 temp |= UCR4_IRSC;
1161
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001162 /* set the trigger level for CTS */
Sachin Kamat82313e62013-01-07 10:25:02 +05301163 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1164 temp |= CTSTL << UCR4_CTSTL_SHF;
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001165
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001166 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167
Huang Shijie772f8992014-05-21 08:56:28 +08001168 /* Reset fifo's and state machines */
1169 i = 100;
1170
1171 temp = readl(sport->port.membase + UCR2);
1172 temp &= ~UCR2_SRST;
1173 writel(temp, sport->port.membase + UCR2);
1174
1175 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1176 udelay(1);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001177
Anton Bondarenko068500e2014-12-09 18:11:32 +09001178 /* Can we enable the DMA support? */
1179 if (is_imx6q_uart(sport) && !uart_console(port) &&
1180 !sport->dma_is_inited)
1181 imx_uart_dma_init(sport);
1182
Xinyu Chen9ec18822012-08-27 09:36:51 +02001183 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 /*
1185 * Finally, clear and enable interrupts
1186 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001187 writel(USR1_RTSD, sport->port.membase + USR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188
Anton Bondarenko068500e2014-12-09 18:11:32 +09001189 if (sport->dma_is_inited && !sport->dma_is_enabled)
1190 imx_enable_dma(sport);
1191
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001192 temp = readl(sport->port.membase + UCR1);
Sascha Hauer789d5252008-04-17 08:44:47 +01001193 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001194
1195 if (USE_IRDA(sport)) {
1196 temp |= UCR1_IREN;
1197 temp &= ~(UCR1_RTSDEN);
1198 }
1199
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001200 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201
Jiada Wang6f026d6b2014-12-09 18:11:34 +09001202 /* Clear any pending ORE flag before enabling interrupt */
1203 temp = readl(sport->port.membase + USR2);
1204 writel(temp | USR2_ORE, sport->port.membase + USR2);
1205
1206 temp = readl(sport->port.membase + UCR4);
1207 temp |= UCR4_OREN;
1208 writel(temp, sport->port.membase + UCR4);
1209
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001210 temp = readl(sport->port.membase + UCR2);
1211 temp |= (UCR2_RXEN | UCR2_TXEN);
Lucas Stachbff09b02013-05-30 15:47:04 +02001212 if (!sport->have_rtscts)
1213 temp |= UCR2_IRTS;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001214 writel(temp, sport->port.membase + UCR2);
1215
Huang Shijiea496e622013-07-08 17:14:17 +08001216 if (!is_imx1_uart(sport)) {
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001217 temp = readl(sport->port.membase + UCR3);
Fabio Estevamb38cb7d2014-05-14 15:55:03 -03001218 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001219 writel(temp, sport->port.membase + UCR3);
1220 }
Marc Kleine-Budde44118052008-07-28 12:10:34 +02001221
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001222 if (USE_IRDA(sport)) {
1223 temp = readl(sport->port.membase + UCR4);
1224 if (sport->irda_inv_rx)
1225 temp |= UCR4_INVR;
1226 else
1227 temp &= ~(UCR4_INVR);
1228 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1229
1230 temp = readl(sport->port.membase + UCR3);
1231 if (sport->irda_inv_tx)
1232 temp |= UCR3_INVT;
1233 else
1234 temp &= ~(UCR3_INVT);
1235 writel(temp, sport->port.membase + UCR3);
1236 }
1237
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 /*
1239 * Enable modem status interrupts
1240 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241 imx_enable_ms(&sport->port);
Sachin Kamat82313e62013-01-07 10:25:02 +05301242 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001244 if (USE_IRDA(sport)) {
1245 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001246 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001247 sport->irda_inv_rx = pdata->irda_inv_rx;
1248 sport->irda_inv_tx = pdata->irda_inv_tx;
1249 sport->trcv_delay = pdata->transceiver_delay;
1250 if (pdata->irda_enable)
1251 pdata->irda_enable(1);
1252 }
1253
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255}
1256
1257static void imx_shutdown(struct uart_port *port)
1258{
1259 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001260 unsigned long temp;
Xinyu Chen9ec18822012-08-27 09:36:51 +02001261 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001263 if (sport->dma_is_enabled) {
Huang Shijiea4688bc2014-09-19 15:42:57 +08001264 int ret;
1265
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001266 /* We have to wait for the DMA to finish. */
Huang Shijiea4688bc2014-09-19 15:42:57 +08001267 ret = wait_event_interruptible(sport->dma_wait,
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001268 !sport->dma_is_rxing && !sport->dma_is_txing);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001269 if (ret != 0) {
1270 sport->dma_is_rxing = 0;
1271 sport->dma_is_txing = 0;
1272 dmaengine_terminate_all(sport->dma_chan_tx);
1273 dmaengine_terminate_all(sport->dma_chan_rx);
1274 }
Jiada Wang73631812014-12-09 18:11:23 +09001275 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001276 imx_stop_tx(port);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001277 imx_stop_rx(port);
1278 imx_disable_dma(sport);
Jiada Wang73631812014-12-09 18:11:23 +09001279 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001280 imx_uart_dma_exit(sport);
1281 }
1282
Xinyu Chen9ec18822012-08-27 09:36:51 +02001283 spin_lock_irqsave(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001284 temp = readl(sport->port.membase + UCR2);
1285 temp &= ~(UCR2_TXEN);
1286 writel(temp, sport->port.membase + UCR2);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001287 spin_unlock_irqrestore(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001288
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001289 if (USE_IRDA(sport)) {
1290 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001291 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001292 if (pdata->irda_enable)
1293 pdata->irda_enable(0);
1294 }
1295
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 /*
1297 * Stop our timer.
1298 */
1299 del_timer_sync(&sport->timer);
1300
1301 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 * Disable all interrupts, port and break condition.
1303 */
1304
Xinyu Chen9ec18822012-08-27 09:36:51 +02001305 spin_lock_irqsave(&sport->port.lock, flags);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001306 temp = readl(sport->port.membase + UCR1);
1307 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001308 if (USE_IRDA(sport))
1309 temp &= ~(UCR1_IREN);
1310
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001311 writel(temp, sport->port.membase + UCR1);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001312 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie28eb4272013-06-04 09:59:33 +08001313
Huang Shijie1cf93e02013-06-28 13:39:42 +08001314 clk_disable_unprepare(sport->clk_per);
1315 clk_disable_unprepare(sport->clk_ipg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316}
1317
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001318static void imx_flush_buffer(struct uart_port *port)
1319{
1320 struct imx_port *sport = (struct imx_port *)port;
Dirk Behme82e86ae2014-12-09 18:11:27 +09001321 struct scatterlist *sgl = &sport->tx_sgl[0];
Dirk Behmea2c718c2014-12-09 18:11:31 +09001322 unsigned long temp;
Fabio Estevam934084a2015-01-13 10:00:26 -02001323 int i = 100, ubir, ubmr, ubrc, uts;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001324
Dirk Behme82e86ae2014-12-09 18:11:27 +09001325 if (!sport->dma_chan_tx)
1326 return;
1327
1328 sport->tx_bytes = 0;
1329 dmaengine_terminate_all(sport->dma_chan_tx);
1330 if (sport->dma_is_txing) {
1331 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1332 DMA_TO_DEVICE);
Dirk Behmea2c718c2014-12-09 18:11:31 +09001333 temp = readl(sport->port.membase + UCR1);
1334 temp &= ~UCR1_TDMAEN;
1335 writel(temp, sport->port.membase + UCR1);
Dirk Behme82e86ae2014-12-09 18:11:27 +09001336 sport->dma_is_txing = false;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001337 }
Fabio Estevam934084a2015-01-13 10:00:26 -02001338
1339 /*
1340 * According to the Reference Manual description of the UART SRST bit:
1341 * "Reset the transmit and receive state machines,
1342 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1343 * and UTS[6-3]". As we don't need to restore the old values from
1344 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1345 */
1346 ubir = readl(sport->port.membase + UBIR);
1347 ubmr = readl(sport->port.membase + UBMR);
1348 ubrc = readl(sport->port.membase + UBRC);
1349 uts = readl(sport->port.membase + IMX21_UTS);
1350
1351 temp = readl(sport->port.membase + UCR2);
1352 temp &= ~UCR2_SRST;
1353 writel(temp, sport->port.membase + UCR2);
1354
1355 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1356 udelay(1);
1357
1358 /* Restore the registers */
1359 writel(ubir, sport->port.membase + UBIR);
1360 writel(ubmr, sport->port.membase + UBMR);
1361 writel(ubrc, sport->port.membase + UBRC);
1362 writel(uts, sport->port.membase + IMX21_UTS);
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001363}
1364
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365static void
Alan Cox606d0992006-12-08 02:38:45 -08001366imx_set_termios(struct uart_port *port, struct ktermios *termios,
1367 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368{
1369 struct imx_port *sport = (struct imx_port *)port;
1370 unsigned long flags;
1371 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1372 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
Oskar Schirmer534fca02009-06-11 14:52:23 +01001373 unsigned int div, ufcr;
1374 unsigned long num, denom;
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001375 uint64_t tdiv64;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376
1377 /*
1378 * If we don't support modem control lines, don't allow
1379 * these to be set.
1380 */
1381 if (0) {
1382 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1383 termios->c_cflag |= CLOCAL;
1384 }
1385
1386 /*
1387 * We only support CS7 and CS8.
1388 */
1389 while ((termios->c_cflag & CSIZE) != CS7 &&
1390 (termios->c_cflag & CSIZE) != CS8) {
1391 termios->c_cflag &= ~CSIZE;
1392 termios->c_cflag |= old_csize;
1393 old_csize = CS8;
1394 }
1395
1396 if ((termios->c_cflag & CSIZE) == CS8)
1397 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1398 else
1399 ucr2 = UCR2_SRST | UCR2_IRTS;
1400
1401 if (termios->c_cflag & CRTSCTS) {
Sachin Kamat82313e62013-01-07 10:25:02 +05301402 if (sport->have_rtscts) {
Sascha Hauer5b802342006-05-04 14:07:42 +01001403 ucr2 &= ~UCR2_IRTS;
1404 ucr2 |= UCR2_CTSC;
1405 } else {
1406 termios->c_cflag &= ~CRTSCTS;
1407 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408 }
1409
1410 if (termios->c_cflag & CSTOPB)
1411 ucr2 |= UCR2_STPB;
1412 if (termios->c_cflag & PARENB) {
1413 ucr2 |= UCR2_PREN;
Matt Reimer3261e362006-01-13 20:51:44 +00001414 if (termios->c_cflag & PARODD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415 ucr2 |= UCR2_PROE;
1416 }
1417
Eric Miao995234d2011-12-23 05:39:27 +08001418 del_timer_sync(&sport->timer);
1419
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420 /*
1421 * Ask the core to calculate the divisor for us.
1422 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001423 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 quot = uart_get_divisor(port, baud);
1425
1426 spin_lock_irqsave(&sport->port.lock, flags);
1427
1428 sport->port.read_status_mask = 0;
1429 if (termios->c_iflag & INPCK)
1430 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1431 if (termios->c_iflag & (BRKINT | PARMRK))
1432 sport->port.read_status_mask |= URXD_BRK;
1433
1434 /*
1435 * Characters to ignore
1436 */
1437 sport->port.ignore_status_mask = 0;
1438 if (termios->c_iflag & IGNPAR)
Eric Nelson865cea82014-12-18 12:37:14 -07001439 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 if (termios->c_iflag & IGNBRK) {
1441 sport->port.ignore_status_mask |= URXD_BRK;
1442 /*
1443 * If we're ignoring parity and break indicators,
1444 * ignore overruns too (for real raw support).
1445 */
1446 if (termios->c_iflag & IGNPAR)
1447 sport->port.ignore_status_mask |= URXD_OVRRUN;
1448 }
1449
Jiada Wang55d86932014-12-09 18:11:22 +09001450 if ((termios->c_cflag & CREAD) == 0)
1451 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1452
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453 /*
1454 * Update the per-port timeout.
1455 */
1456 uart_update_timeout(port, termios->c_cflag, baud);
1457
1458 /*
1459 * disable interrupts and drain transmitter
1460 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001461 old_ucr1 = readl(sport->port.membase + UCR1);
1462 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1463 sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
Sachin Kamat82313e62013-01-07 10:25:02 +05301465 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 barrier();
1467
1468 /* then, disable everything */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001469 old_txrxen = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +05301470 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001471 sport->port.membase + UCR2);
1472 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001474 if (USE_IRDA(sport)) {
1475 /*
1476 * use maximum available submodule frequency to
1477 * avoid missing short pulses due to low sampling rate
1478 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001479 div = 1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001480 } else {
Hubert Feurstein09bd00f2013-07-18 18:52:49 +02001481 /* custom-baudrate handling */
1482 div = sport->port.uartclk / (baud * 16);
1483 if (baud == 38400 && quot != div)
1484 baud = sport->port.uartclk / (quot * 16);
1485
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001486 div = sport->port.uartclk / (baud * 16);
1487 if (div > 7)
1488 div = 7;
1489 if (!div)
1490 div = 1;
1491 }
Sascha Hauer036bb152008-07-05 10:02:44 +02001492
Oskar Schirmer534fca02009-06-11 14:52:23 +01001493 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1494 1 << 16, 1 << 16, &num, &denom);
Sascha Hauer036bb152008-07-05 10:02:44 +02001495
Alan Coxeab4f5a2010-06-01 22:52:52 +02001496 tdiv64 = sport->port.uartclk;
1497 tdiv64 *= num;
1498 do_div(tdiv64, denom * 16 * div);
1499 tty_termios_encode_baud_rate(termios,
Sascha Hauer1a2c4b32009-06-16 17:02:15 +01001500 (speed_t)tdiv64, (speed_t)tdiv64);
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001501
Oskar Schirmer534fca02009-06-11 14:52:23 +01001502 num -= 1;
1503 denom -= 1;
Sascha Hauer036bb152008-07-05 10:02:44 +02001504
1505 ufcr = readl(sport->port.membase + UFCR);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001506 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001507 if (sport->dte_mode)
1508 ufcr |= UFCR_DCEDTE;
Sascha Hauer036bb152008-07-05 10:02:44 +02001509 writel(ufcr, sport->port.membase + UFCR);
1510
Oskar Schirmer534fca02009-06-11 14:52:23 +01001511 writel(num, sport->port.membase + UBIR);
1512 writel(denom, sport->port.membase + UBMR);
1513
Huang Shijiea496e622013-07-08 17:14:17 +08001514 if (!is_imx1_uart(sport))
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001515 writel(sport->port.uartclk / div / 1000,
Shawn Guofe6b5402011-06-25 02:04:33 +08001516 sport->port.membase + IMX21_ONEMS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001518 writel(old_ucr1, sport->port.membase + UCR1);
1519
1520 /* set the parity, stop bits and data size */
1521 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522
1523 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1524 imx_enable_ms(&sport->port);
1525
1526 spin_unlock_irqrestore(&sport->port.lock, flags);
1527}
1528
1529static const char *imx_type(struct uart_port *port)
1530{
1531 struct imx_port *sport = (struct imx_port *)port;
1532
1533 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1534}
1535
1536/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 * Configure/autoconfigure the port.
1538 */
1539static void imx_config_port(struct uart_port *port, int flags)
1540{
1541 struct imx_port *sport = (struct imx_port *)port;
1542
Alexander Shiyanda82f992014-02-22 16:01:33 +04001543 if (flags & UART_CONFIG_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 sport->port.type = PORT_IMX;
1545}
1546
1547/*
1548 * Verify the new serial_struct (for TIOCSSERIAL).
1549 * The only change we allow are to the flags and type, and
1550 * even then only between PORT_IMX and PORT_UNKNOWN
1551 */
1552static int
1553imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1554{
1555 struct imx_port *sport = (struct imx_port *)port;
1556 int ret = 0;
1557
1558 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1559 ret = -EINVAL;
1560 if (sport->port.irq != ser->irq)
1561 ret = -EINVAL;
1562 if (ser->io_type != UPIO_MEM)
1563 ret = -EINVAL;
1564 if (sport->port.uartclk / 16 != ser->baud_base)
1565 ret = -EINVAL;
Olof Johanssona50c44c2013-09-11 21:27:53 -07001566 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567 ret = -EINVAL;
1568 if (sport->port.iobase != ser->port)
1569 ret = -EINVAL;
1570 if (ser->hub6 != 0)
1571 ret = -EINVAL;
1572 return ret;
1573}
1574
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001575#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001576
1577static int imx_poll_init(struct uart_port *port)
1578{
1579 struct imx_port *sport = (struct imx_port *)port;
1580 unsigned long flags;
1581 unsigned long temp;
1582 int retval;
1583
1584 retval = clk_prepare_enable(sport->clk_ipg);
1585 if (retval)
1586 return retval;
1587 retval = clk_prepare_enable(sport->clk_per);
1588 if (retval)
1589 clk_disable_unprepare(sport->clk_ipg);
1590
1591 imx_setup_ufcr(sport, 0);
1592
1593 spin_lock_irqsave(&sport->port.lock, flags);
1594
1595 temp = readl(sport->port.membase + UCR1);
1596 if (is_imx1_uart(sport))
1597 temp |= IMX1_UCR1_UARTCLKEN;
1598 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1599 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1600 writel(temp, sport->port.membase + UCR1);
1601
1602 temp = readl(sport->port.membase + UCR2);
1603 temp |= UCR2_RXEN;
1604 writel(temp, sport->port.membase + UCR2);
1605
1606 spin_unlock_irqrestore(&sport->port.lock, flags);
1607
1608 return 0;
1609}
1610
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001611static int imx_poll_get_char(struct uart_port *port)
1612{
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001613 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
Dirk Behme26c47412014-09-03 12:33:53 +01001614 return NO_POLL_CHAR;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001615
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001616 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001617}
1618
1619static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1620{
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001621 unsigned int status;
1622
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001623 /* drain */
1624 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001625 status = readl_relaxed(port->membase + USR1);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001626 } while (~status & USR1_TRDY);
1627
1628 /* write */
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001629 writel_relaxed(c, port->membase + URTX0);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001630
1631 /* flush */
1632 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001633 status = readl_relaxed(port->membase + USR2);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001634 } while (~status & USR2_TXDC);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001635}
1636#endif
1637
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638static struct uart_ops imx_pops = {
1639 .tx_empty = imx_tx_empty,
1640 .set_mctrl = imx_set_mctrl,
1641 .get_mctrl = imx_get_mctrl,
1642 .stop_tx = imx_stop_tx,
1643 .start_tx = imx_start_tx,
1644 .stop_rx = imx_stop_rx,
1645 .enable_ms = imx_enable_ms,
1646 .break_ctl = imx_break_ctl,
1647 .startup = imx_startup,
1648 .shutdown = imx_shutdown,
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001649 .flush_buffer = imx_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650 .set_termios = imx_set_termios,
1651 .type = imx_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652 .config_port = imx_config_port,
1653 .verify_port = imx_verify_port,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001654#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001655 .poll_init = imx_poll_init,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001656 .poll_get_char = imx_poll_get_char,
1657 .poll_put_char = imx_poll_put_char,
1658#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659};
1660
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001661static struct imx_port *imx_ports[UART_NR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001662
1663#ifdef CONFIG_SERIAL_IMX_CONSOLE
Russell Kingd3587882006-03-20 20:00:09 +00001664static void imx_console_putchar(struct uart_port *port, int ch)
1665{
1666 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001667
Shawn Guofe6b5402011-06-25 02:04:33 +08001668 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
Russell Kingd3587882006-03-20 20:00:09 +00001669 barrier();
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001670
1671 writel(ch, sport->port.membase + URTX0);
Russell Kingd3587882006-03-20 20:00:09 +00001672}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673
1674/*
1675 * Interrupts are disabled on entering
1676 */
1677static void
1678imx_console_write(struct console *co, const char *s, unsigned int count)
1679{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001680 struct imx_port *sport = imx_ports[co->index];
Dirk Behme0ad5a812011-12-22 09:57:52 +01001681 struct imx_port_ucrs old_ucr;
1682 unsigned int ucr1;
Shawn Guof30e8262013-02-18 13:15:36 +08001683 unsigned long flags = 0;
Thomas Gleixner677fe552013-02-14 21:01:06 +01001684 int locked = 1;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001685 int retval;
1686
1687 retval = clk_enable(sport->clk_per);
1688 if (retval)
1689 return;
1690 retval = clk_enable(sport->clk_ipg);
1691 if (retval) {
1692 clk_disable(sport->clk_per);
1693 return;
1694 }
Xinyu Chen9ec18822012-08-27 09:36:51 +02001695
Thomas Gleixner677fe552013-02-14 21:01:06 +01001696 if (sport->port.sysrq)
1697 locked = 0;
1698 else if (oops_in_progress)
1699 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1700 else
1701 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702
1703 /*
Dirk Behme0ad5a812011-12-22 09:57:52 +01001704 * First, save UCR1/2/3 and then disable interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705 */
Dirk Behme0ad5a812011-12-22 09:57:52 +01001706 imx_port_ucrs_save(&sport->port, &old_ucr);
1707 ucr1 = old_ucr.ucr1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708
Shawn Guofe6b5402011-06-25 02:04:33 +08001709 if (is_imx1_uart(sport))
1710 ucr1 |= IMX1_UCR1_UARTCLKEN;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001711 ucr1 |= UCR1_UARTEN;
1712 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1713
1714 writel(ucr1, sport->port.membase + UCR1);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001715
Dirk Behme0ad5a812011-12-22 09:57:52 +01001716 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717
Russell Kingd3587882006-03-20 20:00:09 +00001718 uart_console_write(&sport->port, s, count, imx_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001719
1720 /*
1721 * Finally, wait for transmitter to become empty
Dirk Behme0ad5a812011-12-22 09:57:52 +01001722 * and restore UCR1/2/3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001724 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725
Dirk Behme0ad5a812011-12-22 09:57:52 +01001726 imx_port_ucrs_restore(&sport->port, &old_ucr);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001727
Thomas Gleixner677fe552013-02-14 21:01:06 +01001728 if (locked)
1729 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie1cf93e02013-06-28 13:39:42 +08001730
1731 clk_disable(sport->clk_ipg);
1732 clk_disable(sport->clk_per);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733}
1734
1735/*
1736 * If the port was already initialised (eg, by a boot loader),
1737 * try to determine the current setup.
1738 */
1739static void __init
1740imx_console_get_options(struct imx_port *sport, int *baud,
1741 int *parity, int *bits)
1742{
Sascha Hauer587897f2005-04-29 22:46:40 +01001743
Roel Kluin2e2eb502009-12-09 12:31:36 -08001744 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745 /* ok, the port was enabled */
Sachin Kamat82313e62013-01-07 10:25:02 +05301746 unsigned int ucr2, ubir, ubmr, uartclk;
Sascha Hauer587897f2005-04-29 22:46:40 +01001747 unsigned int baud_raw;
1748 unsigned int ucfr_rfdiv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001750 ucr2 = readl(sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751
1752 *parity = 'n';
1753 if (ucr2 & UCR2_PREN) {
1754 if (ucr2 & UCR2_PROE)
1755 *parity = 'o';
1756 else
1757 *parity = 'e';
1758 }
1759
1760 if (ucr2 & UCR2_WS)
1761 *bits = 8;
1762 else
1763 *bits = 7;
1764
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001765 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1766 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001768 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
Sascha Hauer587897f2005-04-29 22:46:40 +01001769 if (ucfr_rfdiv == 6)
1770 ucfr_rfdiv = 7;
1771 else
1772 ucfr_rfdiv = 6 - ucfr_rfdiv;
1773
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001774 uartclk = clk_get_rate(sport->clk_per);
Sascha Hauer587897f2005-04-29 22:46:40 +01001775 uartclk /= ucfr_rfdiv;
1776
1777 { /*
1778 * The next code provides exact computation of
1779 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1780 * without need of float support or long long division,
1781 * which would be required to prevent 32bit arithmetic overflow
1782 */
1783 unsigned int mul = ubir + 1;
1784 unsigned int div = 16 * (ubmr + 1);
1785 unsigned int rem = uartclk % div;
1786
1787 baud_raw = (uartclk / div) * mul;
1788 baud_raw += (rem * mul + div / 2) / div;
1789 *baud = (baud_raw + 50) / 100 * 100;
1790 }
1791
Sachin Kamat82313e62013-01-07 10:25:02 +05301792 if (*baud != baud_raw)
Sachin Kamat50bbdba2013-01-07 10:25:05 +05301793 pr_info("Console IMX rounded baud rate from %d to %d\n",
Sascha Hauer587897f2005-04-29 22:46:40 +01001794 baud_raw, *baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 }
1796}
1797
1798static int __init
1799imx_console_setup(struct console *co, char *options)
1800{
1801 struct imx_port *sport;
1802 int baud = 9600;
1803 int bits = 8;
1804 int parity = 'n';
1805 int flow = 'n';
Huang Shijie1cf93e02013-06-28 13:39:42 +08001806 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001807
1808 /*
1809 * Check whether an invalid uart number has been specified, and
1810 * if so, search for the first available port that does have
1811 * console support.
1812 */
1813 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1814 co->index = 0;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001815 sport = imx_ports[co->index];
Sachin Kamat82313e62013-01-07 10:25:02 +05301816 if (sport == NULL)
Eric Lammertse76afc42009-05-19 20:53:20 -04001817 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818
Huang Shijie1cf93e02013-06-28 13:39:42 +08001819 /* For setting the registers, we only need to enable the ipg clock. */
1820 retval = clk_prepare_enable(sport->clk_ipg);
1821 if (retval)
1822 goto error_console;
1823
Linus Torvalds1da177e2005-04-16 15:20:36 -07001824 if (options)
1825 uart_parse_options(options, &baud, &parity, &bits, &flow);
1826 else
1827 imx_console_get_options(sport, &baud, &parity, &bits);
1828
Sascha Hauer587897f2005-04-29 22:46:40 +01001829 imx_setup_ufcr(sport, 0);
1830
Huang Shijie1cf93e02013-06-28 13:39:42 +08001831 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1832
1833 clk_disable(sport->clk_ipg);
1834 if (retval) {
1835 clk_unprepare(sport->clk_ipg);
1836 goto error_console;
1837 }
1838
1839 retval = clk_prepare(sport->clk_per);
1840 if (retval)
1841 clk_disable_unprepare(sport->clk_ipg);
1842
1843error_console:
1844 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845}
1846
Vincent Sanders9f4426d2005-10-01 22:56:34 +01001847static struct uart_driver imx_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848static struct console imx_console = {
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001849 .name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850 .write = imx_console_write,
1851 .device = uart_console_device,
1852 .setup = imx_console_setup,
1853 .flags = CON_PRINTBUFFER,
1854 .index = -1,
1855 .data = &imx_reg,
1856};
1857
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858#define IMX_CONSOLE &imx_console
1859#else
1860#define IMX_CONSOLE NULL
1861#endif
1862
1863static struct uart_driver imx_reg = {
1864 .owner = THIS_MODULE,
1865 .driver_name = DRIVER_NAME,
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001866 .dev_name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 .major = SERIAL_IMX_MAJOR,
1868 .minor = MINOR_START,
1869 .nr = ARRAY_SIZE(imx_ports),
1870 .cons = IMX_CONSOLE,
1871};
1872
Russell King3ae5eae2005-11-09 22:32:44 +00001873static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001875 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001876 unsigned int val;
1877
1878 /* enable wakeup from i.MX UART */
1879 val = readl(sport->port.membase + UCR3);
1880 val |= UCR3_AWAKEN;
1881 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
Richard Zhao034dc4d2012-09-18 16:14:59 +08001883 uart_suspend_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001885 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886}
1887
Russell King3ae5eae2005-11-09 22:32:44 +00001888static int serial_imx_resume(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001890 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001891 unsigned int val;
1892
1893 /* disable wakeup from i.MX UART */
1894 val = readl(sport->port.membase + UCR3);
1895 val &= ~UCR3_AWAKEN;
1896 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897
Richard Zhao034dc4d2012-09-18 16:14:59 +08001898 uart_resume_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001900 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901}
1902
Shawn Guo22698aa2011-06-25 02:04:34 +08001903#ifdef CONFIG_OF
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001904/*
1905 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1906 * could successfully get all information from dt or a negative errno.
1907 */
Shawn Guo22698aa2011-06-25 02:04:34 +08001908static int serial_imx_probe_dt(struct imx_port *sport,
1909 struct platform_device *pdev)
1910{
1911 struct device_node *np = pdev->dev.of_node;
1912 const struct of_device_id *of_id =
1913 of_match_device(imx_uart_dt_ids, &pdev->dev);
Shawn Guoff059672011-09-22 14:48:13 +08001914 int ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001915
1916 if (!np)
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001917 /* no device tree device */
1918 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001919
Shawn Guoff059672011-09-22 14:48:13 +08001920 ret = of_alias_get_id(np, "serial");
1921 if (ret < 0) {
1922 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
Uwe Kleine-Königa197a192011-12-14 21:26:51 +01001923 return ret;
Shawn Guoff059672011-09-22 14:48:13 +08001924 }
1925 sport->port.line = ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001926
1927 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1928 sport->have_rtscts = 1;
1929
1930 if (of_get_property(np, "fsl,irda-mode", NULL))
1931 sport->use_irda = 1;
1932
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001933 if (of_get_property(np, "fsl,dte-mode", NULL))
1934 sport->dte_mode = 1;
1935
Shawn Guo22698aa2011-06-25 02:04:34 +08001936 sport->devdata = of_id->data;
1937
1938 return 0;
1939}
1940#else
1941static inline int serial_imx_probe_dt(struct imx_port *sport,
1942 struct platform_device *pdev)
1943{
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001944 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001945}
1946#endif
1947
1948static void serial_imx_probe_pdata(struct imx_port *sport,
1949 struct platform_device *pdev)
1950{
Jingoo Han574de552013-07-30 17:06:57 +09001951 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
Shawn Guo22698aa2011-06-25 02:04:34 +08001952
1953 sport->port.line = pdev->id;
1954 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1955
1956 if (!pdata)
1957 return;
1958
1959 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1960 sport->have_rtscts = 1;
1961
1962 if (pdata->flags & IMXUART_IRDA)
1963 sport->use_irda = 1;
1964}
1965
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001966static int serial_imx_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001968 struct imx_port *sport;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001969 void __iomem *base;
1970 int ret = 0;
1971 struct resource *res;
Sascha Hauer5b802342006-05-04 14:07:42 +01001972
Sachin Kamat42d34192013-01-07 10:25:06 +05301973 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001974 if (!sport)
1975 return -ENOMEM;
1976
Shawn Guo22698aa2011-06-25 02:04:34 +08001977 ret = serial_imx_probe_dt(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001978 if (ret > 0)
Shawn Guo22698aa2011-06-25 02:04:34 +08001979 serial_imx_probe_pdata(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001980 else if (ret < 0)
Sachin Kamat42d34192013-01-07 10:25:06 +05301981 return ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001982
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Alexander Shiyanda82f992014-02-22 16:01:33 +04001984 base = devm_ioremap_resource(&pdev->dev, res);
1985 if (IS_ERR(base))
1986 return PTR_ERR(base);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001987
1988 sport->port.dev = &pdev->dev;
1989 sport->port.mapbase = res->start;
1990 sport->port.membase = base;
1991 sport->port.type = PORT_IMX,
1992 sport->port.iotype = UPIO_MEM;
1993 sport->port.irq = platform_get_irq(pdev, 0);
1994 sport->rxirq = platform_get_irq(pdev, 0);
1995 sport->txirq = platform_get_irq(pdev, 1);
1996 sport->rtsirq = platform_get_irq(pdev, 2);
1997 sport->port.fifosize = 32;
1998 sport->port.ops = &imx_pops;
1999 sport->port.flags = UPF_BOOT_AUTOCONF;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002000 init_timer(&sport->timer);
2001 sport->timer.function = imx_timeout;
2002 sport->timer.data = (unsigned long)sport;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002003
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002004 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2005 if (IS_ERR(sport->clk_ipg)) {
2006 ret = PTR_ERR(sport->clk_ipg);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02002007 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05302008 return ret;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002009 }
Sascha Hauer38a41fd2008-07-05 10:02:46 +02002010
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002011 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2012 if (IS_ERR(sport->clk_per)) {
2013 ret = PTR_ERR(sport->clk_per);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02002014 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05302015 return ret;
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002016 }
2017
Sascha Hauer3a9465f2012-03-07 09:31:43 +01002018 sport->port.uartclk = clk_get_rate(sport->clk_per);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02002019
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02002020 /*
2021 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2022 * chips only have one interrupt.
2023 */
2024 if (sport->txirq > 0) {
2025 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
2026 dev_name(&pdev->dev), sport);
2027 if (ret)
2028 return ret;
2029
2030 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
2031 dev_name(&pdev->dev), sport);
2032 if (ret)
2033 return ret;
2034
2035 /* do not use RTS IRQ on IrDA */
2036 if (!USE_IRDA(sport)) {
2037 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
2038 imx_rtsint, 0,
2039 dev_name(&pdev->dev), sport);
2040 if (ret)
2041 return ret;
2042 }
2043 } else {
2044 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
2045 dev_name(&pdev->dev), sport);
2046 if (ret)
2047 return ret;
2048 }
2049
Shawn Guo22698aa2011-06-25 02:04:34 +08002050 imx_ports[sport->port.line] = sport;
Sascha Hauer5b802342006-05-04 14:07:42 +01002051
Richard Zhao0a86a862012-09-18 16:14:58 +08002052 platform_set_drvdata(pdev, sport);
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002053
Alexander Shiyan45af7802014-02-22 16:01:35 +04002054 return uart_add_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055}
2056
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002057static int serial_imx_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058{
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002059 struct imx_port *sport = platform_get_drvdata(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002060
Alexander Shiyan45af7802014-02-22 16:01:35 +04002061 return uart_remove_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062}
2063
Russell King3ae5eae2005-11-09 22:32:44 +00002064static struct platform_driver serial_imx_driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002065 .probe = serial_imx_probe,
2066 .remove = serial_imx_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067
2068 .suspend = serial_imx_suspend,
2069 .resume = serial_imx_resume,
Shawn Guofe6b5402011-06-25 02:04:33 +08002070 .id_table = imx_uart_devtype,
Russell King3ae5eae2005-11-09 22:32:44 +00002071 .driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002072 .name = "imx-uart",
Shawn Guo22698aa2011-06-25 02:04:34 +08002073 .of_match_table = imx_uart_dt_ids,
Russell King3ae5eae2005-11-09 22:32:44 +00002074 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002075};
2076
2077static int __init imx_serial_init(void)
2078{
Fabio Estevamf0fd1b72014-10-27 14:49:40 -02002079 int ret = uart_register_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002080
Linus Torvalds1da177e2005-04-16 15:20:36 -07002081 if (ret)
2082 return ret;
2083
Russell King3ae5eae2005-11-09 22:32:44 +00002084 ret = platform_driver_register(&serial_imx_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085 if (ret != 0)
2086 uart_unregister_driver(&imx_reg);
2087
Uwe Kleine-Königf2278242011-11-22 14:22:55 +01002088 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089}
2090
2091static void __exit imx_serial_exit(void)
2092{
Russell Kingc889b892005-11-21 17:05:21 +00002093 platform_driver_unregister(&serial_imx_driver);
Sascha Hauer4b300c32007-07-17 13:35:46 +01002094 uart_unregister_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095}
2096
2097module_init(imx_serial_init);
2098module_exit(imx_serial_exit);
2099
2100MODULE_AUTHOR("Sascha Hauer");
2101MODULE_DESCRIPTION("IMX generic serial port driver");
2102MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -07002103MODULE_ALIAS("platform:imx-uart");