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gerrit-public.fairphone.software / kernel / msm-4.9 / 9355e59c332858f0e52c62659bb41a7c2bca0a1b / . / arch / mips / include / uapi / asm / inst.h
blob: b39ba25b41ccd2db0ae723ba01c4fab3a82621a6 [file] [log] [blame]
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]1/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]11 */
12#ifndef _UAPI_ASM_INST_H
13#define _UAPI_ASM_INST_H
14
15/*
16 * Major opcodes; before MIPS IV cop1x was called cop3.
17 */
18enum major_op {
19 spec_op, bcond_op, j_op, jal_op,
20 beq_op, bne_op, blez_op, bgtz_op,
21 addi_op, addiu_op, slti_op, sltiu_op,
22 andi_op, ori_op, xori_op, lui_op,
23 cop0_op, cop1_op, cop2_op, cop1x_op,
24 beql_op, bnel_op, blezl_op, bgtzl_op,
25 daddi_op, daddiu_op, ldl_op, ldr_op,
26 spec2_op, jalx_op, mdmx_op, spec3_op,
27 lb_op, lh_op, lwl_op, lw_op,
28 lbu_op, lhu_op, lwr_op, lwu_op,
29 sb_op, sh_op, swl_op, sw_op,
30 sdl_op, sdr_op, swr_op, cache_op,
31 ll_op, lwc1_op, lwc2_op, pref_op,
32 lld_op, ldc1_op, ldc2_op, ld_op,
33 sc_op, swc1_op, swc2_op, major_3b_op,
34 scd_op, sdc1_op, sdc2_op, sd_op
35};
36
37/*
38 * func field of spec opcode.
39 */
40enum spec_op {
41 sll_op, movc_op, srl_op, sra_op,
42 sllv_op, pmon_op, srlv_op, srav_op,
43 jr_op, jalr_op, movz_op, movn_op,
44 syscall_op, break_op, spim_op, sync_op,
45 mfhi_op, mthi_op, mflo_op, mtlo_op,
46 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
47 mult_op, multu_op, div_op, divu_op,
48 dmult_op, dmultu_op, ddiv_op, ddivu_op,
49 add_op, addu_op, sub_op, subu_op,
50 and_op, or_op, xor_op, nor_op,
51 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
52 dadd_op, daddu_op, dsub_op, dsubu_op,
53 tge_op, tgeu_op, tlt_op, tltu_op,
54 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
55 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
56 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
57};
58
59/*
60 * func field of spec2 opcode.
61 */
62enum spec2_op {
63 madd_op, maddu_op, mul_op, spec2_3_unused_op,
64 msub_op, msubu_op, /* more unused ops */
65 clz_op = 0x20, clo_op,
66 dclz_op = 0x24, dclo_op,
67 sdbpp_op = 0x3f
68};
69
70/*
71 * func field of spec3 opcode.
72 */
73enum spec3_op {
74 ext_op, dextm_op, dextu_op, dext_op,
75 ins_op, dinsm_op, dinsu_op, dins_op,
76 lx_op = 0x0a,
77 bshfl_op = 0x20,
78 dbshfl_op = 0x24,
79 rdhwr_op = 0x3b
80};
81
82/*
83 * rt field of bcond opcodes.
84 */
85enum rt_op {
86 bltz_op, bgez_op, bltzl_op, bgezl_op,
87 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
88 tgei_op, tgeiu_op, tlti_op, tltiu_op,
89 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
90 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
91 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
92 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
93 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
94};
95
96/*
97 * rs field of cop opcodes.
98 */
99enum cop_op {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]100 mfc_op = 0x00, dmfc_op = 0x01,
Leonid Yegoshin1ac944002013-11-07 12:48:28 +0000[diff] [blame]101 cfc_op = 0x02, mfhc_op = 0x03,
102 mtc_op = 0x04, dmtc_op = 0x05,
103 ctc_op = 0x06, mthc_op = 0x07,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]104 bc_op = 0x08, cop_op = 0x10,
105 copm_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]106};
107
108/*
109 * rt field of cop.bc_op opcodes
110 */
111enum bcop_op {
112 bcf_op, bct_op, bcfl_op, bctl_op
113};
114
115/*
116 * func field of cop0 coi opcodes.
117 */
118enum cop0_coi_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]119 tlbr_op = 0x01, tlbwi_op = 0x02,
120 tlbwr_op = 0x06, tlbp_op = 0x08,
121 rfe_op = 0x10, eret_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]122};
123
124/*
125 * func field of cop0 com opcodes.
126 */
127enum cop0_com_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]128 tlbr1_op = 0x01, tlbw_op = 0x02,
129 tlbp1_op = 0x08, dctr_op = 0x09,
130 dctw_op = 0x0a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]131};
132
133/*
134 * fmt field of cop1 opcodes.
135 */
136enum cop1_fmt {
137 s_fmt, d_fmt, e_fmt, q_fmt,
138 w_fmt, l_fmt
139};
140
141/*
142 * func field of cop1 instructions using d, s or w format.
143 */
144enum cop1_sdw_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]145 fadd_op = 0x00, fsub_op = 0x01,
146 fmul_op = 0x02, fdiv_op = 0x03,
147 fsqrt_op = 0x04, fabs_op = 0x05,
148 fmov_op = 0x06, fneg_op = 0x07,
149 froundl_op = 0x08, ftruncl_op = 0x09,
150 fceill_op = 0x0a, ffloorl_op = 0x0b,
151 fround_op = 0x0c, ftrunc_op = 0x0d,
152 fceil_op = 0x0e, ffloor_op = 0x0f,
153 fmovc_op = 0x11, fmovz_op = 0x12,
154 fmovn_op = 0x13, frecip_op = 0x15,
155 frsqrt_op = 0x16, fcvts_op = 0x20,
156 fcvtd_op = 0x21, fcvte_op = 0x22,
157 fcvtw_op = 0x24, fcvtl_op = 0x25,
158 fcmp_op = 0x30
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]159};
160
161/*
162 * func field of cop1x opcodes (MIPS IV).
163 */
164enum cop1x_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]165 lwxc1_op = 0x00, ldxc1_op = 0x01,
166 pfetch_op = 0x07, swxc1_op = 0x08,
167 sdxc1_op = 0x09, madd_s_op = 0x20,
168 madd_d_op = 0x21, madd_e_op = 0x22,
169 msub_s_op = 0x28, msub_d_op = 0x29,
170 msub_e_op = 0x2a, nmadd_s_op = 0x30,
171 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
172 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
173 nmsub_e_op = 0x3a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]174};
175
176/*
177 * func field for mad opcodes (MIPS IV).
178 */
179enum mad_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]180 madd_fp_op = 0x08, msub_fp_op = 0x0a,
181 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]182};
183
184/*
185 * func field for special3 lx opcodes (Cavium Octeon).
186 */
187enum lx_func {
188 lwx_op = 0x00,
189 lhx_op = 0x04,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]190 lbux_op = 0x06,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]191 ldx_op = 0x08,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]192 lwux_op = 0x10,
193 lhux_op = 0x14,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]194 lbx_op = 0x16,
195};
196
197/*
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]198 * (microMIPS) Major opcodes.
199 */
200enum mm_major_op {
201 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
202 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
203 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
204 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
205 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
206 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
207 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
208 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
209 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
210 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
211 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
212 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
213 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
214 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
215 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
216 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
217};
218
219/*
220 * (microMIPS) POOL32I minor opcodes.
221 */
222enum mm_32i_minor_op {
223 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
224 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
225 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
226 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
227 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
228 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
229 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
230 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
231 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
232};
233
234/*
235 * (microMIPS) POOL32A minor opcodes.
236 */
237enum mm_32a_minor_op {
238 mm_sll32_op = 0x000,
239 mm_ins_op = 0x00c,
240 mm_ext_op = 0x02c,
241 mm_pool32axf_op = 0x03c,
242 mm_srl32_op = 0x040,
243 mm_sra_op = 0x080,
244 mm_rotr_op = 0x0c0,
245 mm_lwxs_op = 0x118,
246 mm_addu32_op = 0x150,
247 mm_subu32_op = 0x1d0,
248 mm_and_op = 0x250,
249 mm_or32_op = 0x290,
250 mm_xor32_op = 0x310,
251};
252
253/*
254 * (microMIPS) POOL32B functions.
255 */
256enum mm_32b_func {
257 mm_lwc2_func = 0x0,
258 mm_lwp_func = 0x1,
259 mm_ldc2_func = 0x2,
260 mm_ldp_func = 0x4,
261 mm_lwm32_func = 0x5,
262 mm_cache_func = 0x6,
263 mm_ldm_func = 0x7,
264 mm_swc2_func = 0x8,
265 mm_swp_func = 0x9,
266 mm_sdc2_func = 0xa,
267 mm_sdp_func = 0xc,
268 mm_swm32_func = 0xd,
269 mm_sdm_func = 0xf,
270};
271
272/*
273 * (microMIPS) POOL32C functions.
274 */
275enum mm_32c_func {
276 mm_pref_func = 0x2,
277 mm_ll_func = 0x3,
278 mm_swr_func = 0x9,
279 mm_sc_func = 0xb,
280 mm_lwu_func = 0xe,
281};
282
283/*
284 * (microMIPS) POOL32AXF minor opcodes.
285 */
286enum mm_32axf_minor_op {
287 mm_mfc0_op = 0x003,
288 mm_mtc0_op = 0x00b,
289 mm_tlbp_op = 0x00d,
290 mm_jalr_op = 0x03c,
291 mm_tlbr_op = 0x04d,
292 mm_jalrhb_op = 0x07c,
293 mm_tlbwi_op = 0x08d,
294 mm_tlbwr_op = 0x0cd,
295 mm_jalrs_op = 0x13c,
296 mm_jalrshb_op = 0x17c,
297 mm_syscall_op = 0x22d,
298 mm_eret_op = 0x3cd,
299};
300
301/*
302 * (microMIPS) POOL32F minor opcodes.
303 */
304enum mm_32f_minor_op {
305 mm_32f_00_op = 0x00,
306 mm_32f_01_op = 0x01,
307 mm_32f_02_op = 0x02,
308 mm_32f_10_op = 0x08,
309 mm_32f_11_op = 0x09,
310 mm_32f_12_op = 0x0a,
311 mm_32f_20_op = 0x10,
312 mm_32f_30_op = 0x18,
313 mm_32f_40_op = 0x20,
314 mm_32f_41_op = 0x21,
315 mm_32f_42_op = 0x22,
316 mm_32f_50_op = 0x28,
317 mm_32f_51_op = 0x29,
318 mm_32f_52_op = 0x2a,
319 mm_32f_60_op = 0x30,
320 mm_32f_70_op = 0x38,
321 mm_32f_73_op = 0x3b,
322 mm_32f_74_op = 0x3c,
323};
324
325/*
326 * (microMIPS) POOL32F secondary minor opcodes.
327 */
328enum mm_32f_10_minor_op {
329 mm_lwxc1_op = 0x1,
330 mm_swxc1_op,
331 mm_ldxc1_op,
332 mm_sdxc1_op,
333 mm_luxc1_op,
334 mm_suxc1_op,
335};
336
337enum mm_32f_func {
338 mm_lwxc1_func = 0x048,
339 mm_swxc1_func = 0x088,
340 mm_ldxc1_func = 0x0c8,
341 mm_sdxc1_func = 0x108,
342};
343
344/*
345 * (microMIPS) POOL32F secondary minor opcodes.
346 */
347enum mm_32f_40_minor_op {
348 mm_fmovf_op,
349 mm_fmovt_op,
350};
351
352/*
353 * (microMIPS) POOL32F secondary minor opcodes.
354 */
355enum mm_32f_60_minor_op {
356 mm_fadd_op,
357 mm_fsub_op,
358 mm_fmul_op,
359 mm_fdiv_op,
360};
361
362/*
363 * (microMIPS) POOL32F secondary minor opcodes.
364 */
365enum mm_32f_70_minor_op {
366 mm_fmovn_op,
367 mm_fmovz_op,
368};
369
370/*
371 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
372 */
373enum mm_32f_73_minor_op {
374 mm_fmov0_op = 0x01,
375 mm_fcvtl_op = 0x04,
376 mm_movf0_op = 0x05,
377 mm_frsqrt_op = 0x08,
378 mm_ffloorl_op = 0x0c,
379 mm_fabs0_op = 0x0d,
380 mm_fcvtw_op = 0x24,
381 mm_movt0_op = 0x25,
382 mm_fsqrt_op = 0x28,
383 mm_ffloorw_op = 0x2c,
384 mm_fneg0_op = 0x2d,
385 mm_cfc1_op = 0x40,
386 mm_frecip_op = 0x48,
387 mm_fceill_op = 0x4c,
388 mm_fcvtd0_op = 0x4d,
389 mm_ctc1_op = 0x60,
390 mm_fceilw_op = 0x6c,
391 mm_fcvts0_op = 0x6d,
392 mm_mfc1_op = 0x80,
393 mm_fmov1_op = 0x81,
394 mm_movf1_op = 0x85,
395 mm_ftruncl_op = 0x8c,
396 mm_fabs1_op = 0x8d,
397 mm_mtc1_op = 0xa0,
398 mm_movt1_op = 0xa5,
399 mm_ftruncw_op = 0xac,
400 mm_fneg1_op = 0xad,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame^]401 mm_mfhc1_op = 0xc0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]402 mm_froundl_op = 0xcc,
403 mm_fcvtd1_op = 0xcd,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame^]404 mm_mthc1_op = 0xe0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]405 mm_froundw_op = 0xec,
406 mm_fcvts1_op = 0xed,
407};
408
409/*
410 * (microMIPS) POOL16C minor opcodes.
411 */
412enum mm_16c_minor_op {
413 mm_lwm16_op = 0x04,
414 mm_swm16_op = 0x05,
Tony Wudfb033f2013-06-20 12:32:30 +0000[diff] [blame]415 mm_jr16_op = 0x0c,
416 mm_jrc_op = 0x0d,
417 mm_jalr16_op = 0x0e,
418 mm_jalrs16_op = 0x0f,
419 mm_jraddiusp_op = 0x18,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]420};
421
422/*
423 * (microMIPS) POOL16D minor opcodes.
424 */
425enum mm_16d_minor_op {
426 mm_addius5_func,
427 mm_addiusp_func,
428};
429
430/*
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]431 * (MIPS16e) opcodes.
432 */
433enum MIPS16e_ops {
434 MIPS16e_jal_op = 003,
435 MIPS16e_ld_op = 007,
436 MIPS16e_i8_op = 014,
437 MIPS16e_sd_op = 017,
438 MIPS16e_lb_op = 020,
439 MIPS16e_lh_op = 021,
440 MIPS16e_lwsp_op = 022,
441 MIPS16e_lw_op = 023,
442 MIPS16e_lbu_op = 024,
443 MIPS16e_lhu_op = 025,
444 MIPS16e_lwpc_op = 026,
445 MIPS16e_lwu_op = 027,
446 MIPS16e_sb_op = 030,
447 MIPS16e_sh_op = 031,
448 MIPS16e_swsp_op = 032,
449 MIPS16e_sw_op = 033,
450 MIPS16e_rr_op = 035,
451 MIPS16e_extend_op = 036,
452 MIPS16e_i64_op = 037,
453};
454
455enum MIPS16e_i64_func {
456 MIPS16e_ldsp_func,
457 MIPS16e_sdsp_func,
458 MIPS16e_sdrasp_func,
459 MIPS16e_dadjsp_func,
460 MIPS16e_ldpc_func,
461};
462
463enum MIPS16e_rr_func {
464 MIPS16e_jr_func,
465};
466
467enum MIPS6e_i8_func {
468 MIPS16e_swrasp_func = 02,
469};
470
471/*
Leonid Yegoshin102cedc2013-03-25 12:09:02 -0500[diff] [blame]472 * (microMIPS & MIPS16e) NOP instruction.
473 */
474#define MM_NOP16 0x0c00
475
476/*
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]477 * Damn ... bitfields depend from byteorder :-(
478 */
479#ifdef __MIPSEB__
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]480#define BITFIELD_FIELD(field, more) \
481 field; \
482 more
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]483
484#elif defined(__MIPSEL__)
485
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]486#define BITFIELD_FIELD(field, more) \
487 more \
488 field;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]489
490#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
491#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
492#endif
493
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]494struct j_format {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]495 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]496 BITFIELD_FIELD(unsigned int target : 26,
497 ;))
498};
499
500struct i_format { /* signed immediate format */
501 BITFIELD_FIELD(unsigned int opcode : 6,
502 BITFIELD_FIELD(unsigned int rs : 5,
503 BITFIELD_FIELD(unsigned int rt : 5,
504 BITFIELD_FIELD(signed int simmediate : 16,
505 ;))))
506};
507
508struct u_format { /* unsigned immediate format */
509 BITFIELD_FIELD(unsigned int opcode : 6,
510 BITFIELD_FIELD(unsigned int rs : 5,
511 BITFIELD_FIELD(unsigned int rt : 5,
512 BITFIELD_FIELD(unsigned int uimmediate : 16,
513 ;))))
514};
515
516struct c_format { /* Cache (>= R6000) format */
517 BITFIELD_FIELD(unsigned int opcode : 6,
518 BITFIELD_FIELD(unsigned int rs : 5,
519 BITFIELD_FIELD(unsigned int c_op : 3,
520 BITFIELD_FIELD(unsigned int cache : 2,
521 BITFIELD_FIELD(unsigned int simmediate : 16,
522 ;)))))
523};
524
525struct r_format { /* Register format */
526 BITFIELD_FIELD(unsigned int opcode : 6,
527 BITFIELD_FIELD(unsigned int rs : 5,
528 BITFIELD_FIELD(unsigned int rt : 5,
529 BITFIELD_FIELD(unsigned int rd : 5,
530 BITFIELD_FIELD(unsigned int re : 5,
531 BITFIELD_FIELD(unsigned int func : 6,
532 ;))))))
533};
534
535struct p_format { /* Performance counter format (R10000) */
536 BITFIELD_FIELD(unsigned int opcode : 6,
537 BITFIELD_FIELD(unsigned int rs : 5,
538 BITFIELD_FIELD(unsigned int rt : 5,
539 BITFIELD_FIELD(unsigned int rd : 5,
540 BITFIELD_FIELD(unsigned int re : 5,
541 BITFIELD_FIELD(unsigned int func : 6,
542 ;))))))
543};
544
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]545struct f_format { /* FPU register format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]546 BITFIELD_FIELD(unsigned int opcode : 6,
547 BITFIELD_FIELD(unsigned int : 1,
548 BITFIELD_FIELD(unsigned int fmt : 4,
549 BITFIELD_FIELD(unsigned int rt : 5,
550 BITFIELD_FIELD(unsigned int rd : 5,
551 BITFIELD_FIELD(unsigned int re : 5,
552 BITFIELD_FIELD(unsigned int func : 6,
553 ;)))))))
554};
555
556struct ma_format { /* FPU multiply and add format (MIPS IV) */
557 BITFIELD_FIELD(unsigned int opcode : 6,
558 BITFIELD_FIELD(unsigned int fr : 5,
559 BITFIELD_FIELD(unsigned int ft : 5,
560 BITFIELD_FIELD(unsigned int fs : 5,
561 BITFIELD_FIELD(unsigned int fd : 5,
562 BITFIELD_FIELD(unsigned int func : 4,
563 BITFIELD_FIELD(unsigned int fmt : 2,
564 ;)))))))
565};
566
567struct b_format { /* BREAK and SYSCALL */
568 BITFIELD_FIELD(unsigned int opcode : 6,
569 BITFIELD_FIELD(unsigned int code : 20,
570 BITFIELD_FIELD(unsigned int func : 6,
571 ;)))
572};
573
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]574struct ps_format { /* MIPS-3D / paired single format */
575 BITFIELD_FIELD(unsigned int opcode : 6,
576 BITFIELD_FIELD(unsigned int rs : 5,
577 BITFIELD_FIELD(unsigned int ft : 5,
578 BITFIELD_FIELD(unsigned int fs : 5,
579 BITFIELD_FIELD(unsigned int fd : 5,
580 BITFIELD_FIELD(unsigned int func : 6,
581 ;))))))
582};
583
584struct v_format { /* MDMX vector format */
585 BITFIELD_FIELD(unsigned int opcode : 6,
586 BITFIELD_FIELD(unsigned int sel : 4,
587 BITFIELD_FIELD(unsigned int fmt : 1,
588 BITFIELD_FIELD(unsigned int vt : 5,
589 BITFIELD_FIELD(unsigned int vs : 5,
590 BITFIELD_FIELD(unsigned int vd : 5,
591 BITFIELD_FIELD(unsigned int func : 6,
592 ;)))))))
593};
594
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]595/*
596 * microMIPS instruction formats (32-bit length)
597 *
598 * NOTE:
599 * Parenthesis denote whether the format is a microMIPS instruction or
600 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
601 */
602struct fb_format { /* FPU branch format (MIPS32) */
603 BITFIELD_FIELD(unsigned int opcode : 6,
604 BITFIELD_FIELD(unsigned int bc : 5,
605 BITFIELD_FIELD(unsigned int cc : 3,
606 BITFIELD_FIELD(unsigned int flag : 2,
607 BITFIELD_FIELD(signed int simmediate : 16,
608 ;)))))
609};
610
611struct fp0_format { /* FPU multiply and add format (MIPS32) */
612 BITFIELD_FIELD(unsigned int opcode : 6,
613 BITFIELD_FIELD(unsigned int fmt : 5,
614 BITFIELD_FIELD(unsigned int ft : 5,
615 BITFIELD_FIELD(unsigned int fs : 5,
616 BITFIELD_FIELD(unsigned int fd : 5,
617 BITFIELD_FIELD(unsigned int func : 6,
618 ;))))))
619};
620
621struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
622 BITFIELD_FIELD(unsigned int opcode : 6,
623 BITFIELD_FIELD(unsigned int ft : 5,
624 BITFIELD_FIELD(unsigned int fs : 5,
625 BITFIELD_FIELD(unsigned int fd : 5,
626 BITFIELD_FIELD(unsigned int fmt : 3,
627 BITFIELD_FIELD(unsigned int op : 2,
628 BITFIELD_FIELD(unsigned int func : 6,
629 ;)))))))
630};
631
632struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
633 BITFIELD_FIELD(unsigned int opcode : 6,
634 BITFIELD_FIELD(unsigned int op : 5,
635 BITFIELD_FIELD(unsigned int rt : 5,
636 BITFIELD_FIELD(unsigned int fs : 5,
637 BITFIELD_FIELD(unsigned int fd : 5,
638 BITFIELD_FIELD(unsigned int func : 6,
639 ;))))))
640};
641
642struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
643 BITFIELD_FIELD(unsigned int opcode : 6,
644 BITFIELD_FIELD(unsigned int rt : 5,
645 BITFIELD_FIELD(unsigned int fs : 5,
646 BITFIELD_FIELD(unsigned int fmt : 2,
647 BITFIELD_FIELD(unsigned int op : 8,
648 BITFIELD_FIELD(unsigned int func : 6,
649 ;))))))
650};
651
652struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
653 BITFIELD_FIELD(unsigned int opcode : 6,
654 BITFIELD_FIELD(unsigned int fd : 5,
655 BITFIELD_FIELD(unsigned int fs : 5,
656 BITFIELD_FIELD(unsigned int cc : 3,
657 BITFIELD_FIELD(unsigned int zero : 2,
658 BITFIELD_FIELD(unsigned int fmt : 2,
659 BITFIELD_FIELD(unsigned int op : 3,
660 BITFIELD_FIELD(unsigned int func : 6,
661 ;))))))))
662};
663
664struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
665 BITFIELD_FIELD(unsigned int opcode : 6,
666 BITFIELD_FIELD(unsigned int rt : 5,
667 BITFIELD_FIELD(unsigned int fs : 5,
668 BITFIELD_FIELD(unsigned int fmt : 3,
669 BITFIELD_FIELD(unsigned int op : 7,
670 BITFIELD_FIELD(unsigned int func : 6,
671 ;))))))
672};
673
674struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
675 BITFIELD_FIELD(unsigned int opcode : 6,
676 BITFIELD_FIELD(unsigned int rt : 5,
677 BITFIELD_FIELD(unsigned int fs : 5,
678 BITFIELD_FIELD(unsigned int cc : 3,
679 BITFIELD_FIELD(unsigned int fmt : 3,
680 BITFIELD_FIELD(unsigned int cond : 4,
681 BITFIELD_FIELD(unsigned int func : 6,
682 ;)))))))
683};
684
685struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
686 BITFIELD_FIELD(unsigned int opcode : 6,
687 BITFIELD_FIELD(unsigned int index : 5,
688 BITFIELD_FIELD(unsigned int base : 5,
689 BITFIELD_FIELD(unsigned int fd : 5,
690 BITFIELD_FIELD(unsigned int op : 5,
691 BITFIELD_FIELD(unsigned int func : 6,
692 ;))))))
693};
694
695struct fp6_format { /* FPU madd and msub format (MIPS IV) */
696 BITFIELD_FIELD(unsigned int opcode : 6,
697 BITFIELD_FIELD(unsigned int fr : 5,
698 BITFIELD_FIELD(unsigned int ft : 5,
699 BITFIELD_FIELD(unsigned int fs : 5,
700 BITFIELD_FIELD(unsigned int fd : 5,
701 BITFIELD_FIELD(unsigned int func : 6,
702 ;))))))
703};
704
705struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
706 BITFIELD_FIELD(unsigned int opcode : 6,
707 BITFIELD_FIELD(unsigned int ft : 5,
708 BITFIELD_FIELD(unsigned int fs : 5,
709 BITFIELD_FIELD(unsigned int fd : 5,
710 BITFIELD_FIELD(unsigned int fr : 5,
711 BITFIELD_FIELD(unsigned int func : 6,
712 ;))))))
713};
714
715struct mm_i_format { /* Immediate format (microMIPS) */
716 BITFIELD_FIELD(unsigned int opcode : 6,
717 BITFIELD_FIELD(unsigned int rt : 5,
718 BITFIELD_FIELD(unsigned int rs : 5,
719 BITFIELD_FIELD(signed int simmediate : 16,
720 ;))))
721};
722
723struct mm_m_format { /* Multi-word load/store format (microMIPS) */
724 BITFIELD_FIELD(unsigned int opcode : 6,
725 BITFIELD_FIELD(unsigned int rd : 5,
726 BITFIELD_FIELD(unsigned int base : 5,
727 BITFIELD_FIELD(unsigned int func : 4,
728 BITFIELD_FIELD(signed int simmediate : 12,
729 ;)))))
730};
731
732struct mm_x_format { /* Scaled indexed load format (microMIPS) */
733 BITFIELD_FIELD(unsigned int opcode : 6,
734 BITFIELD_FIELD(unsigned int index : 5,
735 BITFIELD_FIELD(unsigned int base : 5,
736 BITFIELD_FIELD(unsigned int rd : 5,
737 BITFIELD_FIELD(unsigned int func : 11,
738 ;)))))
739};
740
741/*
742 * microMIPS instruction formats (16-bit length)
743 */
744struct mm_b0_format { /* Unconditional branch format (microMIPS) */
745 BITFIELD_FIELD(unsigned int opcode : 6,
746 BITFIELD_FIELD(signed int simmediate : 10,
747 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
748 ;)))
749};
750
751struct mm_b1_format { /* Conditional branch format (microMIPS) */
752 BITFIELD_FIELD(unsigned int opcode : 6,
753 BITFIELD_FIELD(unsigned int rs : 3,
754 BITFIELD_FIELD(signed int simmediate : 7,
755 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
756 ;))))
757};
758
759struct mm16_m_format { /* Multi-word load/store format */
760 BITFIELD_FIELD(unsigned int opcode : 6,
761 BITFIELD_FIELD(unsigned int func : 4,
762 BITFIELD_FIELD(unsigned int rlist : 2,
763 BITFIELD_FIELD(unsigned int imm : 4,
764 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
765 ;)))))
766};
767
768struct mm16_rb_format { /* Signed immediate format */
769 BITFIELD_FIELD(unsigned int opcode : 6,
770 BITFIELD_FIELD(unsigned int rt : 3,
771 BITFIELD_FIELD(unsigned int base : 3,
772 BITFIELD_FIELD(signed int simmediate : 4,
773 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
774 ;)))))
775};
776
777struct mm16_r3_format { /* Load from global pointer format */
778 BITFIELD_FIELD(unsigned int opcode : 6,
779 BITFIELD_FIELD(unsigned int rt : 3,
780 BITFIELD_FIELD(signed int simmediate : 7,
781 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
782 ;))))
783};
784
785struct mm16_r5_format { /* Load/store from stack pointer format */
786 BITFIELD_FIELD(unsigned int opcode : 6,
787 BITFIELD_FIELD(unsigned int rt : 5,
788 BITFIELD_FIELD(signed int simmediate : 5,
789 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
790 ;))))
791};
792
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]793/*
794 * MIPS16e instruction formats (16-bit length)
795 */
796struct m16e_rr {
797 BITFIELD_FIELD(unsigned int opcode : 5,
798 BITFIELD_FIELD(unsigned int rx : 3,
799 BITFIELD_FIELD(unsigned int nd : 1,
800 BITFIELD_FIELD(unsigned int l : 1,
801 BITFIELD_FIELD(unsigned int ra : 1,
802 BITFIELD_FIELD(unsigned int func : 5,
803 ;))))))
804};
805
806struct m16e_jal {
807 BITFIELD_FIELD(unsigned int opcode : 5,
808 BITFIELD_FIELD(unsigned int x : 1,
809 BITFIELD_FIELD(unsigned int imm20_16 : 5,
810 BITFIELD_FIELD(signed int imm25_21 : 5,
811 ;))))
812};
813
814struct m16e_i64 {
815 BITFIELD_FIELD(unsigned int opcode : 5,
816 BITFIELD_FIELD(unsigned int func : 3,
817 BITFIELD_FIELD(unsigned int imm : 8,
818 ;)))
819};
820
821struct m16e_ri64 {
822 BITFIELD_FIELD(unsigned int opcode : 5,
823 BITFIELD_FIELD(unsigned int func : 3,
824 BITFIELD_FIELD(unsigned int ry : 3,
825 BITFIELD_FIELD(unsigned int imm : 5,
826 ;))))
827};
828
829struct m16e_ri {
830 BITFIELD_FIELD(unsigned int opcode : 5,
831 BITFIELD_FIELD(unsigned int rx : 3,
832 BITFIELD_FIELD(unsigned int imm : 8,
833 ;)))
834};
835
836struct m16e_rri {
837 BITFIELD_FIELD(unsigned int opcode : 5,
838 BITFIELD_FIELD(unsigned int rx : 3,
839 BITFIELD_FIELD(unsigned int ry : 3,
840 BITFIELD_FIELD(unsigned int imm : 5,
841 ;))))
842};
843
844struct m16e_i8 {
845 BITFIELD_FIELD(unsigned int opcode : 5,
846 BITFIELD_FIELD(unsigned int func : 3,
847 BITFIELD_FIELD(unsigned int imm : 8,
848 ;)))
849};
850
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]851union mips_instruction {
852 unsigned int word;
853 unsigned short halfword[2];
854 unsigned char byte[4];
855 struct j_format j_format;
856 struct i_format i_format;
857 struct u_format u_format;
858 struct c_format c_format;
859 struct r_format r_format;
860 struct p_format p_format;
861 struct f_format f_format;
862 struct ma_format ma_format;
863 struct b_format b_format;
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]864 struct ps_format ps_format;
865 struct v_format v_format;
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]866 struct fb_format fb_format;
867 struct fp0_format fp0_format;
868 struct mm_fp0_format mm_fp0_format;
869 struct fp1_format fp1_format;
870 struct mm_fp1_format mm_fp1_format;
871 struct mm_fp2_format mm_fp2_format;
872 struct mm_fp3_format mm_fp3_format;
873 struct mm_fp4_format mm_fp4_format;
874 struct mm_fp5_format mm_fp5_format;
875 struct fp6_format fp6_format;
876 struct mm_fp6_format mm_fp6_format;
877 struct mm_i_format mm_i_format;
878 struct mm_m_format mm_m_format;
879 struct mm_x_format mm_x_format;
880 struct mm_b0_format mm_b0_format;
881 struct mm_b1_format mm_b1_format;
882 struct mm16_m_format mm16_m_format ;
883 struct mm16_rb_format mm16_rb_format;
884 struct mm16_r3_format mm16_r3_format;
885 struct mm16_r5_format mm16_r5_format;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]886};
887
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]888union mips16e_instruction {
889 unsigned int full : 16;
890 struct m16e_rr rr;
891 struct m16e_jal jal;
892 struct m16e_i64 i64;
893 struct m16e_ri64 ri64;
894 struct m16e_ri ri;
895 struct m16e_rri rri;
896 struct m16e_i8 i8;
897};
898
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]899#endif /* _UAPI_ASM_INST_H */