Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1 | /* |
John Gregor | 87427da | 2007-06-11 10:21:14 -0700 | [diff] [blame] | 2 | * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
| 4 | * |
| 5 | * This software is available to you under a choice of one of two |
| 6 | * licenses. You may choose to be licensed under the terms of the GNU |
| 7 | * General Public License (GPL) Version 2, available from the file |
| 8 | * COPYING in the main directory of this source tree, or the |
| 9 | * OpenIB.org BSD license below: |
| 10 | * |
| 11 | * Redistribution and use in source and binary forms, with or |
| 12 | * without modification, are permitted provided that the following |
| 13 | * conditions are met: |
| 14 | * |
| 15 | * - Redistributions of source code must retain the above |
| 16 | * copyright notice, this list of conditions and the following |
| 17 | * disclaimer. |
| 18 | * |
| 19 | * - Redistributions in binary form must reproduce the above |
| 20 | * copyright notice, this list of conditions and the following |
| 21 | * disclaimer in the documentation and/or other materials |
| 22 | * provided with the distribution. |
| 23 | * |
| 24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 31 | * SOFTWARE. |
| 32 | */ |
| 33 | /* |
| 34 | * This file contains all of the code that is specific to the |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 35 | * InfiniPath PCIe chip. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 36 | */ |
| 37 | |
| 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/delay.h> |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 41 | #include <rdma/ib_verbs.h> |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 42 | |
| 43 | #include "ipath_kernel.h" |
| 44 | #include "ipath_registers.h" |
| 45 | |
Bryan O'Sullivan | f5408ac | 2007-03-15 14:45:09 -0700 | [diff] [blame] | 46 | static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64); |
| 47 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 48 | /* |
| 49 | * This file contains all the chip-specific register information and |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 50 | * access functions for the QLogic InfiniPath PCI-Express chip. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 51 | * |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 52 | * This lists the InfiniPath registers, in the actual chip layout. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 53 | * This structure should never be directly accessed. |
| 54 | */ |
| 55 | struct _infinipath_do_not_use_kernel_regs { |
| 56 | unsigned long long Revision; |
| 57 | unsigned long long Control; |
| 58 | unsigned long long PageAlign; |
| 59 | unsigned long long PortCnt; |
| 60 | unsigned long long DebugPortSelect; |
| 61 | unsigned long long Reserved0; |
| 62 | unsigned long long SendRegBase; |
| 63 | unsigned long long UserRegBase; |
| 64 | unsigned long long CounterRegBase; |
| 65 | unsigned long long Scratch; |
| 66 | unsigned long long Reserved1; |
| 67 | unsigned long long Reserved2; |
| 68 | unsigned long long IntBlocked; |
| 69 | unsigned long long IntMask; |
| 70 | unsigned long long IntStatus; |
| 71 | unsigned long long IntClear; |
| 72 | unsigned long long ErrorMask; |
| 73 | unsigned long long ErrorStatus; |
| 74 | unsigned long long ErrorClear; |
| 75 | unsigned long long HwErrMask; |
| 76 | unsigned long long HwErrStatus; |
| 77 | unsigned long long HwErrClear; |
| 78 | unsigned long long HwDiagCtrl; |
| 79 | unsigned long long MDIO; |
| 80 | unsigned long long IBCStatus; |
| 81 | unsigned long long IBCCtrl; |
| 82 | unsigned long long ExtStatus; |
| 83 | unsigned long long ExtCtrl; |
| 84 | unsigned long long GPIOOut; |
| 85 | unsigned long long GPIOMask; |
| 86 | unsigned long long GPIOStatus; |
| 87 | unsigned long long GPIOClear; |
| 88 | unsigned long long RcvCtrl; |
| 89 | unsigned long long RcvBTHQP; |
| 90 | unsigned long long RcvHdrSize; |
| 91 | unsigned long long RcvHdrCnt; |
| 92 | unsigned long long RcvHdrEntSize; |
| 93 | unsigned long long RcvTIDBase; |
| 94 | unsigned long long RcvTIDCnt; |
| 95 | unsigned long long RcvEgrBase; |
| 96 | unsigned long long RcvEgrCnt; |
| 97 | unsigned long long RcvBufBase; |
| 98 | unsigned long long RcvBufSize; |
| 99 | unsigned long long RxIntMemBase; |
| 100 | unsigned long long RxIntMemSize; |
| 101 | unsigned long long RcvPartitionKey; |
| 102 | unsigned long long Reserved3; |
| 103 | unsigned long long RcvPktLEDCnt; |
| 104 | unsigned long long Reserved4[8]; |
| 105 | unsigned long long SendCtrl; |
| 106 | unsigned long long SendPIOBufBase; |
| 107 | unsigned long long SendPIOSize; |
| 108 | unsigned long long SendPIOBufCnt; |
| 109 | unsigned long long SendPIOAvailAddr; |
| 110 | unsigned long long TxIntMemBase; |
| 111 | unsigned long long TxIntMemSize; |
| 112 | unsigned long long Reserved5; |
| 113 | unsigned long long PCIeRBufTestReg0; |
| 114 | unsigned long long PCIeRBufTestReg1; |
| 115 | unsigned long long Reserved51[6]; |
| 116 | unsigned long long SendBufferError; |
| 117 | unsigned long long SendBufferErrorCONT1; |
| 118 | unsigned long long Reserved6SBE[6]; |
| 119 | unsigned long long RcvHdrAddr0; |
| 120 | unsigned long long RcvHdrAddr1; |
| 121 | unsigned long long RcvHdrAddr2; |
| 122 | unsigned long long RcvHdrAddr3; |
| 123 | unsigned long long RcvHdrAddr4; |
| 124 | unsigned long long Reserved7RHA[11]; |
| 125 | unsigned long long RcvHdrTailAddr0; |
| 126 | unsigned long long RcvHdrTailAddr1; |
| 127 | unsigned long long RcvHdrTailAddr2; |
| 128 | unsigned long long RcvHdrTailAddr3; |
| 129 | unsigned long long RcvHdrTailAddr4; |
| 130 | unsigned long long Reserved8RHTA[11]; |
| 131 | unsigned long long Reserved9SW[8]; |
| 132 | unsigned long long SerdesConfig0; |
| 133 | unsigned long long SerdesConfig1; |
| 134 | unsigned long long SerdesStatus; |
| 135 | unsigned long long XGXSConfig; |
| 136 | unsigned long long IBPLLCfg; |
| 137 | unsigned long long Reserved10SW2[3]; |
| 138 | unsigned long long PCIEQ0SerdesConfig0; |
| 139 | unsigned long long PCIEQ0SerdesConfig1; |
| 140 | unsigned long long PCIEQ0SerdesStatus; |
| 141 | unsigned long long Reserved11; |
| 142 | unsigned long long PCIEQ1SerdesConfig0; |
| 143 | unsigned long long PCIEQ1SerdesConfig1; |
| 144 | unsigned long long PCIEQ1SerdesStatus; |
| 145 | unsigned long long Reserved12; |
| 146 | }; |
| 147 | |
Ralph Campbell | 3029fcc | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 148 | struct _infinipath_do_not_use_counters { |
| 149 | __u64 LBIntCnt; |
| 150 | __u64 LBFlowStallCnt; |
| 151 | __u64 Reserved1; |
| 152 | __u64 TxUnsupVLErrCnt; |
| 153 | __u64 TxDataPktCnt; |
| 154 | __u64 TxFlowPktCnt; |
| 155 | __u64 TxDwordCnt; |
| 156 | __u64 TxLenErrCnt; |
| 157 | __u64 TxMaxMinLenErrCnt; |
| 158 | __u64 TxUnderrunCnt; |
| 159 | __u64 TxFlowStallCnt; |
| 160 | __u64 TxDroppedPktCnt; |
| 161 | __u64 RxDroppedPktCnt; |
| 162 | __u64 RxDataPktCnt; |
| 163 | __u64 RxFlowPktCnt; |
| 164 | __u64 RxDwordCnt; |
| 165 | __u64 RxLenErrCnt; |
| 166 | __u64 RxMaxMinLenErrCnt; |
| 167 | __u64 RxICRCErrCnt; |
| 168 | __u64 RxVCRCErrCnt; |
| 169 | __u64 RxFlowCtrlErrCnt; |
| 170 | __u64 RxBadFormatCnt; |
| 171 | __u64 RxLinkProblemCnt; |
| 172 | __u64 RxEBPCnt; |
| 173 | __u64 RxLPCRCErrCnt; |
| 174 | __u64 RxBufOvflCnt; |
| 175 | __u64 RxTIDFullErrCnt; |
| 176 | __u64 RxTIDValidErrCnt; |
| 177 | __u64 RxPKeyMismatchCnt; |
| 178 | __u64 RxP0HdrEgrOvflCnt; |
| 179 | __u64 RxP1HdrEgrOvflCnt; |
| 180 | __u64 RxP2HdrEgrOvflCnt; |
| 181 | __u64 RxP3HdrEgrOvflCnt; |
| 182 | __u64 RxP4HdrEgrOvflCnt; |
| 183 | __u64 RxP5HdrEgrOvflCnt; |
| 184 | __u64 RxP6HdrEgrOvflCnt; |
| 185 | __u64 RxP7HdrEgrOvflCnt; |
| 186 | __u64 RxP8HdrEgrOvflCnt; |
| 187 | __u64 Reserved6; |
| 188 | __u64 Reserved7; |
| 189 | __u64 IBStatusChangeCnt; |
| 190 | __u64 IBLinkErrRecoveryCnt; |
| 191 | __u64 IBLinkDownedCnt; |
| 192 | __u64 IBSymbolErrCnt; |
| 193 | }; |
| 194 | |
| 195 | #define IPATH_KREG_OFFSET(field) (offsetof( \ |
| 196 | struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64)) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 197 | #define IPATH_CREG_OFFSET(field) (offsetof( \ |
Ralph Campbell | 3029fcc | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 198 | struct _infinipath_do_not_use_counters, field) / sizeof(u64)) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 199 | |
| 200 | static const struct ipath_kregs ipath_pe_kregs = { |
| 201 | .kr_control = IPATH_KREG_OFFSET(Control), |
| 202 | .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase), |
| 203 | .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect), |
| 204 | .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear), |
| 205 | .kr_errormask = IPATH_KREG_OFFSET(ErrorMask), |
| 206 | .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus), |
| 207 | .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl), |
| 208 | .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus), |
| 209 | .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear), |
| 210 | .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask), |
| 211 | .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut), |
| 212 | .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus), |
| 213 | .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl), |
| 214 | .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear), |
| 215 | .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask), |
| 216 | .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus), |
| 217 | .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl), |
| 218 | .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus), |
| 219 | .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked), |
| 220 | .kr_intclear = IPATH_KREG_OFFSET(IntClear), |
| 221 | .kr_intmask = IPATH_KREG_OFFSET(IntMask), |
| 222 | .kr_intstatus = IPATH_KREG_OFFSET(IntStatus), |
| 223 | .kr_mdio = IPATH_KREG_OFFSET(MDIO), |
| 224 | .kr_pagealign = IPATH_KREG_OFFSET(PageAlign), |
| 225 | .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey), |
| 226 | .kr_portcnt = IPATH_KREG_OFFSET(PortCnt), |
| 227 | .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP), |
| 228 | .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase), |
| 229 | .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize), |
| 230 | .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl), |
| 231 | .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase), |
| 232 | .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt), |
| 233 | .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt), |
| 234 | .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize), |
| 235 | .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize), |
| 236 | .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase), |
| 237 | .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize), |
| 238 | .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase), |
| 239 | .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt), |
| 240 | .kr_revision = IPATH_KREG_OFFSET(Revision), |
| 241 | .kr_scratch = IPATH_KREG_OFFSET(Scratch), |
| 242 | .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError), |
| 243 | .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl), |
| 244 | .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr), |
| 245 | .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase), |
| 246 | .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt), |
| 247 | .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize), |
| 248 | .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase), |
| 249 | .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase), |
| 250 | .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize), |
| 251 | .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase), |
| 252 | .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0), |
| 253 | .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1), |
| 254 | .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus), |
| 255 | .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig), |
| 256 | .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg), |
| 257 | |
| 258 | /* |
Bryan O'Sullivan | c8c6f5d | 2007-03-15 14:45:01 -0700 | [diff] [blame] | 259 | * These should not be used directly via ipath_write_kreg64(), |
| 260 | * use them with ipath_write_kreg64_port(), |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 261 | */ |
| 262 | .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0), |
| 263 | .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0), |
| 264 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 265 | /* The rcvpktled register controls one of the debug port signals, so |
| 266 | * a packet activity LED can be connected to it. */ |
| 267 | .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt), |
| 268 | .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0), |
| 269 | .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1), |
| 270 | .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0), |
| 271 | .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1), |
| 272 | .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus), |
| 273 | .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0), |
| 274 | .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1), |
| 275 | .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus) |
| 276 | }; |
| 277 | |
| 278 | static const struct ipath_cregs ipath_pe_cregs = { |
| 279 | .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt), |
| 280 | .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt), |
| 281 | .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt), |
| 282 | .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt), |
| 283 | .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt), |
| 284 | .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt), |
| 285 | .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt), |
| 286 | .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt), |
| 287 | .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt), |
| 288 | .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt), |
| 289 | .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt), |
| 290 | .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt), |
| 291 | .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt), |
| 292 | .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt), |
| 293 | .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt), |
| 294 | .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt), |
| 295 | .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt), |
| 296 | .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt), |
| 297 | .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt), |
| 298 | .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt), |
| 299 | .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt), |
| 300 | .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt), |
| 301 | .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt), |
| 302 | .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt), |
| 303 | .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt), |
| 304 | .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt), |
| 305 | .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt), |
| 306 | .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt), |
| 307 | .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt), |
| 308 | .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt), |
| 309 | .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt), |
| 310 | .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt), |
| 311 | .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt) |
| 312 | }; |
| 313 | |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 314 | /* kr_control bits */ |
| 315 | #define INFINIPATH_C_RESET 1U |
| 316 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 317 | /* kr_intstatus, kr_intclear, kr_intmask bits */ |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 318 | #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1) |
Ralph Campbell | 9355fb6 | 2008-04-16 21:09:29 -0700 | [diff] [blame^] | 319 | #define INFINIPATH_I_RCVURG_SHIFT 0 |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 320 | #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1) |
Ralph Campbell | 9355fb6 | 2008-04-16 21:09:29 -0700 | [diff] [blame^] | 321 | #define INFINIPATH_I_RCVAVAIL_SHIFT 12 |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 322 | |
| 323 | /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ |
| 324 | #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL |
| 325 | #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0 |
| 326 | #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL |
| 327 | #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL |
| 328 | #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL |
| 329 | #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL |
| 330 | #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL |
| 331 | #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL |
| 332 | #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL |
| 333 | #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL |
| 334 | #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL |
| 335 | #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL |
| 336 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 337 | #define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf |
| 338 | #define IBA6120_IBCS_LINKSTATE_SHIFT 4 |
| 339 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 340 | /* kr_extstatus bits */ |
| 341 | #define INFINIPATH_EXTS_FREQSEL 0x2 |
| 342 | #define INFINIPATH_EXTS_SERDESSEL 0x4 |
| 343 | #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000 |
| 344 | #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000 |
| 345 | |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 346 | /* kr_xgxsconfig bits */ |
| 347 | #define INFINIPATH_XGXS_RESET 0x5ULL |
| 348 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 349 | #define _IPATH_GPIO_SDA_NUM 1 |
| 350 | #define _IPATH_GPIO_SCL_NUM 0 |
| 351 | |
| 352 | #define IPATH_GPIO_SDA (1ULL << \ |
| 353 | (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) |
| 354 | #define IPATH_GPIO_SCL (1ULL << \ |
| 355 | (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) |
| 356 | |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 357 | #define INFINIPATH_RT_BUFSIZE_MASK 0xe0000000ULL |
| 358 | #define INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid) \ |
| 359 | ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) >> 29) + 11 - 1) |
| 360 | #define INFINIPATH_RT_BUFSIZE(tid) (1 << INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid)) |
| 361 | #define INFINIPATH_RT_IS_VALID(tid) \ |
| 362 | (((tid) & INFINIPATH_RT_BUFSIZE_MASK) && \ |
| 363 | ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) != INFINIPATH_RT_BUFSIZE_MASK))) |
| 364 | #define INFINIPATH_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */ |
| 365 | #define INFINIPATH_RT_ADDR_SHIFT 10 |
| 366 | |
Dave Olson | d827486 | 2007-12-21 01:50:59 -0800 | [diff] [blame] | 367 | #define INFINIPATH_R_INTRAVAIL_SHIFT 16 |
| 368 | #define INFINIPATH_R_TAILUPD_SHIFT 31 |
| 369 | |
Bryan O'Sullivan | 8d588f8 | 2006-09-28 09:00:08 -0700 | [diff] [blame] | 370 | /* 6120 specific hardware errors... */ |
| 371 | static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = { |
| 372 | INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"), |
| 373 | INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"), |
| 374 | /* |
| 375 | * In practice, it's unlikely wthat we'll see PCIe PLL, or bus |
| 376 | * parity or memory parity error failures, because most likely we |
| 377 | * won't be able to talk to the core of the chip. Nonetheless, we |
| 378 | * might see them, if they are in parts of the PCIe core that aren't |
| 379 | * essential. |
| 380 | */ |
| 381 | INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"), |
| 382 | INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"), |
| 383 | INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"), |
| 384 | INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"), |
| 385 | INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"), |
| 386 | INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"), |
| 387 | INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"), |
| 388 | }; |
| 389 | |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 390 | #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \ |
| 391 | INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \ |
| 392 | << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 393 | #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \ |
| 394 | << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 395 | |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 396 | static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *, |
| 397 | u32, unsigned long); |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 398 | |
Dave Olson | ddb70c8 | 2008-01-08 01:51:46 -0800 | [diff] [blame] | 399 | /* |
| 400 | * On platforms using this chip, and not having ordered WC stores, we |
| 401 | * can get TXE parity errors due to speculative reads to the PIO buffers, |
| 402 | * and this, due to a chip bug can result in (many) false parity error |
| 403 | * reports. So it's a debug print on those, and an info print on systems |
| 404 | * where the speculative reads don't occur. |
| 405 | */ |
| 406 | static void ipath_pe_txe_recover(struct ipath_devdata *dd) |
| 407 | { |
| 408 | if (ipath_unordered_wc()) |
| 409 | ipath_dbg("Recovering from TXE PIO parity error\n"); |
| 410 | else { |
| 411 | ++ipath_stats.sps_txeparity; |
| 412 | dev_info(&dd->pcidev->dev, |
| 413 | "Recovering from TXE PIO parity error\n"); |
| 414 | } |
| 415 | } |
| 416 | |
| 417 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 418 | /** |
| 419 | * ipath_pe_handle_hwerrors - display hardware errors. |
| 420 | * @dd: the infinipath device |
| 421 | * @msg: the output buffer |
| 422 | * @msgl: the size of the output buffer |
| 423 | * |
| 424 | * Use same msg buffer as regular errors to avoid excessive stack |
| 425 | * use. Most hardware errors are catastrophic, but for right now, |
| 426 | * we'll print them and continue. We reuse the same message buffer as |
| 427 | * ipath_handle_errors() to avoid excessive stack usage. |
| 428 | */ |
Roland Dreier | ac2ae4c | 2006-04-19 11:40:12 -0700 | [diff] [blame] | 429 | static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg, |
| 430 | size_t msgl) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 431 | { |
| 432 | ipath_err_t hwerrs; |
| 433 | u32 bits, ctrl; |
| 434 | int isfatal = 0; |
| 435 | char bitsmsg[64]; |
Michael Albaugh | aecd3b5 | 2007-05-17 07:26:28 -0700 | [diff] [blame] | 436 | int log_idx; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 437 | |
| 438 | hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus); |
| 439 | if (!hwerrs) { |
| 440 | /* |
| 441 | * better than printing cofusing messages |
| 442 | * This seems to be related to clearing the crc error, or |
| 443 | * the pll error during init. |
| 444 | */ |
| 445 | ipath_cdbg(VERBOSE, "Called but no hardware errors set\n"); |
| 446 | return; |
| 447 | } else if (hwerrs == ~0ULL) { |
| 448 | ipath_dev_err(dd, "Read of hardware error status failed " |
| 449 | "(all bits set); ignoring\n"); |
| 450 | return; |
| 451 | } |
| 452 | ipath_stats.sps_hwerrs++; |
| 453 | |
| 454 | /* Always clear the error status register, except MEMBISTFAIL, |
| 455 | * regardless of whether we continue or stop using the chip. |
| 456 | * We want that set so we know it failed, even across driver reload. |
| 457 | * We'll still ignore it in the hwerrmask. We do this partly for |
| 458 | * diagnostics, but also for support */ |
| 459 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, |
| 460 | hwerrs&~INFINIPATH_HWE_MEMBISTFAILED); |
| 461 | |
| 462 | hwerrs &= dd->ipath_hwerrmask; |
| 463 | |
Michael Albaugh | aecd3b5 | 2007-05-17 07:26:28 -0700 | [diff] [blame] | 464 | /* We log some errors to EEPROM, check if we have any of those. */ |
| 465 | for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) |
| 466 | if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log) |
| 467 | ipath_inc_eeprom_err(dd, log_idx, 1); |
| 468 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 469 | /* |
| 470 | * make sure we get this much out, unless told to be quiet, |
| 471 | * or it's occurred within the last 5 seconds |
| 472 | */ |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 473 | if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY | |
| 474 | RXE_EAGER_PARITY)) || |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 475 | (ipath_debug & __IPATH_VERBDBG)) |
| 476 | dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx " |
| 477 | "(cleared)\n", (unsigned long long) hwerrs); |
| 478 | dd->ipath_lasthwerror |= hwerrs; |
| 479 | |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 480 | if (hwerrs & ~dd->ipath_hwe_bitsextant) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 481 | ipath_dev_err(dd, "hwerror interrupt with unknown errors " |
| 482 | "%llx set\n", (unsigned long long) |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 483 | (hwerrs & ~dd->ipath_hwe_bitsextant)); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 484 | |
| 485 | ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control); |
Ralph Campbell | c1702be | 2008-04-16 21:01:14 -0700 | [diff] [blame] | 486 | if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) { |
Bryan O'Sullivan | 89d1e09 | 2006-09-28 09:00:18 -0700 | [diff] [blame] | 487 | /* |
| 488 | * parity errors in send memory are recoverable, |
| 489 | * just cancel the send (if indicated in * sendbuffererror), |
| 490 | * count the occurrence, unfreeze (if no other handled |
| 491 | * hardware error bits are set), and continue. They can |
| 492 | * occur if a processor speculative read is done to the PIO |
| 493 | * buffer while we are sending a packet, for example. |
| 494 | */ |
Dave Olson | ddb70c8 | 2008-01-08 01:51:46 -0800 | [diff] [blame] | 495 | if (hwerrs & TXE_PIO_PARITY) { |
| 496 | ipath_pe_txe_recover(dd); |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 497 | hwerrs &= ~TXE_PIO_PARITY; |
Dave Olson | ddb70c8 | 2008-01-08 01:51:46 -0800 | [diff] [blame] | 498 | } |
| 499 | if (!hwerrs) { |
Dave Olson | 9380068 | 2007-06-18 14:24:41 -0700 | [diff] [blame] | 500 | static u32 freeze_cnt; |
| 501 | |
| 502 | freeze_cnt++; |
| 503 | ipath_dbg("Clearing freezemode on ignored or recovered " |
| 504 | "hardware error (%u)\n", freeze_cnt); |
Dave Olson | 0f4fc5e | 2007-07-06 12:48:33 -0700 | [diff] [blame] | 505 | ipath_clear_freeze(dd); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 506 | } |
| 507 | } |
| 508 | |
| 509 | *msg = '\0'; |
| 510 | |
| 511 | if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) { |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 512 | strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]", |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 513 | msgl); |
| 514 | /* ignore from now on, so disable until driver reloaded */ |
| 515 | *dd->ipath_statusp |= IPATH_STATUS_HWERROR; |
| 516 | dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED; |
| 517 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, |
| 518 | dd->ipath_hwerrmask); |
| 519 | } |
Bryan O'Sullivan | 8d588f8 | 2006-09-28 09:00:08 -0700 | [diff] [blame] | 520 | |
| 521 | ipath_format_hwerrors(hwerrs, |
| 522 | ipath_6120_hwerror_msgs, |
| 523 | sizeof(ipath_6120_hwerror_msgs)/ |
| 524 | sizeof(ipath_6120_hwerror_msgs[0]), |
| 525 | msg, msgl); |
| 526 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 527 | if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK |
| 528 | << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) { |
| 529 | bits = (u32) ((hwerrs >> |
| 530 | INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) & |
| 531 | INFINIPATH_HWE_PCIEMEMPARITYERR_MASK); |
| 532 | snprintf(bitsmsg, sizeof bitsmsg, |
| 533 | "[PCIe Mem Parity Errs %x] ", bits); |
| 534 | strlcat(msg, bitsmsg, msgl); |
| 535 | } |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 536 | |
| 537 | #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ |
| 538 | INFINIPATH_HWE_COREPLL_RFSLIP ) |
| 539 | |
| 540 | if (hwerrs & _IPATH_PLL_FAIL) { |
| 541 | snprintf(bitsmsg, sizeof bitsmsg, |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 542 | "[PLL failed (%llx), InfiniPath hardware unusable]", |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 543 | (unsigned long long) hwerrs & _IPATH_PLL_FAIL); |
| 544 | strlcat(msg, bitsmsg, msgl); |
| 545 | /* ignore from now on, so disable until driver reloaded */ |
| 546 | dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL); |
| 547 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, |
| 548 | dd->ipath_hwerrmask); |
| 549 | } |
| 550 | |
| 551 | if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) { |
| 552 | /* |
Dave Olson | 9e2ef36b | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 553 | * If it occurs, it is left masked since the external |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 554 | * interface is unused |
| 555 | */ |
| 556 | dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED; |
| 557 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, |
| 558 | dd->ipath_hwerrmask); |
| 559 | } |
| 560 | |
Bryan O'Sullivan | f5408ac | 2007-03-15 14:45:09 -0700 | [diff] [blame] | 561 | if (*msg) |
| 562 | ipath_dev_err(dd, "%s hardware error\n", msg); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 563 | if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) { |
| 564 | /* |
| 565 | * for /sys status file ; if no trailing } is copied, we'll |
| 566 | * know it was truncated. |
| 567 | */ |
| 568 | snprintf(dd->ipath_freezemsg, dd->ipath_freezelen, |
| 569 | "{%s}", msg); |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | /** |
| 574 | * ipath_pe_boardname - fill in the board name |
| 575 | * @dd: the infinipath device |
| 576 | * @name: the output buffer |
| 577 | * @namelen: the size of the output buffer |
| 578 | * |
| 579 | * info is based on the board revision register |
| 580 | */ |
| 581 | static int ipath_pe_boardname(struct ipath_devdata *dd, char *name, |
| 582 | size_t namelen) |
| 583 | { |
| 584 | char *n = NULL; |
| 585 | u8 boardrev = dd->ipath_boardrev; |
| 586 | int ret; |
| 587 | |
| 588 | switch (boardrev) { |
| 589 | case 0: |
| 590 | n = "InfiniPath_Emulation"; |
| 591 | break; |
| 592 | case 1: |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 593 | n = "InfiniPath_QLE7140-Bringup"; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 594 | break; |
| 595 | case 2: |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 596 | n = "InfiniPath_QLE7140"; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 597 | break; |
| 598 | case 3: |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 599 | n = "InfiniPath_QMI7140"; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 600 | break; |
| 601 | case 4: |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 602 | n = "InfiniPath_QEM7140"; |
| 603 | break; |
| 604 | case 5: |
| 605 | n = "InfiniPath_QMH7140"; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 606 | break; |
Bryan O'Sullivan | bf3258e | 2006-09-28 09:00:22 -0700 | [diff] [blame] | 607 | case 6: |
| 608 | n = "InfiniPath_QLE7142"; |
| 609 | break; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 610 | default: |
| 611 | ipath_dev_err(dd, |
| 612 | "Don't yet know about board with ID %u\n", |
| 613 | boardrev); |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 614 | snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u", |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 615 | boardrev); |
| 616 | break; |
| 617 | } |
| 618 | if (n) |
| 619 | snprintf(name, namelen, "%s", n); |
| 620 | |
Bryan O'Sullivan | 8307c28 | 2006-07-01 04:36:13 -0700 | [diff] [blame] | 621 | if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) { |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 622 | ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n", |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 623 | dd->ipath_majrev, dd->ipath_minrev); |
| 624 | ret = 1; |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 625 | } else { |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 626 | ret = 0; |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 627 | if (dd->ipath_minrev >= 2) |
| 628 | dd->ipath_f_put_tid = ipath_pe_put_tid_2; |
| 629 | } |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 630 | |
Ralph Campbell | a18e26a | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 631 | /* |
| 632 | * set here, not in ipath_init_*_funcs because we have to do |
| 633 | * it after we can read chip registers. |
| 634 | */ |
| 635 | dd->ipath_ureg_align = |
| 636 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign); |
| 637 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 638 | return ret; |
| 639 | } |
| 640 | |
| 641 | /** |
| 642 | * ipath_pe_init_hwerrors - enable hardware errors |
| 643 | * @dd: the infinipath device |
| 644 | * |
| 645 | * now that we have finished initializing everything that might reasonably |
| 646 | * cause a hardware error, and cleared those errors bits as they occur, |
| 647 | * we can enable hardware errors in the mask (potentially enabling |
| 648 | * freeze mode), and enable hardware errors as errors (along with |
| 649 | * everything else) in errormask |
| 650 | */ |
Roland Dreier | ac2ae4c | 2006-04-19 11:40:12 -0700 | [diff] [blame] | 651 | static void ipath_pe_init_hwerrors(struct ipath_devdata *dd) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 652 | { |
| 653 | ipath_err_t val; |
| 654 | u64 extsval; |
| 655 | |
| 656 | extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus); |
| 657 | |
| 658 | if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST)) |
| 659 | ipath_dev_err(dd, "MemBIST did not complete!\n"); |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 660 | if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND) |
| 661 | ipath_dbg("MemBIST corrected\n"); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 662 | |
| 663 | val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */ |
| 664 | |
| 665 | if (!dd->ipath_boardrev) // no PLL for Emulator |
| 666 | val &= ~INFINIPATH_HWE_SERDESPLLFAILED; |
| 667 | |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 668 | if (dd->ipath_minrev < 2) { |
| 669 | /* workaround bug 9460 in internal interface bus parity |
| 670 | * checking. Fixed (HW bug 9490) in Rev2. |
| 671 | */ |
| 672 | val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM; |
| 673 | } |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 674 | dd->ipath_hwerrmask = val; |
| 675 | } |
| 676 | |
| 677 | /** |
| 678 | * ipath_pe_bringup_serdes - bring up the serdes |
| 679 | * @dd: the infinipath device |
| 680 | */ |
Roland Dreier | ac2ae4c | 2006-04-19 11:40:12 -0700 | [diff] [blame] | 681 | static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 682 | { |
Roland Dreier | 44f8e3f | 2006-12-12 11:50:20 -0800 | [diff] [blame] | 683 | u64 val, config1, prev_val; |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 684 | int ret = 0; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 685 | |
| 686 | ipath_dbg("Trying to bringup serdes\n"); |
| 687 | |
| 688 | if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) & |
| 689 | INFINIPATH_HWE_SERDESPLLFAILED) { |
| 690 | ipath_dbg("At start, serdes PLL failed bit set " |
| 691 | "in hwerrstatus, clearing and continuing\n"); |
| 692 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, |
| 693 | INFINIPATH_HWE_SERDESPLLFAILED); |
| 694 | } |
| 695 | |
| 696 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); |
| 697 | config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1); |
| 698 | |
| 699 | ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, " |
| 700 | "xgxsconfig %llx\n", (unsigned long long) val, |
| 701 | (unsigned long long) config1, (unsigned long long) |
| 702 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); |
| 703 | |
| 704 | /* |
| 705 | * Force reset on, also set rxdetect enable. Must do before reading |
| 706 | * serdesstatus at least for simulation, or some of the bits in |
| 707 | * serdes status will come back as undefined and cause simulation |
| 708 | * failures |
| 709 | */ |
| 710 | val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN |
| 711 | | INFINIPATH_SERDC0_L1PWR_DN; |
| 712 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); |
| 713 | /* be sure chip saw it */ |
Roland Dreier | 44f8e3f | 2006-12-12 11:50:20 -0800 | [diff] [blame] | 714 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 715 | udelay(5); /* need pll reset set at least for a bit */ |
| 716 | /* |
| 717 | * after PLL is reset, set the per-lane Resets and TxIdle and |
| 718 | * clear the PLL reset and rxdetect (to get falling edge). |
| 719 | * Leave L1PWR bits set (permanently) |
| 720 | */ |
| 721 | val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL |
| 722 | | INFINIPATH_SERDC0_L1PWR_DN); |
| 723 | val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE; |
| 724 | ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets " |
| 725 | "and txidle (%llx)\n", (unsigned long long) val); |
| 726 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); |
| 727 | /* be sure chip saw it */ |
Roland Dreier | 44f8e3f | 2006-12-12 11:50:20 -0800 | [diff] [blame] | 728 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 729 | /* need PLL reset clear for at least 11 usec before lane |
| 730 | * resets cleared; give it a few more to be sure */ |
| 731 | udelay(15); |
| 732 | val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE); |
| 733 | |
| 734 | ipath_cdbg(VERBOSE, "Clearing lane resets and txidle " |
| 735 | "(writing %llx)\n", (unsigned long long) val); |
| 736 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); |
| 737 | /* be sure chip saw it */ |
| 738 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
| 739 | |
| 740 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 741 | prev_val = val; |
Dave Olson | 7387273 | 2008-01-08 23:16:17 -0800 | [diff] [blame] | 742 | if (val & INFINIPATH_XGXS_RESET) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 743 | val &= ~INFINIPATH_XGXS_RESET; |
Bryan O'Sullivan | 30fc5c3 | 2006-08-25 11:24:48 -0700 | [diff] [blame] | 744 | if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) & |
| 745 | INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) { |
| 746 | /* need to compensate for Tx inversion in partner */ |
| 747 | val &= ~(INFINIPATH_XGXS_RX_POL_MASK << |
| 748 | INFINIPATH_XGXS_RX_POL_SHIFT); |
| 749 | val |= dd->ipath_rx_pol_inv << |
| 750 | INFINIPATH_XGXS_RX_POL_SHIFT; |
Bryan O'Sullivan | 30fc5c3 | 2006-08-25 11:24:48 -0700 | [diff] [blame] | 751 | } |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 752 | if (val != prev_val) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 753 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); |
| 754 | |
| 755 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); |
| 756 | |
| 757 | /* clear current and de-emphasis bits */ |
| 758 | config1 &= ~0x0ffffffff00ULL; |
| 759 | /* set current to 20ma */ |
| 760 | config1 |= 0x00000000000ULL; |
| 761 | /* set de-emphasis to -5.68dB */ |
| 762 | config1 |= 0x0cccc000000ULL; |
| 763 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1); |
| 764 | |
| 765 | ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx " |
| 766 | "config1=%llx, sstatus=%llx xgxs=%llx\n", |
| 767 | (unsigned long long) val, (unsigned long long) config1, |
| 768 | (unsigned long long) |
| 769 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus), |
| 770 | (unsigned long long) |
| 771 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); |
| 772 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 773 | return ret; |
| 774 | } |
| 775 | |
| 776 | /** |
| 777 | * ipath_pe_quiet_serdes - set serdes to txidle |
| 778 | * @dd: the infinipath device |
| 779 | * Called when driver is being unloaded |
| 780 | */ |
Roland Dreier | ac2ae4c | 2006-04-19 11:40:12 -0700 | [diff] [blame] | 781 | static void ipath_pe_quiet_serdes(struct ipath_devdata *dd) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 782 | { |
| 783 | u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); |
| 784 | |
| 785 | val |= INFINIPATH_SERDC0_TXIDLE; |
| 786 | ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n", |
| 787 | (unsigned long long) val); |
| 788 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); |
| 789 | } |
| 790 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 791 | static int ipath_pe_intconfig(struct ipath_devdata *dd) |
| 792 | { |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 793 | u32 chiprev; |
| 794 | |
| 795 | /* |
| 796 | * If the chip supports added error indication via GPIO pins, |
| 797 | * enable interrupts on those bits so the interrupt routine |
| 798 | * can count the events. Also set flag so interrupt routine |
| 799 | * can know they are expected. |
| 800 | */ |
| 801 | chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT; |
| 802 | if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) { |
| 803 | /* Rev2+ reports extra errors via internal GPIO pins */ |
| 804 | dd->ipath_flags |= IPATH_GPIO_ERRINTRS; |
Arthur Jones | 8f140b4 | 2007-05-10 12:10:49 -0700 | [diff] [blame] | 805 | dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK; |
| 806 | ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask, |
| 807 | dd->ipath_gpio_mask); |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 808 | } |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 809 | return 0; |
| 810 | } |
| 811 | |
| 812 | /** |
| 813 | * ipath_setup_pe_setextled - set the state of the two external LEDs |
| 814 | * @dd: the infinipath device |
| 815 | * @lst: the L state |
| 816 | * @ltst: the LT state |
| 817 | |
| 818 | * These LEDs indicate the physical and logical state of IB link. |
| 819 | * For this chip (at least with recommended board pinouts), LED1 |
| 820 | * is Yellow (logical state) and LED2 is Green (physical state), |
| 821 | * |
| 822 | * Note: We try to match the Mellanox HCA LED behavior as best |
| 823 | * we can. Green indicates physical link state is OK (something is |
| 824 | * plugged in, and we can train). |
| 825 | * Amber indicates the link is logically up (ACTIVE). |
| 826 | * Mellanox further blinks the amber LED to indicate data packet |
| 827 | * activity, but we have no hardware support for that, so it would |
| 828 | * require waking up every 10-20 msecs and checking the counters |
| 829 | * on the chip, and then turning the LED off if appropriate. That's |
| 830 | * visible overhead, so not something we will do. |
| 831 | * |
| 832 | */ |
| 833 | static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst, |
| 834 | u64 ltst) |
| 835 | { |
| 836 | u64 extctl; |
Michael Albaugh | 17b2eb9 | 2007-05-17 07:05:04 -0700 | [diff] [blame] | 837 | unsigned long flags = 0; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 838 | |
| 839 | /* the diags use the LED to indicate diag info, so we leave |
| 840 | * the external LED alone when the diags are running */ |
| 841 | if (ipath_diag_inuse) |
| 842 | return; |
| 843 | |
Michael Albaugh | 82466f0 | 2007-05-16 15:45:09 -0700 | [diff] [blame] | 844 | /* Allow override of LED display for, e.g. Locating system in rack */ |
| 845 | if (dd->ipath_led_override) { |
| 846 | ltst = (dd->ipath_led_override & IPATH_LED_PHYS) |
| 847 | ? INFINIPATH_IBCS_LT_STATE_LINKUP |
| 848 | : INFINIPATH_IBCS_LT_STATE_DISABLED; |
| 849 | lst = (dd->ipath_led_override & IPATH_LED_LOG) |
| 850 | ? INFINIPATH_IBCS_L_STATE_ACTIVE |
| 851 | : INFINIPATH_IBCS_L_STATE_DOWN; |
| 852 | } |
| 853 | |
Michael Albaugh | 17b2eb9 | 2007-05-17 07:05:04 -0700 | [diff] [blame] | 854 | spin_lock_irqsave(&dd->ipath_gpio_lock, flags); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 855 | extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON | |
| 856 | INFINIPATH_EXTC_LED2PRIPORT_ON); |
| 857 | |
Arthur Jones | b848882 | 2008-04-16 21:01:13 -0700 | [diff] [blame] | 858 | if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 859 | extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON; |
| 860 | if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE) |
| 861 | extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON; |
| 862 | dd->ipath_extctrl = extctl; |
| 863 | ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl); |
Michael Albaugh | 17b2eb9 | 2007-05-17 07:05:04 -0700 | [diff] [blame] | 864 | spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 865 | } |
| 866 | |
| 867 | /** |
| 868 | * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff |
| 869 | * @dd: the infinipath device |
| 870 | * |
| 871 | * This is called during driver unload. |
| 872 | * We do the pci_disable_msi here, not in generic code, because it |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 873 | * isn't used for the HT chips. If we do end up needing pci_enable_msi |
| 874 | * at some point in the future for HT, we'll move the call back |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 875 | * into the main init_one code. |
| 876 | */ |
| 877 | static void ipath_setup_pe_cleanup(struct ipath_devdata *dd) |
| 878 | { |
| 879 | dd->ipath_msi_lo = 0; /* just in case unload fails */ |
| 880 | pci_disable_msi(dd->pcidev); |
| 881 | } |
| 882 | |
Arthur Jones | 6ca2abf | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 883 | static void ipath_6120_pcie_params(struct ipath_devdata *dd) |
| 884 | { |
| 885 | u16 linkstat, speed; |
| 886 | int pos; |
| 887 | |
| 888 | pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP); |
| 889 | if (!pos) { |
| 890 | ipath_dev_err(dd, "Can't find PCI Express capability!\n"); |
| 891 | goto bail; |
| 892 | } |
| 893 | |
| 894 | pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA, |
| 895 | &linkstat); |
| 896 | /* |
| 897 | * speed is bits 0-4, linkwidth is bits 4-8 |
| 898 | * no defines for them in headers |
| 899 | */ |
| 900 | speed = linkstat & 0xf; |
| 901 | linkstat >>= 4; |
| 902 | linkstat &= 0x1f; |
| 903 | dd->ipath_lbus_width = linkstat; |
| 904 | |
| 905 | switch (speed) { |
| 906 | case 1: |
| 907 | dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */ |
| 908 | break; |
| 909 | case 2: |
| 910 | dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */ |
| 911 | break; |
| 912 | default: /* not defined, assume gen1 */ |
| 913 | dd->ipath_lbus_speed = 2500; |
| 914 | break; |
| 915 | } |
| 916 | |
| 917 | if (linkstat < 8) |
| 918 | ipath_dev_err(dd, |
| 919 | "PCIe width %u (x8 HCA), performance reduced\n", |
| 920 | linkstat); |
| 921 | else |
| 922 | ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n", |
| 923 | dd->ipath_lbus_speed, linkstat); |
| 924 | |
| 925 | if (speed != 1) |
| 926 | ipath_dev_err(dd, |
| 927 | "PCIe linkspeed %u is incorrect; " |
| 928 | "should be 1 (2500)!\n", speed); |
| 929 | bail: |
| 930 | /* fill in string, even on errors */ |
| 931 | snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info), |
| 932 | "PCIe,%uMHz,x%u\n", |
| 933 | dd->ipath_lbus_speed, |
| 934 | dd->ipath_lbus_width); |
| 935 | |
| 936 | return; |
| 937 | } |
| 938 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 939 | /** |
| 940 | * ipath_setup_pe_config - setup PCIe config related stuff |
| 941 | * @dd: the infinipath device |
| 942 | * @pdev: the PCI device |
| 943 | * |
| 944 | * The pci_enable_msi() call will fail on systems with MSI quirks |
| 945 | * such as those with AMD8131, even if the device of interest is not |
| 946 | * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed |
| 947 | * late in 2.6.16). |
| 948 | * All that can be done is to edit the kernel source to remove the quirk |
| 949 | * check until that is fixed. |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 950 | * We do not need to call enable_msi() for our HyperTransport chip, |
| 951 | * even though it uses MSI, and we want to avoid the quirk warning, so |
| 952 | * So we call enable_msi only for PCIe. If we do end up needing |
| 953 | * pci_enable_msi at some point in the future for HT, we'll move the |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 954 | * call back into the main init_one code. |
| 955 | * We save the msi lo and hi values, so we can restore them after |
| 956 | * chip reset (the kernel PCI infrastructure doesn't yet handle that |
| 957 | * correctly). |
| 958 | */ |
| 959 | static int ipath_setup_pe_config(struct ipath_devdata *dd, |
| 960 | struct pci_dev *pdev) |
| 961 | { |
| 962 | int pos, ret; |
| 963 | |
| 964 | dd->ipath_msi_lo = 0; /* used as a flag during reset processing */ |
| 965 | ret = pci_enable_msi(dd->pcidev); |
| 966 | if (ret) |
| 967 | ipath_dev_err(dd, "pci_enable_msi failed: %d, " |
| 968 | "interrupts may not work\n", ret); |
| 969 | /* continue even if it fails, we may still be OK... */ |
Roland Dreier | 0a1336c | 2006-12-12 11:50:20 -0800 | [diff] [blame] | 970 | dd->ipath_irq = pdev->irq; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 971 | |
| 972 | if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { |
| 973 | u16 control; |
| 974 | pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, |
| 975 | &dd->ipath_msi_lo); |
| 976 | pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, |
| 977 | &dd->ipath_msi_hi); |
| 978 | pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, |
| 979 | &control); |
| 980 | /* now save the data (vector) info */ |
| 981 | pci_read_config_word(dd->pcidev, |
| 982 | pos + ((control & PCI_MSI_FLAGS_64BIT) |
| 983 | ? 12 : 8), |
| 984 | &dd->ipath_msi_data); |
| 985 | ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset " |
| 986 | "0x%x, control=0x%x\n", dd->ipath_msi_data, |
| 987 | pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), |
| 988 | control); |
| 989 | /* we save the cachelinesize also, although it doesn't |
| 990 | * really matter */ |
| 991 | pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, |
| 992 | &dd->ipath_pci_cacheline); |
| 993 | } else |
| 994 | ipath_dev_err(dd, "Can't find MSI capability, " |
| 995 | "can't save MSI settings for reset\n"); |
Arthur Jones | 6ca2abf | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 996 | |
| 997 | ipath_6120_pcie_params(dd); |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 998 | |
| 999 | dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; |
| 1000 | dd->ipath_link_speed_supported = IPATH_IB_SDR; |
| 1001 | dd->ipath_link_width_enabled = IB_WIDTH_4X; |
| 1002 | dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported; |
| 1003 | /* these can't change for this chip, so set once */ |
| 1004 | dd->ipath_link_width_active = dd->ipath_link_width_enabled; |
| 1005 | dd->ipath_link_speed_active = dd->ipath_link_speed_enabled; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1006 | return 0; |
| 1007 | } |
| 1008 | |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1009 | static void ipath_init_pe_variables(struct ipath_devdata *dd) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1010 | { |
| 1011 | /* |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1012 | * setup the register offsets, since they are different for each |
| 1013 | * chip |
| 1014 | */ |
| 1015 | dd->ipath_kregs = &ipath_pe_kregs; |
| 1016 | dd->ipath_cregs = &ipath_pe_cregs; |
| 1017 | |
| 1018 | /* |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1019 | * bits for selecting i2c direction and values, |
| 1020 | * used for I2C serial flash |
| 1021 | */ |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1022 | dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM; |
| 1023 | dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM; |
| 1024 | dd->ipath_gpio_sda = IPATH_GPIO_SDA; |
| 1025 | dd->ipath_gpio_scl = IPATH_GPIO_SCL; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1026 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1027 | /* |
| 1028 | * Fill in data for field-values that change in newer chips. |
| 1029 | * We dynamically specify only the mask for LINKTRAININGSTATE |
| 1030 | * and only the shift for LINKSTATE, as they are the only ones |
| 1031 | * that change. Also precalculate the 3 link states of interest |
| 1032 | * and the combined mask. |
| 1033 | */ |
| 1034 | dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT; |
| 1035 | dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK; |
| 1036 | dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK << |
| 1037 | dd->ibcs_ls_shift) | dd->ibcs_lts_mask; |
| 1038 | dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP << |
| 1039 | INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | |
| 1040 | (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift); |
| 1041 | dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP << |
| 1042 | INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | |
| 1043 | (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift); |
| 1044 | dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP << |
| 1045 | INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) | |
| 1046 | (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift); |
| 1047 | |
| 1048 | /* |
| 1049 | * Fill in data for ibcc field-values that change in newer chips. |
| 1050 | * We dynamically specify only the mask for LINKINITCMD |
| 1051 | * and only the shift for LINKCMD and MAXPKTLEN, as they are |
| 1052 | * the only ones that change. |
| 1053 | */ |
| 1054 | dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK; |
| 1055 | dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT; |
| 1056 | dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT; |
| 1057 | |
Dave Olson | d827486 | 2007-12-21 01:50:59 -0800 | [diff] [blame] | 1058 | /* Fill in shifts for RcvCtrl. */ |
| 1059 | dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT; |
| 1060 | dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT; |
| 1061 | dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT; |
| 1062 | dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */ |
| 1063 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1064 | /* variables for sanity checking interrupt and errors */ |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1065 | dd->ipath_hwe_bitsextant = |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1066 | (INFINIPATH_HWE_RXEMEMPARITYERR_MASK << |
| 1067 | INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) | |
Bryan O'Sullivan | 89d1e09 | 2006-09-28 09:00:18 -0700 | [diff] [blame] | 1068 | (INFINIPATH_HWE_TXEMEMPARITYERR_MASK << |
| 1069 | INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1070 | (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK << |
| 1071 | INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) | |
| 1072 | INFINIPATH_HWE_PCIE1PLLFAILED | |
| 1073 | INFINIPATH_HWE_PCIE0PLLFAILED | |
| 1074 | INFINIPATH_HWE_PCIEPOISONEDTLP | |
| 1075 | INFINIPATH_HWE_PCIECPLTIMEOUT | |
| 1076 | INFINIPATH_HWE_PCIEBUSPARITYXTLH | |
| 1077 | INFINIPATH_HWE_PCIEBUSPARITYXADM | |
| 1078 | INFINIPATH_HWE_PCIEBUSPARITYRADM | |
| 1079 | INFINIPATH_HWE_MEMBISTFAILED | |
| 1080 | INFINIPATH_HWE_COREPLL_FBSLIP | |
| 1081 | INFINIPATH_HWE_COREPLL_RFSLIP | |
| 1082 | INFINIPATH_HWE_SERDESPLLFAILED | |
| 1083 | INFINIPATH_HWE_IBCBUSTOSPCPARITYERR | |
| 1084 | INFINIPATH_HWE_IBCBUSFRSPCPARITYERR; |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1085 | dd->ipath_i_bitsextant = |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1086 | (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) | |
| 1087 | (INFINIPATH_I_RCVAVAIL_MASK << |
| 1088 | INFINIPATH_I_RCVAVAIL_SHIFT) | |
| 1089 | INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT | |
| 1090 | INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO; |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1091 | dd->ipath_e_bitsextant = |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1092 | INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC | |
| 1093 | INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN | |
| 1094 | INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN | |
| 1095 | INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR | |
| 1096 | INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP | |
| 1097 | INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION | |
| 1098 | INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | |
| 1099 | INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN | |
| 1100 | INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK | |
| 1101 | INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN | |
| 1102 | INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN | |
| 1103 | INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT | |
| 1104 | INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | |
| 1105 | INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED | |
| 1106 | INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET | |
| 1107 | INFINIPATH_E_HARDWARE; |
| 1108 | |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1109 | dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK; |
| 1110 | dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK; |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1111 | dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT; |
| 1112 | dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT; |
Michael Albaugh | aecd3b5 | 2007-05-17 07:26:28 -0700 | [diff] [blame] | 1113 | |
| 1114 | /* |
| 1115 | * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity. |
| 1116 | * 2 is Some Misc, 3 is reserved for future. |
| 1117 | */ |
| 1118 | dd->ipath_eep_st_masks[0].hwerrs_to_log = |
| 1119 | INFINIPATH_HWE_TXEMEMPARITYERR_MASK << |
| 1120 | INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT; |
| 1121 | |
| 1122 | /* Ignore errors in PIO/PBC on systems with unordered write-combining */ |
| 1123 | if (ipath_unordered_wc()) |
| 1124 | dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY; |
| 1125 | |
| 1126 | dd->ipath_eep_st_masks[1].hwerrs_to_log = |
| 1127 | INFINIPATH_HWE_RXEMEMPARITYERR_MASK << |
| 1128 | INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT; |
| 1129 | |
| 1130 | dd->ipath_eep_st_masks[2].errs_to_log = |
| 1131 | INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET; |
| 1132 | |
| 1133 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1134 | dd->delay_mult = 2; /* SDR, 4X, can't change */ |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1135 | } |
| 1136 | |
| 1137 | /* setup the MSI stuff again after a reset. I'd like to just call |
| 1138 | * pci_enable_msi() and request_irq() again, but when I do that, |
| 1139 | * the MSI enable bit doesn't get set in the command word, and |
| 1140 | * we switch to to a different interrupt vector, which is confusing, |
| 1141 | * so I instead just do it all inline. Perhaps somehow can tie this |
| 1142 | * into the PCIe hotplug support at some point |
| 1143 | * Note, because I'm doing it all here, I don't call pci_disable_msi() |
| 1144 | * or free_irq() at the start of ipath_setup_pe_reset(). |
| 1145 | */ |
| 1146 | static int ipath_reinit_msi(struct ipath_devdata *dd) |
| 1147 | { |
| 1148 | int pos; |
| 1149 | u16 control; |
| 1150 | int ret; |
| 1151 | |
| 1152 | if (!dd->ipath_msi_lo) { |
| 1153 | dev_info(&dd->pcidev->dev, "Can't restore MSI config, " |
| 1154 | "initial setup failed?\n"); |
| 1155 | ret = 0; |
| 1156 | goto bail; |
| 1157 | } |
| 1158 | |
| 1159 | if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { |
| 1160 | ipath_dev_err(dd, "Can't find MSI capability, " |
| 1161 | "can't restore MSI settings\n"); |
| 1162 | ret = 0; |
| 1163 | goto bail; |
| 1164 | } |
| 1165 | ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", |
| 1166 | dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO); |
| 1167 | pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, |
| 1168 | dd->ipath_msi_lo); |
| 1169 | ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", |
| 1170 | dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI); |
| 1171 | pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, |
| 1172 | dd->ipath_msi_hi); |
| 1173 | pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); |
| 1174 | if (!(control & PCI_MSI_FLAGS_ENABLE)) { |
| 1175 | ipath_cdbg(VERBOSE, "MSI control at off %x was %x, " |
| 1176 | "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS, |
| 1177 | control, control | PCI_MSI_FLAGS_ENABLE); |
| 1178 | control |= PCI_MSI_FLAGS_ENABLE; |
| 1179 | pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, |
| 1180 | control); |
| 1181 | } |
| 1182 | /* now rewrite the data (vector) info */ |
| 1183 | pci_write_config_word(dd->pcidev, pos + |
| 1184 | ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), |
| 1185 | dd->ipath_msi_data); |
| 1186 | /* we restore the cachelinesize also, although it doesn't really |
| 1187 | * matter */ |
| 1188 | pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, |
| 1189 | dd->ipath_pci_cacheline); |
| 1190 | /* and now set the pci master bit again */ |
| 1191 | pci_set_master(dd->pcidev); |
| 1192 | ret = 1; |
| 1193 | |
| 1194 | bail: |
| 1195 | return ret; |
| 1196 | } |
| 1197 | |
| 1198 | /* This routine sleeps, so it can only be called from user context, not |
| 1199 | * from interrupt context. If we need interrupt context, we can split |
| 1200 | * it into two routines. |
| 1201 | */ |
| 1202 | static int ipath_setup_pe_reset(struct ipath_devdata *dd) |
| 1203 | { |
| 1204 | u64 val; |
| 1205 | int i; |
| 1206 | int ret; |
| 1207 | |
| 1208 | /* Use ERROR so it shows up in logs, etc. */ |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1209 | ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit); |
Bryan O'Sullivan | c71c30d | 2006-04-24 14:23:03 -0700 | [diff] [blame] | 1210 | /* keep chip from being accessed in a few places */ |
| 1211 | dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1212 | val = dd->ipath_control | INFINIPATH_C_RESET; |
| 1213 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val); |
| 1214 | mb(); |
| 1215 | |
| 1216 | for (i = 1; i <= 5; i++) { |
| 1217 | int r; |
| 1218 | /* allow MBIST, etc. to complete; longer on each retry. |
| 1219 | * We sometimes get machine checks from bus timeout if no |
| 1220 | * response, so for now, make it *really* long. |
| 1221 | */ |
| 1222 | msleep(1000 + (1 + i) * 2000); |
| 1223 | if ((r = |
| 1224 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, |
| 1225 | dd->ipath_pcibar0))) |
| 1226 | ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", |
| 1227 | r); |
| 1228 | if ((r = |
| 1229 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, |
| 1230 | dd->ipath_pcibar1))) |
| 1231 | ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", |
| 1232 | r); |
| 1233 | /* now re-enable memory access */ |
| 1234 | if ((r = pci_enable_device(dd->pcidev))) |
| 1235 | ipath_dev_err(dd, "pci_enable_device failed after " |
| 1236 | "reset: %d\n", r); |
Bryan O'Sullivan | c71c30d | 2006-04-24 14:23:03 -0700 | [diff] [blame] | 1237 | /* whether it worked or not, mark as present, again */ |
| 1238 | dd->ipath_flags |= IPATH_PRESENT; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1239 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); |
| 1240 | if (val == dd->ipath_revision) { |
| 1241 | ipath_cdbg(VERBOSE, "Got matching revision " |
| 1242 | "register %llx on try %d\n", |
| 1243 | (unsigned long long) val, i); |
| 1244 | ret = ipath_reinit_msi(dd); |
| 1245 | goto bail; |
| 1246 | } |
| 1247 | /* Probably getting -1 back */ |
| 1248 | ipath_dbg("Didn't get expected revision register, " |
| 1249 | "got %llx, try %d\n", (unsigned long long) val, |
| 1250 | i + 1); |
| 1251 | } |
| 1252 | ret = 0; /* failed */ |
| 1253 | |
| 1254 | bail: |
Arthur Jones | 6ca2abf | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 1255 | if (ret) |
| 1256 | ipath_6120_pcie_params(dd); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1257 | return ret; |
| 1258 | } |
| 1259 | |
| 1260 | /** |
| 1261 | * ipath_pe_put_tid - write a TID in chip |
| 1262 | * @dd: the infinipath device |
| 1263 | * @tidptr: pointer to the expected TID (in chip) to udpate |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1264 | * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1265 | * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing |
| 1266 | * |
| 1267 | * This exists as a separate routine to allow for special locking etc. |
| 1268 | * It's used for both the full cleanup on exit, as well as the normal |
| 1269 | * setup and teardown. |
| 1270 | */ |
| 1271 | static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr, |
| 1272 | u32 type, unsigned long pa) |
| 1273 | { |
| 1274 | u32 __iomem *tidp32 = (u32 __iomem *)tidptr; |
| 1275 | unsigned long flags = 0; /* keep gcc quiet */ |
| 1276 | |
| 1277 | if (pa != dd->ipath_tidinvalid) { |
| 1278 | if (pa & ((1U << 11) - 1)) { |
| 1279 | dev_info(&dd->pcidev->dev, "BUG: physaddr %lx " |
Ralph Campbell | 6be979d | 2008-04-16 21:09:24 -0700 | [diff] [blame] | 1280 | "not 2KB aligned!\n", pa); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1281 | return; |
| 1282 | } |
| 1283 | pa >>= 11; |
| 1284 | /* paranoia check */ |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 1285 | if (pa & ~INFINIPATH_RT_ADDR_MASK) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1286 | ipath_dev_err(dd, |
| 1287 | "BUG: Physical page address 0x%lx " |
| 1288 | "has bits set in 31-29\n", pa); |
| 1289 | |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1290 | if (type == RCVHQ_RCV_TYPE_EAGER) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1291 | pa |= dd->ipath_tidtemplate; |
| 1292 | else /* for now, always full 4KB page */ |
| 1293 | pa |= 2 << 29; |
| 1294 | } |
| 1295 | |
Dave Olson | 9ef8617 | 2007-08-09 15:18:48 -0700 | [diff] [blame] | 1296 | /* |
| 1297 | * Workaround chip bug 9437 by writing the scratch register |
| 1298 | * before and after the TID, and with an io write barrier. |
| 1299 | * We use a spinlock around the writes, so they can't intermix |
| 1300 | * with other TID (eager or expected) writes (the chip bug |
| 1301 | * is triggered by back to back TID writes). Unfortunately, this |
| 1302 | * call can be done from interrupt level for the port 0 eager TIDs, |
| 1303 | * so we have to use irqsave locks. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1304 | */ |
| 1305 | spin_lock_irqsave(&dd->ipath_tid_lock, flags); |
| 1306 | ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf); |
| 1307 | if (dd->ipath_kregbase) |
| 1308 | writel(pa, tidp32); |
| 1309 | ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef); |
| 1310 | mmiowb(); |
| 1311 | spin_unlock_irqrestore(&dd->ipath_tid_lock, flags); |
| 1312 | } |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1313 | /** |
| 1314 | * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher |
| 1315 | * @dd: the infinipath device |
| 1316 | * @tidptr: pointer to the expected TID (in chip) to udpate |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1317 | * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1318 | * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing |
| 1319 | * |
| 1320 | * This exists as a separate routine to allow for selection of the |
| 1321 | * appropriate "flavor". The static calls in cleanup just use the |
| 1322 | * revision-agnostic form, as they are not performance critical. |
| 1323 | */ |
| 1324 | static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr, |
| 1325 | u32 type, unsigned long pa) |
| 1326 | { |
| 1327 | u32 __iomem *tidp32 = (u32 __iomem *)tidptr; |
| 1328 | |
| 1329 | if (pa != dd->ipath_tidinvalid) { |
| 1330 | if (pa & ((1U << 11) - 1)) { |
| 1331 | dev_info(&dd->pcidev->dev, "BUG: physaddr %lx " |
Bryan O'Sullivan | 1fd3b40 | 2006-09-28 09:00:13 -0700 | [diff] [blame] | 1332 | "not 2KB aligned!\n", pa); |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1333 | return; |
| 1334 | } |
| 1335 | pa >>= 11; |
| 1336 | /* paranoia check */ |
Dave Olson | f2ceb49 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 1337 | if (pa & ~INFINIPATH_RT_ADDR_MASK) |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1338 | ipath_dev_err(dd, |
| 1339 | "BUG: Physical page address 0x%lx " |
| 1340 | "has bits set in 31-29\n", pa); |
| 1341 | |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1342 | if (type == RCVHQ_RCV_TYPE_EAGER) |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1343 | pa |= dd->ipath_tidtemplate; |
| 1344 | else /* for now, always full 4KB page */ |
| 1345 | pa |= 2 << 29; |
| 1346 | } |
| 1347 | if (dd->ipath_kregbase) |
| 1348 | writel(pa, tidp32); |
| 1349 | mmiowb(); |
| 1350 | } |
| 1351 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1352 | |
| 1353 | /** |
| 1354 | * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager |
| 1355 | * @dd: the infinipath device |
| 1356 | * @port: the port |
| 1357 | * |
| 1358 | * clear all TID entries for a port, expected and eager. |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1359 | * Used from ipath_close(). On this chip, TIDs are only 32 bits, |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1360 | * not 64, but they are still on 64 bit boundaries, so tidbase |
| 1361 | * is declared as u64 * for the pointer math, even though we write 32 bits |
| 1362 | */ |
| 1363 | static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port) |
| 1364 | { |
| 1365 | u64 __iomem *tidbase; |
| 1366 | unsigned long tidinv; |
| 1367 | int i; |
| 1368 | |
| 1369 | if (!dd->ipath_kregbase) |
| 1370 | return; |
| 1371 | |
| 1372 | ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port); |
| 1373 | |
| 1374 | tidinv = dd->ipath_tidinvalid; |
| 1375 | tidbase = (u64 __iomem *) |
| 1376 | ((char __iomem *)(dd->ipath_kregbase) + |
| 1377 | dd->ipath_rcvtidbase + |
| 1378 | port * dd->ipath_rcvtidcnt * sizeof(*tidbase)); |
| 1379 | |
| 1380 | for (i = 0; i < dd->ipath_rcvtidcnt; i++) |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 1381 | dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1382 | tidinv); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1383 | |
| 1384 | tidbase = (u64 __iomem *) |
| 1385 | ((char __iomem *)(dd->ipath_kregbase) + |
| 1386 | dd->ipath_rcvegrbase + |
| 1387 | port * dd->ipath_rcvegrcnt * sizeof(*tidbase)); |
| 1388 | |
| 1389 | for (i = 0; i < dd->ipath_rcvegrcnt; i++) |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 1390 | dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, |
Joan Eslinger | f716cdf | 2007-06-18 14:24:39 -0700 | [diff] [blame] | 1391 | tidinv); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1392 | } |
| 1393 | |
| 1394 | /** |
| 1395 | * ipath_pe_tidtemplate - setup constants for TID updates |
| 1396 | * @dd: the infinipath device |
| 1397 | * |
| 1398 | * We setup stuff that we use a lot, to avoid calculating each time |
| 1399 | */ |
| 1400 | static void ipath_pe_tidtemplate(struct ipath_devdata *dd) |
| 1401 | { |
| 1402 | u32 egrsize = dd->ipath_rcvegrbufsize; |
| 1403 | |
| 1404 | /* For now, we always allocate 4KB buffers (at init) so we can |
| 1405 | * receive max size packets. We may want a module parameter to |
| 1406 | * specify 2KB or 4KB and/or make be per port instead of per device |
| 1407 | * for those who want to reduce memory footprint. Note that the |
| 1408 | * ipath_rcvhdrentsize size must be large enough to hold the largest |
| 1409 | * IB header (currently 96 bytes) that we expect to handle (plus of |
| 1410 | * course the 2 dwords of RHF). |
| 1411 | */ |
| 1412 | if (egrsize == 2048) |
| 1413 | dd->ipath_tidtemplate = 1U << 29; |
| 1414 | else if (egrsize == 4096) |
| 1415 | dd->ipath_tidtemplate = 2U << 29; |
| 1416 | else { |
| 1417 | egrsize = 4096; |
| 1418 | dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize " |
| 1419 | "%u, using %u\n", dd->ipath_rcvegrbufsize, |
| 1420 | egrsize); |
| 1421 | dd->ipath_tidtemplate = 2U << 29; |
| 1422 | } |
| 1423 | dd->ipath_tidinvalid = 0; |
| 1424 | } |
| 1425 | |
| 1426 | static int ipath_pe_early_init(struct ipath_devdata *dd) |
| 1427 | { |
| 1428 | dd->ipath_flags |= IPATH_4BYTE_TID; |
Ralph Campbell | 210d6ca | 2007-07-24 13:55:39 -0700 | [diff] [blame] | 1429 | if (ipath_unordered_wc()) |
| 1430 | dd->ipath_flags |= IPATH_PIO_FLUSH_WC; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1431 | |
| 1432 | /* |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1433 | * For openfabrics, we need to be able to handle an IB header of |
| 1434 | * 24 dwords. HT chip has arbitrary sized receive buffers, so we |
| 1435 | * made them the same size as the PIO buffers. This chip does not |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1436 | * handle arbitrary size buffers, so we need the header large enough |
| 1437 | * to handle largest IB header, but still have room for a 2KB MTU |
| 1438 | * standard IB packet. |
| 1439 | */ |
| 1440 | dd->ipath_rcvhdrentsize = 24; |
| 1441 | dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE; |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1442 | dd->ipath_rhf_offset = 0; |
| 1443 | dd->ipath_egrtidbase = (u64 __iomem *) |
| 1444 | ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1445 | |
Dave Olson | 826d801 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 1446 | dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1447 | /* |
| 1448 | * the min() check here is currently a nop, but it may not always |
| 1449 | * be, depending on just how we do ipath_rcvegrbufsize |
| 1450 | */ |
Dave Olson | 826d801 | 2008-04-16 21:01:12 -0700 | [diff] [blame] | 1451 | dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k : |
| 1452 | dd->ipath_piosize2k, |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1453 | dd->ipath_rcvegrbufsize + |
| 1454 | (dd->ipath_rcvhdrentsize << 2)); |
| 1455 | dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen; |
| 1456 | |
| 1457 | /* |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1458 | * We can request a receive interrupt for 1 or |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1459 | * more packets from current offset. For now, we set this |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1460 | * up for a single packet. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1461 | */ |
| 1462 | dd->ipath_rhdrhead_intr_off = 1ULL<<32; |
| 1463 | |
Bryan O'Sullivan | f2080fa | 2006-05-23 11:32:34 -0700 | [diff] [blame] | 1464 | ipath_get_eeprom_info(dd); |
| 1465 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1466 | return 0; |
| 1467 | } |
| 1468 | |
| 1469 | int __attribute__((weak)) ipath_unordered_wc(void) |
| 1470 | { |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
| 1474 | /** |
| 1475 | * ipath_init_pe_get_base_info - set chip-specific flags for user code |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1476 | * @pd: the infinipath port |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1477 | * @kbase: ipath_base_info pointer |
| 1478 | * |
| 1479 | * We set the PCIE flag because the lower bandwidth on PCIe vs |
Robert P. J. Day | d08df60 | 2007-02-17 19:07:33 +0100 | [diff] [blame] | 1480 | * HyperTransport can affect some user packet algorithms. |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1481 | */ |
| 1482 | static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase) |
| 1483 | { |
| 1484 | struct ipath_base_info *kinfo = kbase; |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1485 | struct ipath_devdata *dd; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1486 | |
| 1487 | if (ipath_unordered_wc()) { |
| 1488 | kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER; |
| 1489 | ipath_cdbg(PROC, "Intel processor, forcing WC order\n"); |
| 1490 | } |
| 1491 | else |
| 1492 | ipath_cdbg(PROC, "Not Intel processor, WC ordered\n"); |
| 1493 | |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1494 | if (pd == NULL) |
| 1495 | goto done; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1496 | |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1497 | dd = pd->port_dd; |
| 1498 | |
Bryan O'Sullivan | 2c9446a | 2006-09-28 09:00:00 -0700 | [diff] [blame] | 1499 | done: |
Arthur Jones | 20bed34 | 2007-09-18 14:44:45 -0700 | [diff] [blame] | 1500 | kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE | |
| 1501 | IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1502 | return 0; |
| 1503 | } |
| 1504 | |
Bryan O'Sullivan | 51f65eb | 2006-11-08 17:44:58 -0800 | [diff] [blame] | 1505 | static void ipath_pe_free_irq(struct ipath_devdata *dd) |
| 1506 | { |
| 1507 | free_irq(dd->ipath_irq, dd); |
| 1508 | dd->ipath_irq = 0; |
| 1509 | } |
| 1510 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1511 | |
| 1512 | static struct ipath_message_header * |
| 1513 | ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr) |
| 1514 | { |
| 1515 | return (struct ipath_message_header *) |
| 1516 | &rhf_addr[sizeof(u64) / sizeof(u32)]; |
| 1517 | } |
| 1518 | |
Ralph Campbell | 60948a4 | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 1519 | static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports) |
| 1520 | { |
| 1521 | dd->ipath_portcnt = |
| 1522 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt); |
| 1523 | dd->ipath_p0_rcvegrcnt = |
| 1524 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); |
| 1525 | } |
| 1526 | |
Ralph Campbell | 3029fcc | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 1527 | static void ipath_pe_read_counters(struct ipath_devdata *dd, |
| 1528 | struct infinipath_counters *cntrs) |
| 1529 | { |
| 1530 | cntrs->LBIntCnt = |
| 1531 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt)); |
| 1532 | cntrs->LBFlowStallCnt = |
| 1533 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt)); |
| 1534 | cntrs->TxSDmaDescCnt = 0; |
| 1535 | cntrs->TxUnsupVLErrCnt = |
| 1536 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt)); |
| 1537 | cntrs->TxDataPktCnt = |
| 1538 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt)); |
| 1539 | cntrs->TxFlowPktCnt = |
| 1540 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt)); |
| 1541 | cntrs->TxDwordCnt = |
| 1542 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt)); |
| 1543 | cntrs->TxLenErrCnt = |
| 1544 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt)); |
| 1545 | cntrs->TxMaxMinLenErrCnt = |
| 1546 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt)); |
| 1547 | cntrs->TxUnderrunCnt = |
| 1548 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt)); |
| 1549 | cntrs->TxFlowStallCnt = |
| 1550 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt)); |
| 1551 | cntrs->TxDroppedPktCnt = |
| 1552 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt)); |
| 1553 | cntrs->RxDroppedPktCnt = |
| 1554 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt)); |
| 1555 | cntrs->RxDataPktCnt = |
| 1556 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt)); |
| 1557 | cntrs->RxFlowPktCnt = |
| 1558 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt)); |
| 1559 | cntrs->RxDwordCnt = |
| 1560 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt)); |
| 1561 | cntrs->RxLenErrCnt = |
| 1562 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt)); |
| 1563 | cntrs->RxMaxMinLenErrCnt = |
| 1564 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt)); |
| 1565 | cntrs->RxICRCErrCnt = |
| 1566 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt)); |
| 1567 | cntrs->RxVCRCErrCnt = |
| 1568 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt)); |
| 1569 | cntrs->RxFlowCtrlErrCnt = |
| 1570 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt)); |
| 1571 | cntrs->RxBadFormatCnt = |
| 1572 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt)); |
| 1573 | cntrs->RxLinkProblemCnt = |
| 1574 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt)); |
| 1575 | cntrs->RxEBPCnt = |
| 1576 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt)); |
| 1577 | cntrs->RxLPCRCErrCnt = |
| 1578 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt)); |
| 1579 | cntrs->RxBufOvflCnt = |
| 1580 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt)); |
| 1581 | cntrs->RxTIDFullErrCnt = |
| 1582 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt)); |
| 1583 | cntrs->RxTIDValidErrCnt = |
| 1584 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt)); |
| 1585 | cntrs->RxPKeyMismatchCnt = |
| 1586 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt)); |
| 1587 | cntrs->RxP0HdrEgrOvflCnt = |
| 1588 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt)); |
| 1589 | cntrs->RxP1HdrEgrOvflCnt = |
| 1590 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt)); |
| 1591 | cntrs->RxP2HdrEgrOvflCnt = |
| 1592 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt)); |
| 1593 | cntrs->RxP3HdrEgrOvflCnt = |
| 1594 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt)); |
| 1595 | cntrs->RxP4HdrEgrOvflCnt = |
| 1596 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt)); |
| 1597 | cntrs->RxP5HdrEgrOvflCnt = 0; |
| 1598 | cntrs->RxP6HdrEgrOvflCnt = 0; |
| 1599 | cntrs->RxP7HdrEgrOvflCnt = 0; |
| 1600 | cntrs->RxP8HdrEgrOvflCnt = 0; |
| 1601 | cntrs->RxP9HdrEgrOvflCnt = 0; |
| 1602 | cntrs->RxP10HdrEgrOvflCnt = 0; |
| 1603 | cntrs->RxP11HdrEgrOvflCnt = 0; |
| 1604 | cntrs->RxP12HdrEgrOvflCnt = 0; |
| 1605 | cntrs->RxP13HdrEgrOvflCnt = 0; |
| 1606 | cntrs->RxP14HdrEgrOvflCnt = 0; |
| 1607 | cntrs->RxP15HdrEgrOvflCnt = 0; |
| 1608 | cntrs->RxP16HdrEgrOvflCnt = 0; |
| 1609 | cntrs->IBStatusChangeCnt = |
| 1610 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt)); |
| 1611 | cntrs->IBLinkErrRecoveryCnt = |
| 1612 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt)); |
| 1613 | cntrs->IBLinkDownedCnt = |
| 1614 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt)); |
| 1615 | cntrs->IBSymbolErrCnt = |
| 1616 | ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt)); |
| 1617 | cntrs->RxVL15DroppedPktCnt = 0; |
| 1618 | cntrs->RxOtherLocalPhyErrCnt = 0; |
| 1619 | cntrs->PcieRetryBufDiagQwordCnt = 0; |
| 1620 | cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs; |
| 1621 | cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs; |
| 1622 | cntrs->RxVlErrCnt = 0; |
| 1623 | cntrs->RxDlidFltrCnt = 0; |
| 1624 | } |
| 1625 | |
Bryan O'Sullivan | 9783ab4 | 2007-03-15 14:45:07 -0700 | [diff] [blame] | 1626 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1627 | /* no interrupt fallback for these chips */ |
| 1628 | static int ipath_pe_nointr_fallback(struct ipath_devdata *dd) |
| 1629 | { |
| 1630 | return 0; |
| 1631 | } |
| 1632 | |
| 1633 | |
| 1634 | /* |
| 1635 | * reset the XGXS (between serdes and IBC). Slightly less intrusive |
| 1636 | * than resetting the IBC or external link state, and useful in some |
| 1637 | * cases to cause some retraining. To do this right, we reset IBC |
| 1638 | * as well. |
| 1639 | */ |
| 1640 | static void ipath_pe_xgxs_reset(struct ipath_devdata *dd) |
| 1641 | { |
| 1642 | u64 val, prev_val; |
| 1643 | |
| 1644 | prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); |
| 1645 | val = prev_val | INFINIPATH_XGXS_RESET; |
| 1646 | prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */ |
| 1647 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, |
| 1648 | dd->ipath_control & ~INFINIPATH_C_LINKENABLE); |
| 1649 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); |
| 1650 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch); |
| 1651 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val); |
| 1652 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, |
| 1653 | dd->ipath_control); |
| 1654 | } |
| 1655 | |
| 1656 | |
| 1657 | static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which) |
| 1658 | { |
| 1659 | int ret; |
| 1660 | |
| 1661 | switch (which) { |
| 1662 | case IPATH_IB_CFG_LWID: |
| 1663 | ret = dd->ipath_link_width_active; |
| 1664 | break; |
| 1665 | case IPATH_IB_CFG_SPD: |
| 1666 | ret = dd->ipath_link_speed_active; |
| 1667 | break; |
| 1668 | case IPATH_IB_CFG_LWID_ENB: |
| 1669 | ret = dd->ipath_link_width_enabled; |
| 1670 | break; |
| 1671 | case IPATH_IB_CFG_SPD_ENB: |
| 1672 | ret = dd->ipath_link_speed_enabled; |
| 1673 | break; |
| 1674 | default: |
| 1675 | ret = -ENOTSUPP; |
| 1676 | break; |
| 1677 | } |
| 1678 | return ret; |
| 1679 | } |
| 1680 | |
| 1681 | |
| 1682 | /* we assume range checking is already done, if needed */ |
| 1683 | static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val) |
| 1684 | { |
| 1685 | int ret = 0; |
| 1686 | |
| 1687 | if (which == IPATH_IB_CFG_LWID_ENB) |
| 1688 | dd->ipath_link_width_enabled = val; |
| 1689 | else if (which == IPATH_IB_CFG_SPD_ENB) |
| 1690 | dd->ipath_link_speed_enabled = val; |
| 1691 | else |
| 1692 | ret = -ENOTSUPP; |
| 1693 | return ret; |
| 1694 | } |
| 1695 | |
| 1696 | static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b) |
| 1697 | { |
| 1698 | } |
| 1699 | |
| 1700 | |
| 1701 | static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs) |
| 1702 | { |
| 1703 | ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs), |
| 1704 | ipath_ib_linktrstate(dd, ibcs)); |
| 1705 | return 0; |
| 1706 | } |
| 1707 | |
| 1708 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1709 | /** |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1710 | * ipath_init_iba6120_funcs - set up the chip-specific function pointers |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1711 | * @dd: the infinipath device |
| 1712 | * |
| 1713 | * This is global, and is called directly at init to set up the |
| 1714 | * chip-specific function pointers for later use. |
| 1715 | */ |
Bryan O'Sullivan | 525d0ca | 2006-08-25 11:24:39 -0700 | [diff] [blame] | 1716 | void ipath_init_iba6120_funcs(struct ipath_devdata *dd) |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1717 | { |
| 1718 | dd->ipath_f_intrsetup = ipath_pe_intconfig; |
| 1719 | dd->ipath_f_bus = ipath_setup_pe_config; |
| 1720 | dd->ipath_f_reset = ipath_setup_pe_reset; |
| 1721 | dd->ipath_f_get_boardname = ipath_pe_boardname; |
| 1722 | dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors; |
| 1723 | dd->ipath_f_early_init = ipath_pe_early_init; |
| 1724 | dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors; |
| 1725 | dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes; |
| 1726 | dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes; |
| 1727 | dd->ipath_f_clear_tids = ipath_pe_clear_tids; |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 1728 | /* |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1729 | * _f_put_tid may get changed after we read the chip revision, |
Dave Olson | cf5b60a | 2007-07-20 13:34:02 -0700 | [diff] [blame] | 1730 | * but we start with the safe version for all revs |
| 1731 | */ |
| 1732 | dd->ipath_f_put_tid = ipath_pe_put_tid; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1733 | dd->ipath_f_cleanup = ipath_setup_pe_cleanup; |
| 1734 | dd->ipath_f_setextled = ipath_setup_pe_setextled; |
| 1735 | dd->ipath_f_get_base_info = ipath_pe_get_base_info; |
Bryan O'Sullivan | 51f65eb | 2006-11-08 17:44:58 -0800 | [diff] [blame] | 1736 | dd->ipath_f_free_irq = ipath_pe_free_irq; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1737 | dd->ipath_f_tidtemplate = ipath_pe_tidtemplate; |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1738 | dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback; |
| 1739 | dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset; |
| 1740 | dd->ipath_f_get_msgheader = ipath_pe_get_msgheader; |
Ralph Campbell | 60948a4 | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 1741 | dd->ipath_f_config_ports = ipath_pe_config_ports; |
Ralph Campbell | 3029fcc | 2008-01-06 21:02:34 -0800 | [diff] [blame] | 1742 | dd->ipath_f_read_counters = ipath_pe_read_counters; |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1743 | dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg; |
| 1744 | dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg; |
| 1745 | dd->ipath_f_config_jint = ipath_pe_config_jint; |
| 1746 | dd->ipath_f_ib_updown = ipath_pe_ib_updown; |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1747 | |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1748 | |
Dave Olson | c4bce80 | 2008-01-08 02:36:46 -0800 | [diff] [blame] | 1749 | /* initialize chip-specific variables */ |
Bryan O'Sullivan | f62fe77 | 2006-09-28 09:00:11 -0700 | [diff] [blame] | 1750 | ipath_init_pe_variables(dd); |
Bryan O'Sullivan | dc741bb | 2006-03-29 15:23:27 -0800 | [diff] [blame] | 1751 | } |
| 1752 | |