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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
Jeff Garzik669a5db2006-08-29 18:12:40 -040036
37#define DRV_NAME "pata_pdc2027x"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040038#define DRV_VERSION "1.0"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039#undef PDC_DEBUG
40
41#ifdef PDC_DEBUG
Harvey Harrison7f5e4e82008-03-05 18:24:52 -080042#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
Jeff Garzik669a5db2006-08-29 18:12:40 -040043#else
44#define PDPRINTK(fmt, args...)
45#endif
46
47enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090048 PDC_MMIO_BAR = 5,
49
Jeff Garzik669a5db2006-08-29 18:12:40 -040050 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63};
64
65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090066static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040067static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -040069static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
Alan Cox9bedb792007-04-11 00:19:00 +010070static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71static int pdc2027x_cable_detect(struct ata_port *ap);
Tejun Heo02607312007-08-06 18:36:23 +090072static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
Jeff Garzik669a5db2006-08-29 18:12:40 -040073
74/*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84} pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90};
91
92static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94} pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98};
99
100static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102} pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110};
111
112static const struct pci_device_id pdc2027x_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121 { } /* terminate list */
122};
123
124static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900128 .remove = ata_pci_remove_one,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129};
130
131static struct scsi_host_template pdc2027x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900132 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400133};
134
135static struct ata_port_operations pdc2027x_pata100_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900136 .inherits = &ata_bmdma_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400137 .check_atapi_dma = pdc2027x_check_atapi_dma,
Alan Cox9bedb792007-04-11 00:19:00 +0100138 .cable_detect = pdc2027x_cable_detect,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900139 .prereset = pdc2027x_prereset,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140};
141
142static struct ata_port_operations pdc2027x_pata133_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900143 .inherits = &pdc2027x_pata100_ops,
144 .mode_filter = pdc2027x_mode_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400145 .set_piomode = pdc2027x_set_piomode,
146 .set_dmamode = pdc2027x_set_dmamode,
Alan Cox9bedb792007-04-11 00:19:00 +0100147 .set_mode = pdc2027x_set_mode,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400148};
149
150static struct ata_port_info pdc2027x_port_info[] = {
151 /* PDC_UDMA_100 */
152 {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400153 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
154 ATA_FLAG_MMIO,
155 .pio_mask = 0x1f, /* pio0-4 */
156 .mwdma_mask = 0x07, /* mwdma0-2 */
157 .udma_mask = ATA_UDMA5, /* udma0-5 */
158 .port_ops = &pdc2027x_pata100_ops,
159 },
160 /* PDC_UDMA_133 */
161 {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
163 ATA_FLAG_MMIO,
164 .pio_mask = 0x1f, /* pio0-4 */
165 .mwdma_mask = 0x07, /* mwdma0-2 */
166 .udma_mask = ATA_UDMA6, /* udma0-6 */
167 .port_ops = &pdc2027x_pata133_ops,
168 },
169};
170
171MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
172MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
173MODULE_LICENSE("GPL");
174MODULE_VERSION(DRV_VERSION);
175MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
176
177/**
178 * port_mmio - Get the MMIO address of PDC2027x extended registers
179 * @ap: Port
180 * @offset: offset from mmio base
181 */
Al Viro7c250412006-09-25 02:57:57 +0100182static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400183{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900184 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400185}
186
187/**
188 * dev_mmio - Get the MMIO address of PDC2027x extended registers
189 * @ap: Port
190 * @adev: device
191 * @offset: offset from mmio base
192 */
Al Viro7c250412006-09-25 02:57:57 +0100193static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400194{
195 u8 adj = (adev->devno) ? 0x08 : 0x00;
196 return port_mmio(ap, offset) + adj;
197}
198
199/**
Alan Cox9bedb792007-04-11 00:19:00 +0100200 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
Jeff Garzik669a5db2006-08-29 18:12:40 -0400201 * @ap: Port for which cable detect info is desired
202 *
203 * Read 80c cable indicator from Promise extended register.
204 * This register is latched when the system is reset.
205 *
206 * LOCKING:
207 * None (inherited from caller).
208 */
Alan Cox9bedb792007-04-11 00:19:00 +0100209static int pdc2027x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210{
211 u32 cgcr;
212
213 /* check cable detect results */
Alan Coxd2a84f42007-09-20 15:07:12 +0100214 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 if (cgcr & (1 << 26))
216 goto cbl40;
217
218 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
219
Alan Cox9bedb792007-04-11 00:19:00 +0100220 return ATA_CBL_PATA80;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400221cbl40:
222 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
Alan Cox9bedb792007-04-11 00:19:00 +0100223 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400224}
225
226/**
227 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
228 * @ap: Port to check
229 */
230static inline int pdc2027x_port_enabled(struct ata_port *ap)
231{
Alan Coxd2a84f42007-09-20 15:07:12 +0100232 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233}
234
235/**
236 * pdc2027x_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900237 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900238 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -0400239 *
240 * Probeinit including cable detection.
241 *
242 * LOCKING:
243 * None (inherited from caller).
244 */
245
Tejun Heocc0680a2007-08-06 18:36:23 +0900246static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400247{
248 /* Check whether port enabled */
Tejun Heocc0680a2007-08-06 18:36:23 +0900249 if (!pdc2027x_port_enabled(link->ap))
Alan Coxc9619222006-09-26 17:53:38 +0100250 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900251 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400252}
253
254/**
Alan Cox9bedb792007-04-11 00:19:00 +0100255 * pdc2720x_mode_filter - mode selection filter
256 * @adev: ATA device
257 * @mask: list of modes proposed
258 *
259 * Block UDMA on devices that cause trouble with this controller.
260 */
261
262static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
263{
264 unsigned char model_num[ATA_ID_PROD_LEN + 1];
265 struct ata_device *pair = ata_dev_pair(adev);
266
267 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
Tejun Heo9363c382008-04-07 22:47:16 +0900268 return ata_bmdma_mode_filter(adev, mask);
Alan Cox9bedb792007-04-11 00:19:00 +0100269
270 /* Check for slave of a Maxtor at UDMA6 */
271 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
272 ATA_ID_PROD_LEN + 1);
273 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
Al Viro4ca4e432007-12-30 09:32:22 +0000274 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
Alan Cox9bedb792007-04-11 00:19:00 +0100275 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
276
Tejun Heo9363c382008-04-07 22:47:16 +0900277 return ata_bmdma_mode_filter(adev, mask);
Alan Cox9bedb792007-04-11 00:19:00 +0100278}
279
280/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
282 * @ap: Port to configure
283 * @adev: um
284 * @pio: PIO mode, 0 - 4
285 *
286 * Set PIO mode for device.
287 *
288 * LOCKING:
289 * None (inherited from caller).
290 */
291
292static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
293{
294 unsigned int pio = adev->pio_mode - XFER_PIO_0;
295 u32 ctcr0, ctcr1;
296
297 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
298
299 /* Sanity check */
300 if (pio > 4) {
301 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
302 return;
303
304 }
305
306 /* Set the PIO timing registers using value table for 133MHz */
307 PDPRINTK("Set pio regs... \n");
308
Alan Coxd2a84f42007-09-20 15:07:12 +0100309 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310 ctcr0 &= 0xffff0000;
311 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
312 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
Alan Coxd2a84f42007-09-20 15:07:12 +0100313 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314
Alan Coxd2a84f42007-09-20 15:07:12 +0100315 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316 ctcr1 &= 0x00ffffff;
317 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
Alan Coxd2a84f42007-09-20 15:07:12 +0100318 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400319
320 PDPRINTK("Set pio regs done\n");
321
322 PDPRINTK("Set to pio mode[%u] \n", pio);
323}
324
325/**
326 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
327 * @ap: Port to configure
328 * @adev: um
329 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
330 *
331 * Set UDMA mode for device.
332 *
333 * LOCKING:
334 * None (inherited from caller).
335 */
336static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
337{
338 unsigned int dma_mode = adev->dma_mode;
339 u32 ctcr0, ctcr1;
340
341 if ((dma_mode >= XFER_UDMA_0) &&
342 (dma_mode <= XFER_UDMA_6)) {
343 /* Set the UDMA timing registers with value table for 133MHz */
344 unsigned int udma_mode = dma_mode & 0x07;
345
346 if (dma_mode == XFER_UDMA_2) {
347 /*
348 * Turn off tHOLD.
349 * If tHOLD is '1', the hardware will add half clock for data hold time.
350 * This code segment seems to be no effect. tHOLD will be overwritten below.
351 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100352 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
353 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354 }
355
356 PDPRINTK("Set udma regs... \n");
357
Alan Coxd2a84f42007-09-20 15:07:12 +0100358 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400359 ctcr1 &= 0xff000000;
360 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
361 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
362 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
Alan Coxd2a84f42007-09-20 15:07:12 +0100363 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364
365 PDPRINTK("Set udma regs done\n");
366
367 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
368
369 } else if ((dma_mode >= XFER_MW_DMA_0) &&
370 (dma_mode <= XFER_MW_DMA_2)) {
371 /* Set the MDMA timing registers with value table for 133MHz */
372 unsigned int mdma_mode = dma_mode & 0x07;
373
374 PDPRINTK("Set mdma regs... \n");
Alan Coxd2a84f42007-09-20 15:07:12 +0100375 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400376
377 ctcr0 &= 0x0000ffff;
378 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
379 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
380
Alan Coxd2a84f42007-09-20 15:07:12 +0100381 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400382 PDPRINTK("Set mdma regs done\n");
383
384 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
385 } else {
386 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
387 }
388}
389
390/**
Alan Cox9bedb792007-04-11 00:19:00 +0100391 * pdc2027x_set_mode - Set the timing registers back to correct values.
Tejun Heo02607312007-08-06 18:36:23 +0900392 * @link: link to configure
Alan Cox9bedb792007-04-11 00:19:00 +0100393 * @r_failed: Returned device for failure
Jeff Garzik669a5db2006-08-29 18:12:40 -0400394 *
395 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
396 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
397 * This function overwrites the possibly incorrect values set by the hardware to be correct.
398 */
Tejun Heo02607312007-08-06 18:36:23 +0900399static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400{
Tejun Heo02607312007-08-06 18:36:23 +0900401 struct ata_port *ap = link->ap;
Tejun Heof58229f2007-08-06 18:36:23 +0900402 struct ata_device *dev;
403 int rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400404
Tejun Heo02607312007-08-06 18:36:23 +0900405 rc = ata_do_set_mode(link, r_failed);
Tejun Heof58229f2007-08-06 18:36:23 +0900406 if (rc < 0)
407 return rc;
Alan Cox9bedb792007-04-11 00:19:00 +0100408
Tejun Heo02607312007-08-06 18:36:23 +0900409 ata_link_for_each_dev(dev, link) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400410 if (ata_dev_enabled(dev)) {
411
412 pdc2027x_set_piomode(ap, dev);
413
414 /*
415 * Enable prefetch if the device support PIO only.
416 */
417 if (dev->xfer_shift == ATA_SHIFT_PIO) {
Alan Coxd2a84f42007-09-20 15:07:12 +0100418 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400419 ctcr1 |= (1 << 25);
Alan Coxd2a84f42007-09-20 15:07:12 +0100420 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400421
422 PDPRINTK("Turn on prefetch\n");
423 } else {
424 pdc2027x_set_dmamode(ap, dev);
425 }
426 }
427 }
Alan Cox9bedb792007-04-11 00:19:00 +0100428 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400429}
430
431/**
432 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
433 * @qc: Metadata associated with taskfile to check
434 *
435 * LOCKING:
436 * None (inherited from caller).
437 *
438 * RETURNS: 0 when ATAPI DMA can be used
439 * 1 otherwise
440 */
441static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
442{
443 struct scsi_cmnd *cmd = qc->scsicmd;
444 u8 *scsicmd = cmd->cmnd;
445 int rc = 1; /* atapi dma off by default */
446
447 /*
448 * This workaround is from Promise's GPL driver.
449 * If ATAPI DMA is used for commands not in the
450 * following white list, say MODE_SENSE and REQUEST_SENSE,
451 * pdc2027x might hit the irq lost problem.
452 */
453 switch (scsicmd[0]) {
454 case READ_10:
455 case WRITE_10:
456 case READ_12:
457 case WRITE_12:
458 case READ_6:
459 case WRITE_6:
460 case 0xad: /* READ_DVD_STRUCTURE */
461 case 0xbe: /* READ_CD */
462 /* ATAPI DMA is ok */
463 rc = 0;
464 break;
465 default:
466 ;
467 }
468
469 return rc;
470}
471
472/**
473 * pdc_read_counter - Read the ctr counter
Tejun Heo5d728822007-04-17 23:44:08 +0900474 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400475 */
476
Tejun Heo5d728822007-04-17 23:44:08 +0900477static long pdc_read_counter(struct ata_host *host)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400478{
Tejun Heo5d728822007-04-17 23:44:08 +0900479 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400480 long counter;
481 int retry = 1;
482 u32 bccrl, bccrh, bccrlv, bccrhv;
483
484retry:
Alan Coxd2a84f42007-09-20 15:07:12 +0100485 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
486 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400487
488 /* Read the counter values again for verification */
Alan Coxd2a84f42007-09-20 15:07:12 +0100489 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
490 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400491
492 counter = (bccrh << 15) | bccrl;
493
494 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
495 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
496
497 /*
498 * The 30-bit decreasing counter are read by 2 pieces.
499 * Incorrect value may be read when both bccrh and bccrl are changing.
500 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
501 */
502 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
503 retry--;
504 PDPRINTK("rereading counter\n");
505 goto retry;
506 }
507
508 return counter;
509}
510
511/**
512 * adjust_pll - Adjust the PLL input clock in Hz.
513 *
514 * @pdc_controller: controller specific information
Tejun Heo5d728822007-04-17 23:44:08 +0900515 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400516 * @pll_clock: The input of PLL in HZ
517 */
Tejun Heo5d728822007-04-17 23:44:08 +0900518static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400519{
Tejun Heo5d728822007-04-17 23:44:08 +0900520 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400521 u16 pll_ctl;
522 long pll_clock_khz = pll_clock / 1000;
523 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
524 long ratio = pout_required / pll_clock_khz;
525 int F, R;
526
527 /* Sanity check */
528 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
529 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
530 return;
531 }
532
533#ifdef PDC_DEBUG
534 PDPRINTK("pout_required is %ld\n", pout_required);
535
536 /* Show the current clock value of PLL control register
537 * (maybe already configured by the firmware)
538 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100539 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400540
541 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
542#endif
543
544 /*
545 * Calculate the ratio of F, R and OD
546 * POUT = (F + 2) / (( R + 2) * NO)
547 */
548 if (ratio < 8600L) { /* 8.6x */
549 /* Using NO = 0x01, R = 0x0D */
550 R = 0x0d;
551 } else if (ratio < 12900L) { /* 12.9x */
552 /* Using NO = 0x01, R = 0x08 */
553 R = 0x08;
554 } else if (ratio < 16100L) { /* 16.1x */
555 /* Using NO = 0x01, R = 0x06 */
556 R = 0x06;
557 } else if (ratio < 64000L) { /* 64x */
558 R = 0x00;
559 } else {
560 /* Invalid ratio */
561 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
562 return;
563 }
564
565 F = (ratio * (R+2)) / 1000 - 2;
566
567 if (unlikely(F < 0 || F > 127)) {
568 /* Invalid F */
569 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
570 return;
571 }
572
573 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
574
575 pll_ctl = (R << 8) | F;
576
577 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
578
Alan Coxd2a84f42007-09-20 15:07:12 +0100579 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
580 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400581
582 /* Wait the PLL circuit to be stable */
583 mdelay(30);
584
585#ifdef PDC_DEBUG
586 /*
587 * Show the current clock value of PLL control register
588 * (maybe configured by the firmware)
589 */
Alan Coxd2a84f42007-09-20 15:07:12 +0100590 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591
592 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
593#endif
594
595 return;
596}
597
598/**
599 * detect_pll_input_clock - Detect the PLL input clock in Hz.
Tejun Heo5d728822007-04-17 23:44:08 +0900600 * @host: target ATA host
Jeff Garzik669a5db2006-08-29 18:12:40 -0400601 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
602 * Half of the PCI clock.
603 */
Tejun Heo5d728822007-04-17 23:44:08 +0900604static long pdc_detect_pll_input_clock(struct ata_host *host)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400605{
Tejun Heo5d728822007-04-17 23:44:08 +0900606 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400607 u32 scr;
608 long start_count, end_count;
Albert Lee8c781bf2007-06-26 13:43:15 +0800609 struct timeval start_time, end_time;
610 long pll_clock, usec_elapsed;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400611
Jeff Garzik669a5db2006-08-29 18:12:40 -0400612 /* Start the test mode */
Alan Coxd2a84f42007-09-20 15:07:12 +0100613 scr = ioread32(mmio_base + PDC_SYS_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400614 PDPRINTK("scr[%X]\n", scr);
Alan Coxd2a84f42007-09-20 15:07:12 +0100615 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
616 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400617
Mikael Pettersson78c4af02007-08-18 22:58:53 +0200618 /* Read current counter value */
619 start_count = pdc_read_counter(host);
620 do_gettimeofday(&start_time);
621
Jeff Garzik669a5db2006-08-29 18:12:40 -0400622 /* Let the counter run for 100 ms. */
623 mdelay(100);
624
625 /* Read the counter values again */
Tejun Heo5d728822007-04-17 23:44:08 +0900626 end_count = pdc_read_counter(host);
Albert Lee8c781bf2007-06-26 13:43:15 +0800627 do_gettimeofday(&end_time);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400628
629 /* Stop the test mode */
Alan Coxd2a84f42007-09-20 15:07:12 +0100630 scr = ioread32(mmio_base + PDC_SYS_CTL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400631 PDPRINTK("scr[%X]\n", scr);
Alan Coxd2a84f42007-09-20 15:07:12 +0100632 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
633 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400634
635 /* calculate the input clock in Hz */
Albert Lee8c781bf2007-06-26 13:43:15 +0800636 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
637 (end_time.tv_usec - start_time.tv_usec);
638
Mikael Pettersson78c4af02007-08-18 22:58:53 +0200639 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
Albert Lee8c781bf2007-06-26 13:43:15 +0800640 (100000000 / usec_elapsed);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400641
642 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
643 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
644
645 return pll_clock;
646}
647
648/**
649 * pdc_hardware_init - Initialize the hardware.
Tejun Heo5d728822007-04-17 23:44:08 +0900650 * @host: target ATA host
651 * @board_idx: board identifier
Jeff Garzik669a5db2006-08-29 18:12:40 -0400652 */
Tejun Heo5d728822007-04-17 23:44:08 +0900653static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400654{
655 long pll_clock;
656
657 /*
658 * Detect PLL input clock rate.
659 * On some system, where PCI bus is running at non-standard clock rate.
660 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
661 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
662 */
Tejun Heo5d728822007-04-17 23:44:08 +0900663 pll_clock = pdc_detect_pll_input_clock(host);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400664
Tejun Heo5d728822007-04-17 23:44:08 +0900665 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400666
667 /* Adjust PLL control register */
Tejun Heo5d728822007-04-17 23:44:08 +0900668 pdc_adjust_pll(host, pll_clock, board_idx);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400669
670 return 0;
671}
672
673/**
674 * pdc_ata_setup_port - setup the mmio address
675 * @port: ata ioports to setup
676 * @base: base address
677 */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900678static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400679{
680 port->cmd_addr =
681 port->data_addr = base;
682 port->feature_addr =
683 port->error_addr = base + 0x05;
684 port->nsect_addr = base + 0x0a;
685 port->lbal_addr = base + 0x0f;
686 port->lbam_addr = base + 0x10;
687 port->lbah_addr = base + 0x15;
688 port->device_addr = base + 0x1a;
689 port->command_addr =
690 port->status_addr = base + 0x1f;
691 port->altstatus_addr =
692 port->ctl_addr = base + 0x81a;
693}
694
695/**
696 * pdc2027x_init_one - PCI probe function
697 * Called when an instance of PCI adapter is inserted.
698 * This function checks whether the hardware is supported,
699 * initialize hardware and register an instance of ata_host to
Tejun Heo5d728822007-04-17 23:44:08 +0900700 * libata. (implements struct pci_driver.probe() )
Jeff Garzik669a5db2006-08-29 18:12:40 -0400701 *
702 * @pdev: instance of pci_dev found
703 * @ent: matching entry in the id_tbl[]
704 */
705static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
706{
707 static int printed_version;
Tejun Heocbcdd872007-08-18 13:14:55 +0900708 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
709 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400710 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900711 const struct ata_port_info *ppi[] =
712 { &pdc2027x_port_info[board_idx], NULL };
713 struct ata_host *host;
Al Viro7c250412006-09-25 02:57:57 +0100714 void __iomem *mmio_base;
Tejun Heocbcdd872007-08-18 13:14:55 +0900715 int i, rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400716
717 if (!printed_version++)
718 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
719
Tejun Heo5d728822007-04-17 23:44:08 +0900720 /* alloc host */
721 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
722 if (!host)
723 return -ENOMEM;
724
725 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900726 rc = pcim_enable_device(pdev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400727 if (rc)
728 return rc;
729
Tejun Heo0d5ff562007-02-01 15:06:36 +0900730 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400731 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900732 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +0900733 host->iomap = pcim_iomap_table(pdev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400734
735 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
736 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900737 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400738
739 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
740 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900741 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400742
Tejun Heo5d728822007-04-17 23:44:08 +0900743 mmio_base = host->iomap[PDC_MMIO_BAR];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400744
Tejun Heocbcdd872007-08-18 13:14:55 +0900745 for (i = 0; i < 2; i++) {
746 struct ata_port *ap = host->ports[i];
747
748 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
749 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
750
751 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
752 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
753 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400754
Jeff Garzik669a5db2006-08-29 18:12:40 -0400755 //pci_enable_intx(pdev);
756
757 /* initialize adapter */
Tejun Heo5d728822007-04-17 23:44:08 +0900758 if (pdc_hardware_init(host, board_idx) != 0)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900759 return -EIO;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400760
Tejun Heo5d728822007-04-17 23:44:08 +0900761 pci_set_master(pdev);
Tejun Heo9363c382008-04-07 22:47:16 +0900762 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
763 IRQF_SHARED, &pdc2027x_sht);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400764}
765
766/**
767 * pdc2027x_init - Called after this module is loaded into the kernel.
768 */
769static int __init pdc2027x_init(void)
770{
Henrik Kretzschmar72dc6792006-10-10 14:29:24 -0700771 return pci_register_driver(&pdc2027x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400772}
773
774/**
775 * pdc2027x_exit - Called before this module unloaded from the kernel
776 */
777static void __exit pdc2027x_exit(void)
778{
779 pci_unregister_driver(&pdc2027x_pci_driver);
780}
781
782module_init(pdc2027x_init);
783module_exit(pdc2027x_exit);