Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 1 | /* |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 2 | * Copyright (C) 2002,2003 Intrinsyc Software |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | * |
| 18 | * History: |
| 19 | * 31-Jul-2002 : Initial version [FB] |
| 20 | * 29-Jan-2003 : added PXA255 support [FB] |
| 21 | * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) |
| 22 | * |
| 23 | * Note: |
| 24 | * This driver may change the memory bus clock rate, but will not do any |
| 25 | * platform specific access timing changes... for example if you have flash |
| 26 | * memory connected to CS0, you will need to register a platform specific |
| 27 | * notifier which will adjust the memory access strobes to maintain a |
| 28 | * minimum strobe width. |
| 29 | * |
| 30 | */ |
| 31 | |
| 32 | #include <linux/kernel.h> |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/init.h> |
| 36 | #include <linux/cpufreq.h> |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 37 | #include <linux/err.h> |
| 38 | #include <linux/regulator/consumer.h> |
Marek Vasut | ad68bb9 | 2010-11-03 16:29:35 +0100 | [diff] [blame] | 39 | #include <linux/io.h> |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 40 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 41 | #include <mach/pxa2xx-regs.h> |
Marek Vasut | ad68bb9 | 2010-11-03 16:29:35 +0100 | [diff] [blame] | 42 | #include <mach/smemc.h> |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 43 | |
| 44 | #ifdef DEBUG |
| 45 | static unsigned int freq_debug; |
Randy Dunlap | c710e39 | 2008-02-27 12:11:16 -0800 | [diff] [blame] | 46 | module_param(freq_debug, uint, 0); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 47 | MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); |
| 48 | #else |
| 49 | #define freq_debug 0 |
| 50 | #endif |
| 51 | |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 52 | static struct regulator *vcc_core; |
| 53 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 54 | static unsigned int pxa27x_maxfreq; |
| 55 | module_param(pxa27x_maxfreq, uint, 0); |
| 56 | MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz" |
| 57 | "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)"); |
| 58 | |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 59 | typedef struct { |
| 60 | unsigned int khz; |
| 61 | unsigned int membus; |
| 62 | unsigned int cccr; |
| 63 | unsigned int div2; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 64 | unsigned int cclkcfg; |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 65 | int vmin; |
| 66 | int vmax; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 67 | } pxa_freqs_t; |
| 68 | |
| 69 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 70 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
Philipp Zabel | a10c287 | 2008-06-29 16:53:34 +0200 | [diff] [blame] | 71 | static unsigned int sdram_rows; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 72 | |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 73 | #define CCLKCFG_TURBO 0x1 |
| 74 | #define CCLKCFG_FCS 0x2 |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 75 | #define CCLKCFG_HALFTURBO 0x4 |
| 76 | #define CCLKCFG_FASTBUS 0x8 |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 77 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
| 78 | #define MDREFR_DRI_MASK 0xFFF |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 79 | |
Philipp Zabel | a10c287 | 2008-06-29 16:53:34 +0200 | [diff] [blame] | 80 | #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) |
| 81 | #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) |
| 82 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 83 | /* |
| 84 | * PXA255 definitions |
| 85 | */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 86 | /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 87 | #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS |
| 88 | |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 89 | static pxa_freqs_t pxa255_run_freqs[] = |
| 90 | { |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 91 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
| 92 | { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ |
| 93 | {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */ |
| 94 | {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */ |
| 95 | {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */ |
| 96 | {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */ |
| 97 | {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 98 | }; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 99 | |
| 100 | /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ |
| 101 | static pxa_freqs_t pxa255_turbo_freqs[] = |
| 102 | { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 103 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 104 | { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ |
| 105 | {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */ |
| 106 | {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */ |
| 107 | {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */ |
| 108 | {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 109 | }; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 110 | |
| 111 | #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) |
| 112 | #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 113 | |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 114 | static struct cpufreq_frequency_table |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 115 | pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1]; |
| 116 | static struct cpufreq_frequency_table |
| 117 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; |
| 118 | |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 119 | static unsigned int pxa255_turbo_table; |
| 120 | module_param(pxa255_turbo_table, uint, 0); |
| 121 | MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); |
| 122 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 123 | /* |
| 124 | * PXA270 definitions |
| 125 | * |
| 126 | * For the PXA27x: |
| 127 | * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. |
| 128 | * |
| 129 | * A = 0 => memory controller clock from table 3-7, |
| 130 | * A = 1 => memory controller clock = system bus clock |
| 131 | * Run mode frequency = 13 MHz * L |
| 132 | * Turbo mode frequency = 13 MHz * L * N |
| 133 | * System bus frequency = 13 MHz * L / (B + 1) |
| 134 | * |
| 135 | * In CCCR: |
| 136 | * A = 1 |
| 137 | * L = 16 oscillator to run mode ratio |
| 138 | * 2N = 6 2 * (turbo mode to run mode ratio) |
| 139 | * |
| 140 | * In CCLKCFG: |
| 141 | * B = 1 Fast bus mode |
| 142 | * HT = 0 Half-Turbo mode |
| 143 | * T = 1 Turbo mode |
| 144 | * |
| 145 | * For now, just support some of the combinations in table 3-7 of |
| 146 | * PXA27x Processor Family Developer's Manual to simplify frequency |
| 147 | * change sequences. |
| 148 | */ |
| 149 | #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) |
| 150 | #define CCLKCFG2(B, HT, T) \ |
| 151 | (CCLKCFG_FCS | \ |
| 152 | ((B) ? CCLKCFG_FASTBUS : 0) | \ |
| 153 | ((HT) ? CCLKCFG_HALFTURBO : 0) | \ |
| 154 | ((T) ? CCLKCFG_TURBO : 0)) |
| 155 | |
| 156 | static pxa_freqs_t pxa27x_freqs[] = { |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 157 | {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 }, |
Dennis O'Brien | 4367216 | 2009-10-10 15:08:52 +0800 | [diff] [blame] | 158 | {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 }, |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 159 | {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 }, |
| 160 | {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 }, |
| 161 | {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 }, |
| 162 | {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 }, |
| 163 | {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 } |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 164 | }; |
| 165 | |
| 166 | #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs) |
| 167 | static struct cpufreq_frequency_table |
| 168 | pxa27x_freq_table[NUM_PXA27x_FREQS+1]; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 169 | |
| 170 | extern unsigned get_clk_frequency_khz(int info); |
| 171 | |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 172 | #ifdef CONFIG_REGULATOR |
| 173 | |
| 174 | static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq) |
| 175 | { |
| 176 | int ret = 0; |
| 177 | int vmin, vmax; |
| 178 | |
| 179 | if (!cpu_is_pxa27x()) |
| 180 | return 0; |
| 181 | |
| 182 | vmin = pxa_freq->vmin; |
| 183 | vmax = pxa_freq->vmax; |
| 184 | if ((vmin == -1) || (vmax == -1)) |
| 185 | return 0; |
| 186 | |
| 187 | ret = regulator_set_voltage(vcc_core, vmin, vmax); |
| 188 | if (ret) |
| 189 | pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n", |
| 190 | vmin, vmax); |
| 191 | return ret; |
| 192 | } |
| 193 | |
Hanjun Guo | 295dbde | 2013-08-13 18:20:09 +0800 | [diff] [blame] | 194 | static void __init pxa_cpufreq_init_voltages(void) |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 195 | { |
| 196 | vcc_core = regulator_get(NULL, "vcc_core"); |
| 197 | if (IS_ERR(vcc_core)) { |
| 198 | pr_info("cpufreq: Didn't find vcc_core regulator\n"); |
| 199 | vcc_core = NULL; |
| 200 | } else { |
| 201 | pr_info("cpufreq: Found vcc_core regulator\n"); |
| 202 | } |
| 203 | } |
| 204 | #else |
| 205 | static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq) |
| 206 | { |
| 207 | return 0; |
| 208 | } |
| 209 | |
Hanjun Guo | 295dbde | 2013-08-13 18:20:09 +0800 | [diff] [blame] | 210 | static void __init pxa_cpufreq_init_voltages(void) { } |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 211 | #endif |
| 212 | |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 213 | static void find_freq_tables(struct cpufreq_frequency_table **freq_table, |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 214 | pxa_freqs_t **pxa_freqs) |
| 215 | { |
| 216 | if (cpu_is_pxa25x()) { |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 217 | if (!pxa255_turbo_table) { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 218 | *pxa_freqs = pxa255_run_freqs; |
| 219 | *freq_table = pxa255_run_freq_table; |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 220 | } else { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 221 | *pxa_freqs = pxa255_turbo_freqs; |
| 222 | *freq_table = pxa255_turbo_freq_table; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 223 | } |
Arnd Bergmann | 7264a2b | 2013-04-25 19:28:57 +0200 | [diff] [blame] | 224 | } else if (cpu_is_pxa27x()) { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 225 | *pxa_freqs = pxa27x_freqs; |
| 226 | *freq_table = pxa27x_freq_table; |
Arnd Bergmann | 7264a2b | 2013-04-25 19:28:57 +0200 | [diff] [blame] | 227 | } else { |
| 228 | BUG(); |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 229 | } |
| 230 | } |
| 231 | |
| 232 | static void pxa27x_guess_max_freq(void) |
| 233 | { |
| 234 | if (!pxa27x_maxfreq) { |
| 235 | pxa27x_maxfreq = 416000; |
| 236 | printk(KERN_INFO "PXA CPU 27x max frequency not defined " |
| 237 | "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n", |
| 238 | pxa27x_maxfreq); |
| 239 | } else { |
| 240 | pxa27x_maxfreq *= 1000; |
| 241 | } |
| 242 | } |
| 243 | |
Philipp Zabel | a10c287 | 2008-06-29 16:53:34 +0200 | [diff] [blame] | 244 | static void init_sdram_rows(void) |
| 245 | { |
Marek Vasut | ad68bb9 | 2010-11-03 16:29:35 +0100 | [diff] [blame] | 246 | uint32_t mdcnfg = __raw_readl(MDCNFG); |
Philipp Zabel | a10c287 | 2008-06-29 16:53:34 +0200 | [diff] [blame] | 247 | unsigned int drac2 = 0, drac0 = 0; |
| 248 | |
| 249 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) |
| 250 | drac2 = MDCNFG_DRAC2(mdcnfg); |
| 251 | |
| 252 | if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) |
| 253 | drac0 = MDCNFG_DRAC0(mdcnfg); |
| 254 | |
| 255 | sdram_rows = 1 << (11 + max(drac0, drac2)); |
| 256 | } |
| 257 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 258 | static u32 mdrefr_dri(unsigned int freq) |
| 259 | { |
Marek Vasut | 3d3d0fb | 2010-06-24 15:57:12 +0200 | [diff] [blame] | 260 | u32 interval = freq * SDRAM_TREF / sdram_rows; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 261 | |
Marek Vasut | 3d3d0fb | 2010-06-24 15:57:12 +0200 | [diff] [blame] | 262 | return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 263 | } |
| 264 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 265 | static unsigned int pxa_cpufreq_get(unsigned int cpu) |
| 266 | { |
| 267 | return get_clk_frequency_khz(0); |
| 268 | } |
| 269 | |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 270 | static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx) |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 271 | { |
| 272 | struct cpufreq_frequency_table *pxa_freqs_table; |
| 273 | pxa_freqs_t *pxa_freq_settings; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 274 | unsigned long flags; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 275 | unsigned int new_freq_cpu, new_freq_mem; |
| 276 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 277 | int ret = 0; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 278 | |
| 279 | /* Get the current policy */ |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 280 | find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 281 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 282 | new_freq_cpu = pxa_freq_settings[idx].khz; |
| 283 | new_freq_mem = pxa_freq_settings[idx].membus; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 284 | |
| 285 | if (freq_debug) |
Joe Perches | d420280 | 2010-09-11 22:10:49 -0700 | [diff] [blame] | 286 | pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 287 | new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ? |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 288 | (new_freq_mem / 2000) : (new_freq_mem / 1000)); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 289 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 290 | if (vcc_core && new_freq_cpu > policy->cur) { |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 291 | ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 292 | if (ret) |
| 293 | return ret; |
| 294 | } |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 295 | |
| 296 | /* Calculate the next MDREFR. If we're slowing down the SDRAM clock |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 297 | * we need to preset the smaller DRI before the change. If we're |
| 298 | * speeding up we need to set the larger DRI value after the change. |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 299 | */ |
Marek Vasut | ad68bb9 | 2010-11-03 16:29:35 +0100 | [diff] [blame] | 300 | preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR); |
| 301 | if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 302 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); |
| 303 | preset_mdrefr |= mdrefr_dri(new_freq_mem); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 304 | } |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 305 | postset_mdrefr = |
| 306 | (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 307 | |
| 308 | /* If we're dividing the memory clock by two for the SDRAM clock, this |
| 309 | * must be set prior to the change. Clearing the divide must be done |
| 310 | * after the change. |
| 311 | */ |
| 312 | if (pxa_freq_settings[idx].div2) { |
| 313 | preset_mdrefr |= MDREFR_DB2_MASK; |
| 314 | postset_mdrefr |= MDREFR_DB2_MASK; |
| 315 | } else { |
| 316 | postset_mdrefr &= ~MDREFR_DB2_MASK; |
| 317 | } |
| 318 | |
| 319 | local_irq_save(flags); |
| 320 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 321 | /* Set new the CCCR and prepare CCLKCFG */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 322 | CCCR = pxa_freq_settings[idx].cccr; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 323 | cclkcfg = pxa_freq_settings[idx].cclkcfg; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 324 | |
| 325 | asm volatile(" \n\ |
| 326 | ldr r4, [%1] /* load MDREFR */ \n\ |
| 327 | b 2f \n\ |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 328 | .align 5 \n\ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 329 | 1: \n\ |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 330 | str %3, [%1] /* preset the MDREFR */ \n\ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 331 | mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 332 | str %4, [%1] /* postset the MDREFR */ \n\ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 333 | \n\ |
| 334 | b 3f \n\ |
| 335 | 2: b 1b \n\ |
| 336 | 3: nop \n\ |
| 337 | " |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 338 | : "=&r" (unused) |
Marek Vasut | ad68bb9 | 2010-11-03 16:29:35 +0100 | [diff] [blame] | 339 | : "r" (MDREFR), "r" (cclkcfg), |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 340 | "r" (preset_mdrefr), "r" (postset_mdrefr) |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 341 | : "r4", "r5"); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 342 | local_irq_restore(flags); |
| 343 | |
| 344 | /* |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 345 | * Even if voltage setting fails, we don't report it, as the frequency |
| 346 | * change succeeded. The voltage reduction is not a critical failure, |
| 347 | * only power savings will suffer from this. |
| 348 | * |
| 349 | * Note: if the voltage change fails, and a return value is returned, a |
| 350 | * bug is triggered (seems a deadlock). Should anybody find out where, |
| 351 | * the "return 0" should become a "return ret". |
| 352 | */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 353 | if (vcc_core && new_freq_cpu < policy->cur) |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 354 | ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); |
| 355 | |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 356 | return 0; |
| 357 | } |
| 358 | |
Eric Miao | 50e77fc | 2010-08-18 11:51:13 +0800 | [diff] [blame] | 359 | static int pxa_cpufreq_init(struct cpufreq_policy *policy) |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 360 | { |
| 361 | int i; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 362 | unsigned int freq; |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 363 | struct cpufreq_frequency_table *pxa255_freq_table; |
| 364 | pxa_freqs_t *pxa255_freqs; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 365 | |
| 366 | /* try to guess pxa27x cpu */ |
| 367 | if (cpu_is_pxa27x()) |
| 368 | pxa27x_guess_max_freq(); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 369 | |
Robert Jarzmik | 3dbeef2 | 2009-05-17 23:03:55 +0200 | [diff] [blame] | 370 | pxa_cpufreq_init_voltages(); |
| 371 | |
Philipp Zabel | a10c287 | 2008-06-29 16:53:34 +0200 | [diff] [blame] | 372 | init_sdram_rows(); |
| 373 | |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 374 | /* set default policy and cpuinfo */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 375 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 376 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 377 | /* Generate pxa25x the run cpufreq_frequency_table struct */ |
| 378 | for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 379 | pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; |
Viresh Kumar | 5070158 | 2013-03-30 16:25:15 +0530 | [diff] [blame] | 380 | pxa255_run_freq_table[i].driver_data = i; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 381 | } |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 382 | pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 383 | |
| 384 | /* Generate pxa25x the turbo cpufreq_frequency_table struct */ |
| 385 | for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 386 | pxa255_turbo_freq_table[i].frequency = |
| 387 | pxa255_turbo_freqs[i].khz; |
Viresh Kumar | 5070158 | 2013-03-30 16:25:15 +0530 | [diff] [blame] | 388 | pxa255_turbo_freq_table[i].driver_data = i; |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 389 | } |
| 390 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; |
| 391 | |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 392 | pxa255_turbo_table = !!pxa255_turbo_table; |
| 393 | |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 394 | /* Generate the pxa27x cpufreq_frequency_table struct */ |
| 395 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { |
| 396 | freq = pxa27x_freqs[i].khz; |
| 397 | if (freq > pxa27x_maxfreq) |
| 398 | break; |
| 399 | pxa27x_freq_table[i].frequency = freq; |
Viresh Kumar | 5070158 | 2013-03-30 16:25:15 +0530 | [diff] [blame] | 400 | pxa27x_freq_table[i].driver_data = i; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 401 | } |
Viresh Kumar | 5070158 | 2013-03-30 16:25:15 +0530 | [diff] [blame] | 402 | pxa27x_freq_table[i].driver_data = i; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 403 | pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; |
| 404 | |
| 405 | /* |
| 406 | * Set the policy's minimum and maximum frequencies from the tables |
| 407 | * just constructed. This sets cpuinfo.mxx_freq, min and max. |
| 408 | */ |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 409 | if (cpu_is_pxa25x()) { |
| 410 | find_freq_tables(&pxa255_freq_table, &pxa255_freqs); |
| 411 | pr_info("PXA255 cpufreq using %s frequency table\n", |
| 412 | pxa255_turbo_table ? "turbo" : "run"); |
Viresh Kumar | 6a77a1e | 2013-09-16 18:56:04 +0530 | [diff] [blame] | 413 | |
Viresh Kumar | 15cc921 | 2013-09-16 18:56:29 +0530 | [diff] [blame] | 414 | cpufreq_table_validate_and_show(policy, pxa255_freq_table); |
Marc Zyngier | 65587f7 | 2008-11-04 13:33:25 +0100 | [diff] [blame] | 415 | } |
Viresh Kumar | 6a77a1e | 2013-09-16 18:56:04 +0530 | [diff] [blame] | 416 | else if (cpu_is_pxa27x()) { |
Viresh Kumar | 15cc921 | 2013-09-16 18:56:29 +0530 | [diff] [blame] | 417 | cpufreq_table_validate_and_show(policy, pxa27x_freq_table); |
Viresh Kumar | 6a77a1e | 2013-09-16 18:56:04 +0530 | [diff] [blame] | 418 | } |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 419 | |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 420 | printk(KERN_INFO "PXA CPU frequency change support initialized\n"); |
| 421 | |
| 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | static struct cpufreq_driver pxa_cpufreq_driver = { |
Viresh Kumar | ae6b427 | 2013-12-03 11:20:45 +0530 | [diff] [blame] | 426 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
Viresh Kumar | bf36e48 | 2013-10-03 20:28:20 +0530 | [diff] [blame] | 427 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 428 | .target_index = pxa_set_target, |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 429 | .init = pxa_cpufreq_init, |
Viresh Kumar | bf36e48 | 2013-10-03 20:28:20 +0530 | [diff] [blame] | 430 | .exit = cpufreq_generic_exit, |
Holger Schurig | ea833f0 | 2008-02-11 16:53:15 +0100 | [diff] [blame] | 431 | .get = pxa_cpufreq_get, |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 432 | .name = "PXA2xx", |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 433 | }; |
| 434 | |
| 435 | static int __init pxa_cpu_init(void) |
| 436 | { |
| 437 | int ret = -ENODEV; |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 438 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 439 | ret = cpufreq_register_driver(&pxa_cpufreq_driver); |
| 440 | return ret; |
| 441 | } |
| 442 | |
| 443 | static void __exit pxa_cpu_exit(void) |
| 444 | { |
Robert Jarzmik | 592eb99 | 2008-05-07 20:39:06 +0100 | [diff] [blame] | 445 | cpufreq_unregister_driver(&pxa_cpufreq_driver); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | |
Robert Jarzmik | 3679389 | 2008-05-07 20:36:34 +0100 | [diff] [blame] | 449 | MODULE_AUTHOR("Intrinsyc Software Inc."); |
| 450 | MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); |
Russell King | 9e2697f | 2007-12-14 13:30:14 +0000 | [diff] [blame] | 451 | MODULE_LICENSE("GPL"); |
| 452 | module_init(pxa_cpu_init); |
| 453 | module_exit(pxa_cpu_exit); |