Mark Brown | be2de99 | 2011-05-10 15:42:08 +0200 | [diff] [blame] | 1 | /* |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 2 | * Copyright 2009 Wolfson Microelectronics plc |
| 3 | * |
| 4 | * S3C64xx CPUfreq Support |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 11 | #define pr_fmt(fmt) "cpufreq: " fmt |
| 12 | |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/types.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/cpufreq.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/regulator/consumer.h> |
Mark Brown | a6ee877 | 2011-07-29 16:19:26 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 21 | |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 22 | static struct regulator *vddarm; |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 23 | static unsigned long regulator_latency; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 24 | |
| 25 | #ifdef CONFIG_CPU_S3C6410 |
| 26 | struct s3c64xx_dvfs { |
| 27 | unsigned int vddarm_min; |
| 28 | unsigned int vddarm_max; |
| 29 | }; |
| 30 | |
| 31 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { |
Mark Brown | e9c08f0 | 2009-11-03 14:42:12 +0000 | [diff] [blame] | 32 | [0] = { 1000000, 1150000 }, |
| 33 | [1] = { 1050000, 1150000 }, |
| 34 | [2] = { 1100000, 1150000 }, |
| 35 | [3] = { 1200000, 1350000 }, |
Mark Brown | c6e2d68 | 2011-06-08 14:49:15 +0100 | [diff] [blame] | 36 | [4] = { 1300000, 1350000 }, |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { |
| 40 | { 0, 66000 }, |
Mark Brown | ef993ef8 | 2011-06-28 20:26:49 -0700 | [diff] [blame] | 41 | { 0, 100000 }, |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 42 | { 0, 133000 }, |
Mark Brown | ef993ef8 | 2011-06-28 20:26:49 -0700 | [diff] [blame] | 43 | { 1, 200000 }, |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 44 | { 1, 222000 }, |
| 45 | { 1, 266000 }, |
| 46 | { 2, 333000 }, |
| 47 | { 2, 400000 }, |
Mark Brown | e9c08f0 | 2009-11-03 14:42:12 +0000 | [diff] [blame] | 48 | { 2, 532000 }, |
| 49 | { 2, 533000 }, |
| 50 | { 3, 667000 }, |
Mark Brown | c6e2d68 | 2011-06-08 14:49:15 +0100 | [diff] [blame] | 51 | { 4, 800000 }, |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 52 | { 0, CPUFREQ_TABLE_END }, |
| 53 | }; |
| 54 | #endif |
| 55 | |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 56 | static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 57 | unsigned int index) |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 58 | { |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 59 | struct s3c64xx_dvfs *dvfs; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 60 | unsigned int old_freq, new_freq; |
| 61 | int ret; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 62 | |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 63 | old_freq = clk_get_rate(policy->clk) / 1000; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 64 | new_freq = s3c64xx_freq_table[index].frequency; |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 65 | dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 66 | |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 67 | #ifdef CONFIG_REGULATOR |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 68 | if (vddarm && new_freq > old_freq) { |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 69 | ret = regulator_set_voltage(vddarm, |
| 70 | dvfs->vddarm_min, |
| 71 | dvfs->vddarm_max); |
| 72 | if (ret != 0) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 73 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 74 | new_freq, ret); |
| 75 | return ret; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | #endif |
| 79 | |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 80 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 81 | if (ret < 0) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 82 | pr_err("Failed to set rate %dkHz: %d\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 83 | new_freq, ret); |
| 84 | return ret; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | #ifdef CONFIG_REGULATOR |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 88 | if (vddarm && new_freq < old_freq) { |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 89 | ret = regulator_set_voltage(vddarm, |
| 90 | dvfs->vddarm_min, |
| 91 | dvfs->vddarm_max); |
| 92 | if (ret != 0) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 93 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 94 | new_freq, ret); |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 95 | if (clk_set_rate(policy->clk, old_freq * 1000) < 0) |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 96 | pr_err("Failed to restore original clock rate\n"); |
| 97 | |
| 98 | return ret; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 99 | } |
| 100 | } |
| 101 | #endif |
| 102 | |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 103 | pr_debug("Set actual frequency %lukHz\n", |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 104 | clk_get_rate(policy->clk) / 1000); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 105 | |
| 106 | return 0; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | #ifdef CONFIG_REGULATOR |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 110 | static void __init s3c64xx_cpufreq_config_regulator(void) |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 111 | { |
| 112 | int count, v, i, found; |
| 113 | struct cpufreq_frequency_table *freq; |
| 114 | struct s3c64xx_dvfs *dvfs; |
| 115 | |
| 116 | count = regulator_count_voltages(vddarm); |
| 117 | if (count < 0) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 118 | pr_err("Unable to check supported voltages\n"); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | freq = s3c64xx_freq_table; |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 122 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 123 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) |
| 124 | continue; |
| 125 | |
Charles Keepax | 0e82443 | 2013-10-14 19:36:47 +0100 | [diff] [blame] | 126 | dvfs = &s3c64xx_dvfs_table[freq->driver_data]; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 127 | found = 0; |
| 128 | |
| 129 | for (i = 0; i < count; i++) { |
| 130 | v = regulator_list_voltage(vddarm, i); |
| 131 | if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) |
| 132 | found = 1; |
| 133 | } |
| 134 | |
| 135 | if (!found) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 136 | pr_debug("%dkHz unsupported by regulator\n", |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 137 | freq->frequency); |
| 138 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
| 139 | } |
| 140 | |
| 141 | freq++; |
| 142 | } |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 143 | |
| 144 | /* Guess based on having to do an I2C/SPI write; in future we |
| 145 | * will be able to query the regulator performance here. */ |
| 146 | regulator_latency = 1 * 1000 * 1000; |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 147 | } |
| 148 | #endif |
| 149 | |
Mark Brown | 6d0de15 | 2011-03-11 16:10:03 +0900 | [diff] [blame] | 150 | static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 151 | { |
| 152 | int ret; |
| 153 | struct cpufreq_frequency_table *freq; |
| 154 | |
| 155 | if (policy->cpu != 0) |
| 156 | return -EINVAL; |
| 157 | |
| 158 | if (s3c64xx_freq_table == NULL) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 159 | pr_err("No frequency information for this CPU\n"); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 160 | return -ENODEV; |
| 161 | } |
| 162 | |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 163 | policy->clk = clk_get(NULL, "armclk"); |
| 164 | if (IS_ERR(policy->clk)) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 165 | pr_err("Unable to obtain ARMCLK: %ld\n", |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 166 | PTR_ERR(policy->clk)); |
| 167 | return PTR_ERR(policy->clk); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | #ifdef CONFIG_REGULATOR |
| 171 | vddarm = regulator_get(NULL, "vddarm"); |
| 172 | if (IS_ERR(vddarm)) { |
| 173 | ret = PTR_ERR(vddarm); |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 174 | pr_err("Failed to obtain VDDARM: %d\n", ret); |
| 175 | pr_err("Only frequency scaling available\n"); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 176 | vddarm = NULL; |
| 177 | } else { |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 178 | s3c64xx_cpufreq_config_regulator(); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 179 | } |
| 180 | #endif |
| 181 | |
| 182 | freq = s3c64xx_freq_table; |
| 183 | while (freq->frequency != CPUFREQ_TABLE_END) { |
| 184 | unsigned long r; |
| 185 | |
| 186 | /* Check for frequencies we can generate */ |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 187 | r = clk_round_rate(policy->clk, freq->frequency * 1000); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 188 | r /= 1000; |
Mark Brown | 383af9c | 2009-11-03 14:42:07 +0000 | [diff] [blame] | 189 | if (r != freq->frequency) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 190 | pr_debug("%dkHz unsupported by clock\n", |
Mark Brown | 383af9c | 2009-11-03 14:42:07 +0000 | [diff] [blame] | 191 | freq->frequency); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 192 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
Mark Brown | 383af9c | 2009-11-03 14:42:07 +0000 | [diff] [blame] | 193 | } |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 194 | |
| 195 | /* If we have no regulator then assume startup |
| 196 | * frequency is the maximum we can support. */ |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 197 | if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 198 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
| 199 | |
| 200 | freq++; |
| 201 | } |
| 202 | |
Mark Brown | 43f1069 | 2009-11-03 14:42:11 +0000 | [diff] [blame] | 203 | /* Datasheet says PLL stabalisation time (if we were to use |
| 204 | * the PLLs, which we don't currently) is ~300us worst case, |
| 205 | * but add some fudge. |
| 206 | */ |
Viresh Kumar | a307a1e | 2013-10-03 20:29:22 +0530 | [diff] [blame] | 207 | ret = cpufreq_generic_init(policy, s3c64xx_freq_table, |
| 208 | (500 * 1000) + regulator_latency); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 209 | if (ret != 0) { |
Mark Brown | a6a4341 | 2011-12-05 18:22:01 +0000 | [diff] [blame] | 210 | pr_err("Failed to configure frequency table: %d\n", |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 211 | ret); |
| 212 | regulator_put(vddarm); |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 213 | clk_put(policy->clk); |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | return ret; |
| 217 | } |
| 218 | |
| 219 | static struct cpufreq_driver s3c64xx_cpufreq_driver = { |
Viresh Kumar | ae6b427 | 2013-12-03 11:20:45 +0530 | [diff] [blame] | 220 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
Viresh Kumar | e96a410 | 2013-10-03 20:28:21 +0530 | [diff] [blame] | 221 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 222 | .target_index = s3c64xx_cpufreq_set_target, |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 223 | .get = cpufreq_generic_get, |
Mark Brown | b3748dd | 2009-06-15 11:23:20 +0100 | [diff] [blame] | 224 | .init = s3c64xx_cpufreq_driver_init, |
| 225 | .name = "s3c", |
| 226 | }; |
| 227 | |
| 228 | static int __init s3c64xx_cpufreq_init(void) |
| 229 | { |
| 230 | return cpufreq_register_driver(&s3c64xx_cpufreq_driver); |
| 231 | } |
| 232 | module_init(s3c64xx_cpufreq_init); |