Mike Frysinger | 16daaf5 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Blackfin On-Chip SPI Driver |
| 3 | * |
| 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 5 | * |
| 6 | * Enter bugs at http://blackfin.uclinux.org/ |
| 7 | * |
| 8 | * Licensed under the GPL-2 or later. |
| 9 | */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | |
| 11 | #ifndef _SPI_CHANNEL_H_ |
| 12 | #define _SPI_CHANNEL_H_ |
| 13 | |
Michael Hennerich | 7513e00 | 2009-04-06 19:00:32 -0700 | [diff] [blame] | 14 | #define MIN_SPI_BAUD_VAL 2 |
| 15 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 16 | #define SPI_READ 0 |
| 17 | #define SPI_WRITE 1 |
| 18 | |
| 19 | #define SPI_CTRL_OFF 0x0 |
| 20 | #define SPI_FLAG_OFF 0x4 |
| 21 | #define SPI_STAT_OFF 0x8 |
| 22 | #define SPI_TXBUFF_OFF 0xc |
| 23 | #define SPI_RXBUFF_OFF 0x10 |
| 24 | #define SPI_BAUD_OFF 0x14 |
| 25 | #define SPI_SHAW_OFF 0x18 |
| 26 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 27 | |
| 28 | #define BIT_CTL_ENABLE 0x4000 |
| 29 | #define BIT_CTL_OPENDRAIN 0x2000 |
| 30 | #define BIT_CTL_MASTER 0x1000 |
| 31 | #define BIT_CTL_POLAR 0x0800 |
| 32 | #define BIT_CTL_PHASE 0x0400 |
| 33 | #define BIT_CTL_BITORDER 0x0200 |
| 34 | #define BIT_CTL_WORDSIZE 0x0100 |
| 35 | #define BIT_CTL_MISOENABLE 0x0020 |
| 36 | #define BIT_CTL_RXMOD 0x0000 |
| 37 | #define BIT_CTL_TXMOD 0x0001 |
| 38 | #define BIT_CTL_TIMOD_DMA_TX 0x0003 |
| 39 | #define BIT_CTL_TIMOD_DMA_RX 0x0002 |
| 40 | #define BIT_CTL_SENDOPT 0x0004 |
| 41 | #define BIT_CTL_TIMOD 0x0003 |
| 42 | |
| 43 | #define BIT_STAT_SPIF 0x0001 |
| 44 | #define BIT_STAT_MODF 0x0002 |
| 45 | #define BIT_STAT_TXE 0x0004 |
| 46 | #define BIT_STAT_TXS 0x0008 |
| 47 | #define BIT_STAT_RBSY 0x0010 |
| 48 | #define BIT_STAT_RXS 0x0020 |
| 49 | #define BIT_STAT_TXCOL 0x0040 |
| 50 | #define BIT_STAT_CLR 0xFFFF |
| 51 | |
| 52 | #define BIT_STU_SENDOVER 0x0001 |
| 53 | #define BIT_STU_RECVFULL 0x0020 |
| 54 | |
| 55 | #define CFG_SPI_ENABLE 1 |
| 56 | #define CFG_SPI_DISABLE 0 |
| 57 | |
| 58 | #define CFG_SPI_OUTENABLE 1 |
| 59 | #define CFG_SPI_OUTDISABLE 0 |
| 60 | |
| 61 | #define CFG_SPI_ACTLOW 1 |
| 62 | #define CFG_SPI_ACTHIGH 0 |
| 63 | |
| 64 | #define CFG_SPI_PHASESTART 1 |
| 65 | #define CFG_SPI_PHASEMID 0 |
| 66 | |
| 67 | #define CFG_SPI_MASTER 1 |
| 68 | #define CFG_SPI_SLAVE 0 |
| 69 | |
| 70 | #define CFG_SPI_SENELAST 0 |
| 71 | #define CFG_SPI_SENDZERO 1 |
| 72 | |
| 73 | #define CFG_SPI_RCVFLUSH 1 |
| 74 | #define CFG_SPI_RCVDISCARD 0 |
| 75 | |
| 76 | #define CFG_SPI_LSBFIRST 1 |
| 77 | #define CFG_SPI_MSBFIRST 0 |
| 78 | |
| 79 | #define CFG_SPI_WORDSIZE16 1 |
| 80 | #define CFG_SPI_WORDSIZE8 0 |
| 81 | |
| 82 | #define CFG_SPI_MISOENABLE 1 |
| 83 | #define CFG_SPI_MISODISABLE 0 |
| 84 | |
| 85 | #define CFG_SPI_READ 0x00 |
| 86 | #define CFG_SPI_WRITE 0x01 |
| 87 | #define CFG_SPI_DMAREAD 0x02 |
| 88 | #define CFG_SPI_DMAWRITE 0x03 |
| 89 | |
| 90 | #define CFG_SPI_CSCLEARALL 0 |
| 91 | #define CFG_SPI_CHIPSEL1 1 |
| 92 | #define CFG_SPI_CHIPSEL2 2 |
| 93 | #define CFG_SPI_CHIPSEL3 3 |
| 94 | #define CFG_SPI_CHIPSEL4 4 |
| 95 | #define CFG_SPI_CHIPSEL5 5 |
| 96 | #define CFG_SPI_CHIPSEL6 6 |
| 97 | #define CFG_SPI_CHIPSEL7 7 |
| 98 | |
| 99 | #define CFG_SPI_CS1VALUE 1 |
| 100 | #define CFG_SPI_CS2VALUE 2 |
| 101 | #define CFG_SPI_CS3VALUE 3 |
| 102 | #define CFG_SPI_CS4VALUE 4 |
| 103 | #define CFG_SPI_CS5VALUE 5 |
| 104 | #define CFG_SPI_CS6VALUE 6 |
| 105 | #define CFG_SPI_CS7VALUE 7 |
| 106 | |
Michael Hennerich | 6e66893 | 2008-02-09 01:54:09 +0800 | [diff] [blame] | 107 | #define CMD_SPI_SET_BAUDRATE 2 |
| 108 | #define CMD_SPI_GET_SYSTEMCLOCK 25 |
| 109 | #define CMD_SPI_SET_WRITECONTINUOUS 26 |
| 110 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 111 | /* device.platform_data for SSP controller devices */ |
| 112 | struct bfin5xx_spi_master { |
| 113 | u16 num_chipselect; |
| 114 | u8 enable_dma; |
Cliff Cai | 1eb19e3 | 2009-03-28 23:31:43 +0800 | [diff] [blame] | 115 | u16 pin_req[7]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | /* spi_board_info.controller_data for SPI slave devices, |
| 119 | * copied to spi_device.platform_data ... mostly for dma tuning |
| 120 | */ |
| 121 | struct bfin5xx_spi_chip { |
| 122 | u16 ctl_reg; |
| 123 | u8 enable_dma; |
| 124 | u8 bits_per_word; |
| 125 | u8 cs_change_per_word; |
Bryan Wu | 62310e5 | 2007-12-04 23:45:20 -0800 | [diff] [blame] | 126 | u16 cs_chg_udelay; /* Some devices require 16-bit delays */ |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame^] | 127 | u32 cs_gpio; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 128 | }; |
| 129 | |
| 130 | #endif /* _SPI_CHANNEL_H_ */ |