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Jeff Garzikdd4969a2009-05-08 17:44:01 -04001/*
Andy Yan20b09c22009-05-08 17:46:40 -04002 * Marvell 88SE64xx/88SE94xx main function head file
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
Xiangliang Yu0b15fb12011-04-26 06:36:51 -07006 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
Andy Yan20b09c22009-05-08 17:46:40 -04007 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
Jeff Garzikdd4969a2009-05-08 17:44:01 -040025
26#ifndef _MV_SAS_H_
27#define _MV_SAS_H_
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/spinlock.h>
32#include <linux/delay.h>
33#include <linux/types.h>
34#include <linux/ctype.h>
35#include <linux/dma-mapping.h>
36#include <linux/pci.h>
37#include <linux/platform_device.h>
38#include <linux/interrupt.h>
39#include <linux/irq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Jeff Garzikdd4969a2009-05-08 17:44:01 -040041#include <linux/vmalloc.h>
42#include <scsi/libsas.h>
Srinivas9dc9fd92010-02-15 00:00:00 -060043#include <scsi/scsi.h>
Jeff Garzikdd4969a2009-05-08 17:44:01 -040044#include <scsi/scsi_tcq.h>
45#include <scsi/sas_ata.h>
Jeff Garzikdd4969a2009-05-08 17:44:01 -040046#include "mv_defs.h"
47
Andy Yan20b09c22009-05-08 17:46:40 -040048#define DRV_NAME "mvsas"
Xiangliang Yu4f3f8122011-09-29 00:35:38 -070049#define DRV_VERSION "0.8.16"
Jeff Garzikdd4969a2009-05-08 17:44:01 -040050#define MVS_ID_NOT_MAPPED 0x7f
Andy Yan20b09c22009-05-08 17:46:40 -040051#define WIDE_PORT_MAX_PHY 4
Andy Yan20b09c22009-05-08 17:46:40 -040052#define mv_printk(fmt, arg ...) \
53 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
54#ifdef MV_DEBUG
55#define mv_dprintk(format, arg...) \
56 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
57#else
58#define mv_dprintk(format, arg...)
59#endif
60#define MV_MAX_U32 0xffffffff
Jeff Garzikdd4969a2009-05-08 17:44:01 -040061
Xiangliang Yu83c7b612011-05-24 22:31:47 +080062extern int interrupt_coalescing;
Andy Yan20b09c22009-05-08 17:46:40 -040063extern struct mvs_tgt_initiator mvs_tgt;
64extern struct mvs_info *tgt_mvi;
65extern const struct mvs_dispatch mvs_64xx_dispatch;
66extern const struct mvs_dispatch mvs_94xx_dispatch;
Xiangliang Yu0b15fb12011-04-26 06:36:51 -070067extern struct kmem_cache *mvs_task_list_cache;
Andy Yan20b09c22009-05-08 17:46:40 -040068
69#define DEV_IS_EXPANDER(type) \
James Bottomleyaa9f8322013-05-07 14:44:06 -070070 ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
Andy Yan20b09c22009-05-08 17:46:40 -040071
Xi Wangbeecade2012-11-16 14:40:03 -050072#define bit(n) ((u64)1 << n)
Andy Yan20b09c22009-05-08 17:46:40 -040073
74#define for_each_phy(__lseq_mask, __mc, __lseq) \
75 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
76 (__mc) != 0 ; \
Jeff Garzikdd4969a2009-05-08 17:44:01 -040077 (++__lseq), (__mc) >>= 1)
78
Xiangliang Yu7c237c52013-01-30 00:25:53 +080079#define MVS_PHY_ID (1U << sas_phy->id)
Andy Yan20b09c22009-05-08 17:46:40 -040080#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
81#define UNASSOC_D2H_FIS(id) \
82 ((void *) mvi->rx_fis + 0x100 * id)
83#define SATA_RECEIVED_FIS_LIST(reg_set) \
84 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
85#define SATA_RECEIVED_SDB_FIS(reg_set) \
86 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
87#define SATA_RECEIVED_D2H_FIS(reg_set) \
88 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
89#define SATA_RECEIVED_PIO_FIS(reg_set) \
90 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
91#define SATA_RECEIVED_DMA_FIS(reg_set) \
92 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
93
94enum dev_status {
95 MVS_DEV_NORMAL = 0x0,
96 MVS_DEV_EH = 0x1,
Jeff Garzikdd4969a2009-05-08 17:44:01 -040097};
98
Xiangliang Yua4632aa2011-05-24 22:36:02 +080099enum dev_reset {
100 MVS_SOFT_RESET = 0,
101 MVS_HARD_RESET = 1,
102 MVS_PHY_TUNE = 2,
103};
Andy Yan20b09c22009-05-08 17:46:40 -0400104
105struct mvs_info;
106
107struct mvs_dispatch {
108 char *name;
109 int (*chip_init)(struct mvs_info *mvi);
110 int (*spi_init)(struct mvs_info *mvi);
111 int (*chip_ioremap)(struct mvs_info *mvi);
112 void (*chip_iounmap)(struct mvs_info *mvi);
113 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
114 u32 (*isr_status)(struct mvs_info *mvi, int irq);
115 void (*interrupt_enable)(struct mvs_info *mvi);
116 void (*interrupt_disable)(struct mvs_info *mvi);
117
118 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
119 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
120
121 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
122 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
123 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
124
125 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
126 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
127 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
128
129 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
130 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
131
132 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
133 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
134
Andy Yan20b09c22009-05-08 17:46:40 -0400135 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
Srinivas9dc9fd92010-02-15 00:00:00 -0600136 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
Andy Yan20b09c22009-05-08 17:46:40 -0400137 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
138 u32 tfs);
139 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
140 u32 (*rx_update)(struct mvs_info *mvi);
141 void (*int_full)(struct mvs_info *mvi);
142 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
143 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
144 u32 (*prd_size)(void);
145 u32 (*prd_count)(void);
146 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
147 void (*detect_porttype)(struct mvs_info *mvi, int i);
148 int (*oob_done)(struct mvs_info *mvi, int i);
149 void (*fix_phy_info)(struct mvs_info *mvi, int i,
150 struct sas_identify_frame *id);
151 void (*phy_work_around)(struct mvs_info *mvi, int i);
152 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
153 struct sas_phy_linkrates *rates);
154 u32 (*phy_max_link_rate)(void);
155 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
156 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
157 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
158 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
159 void (*clear_active_cmds)(struct mvs_info *mvi);
160 u32 (*spi_read_data)(struct mvs_info *mvi);
161 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
162 int (*spi_buildcmd)(struct mvs_info *mvi,
163 u32 *dwCmd,
164 u8 cmd,
165 u8 read,
166 u8 length,
167 u32 addr
168 );
169 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
170 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
Xiangliang Yu8882f082011-05-24 22:33:11 +0800171 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
172 int buf_len, int from, void *prd);
Xiangliang Yu83c7b612011-05-24 22:31:47 +0800173 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
Xiangliang Yu534ff102011-05-24 22:26:50 +0800174 void (*non_spec_ncq_error)(struct mvs_info *mvi);
Andy Yan20b09c22009-05-08 17:46:40 -0400175
176};
177
178struct mvs_chip_info {
179 u32 n_host;
180 u32 n_phy;
181 u32 fis_offs;
182 u32 fis_count;
183 u32 srs_sz;
Xiangliang Yua4632aa2011-05-24 22:36:02 +0800184 u32 sg_width;
Andy Yan20b09c22009-05-08 17:46:40 -0400185 u32 slot_width;
186 const struct mvs_dispatch *dispatch;
187};
Xiangliang Yua4632aa2011-05-24 22:36:02 +0800188#define MVS_MAX_SG (1U << mvi->chip->sg_width)
Andy Yan20b09c22009-05-08 17:46:40 -0400189#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
190#define MVS_RX_FISL_SZ \
191 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
192#define MVS_CHIP_DISP (mvi->chip->dispatch)
193
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400194struct mvs_err_info {
195 __le32 flags;
196 __le32 flags2;
197};
198
199struct mvs_cmd_hdr {
200 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
201 __le32 lens; /* cmd, max resp frame len */
202 __le32 tags; /* targ port xfer tag; tag */
203 __le32 data_len; /* data xfer len */
Andy Yan20b09c22009-05-08 17:46:40 -0400204 __le64 cmd_tbl; /* command table address */
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400205 __le64 open_frame; /* open addr frame address */
206 __le64 status_buf; /* status buffer address */
207 __le64 prd_tbl; /* PRD tbl address */
208 __le32 reserved[4];
209};
210
211struct mvs_port {
212 struct asd_sas_port sas_port;
213 u8 port_attached;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400214 u8 wide_port_phymap;
215 struct list_head list;
216};
217
218struct mvs_phy {
Andy Yan20b09c22009-05-08 17:46:40 -0400219 struct mvs_info *mvi;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400220 struct mvs_port *port;
221 struct asd_sas_phy sas_phy;
222 struct sas_identify identify;
223 struct scsi_device *sdev;
Andy Yan20b09c22009-05-08 17:46:40 -0400224 struct timer_list timer;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400225 u64 dev_sas_addr;
226 u64 att_dev_sas_addr;
227 u32 att_dev_info;
228 u32 dev_info;
229 u32 phy_type;
230 u32 phy_status;
231 u32 irq_status;
232 u32 frame_rcvd_size;
233 u8 frame_rcvd[32];
234 u8 phy_attached;
Andy Yan20b09c22009-05-08 17:46:40 -0400235 u8 phy_mode;
236 u8 reserved[2];
237 u32 phy_event;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400238 enum sas_linkrate minimum_linkrate;
239 enum sas_linkrate maximum_linkrate;
240};
241
Andy Yan20b09c22009-05-08 17:46:40 -0400242struct mvs_device {
Andy Yan9870d9a2009-05-11 22:19:25 +0800243 struct list_head dev_entry;
James Bottomleyaa9f8322013-05-07 14:44:06 -0700244 enum sas_device_type dev_type;
Andy Yan9870d9a2009-05-11 22:19:25 +0800245 struct mvs_info *mvi_info;
Andy Yan20b09c22009-05-08 17:46:40 -0400246 struct domain_device *sas_device;
Srinivas9dc9fd92010-02-15 00:00:00 -0600247 struct timer_list timer;
Andy Yan20b09c22009-05-08 17:46:40 -0400248 u32 attached_phy;
249 u32 device_id;
Srinivas9dc9fd92010-02-15 00:00:00 -0600250 u32 running_req;
Andy Yan20b09c22009-05-08 17:46:40 -0400251 u8 taskfileset;
252 u8 dev_status;
253 u16 reserved;
Andy Yan20b09c22009-05-08 17:46:40 -0400254};
255
Xiangliang Yuf1f82a92011-05-24 22:28:31 +0800256/* Generate PHY tunning parameters */
257struct phy_tuning {
258 /* 1 bit, transmitter emphasis enable */
259 u8 trans_emp_en:1;
260 /* 4 bits, transmitter emphasis amplitude */
261 u8 trans_emp_amp:4;
262 /* 3 bits, reserved space */
263 u8 Reserved_2bit_1:3;
264 /* 5 bits, transmitter amplitude */
265 u8 trans_amp:5;
266 /* 2 bits, transmitter amplitude adjust */
267 u8 trans_amp_adj:2;
268 /* 1 bit, reserved space */
269 u8 resv_2bit_2:1;
270 /* 2 bytes, reserved space */
271 u8 reserved[2];
272};
273
274struct ffe_control {
275 /* 4 bits, FFE Capacitor Select (value range 0~F) */
276 u8 ffe_cap_sel:4;
277 /* 3 bits, FFE Resistor Select (value range 0~7) */
278 u8 ffe_rss_sel:3;
279 /* 1 bit reserve*/
280 u8 reserved:1;
281};
282
283/*
284 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
285 * The data area is valid only Signature="MRVL".
286 * If any member fills with 0xFF, the member is invalid.
287 */
288struct hba_info_page {
289 /* Dword 0 */
290 /* 4 bytes, structure signature,should be "MRVL" at first initial */
291 u8 signature[4];
292
293 /* Dword 1-13 */
294 u32 reserved1[13];
295
296 /* Dword 14-29 */
297 /* 64 bytes, SAS address for each port */
298 u64 sas_addr[8];
299
300 /* Dword 30-31 */
301 /* 8 bytes for vanir 8 port PHY FFE seeting
302 * BIT 0~3 : FFE Capacitor select(value range 0~F)
303 * BIT 4~6 : FFE Resistor select(value range 0~7)
304 * BIT 7: reserve.
305 */
306
307 struct ffe_control ffe_ctl[8];
308 /* Dword 32 -43 */
309 u32 reserved2[12];
310
311 /* Dword 44-45 */
312 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
313 u8 phy_rate[8];
314
315 /* Dword 46-53 */
316 /* 32 bytes, PHY tuning parameters for each PHY*/
317 struct phy_tuning phy_tuning[8];
318
319 /* Dword 54-63 */
320 u32 reserved3[10];
321}; /* total 256 bytes */
322
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400323struct mvs_slot_info {
Andy Yan20b09c22009-05-08 17:46:40 -0400324 struct list_head entry;
325 union {
326 struct sas_task *task;
327 void *tdata;
328 };
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400329 u32 n_elem;
330 u32 tx;
Andy Yan20b09c22009-05-08 17:46:40 -0400331 u32 slot_tag;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400332
333 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
334 * and PRD table
335 */
336 void *buf;
337 dma_addr_t buf_dma;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400338 void *response;
339 struct mvs_port *port;
Andy Yan20b09c22009-05-08 17:46:40 -0400340 struct mvs_device *device;
341 void *open_frame;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400342};
343
344struct mvs_info {
345 unsigned long flags;
346
347 /* host-wide lock */
348 spinlock_t lock;
349
350 /* our device */
351 struct pci_dev *pdev;
Andy Yan20b09c22009-05-08 17:46:40 -0400352 struct device *dev;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400353
354 /* enhanced mode registers */
355 void __iomem *regs;
356
Andy Yan20b09c22009-05-08 17:46:40 -0400357 /* peripheral or soc registers */
358 void __iomem *regs_ex;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400359 u8 sas_addr[SAS_ADDR_SIZE];
360
361 /* SCSI/SAS glue */
Andy Yan20b09c22009-05-08 17:46:40 -0400362 struct sas_ha_struct *sas;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400363 struct Scsi_Host *shost;
364
365 /* TX (delivery) DMA ring */
366 __le32 *tx;
367 dma_addr_t tx_dma;
368
369 /* cached next-producer idx */
370 u32 tx_prod;
371
372 /* RX (completion) DMA ring */
Andy Yan20b09c22009-05-08 17:46:40 -0400373 __le32 *rx;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400374 dma_addr_t rx_dma;
375
376 /* RX consumer idx */
377 u32 rx_cons;
378
379 /* RX'd FIS area */
380 __le32 *rx_fis;
381 dma_addr_t rx_fis_dma;
382
383 /* DMA command header slots */
384 struct mvs_cmd_hdr *slot;
385 dma_addr_t slot_dma;
386
Andy Yan20b09c22009-05-08 17:46:40 -0400387 u32 chip_id;
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400388 const struct mvs_chip_info *chip;
389
Andy Yan20b09c22009-05-08 17:46:40 -0400390 int tags_num;
Xiangliang Yub89e8f52011-05-24 22:35:09 +0800391 unsigned long *tags;
Andy Yan20b09c22009-05-08 17:46:40 -0400392 /* further per-slot information */
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400393 struct mvs_phy phy[MVS_MAX_PHYS];
394 struct mvs_port port[MVS_MAX_PHYS];
Andy Yan20b09c22009-05-08 17:46:40 -0400395 u32 id;
396 u64 sata_reg_set;
397 struct list_head *hba_list;
398 struct list_head soc_entry;
399 struct list_head wq_list;
400 unsigned long instance;
401 u16 flashid;
402 u32 flashsize;
403 u32 flashsectSize;
404
405 void *addon;
Xiangliang Yuf1f82a92011-05-24 22:28:31 +0800406 struct hba_info_page hba_info_param;
Andy Yan20b09c22009-05-08 17:46:40 -0400407 struct mvs_device devices[MVS_MAX_DEVICES];
Andy Yan20b09c22009-05-08 17:46:40 -0400408 void *bulk_buffer;
409 dma_addr_t bulk_buffer_dma;
Xiangliang Yu8882f082011-05-24 22:33:11 +0800410 void *bulk_buffer1;
411 dma_addr_t bulk_buffer_dma1;
Andy Yan20b09c22009-05-08 17:46:40 -0400412#define TRASH_BUCKET_SIZE 0x20000
Xiangliang Yu0b15fb12011-04-26 06:36:51 -0700413 void *dma_pool;
Andy Yan20b09c22009-05-08 17:46:40 -0400414 struct mvs_slot_info slot_info[0];
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400415};
416
Andy Yan20b09c22009-05-08 17:46:40 -0400417struct mvs_prv_info{
418 u8 n_host;
419 u8 n_phy;
Xiangliang Yu84fbd0c2011-05-24 22:37:25 +0800420 u8 scan_finished;
421 u8 reserve;
Andy Yan20b09c22009-05-08 17:46:40 -0400422 struct mvs_info *mvi[2];
Xiangliang Yu6f8ac162011-06-30 22:27:36 +0800423 struct tasklet_struct mv_tasklet;
Andy Yan20b09c22009-05-08 17:46:40 -0400424};
425
426struct mvs_wq {
427 struct delayed_work work_q;
428 struct mvs_info *mvi;
429 void *data;
430 int handler;
431 struct list_head entry;
432};
433
434struct mvs_task_exec_info {
435 struct sas_task *task;
436 struct mvs_cmd_hdr *hdr;
437 struct mvs_port *port;
438 u32 tag;
439 int n_elem;
440};
441
Xiangliang Yu0b15fb12011-04-26 06:36:51 -0700442struct mvs_task_list {
443 struct sas_task *task;
444 struct list_head list;
445};
446
Andy Yan20b09c22009-05-08 17:46:40 -0400447
448/******************** function prototype *********************/
449void mvs_get_sas_addr(void *buf, u32 buflen);
450void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
451void mvs_tag_free(struct mvs_info *mvi, u32 tag);
452void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
453int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
454void mvs_tag_init(struct mvs_info *mvi);
455void mvs_iounmap(void __iomem *regs);
456int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
457void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400458int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
459 void *funcdata);
Greg Kroah-Hartman6f039792012-12-21 13:08:55 -0800460void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
461 u32 off_hi, u64 sas_addr);
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400462void mvs_scan_start(struct Scsi_Host *shost);
463int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
Andy Yan20b09c22009-05-08 17:46:40 -0400464int mvs_queue_command(struct sas_task *task, const int num,
465 gfp_t gfp_flags);
466int mvs_abort_task(struct sas_task *task);
467int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
468int mvs_clear_aca(struct domain_device *dev, u8 *lun);
469int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400470void mvs_port_formed(struct asd_sas_phy *sas_phy);
Andy Yan20b09c22009-05-08 17:46:40 -0400471void mvs_port_deformed(struct asd_sas_phy *sas_phy);
472int mvs_dev_found(struct domain_device *dev);
473void mvs_dev_gone(struct domain_device *dev);
474int mvs_lu_reset(struct domain_device *dev, u8 *lun);
475int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400476int mvs_I_T_nexus_reset(struct domain_device *dev);
Andy Yan20b09c22009-05-08 17:46:40 -0400477int mvs_query_task(struct sas_task *task);
Srinivas9dc9fd92010-02-15 00:00:00 -0600478void mvs_release_task(struct mvs_info *mvi,
479 struct domain_device *dev);
480void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
Andy Yan20b09c22009-05-08 17:46:40 -0400481 struct domain_device *dev);
482void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
483void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
484int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
Xiangliang Yu534ff102011-05-24 22:26:50 +0800485struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400486#endif
Andy Yan20b09c22009-05-08 17:46:40 -0400487