Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1 | /* |
| 2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers |
| 3 | * |
| 4 | * Copyright 2005 Tejun Heo |
| 5 | * |
| 6 | * Based on preview driver from Silicon Image. |
| 7 | * |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2, or (at your option) any |
| 11 | * later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 27 | #include <linux/device.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 28 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 29 | #include <scsi/scsi_cmnd.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 30 | #include <linux/libata.h> |
| 31 | #include <asm/io.h> |
| 32 | |
| 33 | #define DRV_NAME "sata_sil24" |
Jeff Garzik | af64371 | 2006-04-02 20:41:36 -0400 | [diff] [blame] | 34 | #define DRV_VERSION "0.24" |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 35 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 36 | /* |
| 37 | * Port request block (PRB) 32 bytes |
| 38 | */ |
| 39 | struct sil24_prb { |
| 40 | u16 ctrl; |
| 41 | u16 prot; |
| 42 | u32 rx_cnt; |
| 43 | u8 fis[6 * 4]; |
| 44 | }; |
| 45 | |
| 46 | /* |
| 47 | * Scatter gather entry (SGE) 16 bytes |
| 48 | */ |
| 49 | struct sil24_sge { |
| 50 | u64 addr; |
| 51 | u32 cnt; |
| 52 | u32 flags; |
| 53 | }; |
| 54 | |
| 55 | /* |
| 56 | * Port multiplier |
| 57 | */ |
| 58 | struct sil24_port_multiplier { |
| 59 | u32 diag; |
| 60 | u32 sactive; |
| 61 | }; |
| 62 | |
| 63 | enum { |
| 64 | /* |
| 65 | * Global controller registers (128 bytes @ BAR0) |
| 66 | */ |
| 67 | /* 32 bit regs */ |
| 68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ |
| 69 | HOST_CTRL = 0x40, |
| 70 | HOST_IRQ_STAT = 0x44, |
| 71 | HOST_PHY_CFG = 0x48, |
| 72 | HOST_BIST_CTRL = 0x50, |
| 73 | HOST_BIST_PTRN = 0x54, |
| 74 | HOST_BIST_STAT = 0x58, |
| 75 | HOST_MEM_BIST_STAT = 0x5c, |
| 76 | HOST_FLASH_CMD = 0x70, |
| 77 | /* 8 bit regs */ |
| 78 | HOST_FLASH_DATA = 0x74, |
| 79 | HOST_TRANSITION_DETECT = 0x75, |
| 80 | HOST_GPIO_CTRL = 0x76, |
| 81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ |
| 82 | HOST_I2C_DATA = 0x7c, |
| 83 | HOST_I2C_XFER_CNT = 0x7e, |
| 84 | HOST_I2C_CTRL = 0x7f, |
| 85 | |
| 86 | /* HOST_SLOT_STAT bits */ |
| 87 | HOST_SSTAT_ATTN = (1 << 31), |
| 88 | |
Tejun Heo | 7dafc3f | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 89 | /* HOST_CTRL bits */ |
| 90 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ |
| 91 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ |
| 92 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ |
| 93 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ |
| 94 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ |
| 95 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 96 | /* |
| 97 | * Port registers |
| 98 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) |
| 99 | */ |
| 100 | PORT_REGS_SIZE = 0x2000, |
| 101 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 102 | |
| 103 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ |
| 104 | /* 32 bit regs */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 105 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
| 106 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ |
| 107 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ |
| 108 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ |
| 109 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 110 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 111 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
| 112 | PORT_CMD_ERR = 0x1024, /* command error number */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 113 | PORT_FIS_CFG = 0x1028, |
| 114 | PORT_FIFO_THRES = 0x102c, |
| 115 | /* 16 bit regs */ |
| 116 | PORT_DECODE_ERR_CNT = 0x1040, |
| 117 | PORT_DECODE_ERR_THRESH = 0x1042, |
| 118 | PORT_CRC_ERR_CNT = 0x1044, |
| 119 | PORT_CRC_ERR_THRESH = 0x1046, |
| 120 | PORT_HSHK_ERR_CNT = 0x1048, |
| 121 | PORT_HSHK_ERR_THRESH = 0x104a, |
| 122 | /* 32 bit regs */ |
| 123 | PORT_PHY_CFG = 0x1050, |
| 124 | PORT_SLOT_STAT = 0x1800, |
| 125 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ |
| 126 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
| 127 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ |
| 128 | PORT_SCONTROL = 0x1f00, |
| 129 | PORT_SSTATUS = 0x1f04, |
| 130 | PORT_SERROR = 0x1f08, |
| 131 | PORT_SACTIVE = 0x1f0c, |
| 132 | |
| 133 | /* PORT_CTRL_STAT bits */ |
| 134 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ |
| 135 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ |
| 136 | PORT_CS_INIT = (1 << 2), /* port initialize */ |
| 137 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 138 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
Tejun Heo | e382eb1 | 2005-08-17 13:09:13 +0900 | [diff] [blame] | 139 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
| 140 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
| 141 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ |
| 142 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 143 | |
| 144 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ |
| 145 | /* bits[11:0] are masked */ |
| 146 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ |
| 147 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ |
| 148 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ |
| 149 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ |
| 150 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ |
| 151 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ |
Tejun Heo | 7dafc3f | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 152 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
| 153 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ |
| 154 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ |
| 155 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ |
| 156 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ |
Tejun Heo | 3b9f1d0 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 157 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 158 | |
| 159 | /* bits[27:16] are unmasked (raw) */ |
| 160 | PORT_IRQ_RAW_SHIFT = 16, |
| 161 | PORT_IRQ_MASKED_MASK = 0x7ff, |
| 162 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), |
| 163 | |
| 164 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ |
| 165 | PORT_IRQ_STEER_SHIFT = 30, |
| 166 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), |
| 167 | |
| 168 | /* PORT_CMD_ERR constants */ |
| 169 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ |
| 170 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ |
| 171 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ |
| 172 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ |
| 173 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ |
| 174 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ |
| 175 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ |
| 176 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ |
| 177 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ |
| 178 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ |
| 179 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ |
| 180 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ |
| 181 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ |
| 182 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ |
| 183 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ |
| 184 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ |
| 185 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ |
| 186 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ |
| 187 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ |
Tejun Heo | 6400880 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 188 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 189 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 190 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 191 | |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 192 | /* bits of PRB control field */ |
| 193 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ |
| 194 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ |
| 195 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ |
| 196 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ |
| 197 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ |
| 198 | |
| 199 | /* PRB protocol field */ |
| 200 | PRB_PROT_PACKET = (1 << 0), |
| 201 | PRB_PROT_TCQ = (1 << 1), |
| 202 | PRB_PROT_NCQ = (1 << 2), |
| 203 | PRB_PROT_READ = (1 << 3), |
| 204 | PRB_PROT_WRITE = (1 << 4), |
| 205 | PRB_PROT_TRANSPARENT = (1 << 5), |
| 206 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 207 | /* |
| 208 | * Other constants |
| 209 | */ |
| 210 | SGE_TRM = (1 << 31), /* Last SGE in chain */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 211 | SGE_LNK = (1 << 30), /* linked list |
| 212 | Points to SGT, not SGE */ |
| 213 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) |
| 214 | data address ignored */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 215 | |
| 216 | /* board id */ |
| 217 | BID_SIL3124 = 0, |
| 218 | BID_SIL3132 = 1, |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 219 | BID_SIL3131 = 2, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 220 | |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame^] | 221 | /* host flags */ |
| 222 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 223 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
| 224 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 225 | IRQ_STAT_4PORTS = 0xf, |
| 226 | }; |
| 227 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 228 | struct sil24_ata_block { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 229 | struct sil24_prb prb; |
| 230 | struct sil24_sge sge[LIBATA_MAX_PRD]; |
| 231 | }; |
| 232 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 233 | struct sil24_atapi_block { |
| 234 | struct sil24_prb prb; |
| 235 | u8 cdb[16]; |
| 236 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; |
| 237 | }; |
| 238 | |
| 239 | union sil24_cmd_block { |
| 240 | struct sil24_ata_block ata; |
| 241 | struct sil24_atapi_block atapi; |
| 242 | }; |
| 243 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 244 | /* |
| 245 | * ap->private_data |
| 246 | * |
| 247 | * The preview driver always returned 0 for status. We emulate it |
| 248 | * here from the previous interrupt. |
| 249 | */ |
| 250 | struct sil24_port_priv { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 251 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 252 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 253 | struct ata_taskfile tf; /* Cached taskfile registers */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | /* ap->host_set->private_data */ |
| 257 | struct sil24_host_priv { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 258 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
| 259 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 260 | }; |
| 261 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 262 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 263 | static u8 sil24_check_status(struct ata_port *ap); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 264 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
| 265 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 266 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 267 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 268 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 269 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 270 | static void sil24_irq_clear(struct ata_port *ap); |
| 271 | static void sil24_eng_timeout(struct ata_port *ap); |
| 272 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); |
| 273 | static int sil24_port_start(struct ata_port *ap); |
| 274 | static void sil24_port_stop(struct ata_port *ap); |
| 275 | static void sil24_host_stop(struct ata_host_set *host_set); |
| 276 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
| 277 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 278 | static const struct pci_device_id sil24_pci_tbl[] = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 279 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
Tejun Heo | 4b9d7e0 | 2006-02-23 10:46:47 +0900 | [diff] [blame] | 280 | { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 281 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 282 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
| 283 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
Tejun Heo | 1fcce839 | 2005-10-09 09:31:33 -0400 | [diff] [blame] | 284 | { } /* terminate list */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | static struct pci_driver sil24_pci_driver = { |
| 288 | .name = DRV_NAME, |
| 289 | .id_table = sil24_pci_tbl, |
| 290 | .probe = sil24_init_one, |
| 291 | .remove = ata_pci_remove_one, /* safe? */ |
| 292 | }; |
| 293 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 294 | static struct scsi_host_template sil24_sht = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 295 | .module = THIS_MODULE, |
| 296 | .name = DRV_NAME, |
| 297 | .ioctl = ata_scsi_ioctl, |
| 298 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 299 | .can_queue = ATA_DEF_QUEUE, |
| 300 | .this_id = ATA_SHT_THIS_ID, |
| 301 | .sg_tablesize = LIBATA_MAX_PRD, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 302 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 303 | .emulated = ATA_SHT_EMULATED, |
| 304 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 305 | .proc_name = DRV_NAME, |
| 306 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 307 | .slave_configure = ata_scsi_slave_config, |
| 308 | .bios_param = ata_std_bios_param, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 309 | }; |
| 310 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 311 | static const struct ata_port_operations sil24_ops = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 312 | .port_disable = ata_port_disable, |
| 313 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 314 | .dev_config = sil24_dev_config, |
| 315 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 316 | .check_status = sil24_check_status, |
| 317 | .check_altstatus = sil24_check_status, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 318 | .dev_select = ata_noop_dev_select, |
| 319 | |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 320 | .tf_read = sil24_tf_read, |
| 321 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 322 | .probe_reset = sil24_probe_reset, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 323 | |
| 324 | .qc_prep = sil24_qc_prep, |
| 325 | .qc_issue = sil24_qc_issue, |
| 326 | |
| 327 | .eng_timeout = sil24_eng_timeout, |
| 328 | |
| 329 | .irq_handler = sil24_interrupt, |
| 330 | .irq_clear = sil24_irq_clear, |
| 331 | |
| 332 | .scr_read = sil24_scr_read, |
| 333 | .scr_write = sil24_scr_write, |
| 334 | |
| 335 | .port_start = sil24_port_start, |
| 336 | .port_stop = sil24_port_stop, |
| 337 | .host_stop = sil24_host_stop, |
| 338 | }; |
| 339 | |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 340 | /* |
| 341 | * Use bits 30-31 of host_flags to encode available port numbers. |
| 342 | * Current maxium is 4. |
| 343 | */ |
| 344 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) |
| 345 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) |
| 346 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 347 | static struct ata_port_info sil24_port_info[] = { |
| 348 | /* sil_3124 */ |
| 349 | { |
| 350 | .sht = &sil24_sht, |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame^] | 351 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4), |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 352 | .pio_mask = 0x1f, /* pio0-4 */ |
| 353 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 354 | .udma_mask = 0x3f, /* udma0-5 */ |
| 355 | .port_ops = &sil24_ops, |
| 356 | }, |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 357 | /* sil_3132 */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 358 | { |
| 359 | .sht = &sil24_sht, |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame^] | 360 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 361 | .pio_mask = 0x1f, /* pio0-4 */ |
| 362 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 363 | .udma_mask = 0x3f, /* udma0-5 */ |
| 364 | .port_ops = &sil24_ops, |
| 365 | }, |
| 366 | /* sil_3131/sil_3531 */ |
| 367 | { |
| 368 | .sht = &sil24_sht, |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame^] | 369 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 370 | .pio_mask = 0x1f, /* pio0-4 */ |
| 371 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 372 | .udma_mask = 0x3f, /* udma0-5 */ |
| 373 | .port_ops = &sil24_ops, |
| 374 | }, |
| 375 | }; |
| 376 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 377 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
| 378 | { |
| 379 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 380 | |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 381 | if (dev->cdb_len == 16) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 382 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
| 383 | else |
| 384 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); |
| 385 | } |
| 386 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 387 | static inline void sil24_update_tf(struct ata_port *ap) |
| 388 | { |
| 389 | struct sil24_port_priv *pp = ap->private_data; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 390 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 391 | struct sil24_prb __iomem *prb = port; |
| 392 | u8 fis[6 * 4]; |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 393 | |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 394 | memcpy_fromio(fis, prb->fis, 6 * 4); |
| 395 | ata_tf_from_fis(fis, &pp->tf); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 396 | } |
| 397 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 398 | static u8 sil24_check_status(struct ata_port *ap) |
| 399 | { |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 400 | struct sil24_port_priv *pp = ap->private_data; |
| 401 | return pp->tf.command; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 402 | } |
| 403 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 404 | static int sil24_scr_map[] = { |
| 405 | [SCR_CONTROL] = 0, |
| 406 | [SCR_STATUS] = 1, |
| 407 | [SCR_ERROR] = 2, |
| 408 | [SCR_ACTIVE] = 3, |
| 409 | }; |
| 410 | |
| 411 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) |
| 412 | { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 413 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 414 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 415 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 416 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
| 417 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
| 418 | } |
| 419 | return 0xffffffffU; |
| 420 | } |
| 421 | |
| 422 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
| 423 | { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 424 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 425 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 426 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 427 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
| 428 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); |
| 429 | } |
| 430 | } |
| 431 | |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 432 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 433 | { |
| 434 | struct sil24_port_priv *pp = ap->private_data; |
| 435 | *tf = pp->tf; |
| 436 | } |
| 437 | |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 438 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 439 | { |
| 440 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 441 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 442 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 443 | dma_addr_t paddr = pp->cmd_block_dma; |
Tejun Heo | 7dd29dd | 2006-04-11 22:22:30 +0900 | [diff] [blame] | 444 | u32 mask, irq_enable, irq_stat; |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 445 | const char *reason; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 446 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 447 | DPRINTK("ENTER\n"); |
| 448 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 449 | if (!sata_dev_present(ap)) { |
| 450 | DPRINTK("PHY reports no device\n"); |
| 451 | *class = ATA_DEV_NONE; |
| 452 | goto out; |
| 453 | } |
| 454 | |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 455 | /* temporarily turn off IRQs during SRST */ |
| 456 | irq_enable = readl(port + PORT_IRQ_ENABLE_SET); |
| 457 | writel(irq_enable, port + PORT_IRQ_ENABLE_CLR); |
| 458 | |
| 459 | /* |
| 460 | * XXX: Not sure whether the following sleep is needed or not. |
| 461 | * The original driver had it. So.... |
| 462 | */ |
| 463 | msleep(10); |
| 464 | |
| 465 | prb->ctrl = PRB_CTRL_SRST; |
| 466 | prb->fis[1] = 0; /* no PM yet */ |
| 467 | |
| 468 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
| 469 | |
Tejun Heo | 7dd29dd | 2006-04-11 22:22:30 +0900 | [diff] [blame] | 470 | mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; |
| 471 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, |
| 472 | 100, ATA_TMOUT_BOOT / HZ * 1000); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 473 | |
Tejun Heo | 7dd29dd | 2006-04-11 22:22:30 +0900 | [diff] [blame] | 474 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ |
| 475 | irq_stat >>= PORT_IRQ_RAW_SHIFT; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 476 | |
| 477 | /* restore IRQs */ |
| 478 | writel(irq_enable, port + PORT_IRQ_ENABLE_SET); |
| 479 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 480 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 481 | if (irq_stat & PORT_IRQ_ERROR) |
| 482 | reason = "SRST command error"; |
| 483 | else |
| 484 | reason = "timeout"; |
| 485 | goto err; |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 486 | } |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 487 | |
| 488 | sil24_update_tf(ap); |
| 489 | *class = ata_dev_classify(&pp->tf); |
| 490 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 491 | if (*class == ATA_DEV_UNKNOWN) |
| 492 | *class = ATA_DEV_NONE; |
| 493 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 494 | out: |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 495 | DPRINTK("EXIT, class=%u\n", *class); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 496 | return 0; |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 497 | |
| 498 | err: |
| 499 | printk(KERN_ERR "ata%u: softreset failed (%s)\n", ap->id, reason); |
| 500 | return -EIO; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 501 | } |
| 502 | |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 503 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 504 | { |
| 505 | unsigned int dummy_class; |
| 506 | |
| 507 | /* sil24 doesn't report device signature after hard reset */ |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 508 | return sata_std_hardreset(ap, &dummy_class); |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 509 | } |
| 510 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 511 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 512 | { |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 513 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 514 | sil24_softreset, sil24_hardreset, |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 515 | ata_std_postreset, classes); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 519 | struct sil24_sge *sge) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 520 | { |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 521 | struct scatterlist *sg; |
| 522 | unsigned int idx = 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 523 | |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 524 | ata_for_each_sg(sg, qc) { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 525 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
| 526 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 527 | if (ata_sg_is_last(sg, qc)) |
| 528 | sge->flags = cpu_to_le32(SGE_TRM); |
| 529 | else |
| 530 | sge->flags = 0; |
| 531 | |
| 532 | sge++; |
| 533 | idx++; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | |
| 537 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
| 538 | { |
| 539 | struct ata_port *ap = qc->ap; |
| 540 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 541 | union sil24_cmd_block *cb = pp->cmd_block + qc->tag; |
| 542 | struct sil24_prb *prb; |
| 543 | struct sil24_sge *sge; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 544 | |
| 545 | switch (qc->tf.protocol) { |
| 546 | case ATA_PROT_PIO: |
| 547 | case ATA_PROT_DMA: |
| 548 | case ATA_PROT_NODATA: |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 549 | prb = &cb->ata.prb; |
| 550 | sge = cb->ata.sge; |
| 551 | prb->ctrl = 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 552 | break; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 553 | |
| 554 | case ATA_PROT_ATAPI: |
| 555 | case ATA_PROT_ATAPI_DMA: |
| 556 | case ATA_PROT_ATAPI_NODATA: |
| 557 | prb = &cb->atapi.prb; |
| 558 | sge = cb->atapi.sge; |
| 559 | memset(cb->atapi.cdb, 0, 32); |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 560 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 561 | |
| 562 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { |
| 563 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 564 | prb->ctrl = PRB_CTRL_PACKET_WRITE; |
| 565 | else |
| 566 | prb->ctrl = PRB_CTRL_PACKET_READ; |
| 567 | } else |
| 568 | prb->ctrl = 0; |
| 569 | |
| 570 | break; |
| 571 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 572 | default: |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 573 | prb = NULL; /* shut up, gcc */ |
| 574 | sge = NULL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 575 | BUG(); |
| 576 | } |
| 577 | |
| 578 | ata_tf_to_fis(&qc->tf, prb->fis, 0); |
| 579 | |
| 580 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 581 | sil24_fill_sg(qc, sge); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 582 | } |
| 583 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 584 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 585 | { |
| 586 | struct ata_port *ap = qc->ap; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 587 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 588 | struct sil24_port_priv *pp = ap->private_data; |
| 589 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); |
| 590 | |
Tejun Heo | 4f50c3c | 2005-08-17 13:09:07 +0900 | [diff] [blame] | 591 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 592 | return 0; |
| 593 | } |
| 594 | |
| 595 | static void sil24_irq_clear(struct ata_port *ap) |
| 596 | { |
| 597 | /* unused */ |
| 598 | } |
| 599 | |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 600 | static int __sil24_restart_controller(void __iomem *port) |
| 601 | { |
| 602 | u32 tmp; |
| 603 | int cnt; |
| 604 | |
| 605 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
| 606 | |
| 607 | /* Max ~10ms */ |
| 608 | for (cnt = 0; cnt < 10000; cnt++) { |
| 609 | tmp = readl(port + PORT_CTRL_STAT); |
| 610 | if (tmp & PORT_CS_RDY) |
| 611 | return 0; |
| 612 | udelay(1); |
| 613 | } |
| 614 | |
| 615 | return -1; |
| 616 | } |
| 617 | |
| 618 | static void sil24_restart_controller(struct ata_port *ap) |
| 619 | { |
| 620 | if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
| 621 | printk(KERN_ERR DRV_NAME |
| 622 | " ata%u: failed to restart controller\n", ap->id); |
| 623 | } |
| 624 | |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 625 | static int __sil24_reset_controller(void __iomem *port) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 626 | { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 627 | int cnt; |
| 628 | u32 tmp; |
| 629 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 630 | /* Reset controller state. Is this correct? */ |
| 631 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); |
| 632 | readl(port + PORT_CTRL_STAT); /* sync */ |
| 633 | |
| 634 | /* Max ~100ms */ |
| 635 | for (cnt = 0; cnt < 1000; cnt++) { |
| 636 | udelay(100); |
| 637 | tmp = readl(port + PORT_CTRL_STAT); |
| 638 | if (!(tmp & PORT_CS_DEV_RST)) |
| 639 | break; |
| 640 | } |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 641 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 642 | if (tmp & PORT_CS_DEV_RST) |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 643 | return -1; |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 644 | |
| 645 | if (tmp & PORT_CS_RDY) |
| 646 | return 0; |
| 647 | |
| 648 | return __sil24_restart_controller(port); |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 649 | } |
| 650 | |
| 651 | static void sil24_reset_controller(struct ata_port *ap) |
| 652 | { |
| 653 | printk(KERN_NOTICE DRV_NAME |
| 654 | " ata%u: resetting controller...\n", ap->id); |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 655 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 656 | printk(KERN_ERR DRV_NAME |
| 657 | " ata%u: failed to reset controller\n", ap->id); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 658 | } |
| 659 | |
| 660 | static void sil24_eng_timeout(struct ata_port *ap) |
| 661 | { |
| 662 | struct ata_queued_cmd *qc; |
| 663 | |
| 664 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 665 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 666 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); |
Tejun Heo | 11a56d2 | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 667 | qc->err_mask |= AC_ERR_TIMEOUT; |
Tejun Heo | a72ec4c | 2006-01-23 13:09:37 +0900 | [diff] [blame] | 668 | ata_eh_qc_complete(qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 669 | |
| 670 | sil24_reset_controller(ap); |
| 671 | } |
| 672 | |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 673 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
| 674 | { |
| 675 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 676 | struct sil24_port_priv *pp = ap->private_data; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 677 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 678 | u32 irq_stat, cmd_err, sstatus, serror; |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 679 | unsigned int err_mask; |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 680 | |
| 681 | irq_stat = readl(port + PORT_IRQ_STAT); |
Tejun Heo | ad6e90f | 2005-10-06 11:43:29 +0900 | [diff] [blame] | 682 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
| 683 | |
| 684 | if (!(irq_stat & PORT_IRQ_ERROR)) { |
| 685 | /* ignore non-completion, non-error irqs for now */ |
| 686 | printk(KERN_WARNING DRV_NAME |
| 687 | "ata%u: non-error exception irq (irq_stat %x)\n", |
| 688 | ap->id, irq_stat); |
| 689 | return; |
| 690 | } |
| 691 | |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 692 | cmd_err = readl(port + PORT_CMD_ERR); |
| 693 | sstatus = readl(port + PORT_SSTATUS); |
| 694 | serror = readl(port + PORT_SERROR); |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 695 | if (serror) |
| 696 | writel(serror, port + PORT_SERROR); |
| 697 | |
Tejun Heo | c0ab424 | 2005-11-18 14:22:03 +0900 | [diff] [blame] | 698 | /* |
| 699 | * Don't log ATAPI device errors. They're supposed to happen |
| 700 | * and any serious errors will be logged using sense data by |
| 701 | * the SCSI layer. |
| 702 | */ |
| 703 | if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB) |
| 704 | printk("ata%u: error interrupt on port%d\n" |
| 705 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", |
| 706 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 707 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 708 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
| 709 | /* |
| 710 | * Device is reporting error, tf registers are valid. |
| 711 | */ |
| 712 | sil24_update_tf(ap); |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 713 | err_mask = ac_err_mask(pp->tf.command); |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 714 | sil24_restart_controller(ap); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 715 | } else { |
| 716 | /* |
| 717 | * Other errors. libata currently doesn't have any |
| 718 | * mechanism to report these errors. Just turn on |
| 719 | * ATA_ERR. |
| 720 | */ |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 721 | err_mask = AC_ERR_OTHER; |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 722 | sil24_reset_controller(ap); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 723 | } |
| 724 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 725 | if (qc) { |
| 726 | qc->err_mask |= err_mask; |
| 727 | ata_qc_complete(qc); |
| 728 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 729 | } |
| 730 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 731 | static inline void sil24_host_intr(struct ata_port *ap) |
| 732 | { |
| 733 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 734 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 735 | u32 slot_stat; |
| 736 | |
| 737 | slot_stat = readl(port + PORT_SLOT_STAT); |
| 738 | if (!(slot_stat & HOST_SSTAT_ATTN)) { |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 739 | struct sil24_port_priv *pp = ap->private_data; |
| 740 | /* |
| 741 | * !HOST_SSAT_ATTN guarantees successful completion, |
| 742 | * so reading back tf registers is unnecessary for |
| 743 | * most commands. TODO: read tf registers for |
| 744 | * commands which require these values on successful |
| 745 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, |
| 746 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). |
| 747 | */ |
| 748 | sil24_update_tf(ap); |
| 749 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 750 | if (qc) { |
| 751 | qc->err_mask |= ac_err_mask(pp->tf.command); |
| 752 | ata_qc_complete(qc); |
| 753 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 754 | } else |
| 755 | sil24_error_intr(ap, slot_stat); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) |
| 759 | { |
| 760 | struct ata_host_set *host_set = dev_instance; |
| 761 | struct sil24_host_priv *hpriv = host_set->private_data; |
| 762 | unsigned handled = 0; |
| 763 | u32 status; |
| 764 | int i; |
| 765 | |
| 766 | status = readl(hpriv->host_base + HOST_IRQ_STAT); |
| 767 | |
Tejun Heo | 06460ae | 2005-08-17 13:08:52 +0900 | [diff] [blame] | 768 | if (status == 0xffffffff) { |
| 769 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " |
| 770 | "PCI fault or device removal?\n"); |
| 771 | goto out; |
| 772 | } |
| 773 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 774 | if (!(status & IRQ_STAT_4PORTS)) |
| 775 | goto out; |
| 776 | |
| 777 | spin_lock(&host_set->lock); |
| 778 | |
| 779 | for (i = 0; i < host_set->n_ports; i++) |
| 780 | if (status & (1 << i)) { |
| 781 | struct ata_port *ap = host_set->ports[i]; |
Tejun Heo | 198e0fe | 2006-04-02 18:51:52 +0900 | [diff] [blame] | 782 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 783 | sil24_host_intr(host_set->ports[i]); |
Tejun Heo | 3cc4571 | 2005-08-17 13:08:47 +0900 | [diff] [blame] | 784 | handled++; |
| 785 | } else |
| 786 | printk(KERN_ERR DRV_NAME |
| 787 | ": interrupt from disabled port %d\n", i); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 788 | } |
| 789 | |
| 790 | spin_unlock(&host_set->lock); |
| 791 | out: |
| 792 | return IRQ_RETVAL(handled); |
| 793 | } |
| 794 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 795 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
| 796 | { |
| 797 | const size_t cb_size = sizeof(*pp->cmd_block); |
| 798 | |
| 799 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); |
| 800 | } |
| 801 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 802 | static int sil24_port_start(struct ata_port *ap) |
| 803 | { |
| 804 | struct device *dev = ap->host_set->dev; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 805 | struct sil24_port_priv *pp; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 806 | union sil24_cmd_block *cb; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 807 | size_t cb_size = sizeof(*cb); |
| 808 | dma_addr_t cb_dma; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 809 | int rc = -ENOMEM; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 810 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 811 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 812 | if (!pp) |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 813 | goto err_out; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 814 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 815 | pp->tf.command = ATA_DRDY; |
| 816 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 817 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 818 | if (!cb) |
| 819 | goto err_out_pp; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 820 | memset(cb, 0, cb_size); |
| 821 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 822 | rc = ata_pad_alloc(ap, dev); |
| 823 | if (rc) |
| 824 | goto err_out_pad; |
| 825 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 826 | pp->cmd_block = cb; |
| 827 | pp->cmd_block_dma = cb_dma; |
| 828 | |
| 829 | ap->private_data = pp; |
| 830 | |
| 831 | return 0; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 832 | |
| 833 | err_out_pad: |
| 834 | sil24_cblk_free(pp, dev); |
| 835 | err_out_pp: |
| 836 | kfree(pp); |
| 837 | err_out: |
| 838 | return rc; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 839 | } |
| 840 | |
| 841 | static void sil24_port_stop(struct ata_port *ap) |
| 842 | { |
| 843 | struct device *dev = ap->host_set->dev; |
| 844 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 845 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 846 | sil24_cblk_free(pp, dev); |
Tejun Heo | e9c05af | 2005-11-14 00:24:18 +0900 | [diff] [blame] | 847 | ata_pad_free(ap, dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 848 | kfree(pp); |
| 849 | } |
| 850 | |
| 851 | static void sil24_host_stop(struct ata_host_set *host_set) |
| 852 | { |
| 853 | struct sil24_host_priv *hpriv = host_set->private_data; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 854 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 855 | |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 856 | pci_iounmap(pdev, hpriv->host_base); |
| 857 | pci_iounmap(pdev, hpriv->port_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 858 | kfree(hpriv); |
| 859 | } |
| 860 | |
| 861 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 862 | { |
| 863 | static int printed_version = 0; |
| 864 | unsigned int board_id = (unsigned int)ent->driver_data; |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 865 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 866 | struct ata_probe_ent *probe_ent = NULL; |
| 867 | struct sil24_host_priv *hpriv = NULL; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 868 | void __iomem *host_base = NULL; |
| 869 | void __iomem *port_base = NULL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 870 | int i, rc; |
| 871 | |
| 872 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 873 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 874 | |
| 875 | rc = pci_enable_device(pdev); |
| 876 | if (rc) |
| 877 | return rc; |
| 878 | |
| 879 | rc = pci_request_regions(pdev, DRV_NAME); |
| 880 | if (rc) |
| 881 | goto out_disable; |
| 882 | |
| 883 | rc = -ENOMEM; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 884 | /* map mmio registers */ |
| 885 | host_base = pci_iomap(pdev, 0, 0); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 886 | if (!host_base) |
| 887 | goto out_free; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 888 | port_base = pci_iomap(pdev, 2, 0); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 889 | if (!port_base) |
| 890 | goto out_free; |
| 891 | |
| 892 | /* allocate & init probe_ent and hpriv */ |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 893 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 894 | if (!probe_ent) |
| 895 | goto out_free; |
| 896 | |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 897 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 898 | if (!hpriv) |
| 899 | goto out_free; |
| 900 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 901 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 902 | INIT_LIST_HEAD(&probe_ent->node); |
| 903 | |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 904 | probe_ent->sht = pinfo->sht; |
| 905 | probe_ent->host_flags = pinfo->host_flags; |
| 906 | probe_ent->pio_mask = pinfo->pio_mask; |
Tejun Heo | fbfda6e | 2006-03-05 23:03:42 +0900 | [diff] [blame] | 907 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 908 | probe_ent->udma_mask = pinfo->udma_mask; |
| 909 | probe_ent->port_ops = pinfo->port_ops; |
| 910 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 911 | |
| 912 | probe_ent->irq = pdev->irq; |
| 913 | probe_ent->irq_flags = SA_SHIRQ; |
| 914 | probe_ent->mmio_base = port_base; |
| 915 | probe_ent->private_data = hpriv; |
| 916 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 917 | hpriv->host_base = host_base; |
| 918 | hpriv->port_base = port_base; |
| 919 | |
| 920 | /* |
| 921 | * Configure the device |
| 922 | */ |
| 923 | /* |
| 924 | * FIXME: This device is certainly 64-bit capable. We just |
| 925 | * don't know how to use it. After fixing 32bit activation in |
| 926 | * this function, enable 64bit masks here. |
| 927 | */ |
| 928 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 929 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 930 | dev_printk(KERN_ERR, &pdev->dev, |
| 931 | "32-bit DMA enable failed\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 932 | goto out_free; |
| 933 | } |
| 934 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 935 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 936 | dev_printk(KERN_ERR, &pdev->dev, |
| 937 | "32-bit consistent DMA enable failed\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 938 | goto out_free; |
| 939 | } |
| 940 | |
| 941 | /* GPIO off */ |
| 942 | writel(0, host_base + HOST_FLASH_CMD); |
| 943 | |
Tejun Heo | 7dd29dd | 2006-04-11 22:22:30 +0900 | [diff] [blame] | 944 | /* clear global reset & mask interrupts during initialization */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 945 | writel(0, host_base + HOST_CTRL); |
| 946 | |
| 947 | for (i = 0; i < probe_ent->n_ports; i++) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 948 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 949 | unsigned long portu = (unsigned long)port; |
| 950 | u32 tmp; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 951 | |
Tejun Heo | 4f50c3c | 2005-08-17 13:09:07 +0900 | [diff] [blame] | 952 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 953 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
| 954 | |
| 955 | ata_std_ports(&probe_ent->port[i]); |
| 956 | |
| 957 | /* Initial PHY setting */ |
| 958 | writel(0x20c, port + PORT_PHY_CFG); |
| 959 | |
| 960 | /* Clear port RST */ |
| 961 | tmp = readl(port + PORT_CTRL_STAT); |
| 962 | if (tmp & PORT_CS_PORT_RST) { |
| 963 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
Tejun Heo | 7dd29dd | 2006-04-11 22:22:30 +0900 | [diff] [blame] | 964 | tmp = ata_wait_register(port + PORT_CTRL_STAT, |
| 965 | PORT_CS_PORT_RST, |
| 966 | PORT_CS_PORT_RST, 10, 100); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 967 | if (tmp & PORT_CS_PORT_RST) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 968 | dev_printk(KERN_ERR, &pdev->dev, |
| 969 | "failed to clear port RST\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 970 | } |
| 971 | |
| 972 | /* Zero error counters. */ |
| 973 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); |
| 974 | writel(0x8000, port + PORT_CRC_ERR_THRESH); |
| 975 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); |
| 976 | writel(0x0000, port + PORT_DECODE_ERR_CNT); |
| 977 | writel(0x0000, port + PORT_CRC_ERR_CNT); |
| 978 | writel(0x0000, port + PORT_HSHK_ERR_CNT); |
| 979 | |
| 980 | /* FIXME: 32bit activation? */ |
| 981 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); |
| 982 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); |
| 983 | |
| 984 | /* Configure interrupts */ |
| 985 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); |
Tejun Heo | 3b9f1d0 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 986 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
| 987 | PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 988 | |
| 989 | /* Clear interrupts */ |
| 990 | writel(0x0fff0fff, port + PORT_IRQ_STAT); |
| 991 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 992 | |
| 993 | /* Clear port multiplier enable and resume bits */ |
| 994 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); |
| 995 | |
| 996 | /* Reset itself */ |
| 997 | if (__sil24_reset_controller(port)) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 998 | dev_printk(KERN_ERR, &pdev->dev, |
| 999 | "failed to reset controller\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1000 | } |
| 1001 | |
| 1002 | /* Turn on interrupts */ |
| 1003 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); |
| 1004 | |
| 1005 | pci_set_master(pdev); |
| 1006 | |
Tejun Heo | 1483467 | 2005-08-17 13:08:42 +0900 | [diff] [blame] | 1007 | /* FIXME: check ata_device_add return value */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1008 | ata_device_add(probe_ent); |
| 1009 | |
| 1010 | kfree(probe_ent); |
| 1011 | return 0; |
| 1012 | |
| 1013 | out_free: |
| 1014 | if (host_base) |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 1015 | pci_iounmap(pdev, host_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1016 | if (port_base) |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 1017 | pci_iounmap(pdev, port_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1018 | kfree(probe_ent); |
| 1019 | kfree(hpriv); |
| 1020 | pci_release_regions(pdev); |
| 1021 | out_disable: |
| 1022 | pci_disable_device(pdev); |
| 1023 | return rc; |
| 1024 | } |
| 1025 | |
| 1026 | static int __init sil24_init(void) |
| 1027 | { |
| 1028 | return pci_module_init(&sil24_pci_driver); |
| 1029 | } |
| 1030 | |
| 1031 | static void __exit sil24_exit(void) |
| 1032 | { |
| 1033 | pci_unregister_driver(&sil24_pci_driver); |
| 1034 | } |
| 1035 | |
| 1036 | MODULE_AUTHOR("Tejun Heo"); |
| 1037 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); |
| 1038 | MODULE_LICENSE("GPL"); |
| 1039 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); |
| 1040 | |
| 1041 | module_init(sil24_init); |
| 1042 | module_exit(sil24_exit); |