Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Copyright 2007-2009 Analog Devices Inc. |
| 3 | * Philippe Gerum <rpm@xenomai.org> |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 4 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 5 | * Licensed under the GPL-2 or later. |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/init.h> |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/sched.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <asm/smp.h> |
| 13 | #include <asm/dma.h> |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 14 | #include <asm/time.h> |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 15 | |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 16 | static DEFINE_SPINLOCK(boot_lock); |
| 17 | |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 18 | /* |
| 19 | * platform_init_cpus() - Tell the world about how many cores we |
| 20 | * have. This is called while setting up the architecture support |
| 21 | * (setup_arch()), so don't be too demanding here with respect to |
| 22 | * available kernel services. |
| 23 | */ |
| 24 | |
| 25 | void __init platform_init_cpus(void) |
| 26 | { |
| 27 | cpu_set(0, cpu_possible_map); /* CoreA */ |
| 28 | cpu_set(1, cpu_possible_map); /* CoreB */ |
| 29 | } |
| 30 | |
| 31 | void __init platform_prepare_cpus(unsigned int max_cpus) |
| 32 | { |
| 33 | int len; |
| 34 | |
| 35 | len = &coreb_trampoline_end - &coreb_trampoline_start + 1; |
Graf Yang | dbc895f | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 36 | BUG_ON(len > L1_CODE_LENGTH); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 37 | |
Graf Yang | dbc895f | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 38 | dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 39 | |
| 40 | /* Both cores ought to be present on a bf561! */ |
| 41 | cpu_set(0, cpu_present_map); /* CoreA */ |
| 42 | cpu_set(1, cpu_present_map); /* CoreB */ |
| 43 | |
Graf Yang | dbc895f | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 44 | printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ |
| 48 | { |
| 49 | return -EINVAL; |
| 50 | } |
| 51 | |
| 52 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 53 | { |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 54 | /* Clone setup for peripheral interrupt sources from CoreA. */ |
Mike Frysinger | 39c9996 | 2010-10-19 18:44:23 +0000 | [diff] [blame] | 55 | bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); |
| 56 | bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1()); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 57 | SSYNC(); |
| 58 | |
| 59 | /* Clone setup for IARs from CoreA. */ |
Mike Frysinger | 39c9996 | 2010-10-19 18:44:23 +0000 | [diff] [blame] | 60 | bfin_write_SICB_IAR0(bfin_read_SIC_IAR0()); |
| 61 | bfin_write_SICB_IAR1(bfin_read_SIC_IAR1()); |
| 62 | bfin_write_SICB_IAR2(bfin_read_SIC_IAR2()); |
| 63 | bfin_write_SICB_IAR3(bfin_read_SIC_IAR3()); |
| 64 | bfin_write_SICB_IAR4(bfin_read_SIC_IAR4()); |
| 65 | bfin_write_SICB_IAR5(bfin_read_SIC_IAR5()); |
| 66 | bfin_write_SICB_IAR6(bfin_read_SIC_IAR6()); |
| 67 | bfin_write_SICB_IAR7(bfin_read_SIC_IAR7()); |
Graf Yang | 0b39db2 | 2009-12-28 11:13:51 +0000 | [diff] [blame] | 68 | bfin_write_SICB_IWR0(IWR_DISABLE_ALL); |
| 69 | bfin_write_SICB_IWR1(IWR_DISABLE_ALL); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 70 | SSYNC(); |
| 71 | |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 72 | /* Store CPU-private information to the cpu_data array. */ |
| 73 | bfin_setup_cpudata(cpu); |
| 74 | |
| 75 | /* We are done with local CPU inits, unblock the boot CPU. */ |
Graf Yang | 682f5dc | 2009-12-28 09:27:27 +0000 | [diff] [blame] | 76 | set_cpu_online(cpu, true); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 77 | spin_lock(&boot_lock); |
| 78 | spin_unlock(&boot_lock); |
| 79 | } |
| 80 | |
| 81 | int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 82 | { |
| 83 | unsigned long timeout; |
| 84 | |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 85 | printk(KERN_INFO "Booting Core B.\n"); |
| 86 | |
| 87 | spin_lock(&boot_lock); |
| 88 | |
Mike Frysinger | 94a038c | 2010-10-27 10:06:32 -0400 | [diff] [blame^] | 89 | if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { |
Graf Yang | 0b39db2 | 2009-12-28 11:13:51 +0000 | [diff] [blame] | 90 | /* CoreB already running, sending ipi to wakeup it */ |
| 91 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); |
| 92 | } else { |
| 93 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ |
Mike Frysinger | 94a038c | 2010-10-27 10:06:32 -0400 | [diff] [blame^] | 94 | bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); |
Graf Yang | 0b39db2 | 2009-12-28 11:13:51 +0000 | [diff] [blame] | 95 | SSYNC(); |
| 96 | } |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 97 | |
| 98 | timeout = jiffies + 1 * HZ; |
| 99 | while (time_before(jiffies, timeout)) { |
Graf Yang | 682f5dc | 2009-12-28 09:27:27 +0000 | [diff] [blame] | 100 | if (cpu_online(cpu)) |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 101 | break; |
| 102 | udelay(100); |
| 103 | barrier(); |
| 104 | } |
| 105 | |
Graf Yang | 682f5dc | 2009-12-28 09:27:27 +0000 | [diff] [blame] | 106 | if (cpu_online(cpu)) { |
Yi Li | 578d36f | 2009-12-02 07:58:12 +0000 | [diff] [blame] | 107 | /* release the lock and let coreb run */ |
| 108 | spin_unlock(&boot_lock); |
| 109 | return 0; |
| 110 | } else |
| 111 | panic("CPU%u: processor failed to boot\n", cpu); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | void __init platform_request_ipi(irq_handler_t handler) |
| 115 | { |
| 116 | int ret; |
| 117 | |
| 118 | ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 119 | "Supplemental Interrupt0", handler); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 120 | if (ret) |
Mike Frysinger | d8804ad | 2009-04-29 06:26:46 +0000 | [diff] [blame] | 121 | panic("Cannot request supplemental interrupt 0 for IPI service"); |
Graf Yang | c51b448 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | void platform_send_ipi(cpumask_t callmap) |
| 125 | { |
| 126 | unsigned int cpu; |
| 127 | |
| 128 | for_each_cpu_mask(cpu, callmap) { |
| 129 | BUG_ON(cpu >= 2); |
| 130 | SSYNC(); |
| 131 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); |
| 132 | SSYNC(); |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | void platform_send_ipi_cpu(unsigned int cpu) |
| 137 | { |
| 138 | BUG_ON(cpu >= 2); |
| 139 | SSYNC(); |
| 140 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); |
| 141 | SSYNC(); |
| 142 | } |
| 143 | |
| 144 | void platform_clear_ipi(unsigned int cpu) |
| 145 | { |
| 146 | BUG_ON(cpu >= 2); |
| 147 | SSYNC(); |
| 148 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); |
| 149 | SSYNC(); |
| 150 | } |
Yi Li | 0d152c2 | 2009-12-28 10:21:49 +0000 | [diff] [blame] | 151 | |
| 152 | /* |
| 153 | * Setup core B's local core timer. |
| 154 | * In SMP, core timer is used for clock event device. |
| 155 | */ |
| 156 | void __cpuinit bfin_local_timer_setup(void) |
| 157 | { |
| 158 | #if defined(CONFIG_TICKSOURCE_CORETMR) |
| 159 | bfin_coretmr_init(); |
| 160 | bfin_coretmr_clockevent_init(); |
| 161 | get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR); |
| 162 | #else |
| 163 | /* Power down the core timer, just to play safe. */ |
| 164 | bfin_write_TCNTL(0); |
| 165 | #endif |
| 166 | |
| 167 | } |