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Michael Henneriche6c91b62008-04-25 04:58:29 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Blackfin core clock scaling
Michael Henneriche6c91b62008-04-25 04:58:29 +08003 *
Michael Hennerich8944b5a2011-02-28 21:23:36 +00004 * Copyright 2008-2011 Analog Devices Inc.
Michael Henneriche6c91b62008-04-25 04:58:29 +08005 *
Robin Getz96f10502009-09-24 14:11:24 +00006 * Licensed under the GPL-2 or later.
Michael Henneriche6c91b62008-04-25 04:58:29 +08007 */
8
9#include <linux/kernel.h>
Paul Gortmaker6a550b92011-08-09 16:54:30 -040010#include <linux/module.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080011#include <linux/types.h>
12#include <linux/init.h>
Steven Miao96900312012-05-16 17:49:52 +080013#include <linux/clk.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080014#include <linux/cpufreq.h>
15#include <linux/fs.h>
Graf Yang7998a872010-03-08 03:01:35 +000016#include <linux/delay.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080017#include <asm/blackfin.h>
18#include <asm/time.h>
Mike Frysinger761ec442009-10-15 17:12:05 +000019#include <asm/dpmc.h>
Michael Henneriche6c91b62008-04-25 04:58:29 +080020
Steven Miao96900312012-05-16 17:49:52 +080021
Michael Henneriche6c91b62008-04-25 04:58:29 +080022/* this is the table of CCLK frequencies, in Hz */
Viresh Kumar50701582013-03-30 16:25:15 +053023/* .driver_data is the entry in the auxiliary dpm_state_table[] */
Michael Henneriche6c91b62008-04-25 04:58:29 +080024static struct cpufreq_frequency_table bfin_freq_table[] = {
25 {
26 .frequency = CPUFREQ_TABLE_END,
Viresh Kumar50701582013-03-30 16:25:15 +053027 .driver_data = 0,
Michael Henneriche6c91b62008-04-25 04:58:29 +080028 },
29 {
30 .frequency = CPUFREQ_TABLE_END,
Viresh Kumar50701582013-03-30 16:25:15 +053031 .driver_data = 1,
Michael Henneriche6c91b62008-04-25 04:58:29 +080032 },
33 {
34 .frequency = CPUFREQ_TABLE_END,
Viresh Kumar50701582013-03-30 16:25:15 +053035 .driver_data = 2,
Michael Henneriche6c91b62008-04-25 04:58:29 +080036 },
37 {
38 .frequency = CPUFREQ_TABLE_END,
Viresh Kumar50701582013-03-30 16:25:15 +053039 .driver_data = 0,
Michael Henneriche6c91b62008-04-25 04:58:29 +080040 },
41};
42
43static struct bfin_dpm_state {
44 unsigned int csel; /* system clock divider */
45 unsigned int tscale; /* change the divider on the core timer interrupt */
46} dpm_state_table[3];
47
Graf Yang6c2b7072010-01-27 11:16:32 +000048#if defined(CONFIG_CYCLES_CLOCKSOURCE)
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080049/*
Michael Hennerich8944b5a2011-02-28 21:23:36 +000050 * normalized to maximum frequency offset for CYCLES,
Graf Yang6c2b7072010-01-27 11:16:32 +000051 * used in time-ts cycles clock source, but could be used
52 * somewhere also.
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080053 */
54unsigned long long __bfin_cycles_off;
55unsigned int __bfin_cycles_mod;
Graf Yang6c2b7072010-01-27 11:16:32 +000056#endif
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080057
Michael Henneriche6c91b62008-04-25 04:58:29 +080058/**************************************************************************/
Graf Yang6c2b7072010-01-27 11:16:32 +000059static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
Michael Henneriche6c91b62008-04-25 04:58:29 +080060{
61
Graf Yang6c2b7072010-01-27 11:16:32 +000062 unsigned long csel, min_cclk;
Michael Henneriche6c91b62008-04-25 04:58:29 +080063 int index;
64
Graf Yang6c2b7072010-01-27 11:16:32 +000065 /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
Sonic Zhang7f3aee32009-05-07 10:04:19 +000066#if ANOMALY_05000273 || ANOMALY_05000274 || \
Sonic Zhang7c7d0272012-07-17 13:40:15 +080067 (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
68 && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
Michael Henneriche6c91b62008-04-25 04:58:29 +080069 min_cclk = sclk * 2;
70#else
71 min_cclk = sclk;
72#endif
Steven Miao96900312012-05-16 17:49:52 +080073
74#ifndef CONFIG_BF60x
Michael Henneriche6c91b62008-04-25 04:58:29 +080075 csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
Steven Miao96900312012-05-16 17:49:52 +080076#else
77 csel = bfin_read32(CGU0_DIV) & 0x1F;
78#endif
Michael Henneriche6c91b62008-04-25 04:58:29 +080079
James Cosin810f1512012-08-20 11:55:36 +080080 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
Michael Henneriche6c91b62008-04-25 04:58:29 +080081 bfin_freq_table[index].frequency = cclk >> index;
Steven Miao96900312012-05-16 17:49:52 +080082#ifndef CONFIG_BF60x
Michael Henneriche6c91b62008-04-25 04:58:29 +080083 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
Steven Miao96900312012-05-16 17:49:52 +080084#else
85 dpm_state_table[index].csel = csel;
Steven Miao96900312012-05-16 17:49:52 +080086#endif
James Cosin810f1512012-08-20 11:55:36 +080087 dpm_state_table[index].tscale = (TIME_SCALE >> index) - 1;
Michael Henneriche6c91b62008-04-25 04:58:29 +080088
Michael Hennericha10101d2008-10-28 14:18:29 +080089 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
Michael Henneriche6c91b62008-04-25 04:58:29 +080090 bfin_freq_table[index].frequency,
91 dpm_state_table[index].csel,
92 dpm_state_table[index].tscale);
93 }
Graf Yang6c2b7072010-01-27 11:16:32 +000094 return;
95}
96
97static void bfin_adjust_core_timer(void *info)
98{
99 unsigned int tscale;
100 unsigned int index = *(unsigned int *)info;
101
102 /* we have to adjust the core timer, because it is using cclk */
103 tscale = dpm_state_table[index].tscale;
104 bfin_write_TSCALE(tscale);
105 return;
106}
107
108static unsigned int bfin_getfreq_khz(unsigned int cpu)
109{
110 /* Both CoreA/B have the same core clock */
111 return get_cclk() / 1000;
112}
113
Bob Liu3a3cf0d2012-05-17 14:21:22 +0800114#ifdef CONFIG_BF60x
Steven Miao96900312012-05-16 17:49:52 +0800115unsigned long cpu_set_cclk(int cpu, unsigned long new)
116{
117 struct clk *clk;
118 int ret;
119
120 clk = clk_get(NULL, "CCLK");
121 if (IS_ERR(clk))
122 return -ENODEV;
123
124 ret = clk_set_rate(clk, new);
125 clk_put(clk);
126 return ret;
127}
Bob Liu3a3cf0d2012-05-17 14:21:22 +0800128#endif
Steven Miao96900312012-05-16 17:49:52 +0800129
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +0530130static int bfin_target(struct cpufreq_policy *policy, unsigned int index)
Graf Yang6c2b7072010-01-27 11:16:32 +0000131{
Bob Liu3a3cf0d2012-05-17 14:21:22 +0800132#ifndef CONFIG_BF60x
133 unsigned int plldiv;
134#endif
Graf Yang7998a872010-03-08 03:01:35 +0000135 static unsigned long lpj_ref;
136 static unsigned int lpj_ref_freq;
Viresh Kumard4019f02013-08-14 19:38:24 +0530137 unsigned int old_freq, new_freq;
Steven Miao96900312012-05-16 17:49:52 +0800138 int ret = 0;
Graf Yang7998a872010-03-08 03:01:35 +0000139
Graf Yang6c2b7072010-01-27 11:16:32 +0000140#if defined(CONFIG_CYCLES_CLOCKSOURCE)
141 cycles_t cycles;
142#endif
143
Viresh Kumard4019f02013-08-14 19:38:24 +0530144 old_freq = bfin_getfreq_khz(0);
145 new_freq = bfin_freq_table[index].frequency;
Graf Yang6c2b7072010-01-27 11:16:32 +0000146
Steven Miao96900312012-05-16 17:49:52 +0800147#ifndef CONFIG_BF60x
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530148 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
149 bfin_write_PLL_DIV(plldiv);
Steven Miao96900312012-05-16 17:49:52 +0800150#else
Viresh Kumard4019f02013-08-14 19:38:24 +0530151 ret = cpu_set_cclk(policy->cpu, new_freq * 1000);
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530152 if (ret != 0) {
153 WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
154 return ret;
Graf Yang6c2b7072010-01-27 11:16:32 +0000155 }
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530156#endif
157 on_each_cpu(bfin_adjust_core_timer, &index, 1);
158#if defined(CONFIG_CYCLES_CLOCKSOURCE)
159 cycles = get_cycles();
160 SSYNC();
161 cycles += 10; /* ~10 cycles we lose after get_cycles() */
162 __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
163 __bfin_cycles_mod = index;
164#endif
165 if (!lpj_ref_freq) {
166 lpj_ref = loops_per_jiffy;
Viresh Kumard4019f02013-08-14 19:38:24 +0530167 lpj_ref_freq = old_freq;
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530168 }
Viresh Kumard4019f02013-08-14 19:38:24 +0530169 if (new_freq != old_freq) {
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530170 loops_per_jiffy = cpufreq_scale(lpj_ref,
Viresh Kumard4019f02013-08-14 19:38:24 +0530171 lpj_ref_freq, new_freq);
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530172 }
173
Steven Miao96900312012-05-16 17:49:52 +0800174 return ret;
Graf Yang6c2b7072010-01-27 11:16:32 +0000175}
176
Steven Miao96900312012-05-16 17:49:52 +0800177static int __bfin_cpu_init(struct cpufreq_policy *policy)
Graf Yang6c2b7072010-01-27 11:16:32 +0000178{
179
180 unsigned long cclk, sclk;
181
182 cclk = get_cclk() / 1000;
183 sclk = get_sclk() / 1000;
184
185 if (policy->cpu == CPUFREQ_CPU)
186 bfin_init_tables(cclk, sclk);
Michael Henneriche6c91b62008-04-25 04:58:29 +0800187
Michael Hennerichd887a1c2009-09-25 09:03:21 +0000188 policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
189
Viresh Kumare2889e22013-09-16 18:56:09 +0530190 return cpufreq_table_validate_and_show(policy, bfin_freq_table);
Michael Henneriche6c91b62008-04-25 04:58:29 +0800191}
192
Michael Henneriche6c91b62008-04-25 04:58:29 +0800193static struct cpufreq_driver bfin_driver = {
Viresh Kumar00ff4242013-10-03 20:27:59 +0530194 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +0530195 .target_index = bfin_target,
Michael Hennericha10101d2008-10-28 14:18:29 +0800196 .get = bfin_getfreq_khz,
Michael Henneriche6c91b62008-04-25 04:58:29 +0800197 .init = __bfin_cpu_init,
198 .name = "bfin cpufreq",
Viresh Kumar00ff4242013-10-03 20:27:59 +0530199 .attr = cpufreq_generic_attr,
Michael Henneriche6c91b62008-04-25 04:58:29 +0800200};
201
202static int __init bfin_cpu_init(void)
203{
204 return cpufreq_register_driver(&bfin_driver);
205}
206
207static void __exit bfin_cpu_exit(void)
208{
209 cpufreq_unregister_driver(&bfin_driver);
210}
211
212MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
213MODULE_DESCRIPTION("cpufreq driver for Blackfin");
214MODULE_LICENSE("GPL");
215
216module_init(bfin_cpu_init);
217module_exit(bfin_cpu_exit);