blob: b137c889152b14be6486fe9271f00658f81df031 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchings906bb262009-11-29 15:16:19 +00004 * Copyright 2005-2009 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11/* Common definitions for all Efx net driver code */
12
13#ifndef EFX_NET_DRIVER_H
14#define EFX_NET_DRIVER_H
15
Ben Hutchings62776d02010-06-23 11:30:07 +000016#if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
17#define DEBUG
18#endif
19
Ben Hutchings8ceee662008-04-27 12:55:59 +010020#include <linux/version.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/ethtool.h>
24#include <linux/if_vlan.h>
Steve Hodgson90d683a2010-06-01 11:19:39 +000025#include <linux/timer.h>
Ben Hutchings68e7f452009-04-29 08:05:08 +000026#include <linux/mdio.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010027#include <linux/list.h>
28#include <linux/pci.h>
29#include <linux/device.h>
30#include <linux/highmem.h>
31#include <linux/workqueue.h>
David S. Miller10ed61c2010-09-21 16:11:06 -070032#include <linux/vmalloc.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010033#include <linux/i2c.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010034
35#include "enum.h"
36#include "bitfield.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010037
Ben Hutchings8ceee662008-04-27 12:55:59 +010038/**************************************************************************
39 *
40 * Build definitions
41 *
42 **************************************************************************/
Ben Hutchingsc5d5f5f2010-06-23 11:30:26 +000043
Ben Hutchings906bb262009-11-29 15:16:19 +000044#define EFX_DRIVER_VERSION "3.0"
Ben Hutchings8ceee662008-04-27 12:55:59 +010045
46#ifdef EFX_ENABLE_DEBUG
47#define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
48#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49#else
50#define EFX_BUG_ON_PARANOID(x) do {} while (0)
51#define EFX_WARN_ON_PARANOID(x) do {} while (0)
52#endif
53
Ben Hutchings8ceee662008-04-27 12:55:59 +010054/**************************************************************************
55 *
56 * Efx data structures
57 *
58 **************************************************************************/
59
60#define EFX_MAX_CHANNELS 32
Ben Hutchings8ceee662008-04-27 12:55:59 +010061#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62
Ben Hutchingsa4900ac2010-04-28 09:30:43 +000063/* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
65 * queues. */
66#define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS
67#define EFX_TXQ_TYPE_OFFLOAD 1
68#define EFX_TXQ_TYPES 2
69#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
Ben Hutchings60ac1062008-09-01 12:44:59 +010070
Ben Hutchings8ceee662008-04-27 12:55:59 +010071/**
72 * struct efx_special_buffer - An Efx special buffer
73 * @addr: CPU base address of the buffer
74 * @dma_addr: DMA base address of the buffer
75 * @len: Buffer length, in bytes
76 * @index: Buffer index within controller;s buffer table
77 * @entries: Number of buffer table entries
78 *
79 * Special buffers are used for the event queues and the TX and RX
80 * descriptor queues for each channel. They are *not* used for the
81 * actual transmit and receive buffers.
Ben Hutchings8ceee662008-04-27 12:55:59 +010082 */
83struct efx_special_buffer {
84 void *addr;
85 dma_addr_t dma_addr;
86 unsigned int len;
87 int index;
88 int entries;
89};
90
Ben Hutchings127e6e12009-11-25 16:09:55 +000091enum efx_flush_state {
92 FLUSH_NONE,
93 FLUSH_PENDING,
94 FLUSH_FAILED,
95 FLUSH_DONE,
96};
97
Ben Hutchings8ceee662008-04-27 12:55:59 +010098/**
99 * struct efx_tx_buffer - An Efx TX buffer
100 * @skb: The associated socket buffer.
101 * Set only on the final fragment of a packet; %NULL for all other
102 * fragments. When this fragment completes, then we can free this
103 * skb.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100104 * @tsoh: The associated TSO header structure, or %NULL if this
105 * buffer is not a TSO header.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100106 * @dma_addr: DMA address of the fragment.
107 * @len: Length of this fragment.
108 * This field is zero when the queue slot is empty.
109 * @continuation: True if this fragment is not the end of a packet.
110 * @unmap_single: True if pci_unmap_single should be used.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100111 * @unmap_len: Length of this fragment to unmap
112 */
113struct efx_tx_buffer {
114 const struct sk_buff *skb;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100115 struct efx_tso_header *tsoh;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100116 dma_addr_t dma_addr;
117 unsigned short len;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100118 bool continuation;
119 bool unmap_single;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100120 unsigned short unmap_len;
121};
122
123/**
124 * struct efx_tx_queue - An Efx TX queue
125 *
126 * This is a ring buffer of TX fragments.
127 * Since the TX completion path always executes on the same
128 * CPU and the xmit path can operate on different CPUs,
129 * performance is increased by ensuring that the completion
130 * path and the xmit path operate on different cache lines.
131 * This is particularly important if the xmit path is always
132 * executing on one CPU which is different from the completion
133 * path. There is also a cache line for members which are
134 * read but not written on the fast path.
135 *
136 * @efx: The associated Efx NIC
137 * @queue: DMA queue number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100138 * @channel: The associated channel
139 * @buffer: The software buffer ring
140 * @txd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000141 * @ptr_mask: The size of the ring minus 1.
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100142 * @flushed: Used when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100143 * @read_count: Current read pointer.
144 * This is the number of buffers that have been removed from both rings.
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100145 * @stopped: Stopped count.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100146 * Set if this TX queue is currently stopping its port.
147 * @insert_count: Current insert pointer
148 * This is the number of buffers that have been added to the
149 * software ring.
150 * @write_count: Current write pointer
151 * This is the number of buffers that have been added to the
152 * hardware ring.
153 * @old_read_count: The value of read_count when last checked.
154 * This is here for performance reasons. The xmit path will
155 * only get the up-to-date value of read_count if this
156 * variable indicates that the queue is full. This is to
157 * avoid cache-line ping-pong between the xmit path and the
158 * completion path.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100159 * @tso_headers_free: A list of TSO headers allocated for this TX queue
160 * that are not in use, and so available for new TSO sends. The list
161 * is protected by the TX queue lock.
162 * @tso_bursts: Number of times TSO xmit invoked by kernel
163 * @tso_long_headers: Number of packets with headers too long for standard
164 * blocks
165 * @tso_packets: Number of packets via the TSO xmit path
Ben Hutchings8ceee662008-04-27 12:55:59 +0100166 */
167struct efx_tx_queue {
168 /* Members which don't change on the fast path */
169 struct efx_nic *efx ____cacheline_aligned_in_smp;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000170 unsigned queue;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100171 struct efx_channel *channel;
172 struct efx_nic *nic;
173 struct efx_tx_buffer *buffer;
174 struct efx_special_buffer txd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000175 unsigned int ptr_mask;
Ben Hutchings127e6e12009-11-25 16:09:55 +0000176 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100177
178 /* Members used mainly on the completion path */
179 unsigned int read_count ____cacheline_aligned_in_smp;
180 int stopped;
181
182 /* Members used only on the xmit path */
183 unsigned int insert_count ____cacheline_aligned_in_smp;
184 unsigned int write_count;
185 unsigned int old_read_count;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100186 struct efx_tso_header *tso_headers_free;
187 unsigned int tso_bursts;
188 unsigned int tso_long_headers;
189 unsigned int tso_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100190};
191
192/**
193 * struct efx_rx_buffer - An Efx RX data buffer
194 * @dma_addr: DMA base address of the buffer
195 * @skb: The associated socket buffer, if any.
196 * If both this and page are %NULL, the buffer slot is currently free.
197 * @page: The associated page buffer, if any.
198 * If both this and skb are %NULL, the buffer slot is currently free.
199 * @data: Pointer to ethernet header
200 * @len: Buffer length, in bytes.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100201 */
202struct efx_rx_buffer {
203 dma_addr_t dma_addr;
204 struct sk_buff *skb;
205 struct page *page;
206 char *data;
207 unsigned int len;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100208};
209
210/**
Steve Hodgson62b330b2010-06-01 11:20:53 +0000211 * struct efx_rx_page_state - Page-based rx buffer state
212 *
213 * Inserted at the start of every page allocated for receive buffers.
214 * Used to facilitate sharing dma mappings between recycled rx buffers
215 * and those passed up to the kernel.
216 *
217 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
218 * When refcnt falls to zero, the page is unmapped for dma
219 * @dma_addr: The dma address of this page.
220 */
221struct efx_rx_page_state {
222 unsigned refcnt;
223 dma_addr_t dma_addr;
224
225 unsigned int __pad[0] ____cacheline_aligned;
226};
227
228/**
Ben Hutchings8ceee662008-04-27 12:55:59 +0100229 * struct efx_rx_queue - An Efx RX queue
230 * @efx: The associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100231 * @buffer: The software buffer ring
232 * @rxd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000233 * @ptr_mask: The size of the ring minus 1.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100234 * @added_count: Number of buffers added to the receive queue.
235 * @notified_count: Number of buffers given to NIC (<= @added_count).
236 * @removed_count: Number of buffers removed from the receive queue.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100237 * @max_fill: RX descriptor maximum fill level (<= ring size)
238 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
239 * (<= @max_fill)
240 * @fast_fill_limit: The level to which a fast fill will fill
241 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
242 * @min_fill: RX descriptor minimum non-zero fill level.
243 * This records the minimum fill level observed when a ring
244 * refill was triggered.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100245 * @alloc_page_count: RX allocation strategy counter.
246 * @alloc_skb_count: RX allocation strategy counter.
Steve Hodgson90d683a2010-06-01 11:19:39 +0000247 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100248 * @flushed: Use when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100249 */
250struct efx_rx_queue {
251 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100252 struct efx_rx_buffer *buffer;
253 struct efx_special_buffer rxd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000254 unsigned int ptr_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100255
256 int added_count;
257 int notified_count;
258 int removed_count;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100259 unsigned int max_fill;
260 unsigned int fast_fill_trigger;
261 unsigned int fast_fill_limit;
262 unsigned int min_fill;
263 unsigned int min_overfill;
264 unsigned int alloc_page_count;
265 unsigned int alloc_skb_count;
Steve Hodgson90d683a2010-06-01 11:19:39 +0000266 struct timer_list slow_fill;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100267 unsigned int slow_fill_count;
268
Ben Hutchings127e6e12009-11-25 16:09:55 +0000269 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100270};
271
272/**
273 * struct efx_buffer - An Efx general-purpose buffer
274 * @addr: host base address of the buffer
275 * @dma_addr: DMA base address of the buffer
276 * @len: Buffer length, in bytes
277 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000278 * The NIC uses these buffers for its interrupt status registers and
Ben Hutchings8ceee662008-04-27 12:55:59 +0100279 * MAC stats dumps.
280 */
281struct efx_buffer {
282 void *addr;
283 dma_addr_t dma_addr;
284 unsigned int len;
285};
286
287
Ben Hutchings8ceee662008-04-27 12:55:59 +0100288enum efx_rx_alloc_method {
289 RX_ALLOC_METHOD_AUTO = 0,
290 RX_ALLOC_METHOD_SKB = 1,
291 RX_ALLOC_METHOD_PAGE = 2,
292};
293
294/**
295 * struct efx_channel - An Efx channel
296 *
297 * A channel comprises an event queue, at least one TX queue, at least
298 * one RX queue, and an associated tasklet for processing the event
299 * queue.
300 *
301 * @efx: Associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100302 * @channel: Channel instance number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100303 * @enabled: Channel enabled indicator
304 * @irq: IRQ number (MSI and MSI-X only)
Ben Hutchings0d86ebd2009-10-23 08:32:13 +0000305 * @irq_moderation: IRQ moderation value (in hardware ticks)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100306 * @napi_dev: Net device used with NAPI
307 * @napi_str: NAPI control structure
308 * @reset_work: Scheduled reset work thread
309 * @work_pending: Is work pending via NAPI?
310 * @eventq: Event queue buffer
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000311 * @eventq_mask: Event queue pointer mask
Ben Hutchings8ceee662008-04-27 12:55:59 +0100312 * @eventq_read_ptr: Event queue read pointer
313 * @last_eventq_read_ptr: Last event queue read pointer value.
Steve Hodgsond730dc52010-06-01 11:19:09 +0000314 * @magic_count: Event queue test event count
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000315 * @irq_count: Number of IRQs since last adaptive moderation decision
316 * @irq_mod_score: IRQ moderation score
Ben Hutchings8ceee662008-04-27 12:55:59 +0100317 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
318 * and diagnostic counters
319 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
320 * descriptors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100321 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100322 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
323 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000324 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
Ben Hutchings8ceee662008-04-27 12:55:59 +0100325 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
326 * @n_rx_overlength: Count of RX_OVERLENGTH errors
327 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
Ben Hutchings8313aca2010-09-10 06:41:57 +0000328 * @rx_queue: RX queue for this channel
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000329 * @tx_stop_count: Core TX queue stop count
330 * @tx_stop_lock: Core TX queue stop lock
Ben Hutchings8313aca2010-09-10 06:41:57 +0000331 * @tx_queue: TX queues for this channel
Ben Hutchings8ceee662008-04-27 12:55:59 +0100332 */
333struct efx_channel {
334 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100335 int channel;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100336 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100337 int irq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100338 unsigned int irq_moderation;
339 struct net_device *napi_dev;
340 struct napi_struct napi_str;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100341 bool work_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100342 struct efx_special_buffer eventq;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000343 unsigned int eventq_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100344 unsigned int eventq_read_ptr;
345 unsigned int last_eventq_read_ptr;
Steve Hodgsond730dc52010-06-01 11:19:09 +0000346 unsigned int magic_count;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100347
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000348 unsigned int irq_count;
349 unsigned int irq_mod_score;
350
Ben Hutchings8ceee662008-04-27 12:55:59 +0100351 int rx_alloc_level;
352 int rx_alloc_push_pages;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100353
354 unsigned n_rx_tobe_disc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100355 unsigned n_rx_ip_hdr_chksum_err;
356 unsigned n_rx_tcp_udp_chksum_err;
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000357 unsigned n_rx_mcast_mismatch;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100358 unsigned n_rx_frm_trunc;
359 unsigned n_rx_overlength;
360 unsigned n_skbuff_leaks;
361
362 /* Used to pipeline received packets in order to optimise memory
363 * access with prefetches.
364 */
365 struct efx_rx_buffer *rx_pkt;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100366 bool rx_pkt_csummed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100367
Ben Hutchings8313aca2010-09-10 06:41:57 +0000368 struct efx_rx_queue rx_queue;
369
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000370 atomic_t tx_stop_count;
371 spinlock_t tx_stop_lock;
Ben Hutchings8313aca2010-09-10 06:41:57 +0000372
373 struct efx_tx_queue tx_queue[2];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100374};
375
Ben Hutchings398468e2009-11-23 16:03:45 +0000376enum efx_led_mode {
377 EFX_LED_OFF = 0,
378 EFX_LED_ON = 1,
379 EFX_LED_DEFAULT = 2
380};
381
Ben Hutchingsc4593022009-11-23 16:08:17 +0000382#define STRING_TABLE_LOOKUP(val, member) \
383 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
384
385extern const char *efx_loopback_mode_names[];
386extern const unsigned int efx_loopback_mode_max;
387#define LOOPBACK_MODE(efx) \
388 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
389
Ben Hutchingsc4593022009-11-23 16:08:17 +0000390extern const char *efx_reset_type_names[];
391extern const unsigned int efx_reset_type_max;
392#define RESET_TYPE(type) \
393 STRING_TABLE_LOOKUP(type, efx_reset_type)
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100394
Ben Hutchings8ceee662008-04-27 12:55:59 +0100395enum efx_int_mode {
396 /* Be careful if altering to correct macro below */
397 EFX_INT_MODE_MSIX = 0,
398 EFX_INT_MODE_MSI = 1,
399 EFX_INT_MODE_LEGACY = 2,
400 EFX_INT_MODE_MAX /* Insert any new items before this */
401};
402#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
403
Ben Hutchings8ceee662008-04-27 12:55:59 +0100404enum nic_state {
405 STATE_INIT = 0,
406 STATE_RUNNING = 1,
407 STATE_FINI = 2,
Ben Hutchings3c787082008-09-01 12:49:08 +0100408 STATE_DISABLED = 3,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100409 STATE_MAX,
410};
411
412/*
413 * Alignment of page-allocated RX buffers
414 *
415 * Controls the number of bytes inserted at the start of an RX buffer.
416 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
417 * of the skb->head for hardware DMA].
418 */
Ben Hutchings13e9ab12008-09-01 12:50:28 +0100419#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Ben Hutchings8ceee662008-04-27 12:55:59 +0100420#define EFX_PAGE_IP_ALIGN 0
421#else
422#define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
423#endif
424
425/*
426 * Alignment of the skb->head which wraps a page-allocated RX buffer
427 *
428 * The skb allocated to wrap an rx_buffer can have this alignment. Since
429 * the data is memcpy'd from the rx_buf, it does not need to be equal to
430 * EFX_PAGE_IP_ALIGN.
431 */
432#define EFX_PAGE_SKB_ALIGN 2
433
434/* Forward declaration */
435struct efx_nic;
436
437/* Pseudo bit-mask flow control field */
438enum efx_fc_type {
Ben Hutchings3f926da2009-04-29 08:20:37 +0000439 EFX_FC_RX = FLOW_CTRL_RX,
440 EFX_FC_TX = FLOW_CTRL_TX,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100441 EFX_FC_AUTO = 4,
442};
443
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800444/**
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000445 * struct efx_link_state - Current state of the link
446 * @up: Link is up
447 * @fd: Link is full-duplex
448 * @fc: Actual flow control flags
449 * @speed: Link speed (Mbps)
450 */
451struct efx_link_state {
452 bool up;
453 bool fd;
454 enum efx_fc_type fc;
455 unsigned int speed;
456};
457
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000458static inline bool efx_link_state_equal(const struct efx_link_state *left,
459 const struct efx_link_state *right)
460{
461 return left->up == right->up && left->fd == right->fd &&
462 left->fc == right->fc && left->speed == right->speed;
463}
464
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000465/**
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800466 * struct efx_mac_operations - Efx MAC operations table
467 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
468 * @update_stats: Update statistics
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000469 * @check_fault: Check fault state. True if fault present.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800470 */
471struct efx_mac_operations {
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000472 int (*reconfigure) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800473 void (*update_stats) (struct efx_nic *efx);
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000474 bool (*check_fault)(struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800475};
476
Ben Hutchings8ceee662008-04-27 12:55:59 +0100477/**
478 * struct efx_phy_operations - Efx PHY operations table
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000479 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
480 * efx->loopback_modes.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100481 * @init: Initialise PHY
482 * @fini: Shut down PHY
483 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000484 * @poll: Update @link_state and report whether it changed.
485 * Serialised by the mac_lock.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800486 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
487 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000488 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800489 * (only needed where AN bit is set in mmds)
Ben Hutchings4f16c072010-02-03 09:30:50 +0000490 * @test_alive: Test that PHY is 'alive' (online)
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000491 * @test_name: Get the name of a PHY-specific test/result
Ben Hutchings4f16c072010-02-03 09:30:50 +0000492 * @run_tests: Run tests and record results as appropriate (offline).
Ben Hutchings17967212008-12-26 13:47:25 -0800493 * Flags are the ethtool tests flags.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100494 */
495struct efx_phy_operations {
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000496 int (*probe) (struct efx_nic *efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100497 int (*init) (struct efx_nic *efx);
498 void (*fini) (struct efx_nic *efx);
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000499 void (*remove) (struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000500 int (*reconfigure) (struct efx_nic *efx);
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000501 bool (*poll) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800502 void (*get_settings) (struct efx_nic *efx,
503 struct ethtool_cmd *ecmd);
504 int (*set_settings) (struct efx_nic *efx,
505 struct ethtool_cmd *ecmd);
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000506 void (*set_npage_adv) (struct efx_nic *efx, u32);
Ben Hutchings4f16c072010-02-03 09:30:50 +0000507 int (*test_alive) (struct efx_nic *efx);
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000508 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
Ben Hutchings17967212008-12-26 13:47:25 -0800509 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100510};
511
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100512/**
513 * @enum efx_phy_mode - PHY operating mode flags
514 * @PHY_MODE_NORMAL: on and should pass traffic
515 * @PHY_MODE_TX_DISABLED: on with TX disabled
Ben Hutchings3e133c42008-11-04 20:34:56 +0000516 * @PHY_MODE_LOW_POWER: set to low power through MDIO
517 * @PHY_MODE_OFF: switched off through external control
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100518 * @PHY_MODE_SPECIAL: on but will not pass traffic
519 */
520enum efx_phy_mode {
521 PHY_MODE_NORMAL = 0,
522 PHY_MODE_TX_DISABLED = 1,
Ben Hutchings3e133c42008-11-04 20:34:56 +0000523 PHY_MODE_LOW_POWER = 2,
524 PHY_MODE_OFF = 4,
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100525 PHY_MODE_SPECIAL = 8,
526};
527
528static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
529{
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100530 return !!(mode & ~PHY_MODE_TX_DISABLED);
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100531}
532
Ben Hutchings8ceee662008-04-27 12:55:59 +0100533/*
534 * Efx extended statistics
535 *
536 * Not all statistics are provided by all supported MACs. The purpose
537 * is this structure is to contain the raw statistics provided by each
538 * MAC.
539 */
540struct efx_mac_stats {
541 u64 tx_bytes;
542 u64 tx_good_bytes;
543 u64 tx_bad_bytes;
544 unsigned long tx_packets;
545 unsigned long tx_bad;
546 unsigned long tx_pause;
547 unsigned long tx_control;
548 unsigned long tx_unicast;
549 unsigned long tx_multicast;
550 unsigned long tx_broadcast;
551 unsigned long tx_lt64;
552 unsigned long tx_64;
553 unsigned long tx_65_to_127;
554 unsigned long tx_128_to_255;
555 unsigned long tx_256_to_511;
556 unsigned long tx_512_to_1023;
557 unsigned long tx_1024_to_15xx;
558 unsigned long tx_15xx_to_jumbo;
559 unsigned long tx_gtjumbo;
560 unsigned long tx_collision;
561 unsigned long tx_single_collision;
562 unsigned long tx_multiple_collision;
563 unsigned long tx_excessive_collision;
564 unsigned long tx_deferred;
565 unsigned long tx_late_collision;
566 unsigned long tx_excessive_deferred;
567 unsigned long tx_non_tcpudp;
568 unsigned long tx_mac_src_error;
569 unsigned long tx_ip_src_error;
570 u64 rx_bytes;
571 u64 rx_good_bytes;
572 u64 rx_bad_bytes;
573 unsigned long rx_packets;
574 unsigned long rx_good;
575 unsigned long rx_bad;
576 unsigned long rx_pause;
577 unsigned long rx_control;
578 unsigned long rx_unicast;
579 unsigned long rx_multicast;
580 unsigned long rx_broadcast;
581 unsigned long rx_lt64;
582 unsigned long rx_64;
583 unsigned long rx_65_to_127;
584 unsigned long rx_128_to_255;
585 unsigned long rx_256_to_511;
586 unsigned long rx_512_to_1023;
587 unsigned long rx_1024_to_15xx;
588 unsigned long rx_15xx_to_jumbo;
589 unsigned long rx_gtjumbo;
590 unsigned long rx_bad_lt64;
591 unsigned long rx_bad_64_to_15xx;
592 unsigned long rx_bad_15xx_to_jumbo;
593 unsigned long rx_bad_gtjumbo;
594 unsigned long rx_overflow;
595 unsigned long rx_missed;
596 unsigned long rx_false_carrier;
597 unsigned long rx_symbol_error;
598 unsigned long rx_align_error;
599 unsigned long rx_length_error;
600 unsigned long rx_internal_error;
601 unsigned long rx_good_lt64;
602};
603
604/* Number of bits used in a multicast filter hash address */
605#define EFX_MCAST_HASH_BITS 8
606
607/* Number of (single-bit) entries in a multicast filter hash */
608#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
609
610/* An Efx multicast filter hash */
611union efx_multicast_hash {
612 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
613 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
614};
615
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000616struct efx_filter_state;
617
Ben Hutchings8ceee662008-04-27 12:55:59 +0100618/**
619 * struct efx_nic - an Efx NIC
620 * @name: Device name (net device name or bus id before net device registered)
621 * @pci_dev: The PCI device
622 * @type: Controller type attributes
623 * @legacy_irq: IRQ number
Ben Hutchings94dec6a2010-12-07 19:24:45 +0000624 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
Ben Hutchings8d9853d2008-07-18 19:01:20 +0100625 * @workqueue: Workqueue for port reconfigures and the HW monitor.
626 * Work items do not hold and must not acquire RTNL.
Ben Hutchings6977dc62008-12-26 13:44:39 -0800627 * @workqueue_name: Name of workqueue
Ben Hutchings8ceee662008-04-27 12:55:59 +0100628 * @reset_work: Scheduled reset workitem
629 * @monitor_work: Hardware monitor workitem
630 * @membase_phys: Memory BAR value as physical address
631 * @membase: Memory BAR value
632 * @biu_lock: BIU (bus interface unit) lock
633 * @interrupt_mode: Interrupt mode
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000634 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
635 * @irq_rx_moderation: IRQ moderation time for RX event queues
Ben Hutchings62776d02010-06-23 11:30:07 +0000636 * @msg_enable: Log message enable flags
Ben Hutchings8ceee662008-04-27 12:55:59 +0100637 * @state: Device state flag. Serialised by the rtnl_lock.
638 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
639 * @tx_queue: TX DMA queues
640 * @rx_queue: RX DMA queues
641 * @channel: Channels
Ben Hutchings46426102010-09-10 06:42:33 +0000642 * @channel_name: Names for channels and their IRQs
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000643 * @rxq_entries: Size of receive queues requested by user.
644 * @txq_entries: Size of transmit queues requested by user.
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000645 * @next_buffer_table: First available buffer table id
Neil Turton28b581a2008-12-12 21:41:06 -0800646 * @n_channels: Number of channels in use
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000647 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
648 * @n_tx_channels: Number of channels used for TX
Ben Hutchings8ceee662008-04-27 12:55:59 +0100649 * @rx_buffer_len: RX buffer length
650 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
Ben Hutchings765c9f42010-06-30 05:06:28 +0000651 * @rx_indir_table: Indirection table for RSS
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000652 * @int_error_count: Number of internal errors seen recently
653 * @int_error_expire: Time at which error count will be expired
Ben Hutchings8ceee662008-04-27 12:55:59 +0100654 * @irq_status: Interrupt status buffer
655 * @last_irq_cpu: Last CPU to handle interrupt.
656 * This register is written with the SMP processor ID whenever an
Ben Hutchings754c6532010-02-03 09:31:57 +0000657 * interrupt is handled. It is used by efx_nic_test_interrupt()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100658 * to verify that an interrupt has occurred.
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000659 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
Steve Hodgson63695452010-04-28 09:27:36 +0000660 * @fatal_irq_level: IRQ level (bit number) used for serious errors
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100661 * @spi_flash: SPI flash device
Ben Hutchings76884832009-11-29 15:10:44 +0000662 * This field will be %NULL if no flash device is present (or for Siena).
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100663 * @spi_eeprom: SPI EEPROM device
Ben Hutchings76884832009-11-29 15:10:44 +0000664 * This field will be %NULL if no EEPROM device is present (or for Siena).
Ben Hutchingsf4150722008-11-04 20:34:28 +0000665 * @spi_lock: SPI bus lock
Ben Hutchings76884832009-11-29 15:10:44 +0000666 * @mtd_list: List of MTDs attached to the NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100667 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
668 * @nic_data: Hardware dependant state
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100669 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
670 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100671 * @port_enabled: Port enabled indicator.
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000672 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
673 * efx_mac_work() with kernel interfaces. Safe to read under any
674 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
675 * be held to modify it.
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100676 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100677 * @port_initialized: Port initialized?
678 * @net_dev: Operating system network device. Consider holding the rtnl lock
679 * @rx_checksum_enabled: RX checksumming enabled
Ben Hutchings8ceee662008-04-27 12:55:59 +0100680 * @mac_stats: MAC statistics. These include all statistics the MACs
681 * can provide. Generic code converts these into a standard
682 * &struct net_device_stats.
683 * @stats_buffer: DMA buffer for statistics
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100684 * @stats_lock: Statistics update lock. Serialises statistics fetches
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800685 * @mac_op: MAC interface
Ben Hutchings8ceee662008-04-27 12:55:59 +0100686 * @mac_address: Permanent MAC address
687 * @phy_type: PHY type
Steve Hodgsonab867462009-11-28 05:34:44 +0000688 * @mdio_lock: MDIO lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100689 * @phy_op: PHY interface
690 * @phy_data: PHY private data (including PHY-specific stats)
Ben Hutchings68e7f452009-04-29 08:05:08 +0000691 * @mdio: PHY MDIO interface
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000692 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100693 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000694 * @xmac_poll_required: XMAC link state needs polling
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000695 * @link_advertising: Autonegotiation advertising flags
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000696 * @link_state: Current state of the link
Ben Hutchings8ceee662008-04-27 12:55:59 +0100697 * @n_link_state_changes: Number of times the link has changed state
698 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
699 * @multicast_hash: Multicast hash table
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800700 * @wanted_fc: Wanted flow control flags
Ben Hutchings8be4f3e2009-11-25 16:12:16 +0000701 * @mac_work: Work item for changing MAC promiscuity and multicast hash
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100702 * @loopback_mode: Loopback status
703 * @loopback_modes: Supported loopback mode bitmask
704 * @loopback_selftest: Offline self-test private state
Ben Hutchings8ceee662008-04-27 12:55:59 +0100705 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000706 * This is stored in the private area of the &struct net_device.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100707 */
708struct efx_nic {
709 char name[IFNAMSIZ];
710 struct pci_dev *pci_dev;
711 const struct efx_nic_type *type;
712 int legacy_irq;
Ben Hutchings94dec6a2010-12-07 19:24:45 +0000713 bool legacy_irq_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100714 struct workqueue_struct *workqueue;
Ben Hutchings6977dc62008-12-26 13:44:39 -0800715 char workqueue_name[16];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100716 struct work_struct reset_work;
717 struct delayed_work monitor_work;
Ben Hutchings086ea352008-05-16 21:17:06 +0100718 resource_size_t membase_phys;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100719 void __iomem *membase;
720 spinlock_t biu_lock;
721 enum efx_int_mode interrupt_mode;
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000722 bool irq_rx_adaptive;
723 unsigned int irq_rx_moderation;
Ben Hutchings62776d02010-06-23 11:30:07 +0000724 u32 msg_enable;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100725
Ben Hutchings8ceee662008-04-27 12:55:59 +0100726 enum nic_state state;
727 enum reset_type reset_pending;
728
Ben Hutchings8313aca2010-09-10 06:41:57 +0000729 struct efx_channel *channel[EFX_MAX_CHANNELS];
Ben Hutchingsefbc2d72010-09-13 04:14:49 +0000730 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100731
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000732 unsigned rxq_entries;
733 unsigned txq_entries;
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000734 unsigned next_buffer_table;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000735 unsigned n_channels;
736 unsigned n_rx_channels;
737 unsigned n_tx_channels;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100738 unsigned int rx_buffer_len;
739 unsigned int rx_buffer_order;
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000740 u8 rx_hash_key[40];
Ben Hutchings765c9f42010-06-30 05:06:28 +0000741 u32 rx_indir_table[128];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100742
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000743 unsigned int_error_count;
744 unsigned long int_error_expire;
745
Ben Hutchings8ceee662008-04-27 12:55:59 +0100746 struct efx_buffer irq_status;
747 volatile signed int last_irq_cpu;
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000748 unsigned irq_zero_count;
Steve Hodgson63695452010-04-28 09:27:36 +0000749 unsigned fatal_irq_level;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100750
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100751 struct efx_spi_device *spi_flash;
752 struct efx_spi_device *spi_eeprom;
Ben Hutchingsf4150722008-11-04 20:34:28 +0000753 struct mutex spi_lock;
Ben Hutchings76884832009-11-29 15:10:44 +0000754#ifdef CONFIG_SFC_MTD
755 struct list_head mtd_list;
756#endif
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100757
Ben Hutchings8ceee662008-04-27 12:55:59 +0100758 unsigned n_rx_nodesc_drop_cnt;
759
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000760 void *nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100761
762 struct mutex mac_lock;
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800763 struct work_struct mac_work;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100764 bool port_enabled;
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100765 bool port_inhibited;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100766
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100767 bool port_initialized;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100768 struct net_device *net_dev;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100769 bool rx_checksum_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100770
Ben Hutchings8ceee662008-04-27 12:55:59 +0100771 struct efx_mac_stats mac_stats;
772 struct efx_buffer stats_buffer;
773 spinlock_t stats_lock;
774
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800775 struct efx_mac_operations *mac_op;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100776 unsigned char mac_address[ETH_ALEN];
777
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000778 unsigned int phy_type;
Steve Hodgsonab867462009-11-28 05:34:44 +0000779 struct mutex mdio_lock;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100780 struct efx_phy_operations *phy_op;
781 void *phy_data;
Ben Hutchings68e7f452009-04-29 08:05:08 +0000782 struct mdio_if_info mdio;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000783 unsigned int mdio_bus;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100784 enum efx_phy_mode phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100785
Ben Hutchings9007b9f2009-11-25 16:12:01 +0000786 bool xmac_poll_required;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000787 u32 link_advertising;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000788 struct efx_link_state link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100789 unsigned int n_link_state_changes;
790
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100791 bool promiscuous;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100792 union efx_multicast_hash multicast_hash;
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800793 enum efx_fc_type wanted_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100794
795 atomic_t rx_reset;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100796 enum efx_loopback_mode loopback_mode;
Ben Hutchingse58f69f2009-11-29 15:08:41 +0000797 u64 loopback_modes;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100798
799 void *loopback_selftest;
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000800
801 struct efx_filter_state *filter_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100802};
803
Ben Hutchings55668612008-05-16 21:16:10 +0100804static inline int efx_dev_registered(struct efx_nic *efx)
805{
806 return efx->net_dev->reg_state == NETREG_REGISTERED;
807}
808
809/* Net device name, for inclusion in log messages if it has been registered.
810 * Use efx->name not efx->net_dev->name so that races with (un)registration
811 * are harmless.
812 */
813static inline const char *efx_dev_name(struct efx_nic *efx)
814{
815 return efx_dev_registered(efx) ? efx->name : "";
816}
817
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000818static inline unsigned int efx_port_num(struct efx_nic *efx)
819{
Ben Hutchings3df95ce2010-06-02 10:39:56 +0000820 return efx->net_dev->dev_id;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000821}
822
Ben Hutchings8ceee662008-04-27 12:55:59 +0100823/**
824 * struct efx_nic_type - Efx device type definition
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000825 * @probe: Probe the controller
826 * @remove: Free resources allocated by probe()
827 * @init: Initialise the controller
828 * @fini: Shut down the controller
829 * @monitor: Periodic function for polling link state and hardware monitor
830 * @reset: Reset the controller hardware and possibly the PHY. This will
831 * be called while the controller is uninitialised.
832 * @probe_port: Probe the MAC and PHY
833 * @remove_port: Free resources allocated by probe_port()
834 * @prepare_flush: Prepare the hardware for flushing the DMA queues
835 * @update_stats: Update statistics not provided by event handling
836 * @start_stats: Start the regular fetching of statistics
837 * @stop_stats: Stop the regular fetching of statistics
Ben Hutchings06629f02009-11-29 03:43:43 +0000838 * @set_id_led: Set state of identifying LED or revert to automatic function
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000839 * @push_irq_moderation: Apply interrupt moderation value
840 * @push_multicast_hash: Apply multicast hash table
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000841 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
Ben Hutchings89c758f2009-11-29 03:43:07 +0000842 * @get_wol: Get WoL configuration from driver state
843 * @set_wol: Push WoL configuration to the NIC
844 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000845 * @test_registers: Test read/write functionality of control registers
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000846 * @test_nvram: Test validity of NVRAM contents
Steve Hodgsonb895d732009-11-28 05:35:00 +0000847 * @default_mac_ops: efx_mac_operations to set at startup
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000848 * @revision: Hardware architecture revision
Ben Hutchings8ceee662008-04-27 12:55:59 +0100849 * @mem_map_size: Memory BAR mapped size
850 * @txd_ptr_tbl_base: TX descriptor ring base address
851 * @rxd_ptr_tbl_base: RX descriptor ring base address
852 * @buf_tbl_base: Buffer table base address
853 * @evq_ptr_tbl_base: Event queue pointer table base address
854 * @evq_rptr_tbl_base: Event queue read-pointer table base address
Ben Hutchings8ceee662008-04-27 12:55:59 +0100855 * @max_dma_mask: Maximum possible DMA mask
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000856 * @rx_buffer_hash_size: Size of hash at start of RX buffer
857 * @rx_buffer_padding: Size of padding at end of RX buffer
Ben Hutchings8ceee662008-04-27 12:55:59 +0100858 * @max_interrupt_mode: Highest capability interrupt mode supported
859 * from &enum efx_init_mode.
860 * @phys_addr_channels: Number of channels with physically addressed
861 * descriptors
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000862 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
863 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
Ben Hutchingsc383b532009-11-29 15:11:02 +0000864 * @offload_features: net_device feature flags for protocol offload
865 * features implemented in hardware
Ben Hutchingseb9f6742009-11-29 03:43:15 +0000866 * @reset_world_flags: Flags for additional components covered by
867 * reset method RESET_TYPE_WORLD
Ben Hutchings8ceee662008-04-27 12:55:59 +0100868 */
869struct efx_nic_type {
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000870 int (*probe)(struct efx_nic *efx);
871 void (*remove)(struct efx_nic *efx);
872 int (*init)(struct efx_nic *efx);
873 void (*fini)(struct efx_nic *efx);
874 void (*monitor)(struct efx_nic *efx);
875 int (*reset)(struct efx_nic *efx, enum reset_type method);
876 int (*probe_port)(struct efx_nic *efx);
877 void (*remove_port)(struct efx_nic *efx);
878 void (*prepare_flush)(struct efx_nic *efx);
879 void (*update_stats)(struct efx_nic *efx);
880 void (*start_stats)(struct efx_nic *efx);
881 void (*stop_stats)(struct efx_nic *efx);
Ben Hutchings06629f02009-11-29 03:43:43 +0000882 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000883 void (*push_irq_moderation)(struct efx_channel *channel);
884 void (*push_multicast_hash)(struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000885 int (*reconfigure_port)(struct efx_nic *efx);
Ben Hutchings89c758f2009-11-29 03:43:07 +0000886 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
887 int (*set_wol)(struct efx_nic *efx, u32 type);
888 void (*resume_wol)(struct efx_nic *efx);
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000889 int (*test_registers)(struct efx_nic *efx);
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000890 int (*test_nvram)(struct efx_nic *efx);
Steve Hodgsonb895d732009-11-28 05:35:00 +0000891 struct efx_mac_operations *default_mac_ops;
892
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000893 int revision;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100894 unsigned int mem_map_size;
895 unsigned int txd_ptr_tbl_base;
896 unsigned int rxd_ptr_tbl_base;
897 unsigned int buf_tbl_base;
898 unsigned int evq_ptr_tbl_base;
899 unsigned int evq_rptr_tbl_base;
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100900 u64 max_dma_mask;
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000901 unsigned int rx_buffer_hash_size;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100902 unsigned int rx_buffer_padding;
903 unsigned int max_interrupt_mode;
904 unsigned int phys_addr_channels;
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000905 unsigned int tx_dc_base;
906 unsigned int rx_dc_base;
Ben Hutchingsc383b532009-11-29 15:11:02 +0000907 unsigned long offload_features;
Ben Hutchingseb9f6742009-11-29 03:43:15 +0000908 u32 reset_world_flags;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100909};
910
911/**************************************************************************
912 *
913 * Prototypes and inline functions
914 *
915 *************************************************************************/
916
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000917static inline struct efx_channel *
918efx_get_channel(struct efx_nic *efx, unsigned index)
919{
920 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
Ben Hutchings8313aca2010-09-10 06:41:57 +0000921 return efx->channel[index];
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000922}
923
Ben Hutchings8ceee662008-04-27 12:55:59 +0100924/* Iterate over all used channels */
925#define efx_for_each_channel(_channel, _efx) \
Ben Hutchings8313aca2010-09-10 06:41:57 +0000926 for (_channel = (_efx)->channel[0]; \
927 _channel; \
928 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
929 (_efx)->channel[_channel->channel + 1] : NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100930
Ben Hutchings8313aca2010-09-10 06:41:57 +0000931extern struct efx_tx_queue *
932efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type);
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000933
934static inline struct efx_tx_queue *
935efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
936{
937 struct efx_tx_queue *tx_queue = channel->tx_queue;
938 EFX_BUG_ON_PARANOID(type >= EFX_TXQ_TYPES);
Ben Hutchings8313aca2010-09-10 06:41:57 +0000939 return tx_queue->channel ? tx_queue + type : NULL;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000940}
Ben Hutchings8ceee662008-04-27 12:55:59 +0100941
942/* Iterate over all TX queues belonging to a channel */
943#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
Ben Hutchings8313aca2010-09-10 06:41:57 +0000944 for (_tx_queue = efx_channel_get_tx_queue(channel, 0); \
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000945 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
946 _tx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100947
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000948static inline struct efx_rx_queue *
949efx_get_rx_queue(struct efx_nic *efx, unsigned index)
950{
951 EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels);
Ben Hutchings8313aca2010-09-10 06:41:57 +0000952 return &efx->channel[index]->rx_queue;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000953}
954
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000955static inline struct efx_rx_queue *
956efx_channel_get_rx_queue(struct efx_channel *channel)
957{
Ben Hutchings8313aca2010-09-10 06:41:57 +0000958 return channel->channel < channel->efx->n_rx_channels ?
959 &channel->rx_queue : NULL;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000960}
961
Ben Hutchings8ceee662008-04-27 12:55:59 +0100962/* Iterate over all RX queues belonging to a channel */
963#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
Ben Hutchings8313aca2010-09-10 06:41:57 +0000964 for (_rx_queue = efx_channel_get_rx_queue(channel); \
Ben Hutchingsa2589022008-09-01 12:47:57 +0100965 _rx_queue; \
Ben Hutchings8313aca2010-09-10 06:41:57 +0000966 _rx_queue = NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100967
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000968static inline struct efx_channel *
969efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
970{
Ben Hutchings8313aca2010-09-10 06:41:57 +0000971 return container_of(rx_queue, struct efx_channel, rx_queue);
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000972}
973
974static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
975{
Ben Hutchings8313aca2010-09-10 06:41:57 +0000976 return efx_rx_queue_channel(rx_queue)->channel;
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000977}
978
Ben Hutchings8ceee662008-04-27 12:55:59 +0100979/* Returns a pointer to the specified receive buffer in the RX
980 * descriptor queue.
981 */
982static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
983 unsigned int index)
984{
Eric Dumazet807540b2010-09-23 05:40:09 +0000985 return &rx_queue->buffer[index];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100986}
987
988/* Set bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +0100989static inline void set_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100990{
991 addr[nr / 8] |= (1 << (nr % 8));
992}
993
994/* Clear bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +0100995static inline void clear_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100996{
997 addr[nr / 8] &= ~(1 << (nr % 8));
998}
999
1000
1001/**
1002 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1003 *
1004 * This calculates the maximum frame length that will be used for a
1005 * given MTU. The frame length will be equal to the MTU plus a
1006 * constant amount of header space and padding. This is the quantity
1007 * that the net driver will program into the MAC as the maximum frame
1008 * length.
1009 *
Ben Hutchings754c6532010-02-03 09:31:57 +00001010 * The 10G MAC requires 8-byte alignment on the frame
Ben Hutchings8ceee662008-04-27 12:55:59 +01001011 * length, so we round up to the nearest 8.
Ben Hutchingscc117632009-08-26 08:17:59 +00001012 *
1013 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1014 * XGMII cycle). If the frame length reaches the maximum value in the
1015 * same cycle, the XMAC can miss the IPG altogether. We work around
1016 * this by adding a further 16 bytes.
Ben Hutchings8ceee662008-04-27 12:55:59 +01001017 */
1018#define EFX_MAX_FRAME_LEN(mtu) \
Ben Hutchingscc117632009-08-26 08:17:59 +00001019 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001020
1021
1022#endif /* EFX_NET_DRIVER_H */