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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/arm/mach-pxa/time.c
3 *
Bill Gatliff7bbb18c2007-07-21 03:39:36 +01004 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
6 *
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/kernel.h>
16#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/interrupt.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020018#include <linux/clk.h>
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010019#include <linux/clockchips.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020020#include <linux/of_address.h>
21#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070022#include <linux/sched_clock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010024#include <asm/div64.h>
Robert Jarzmikab5354c2014-07-14 18:52:02 +020025
26#define OSMR0 0x00 /* OS Timer 0 Match Register */
27#define OSMR1 0x04 /* OS Timer 1 Match Register */
28#define OSMR2 0x08 /* OS Timer 2 Match Register */
29#define OSMR3 0x0C /* OS Timer 3 Match Register */
30
31#define OSCR 0x10 /* OS Timer Counter Register */
32#define OSSR 0x14 /* OS Timer Status Register */
33#define OWER 0x18 /* OS Timer Watchdog Enable Register */
34#define OIER 0x1C /* OS Timer Interrupt Enable Register */
35
36#define OSSR_M3 (1 << 3) /* Match status channel 3 */
37#define OSSR_M2 (1 << 2) /* Match status channel 2 */
38#define OSSR_M1 (1 << 1) /* Match status channel 1 */
39#define OSSR_M0 (1 << 0) /* Match status channel 0 */
40
41#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010043/*
44 * This is PXA's sched_clock implementation. This has a resolution
45 * of at least 308 ns and a maximum value of 208 days.
46 *
47 * The return value is guaranteed to be monotonic in that range as
48 * long as there is always less than 582 seconds between successive
49 * calls to sched_clock() which should always be the case in practice.
50 */
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010051
Robert Jarzmikab5354c2014-07-14 18:52:02 +020052#define timer_readl(reg) readl_relaxed(timer_base + (reg))
53#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
54
55static void __iomem *timer_base;
56
Stephen Boyd364ed1e2013-11-15 15:26:19 -080057static u64 notrace pxa_read_sched_clock(void)
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010058{
Robert Jarzmikab5354c2014-07-14 18:52:02 +020059 return timer_readl(OSCR);
Nicolas Pitre6c3a1582007-08-17 16:55:22 +010060}
61
62
Russell Kinga88264c2007-11-12 22:45:16 +000063#define MIN_OSCR_DELTA 16
64
Linus Torvalds1da177e2005-04-16 15:20:36 -070065static irqreturn_t
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010066pxa_ost0_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070067{
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010068 struct clock_event_device *c = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Russell Kinga88264c2007-11-12 22:45:16 +000070 /* Disarm the compare/match, signal the event. */
Robert Jarzmikab5354c2014-07-14 18:52:02 +020071 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
72 timer_writel(OSSR_M0, OSSR);
Russell Kinga88264c2007-11-12 22:45:16 +000073 c->event_handler(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 return IRQ_HANDLED;
76}
77
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010078static int
79pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
80{
Uwe Kleine-Königa602f0f2009-12-17 12:43:29 +010081 unsigned long next, oscr;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010082
Robert Jarzmikab5354c2014-07-14 18:52:02 +020083 timer_writel(timer_readl(OIER) | OIER_E0, OIER);
84 next = timer_readl(OSCR) + delta;
85 timer_writel(next, OSMR0);
86 oscr = timer_readl(OSCR);
Russell King91bc51d2007-11-08 23:35:46 +000087
88 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010089}
90
Viresh Kumar47d490e2015-06-18 16:24:30 +053091static int pxa_osmr0_shutdown(struct clock_event_device *evt)
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010092{
Viresh Kumar47d490e2015-06-18 16:24:30 +053093 /* initializing, released, or preparing for suspend */
94 timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
95 timer_writel(OSSR_M0, OSSR);
96 return 0;
Bill Gatliff7bbb18c2007-07-21 03:39:36 +010097}
98
Stephen Warren5b30d5b2012-11-07 16:34:13 -070099#ifdef CONFIG_PM
100static unsigned long osmr[4], oier, oscr;
101
102static void pxa_timer_suspend(struct clock_event_device *cedev)
103{
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200104 osmr[0] = timer_readl(OSMR0);
105 osmr[1] = timer_readl(OSMR1);
106 osmr[2] = timer_readl(OSMR2);
107 osmr[3] = timer_readl(OSMR3);
108 oier = timer_readl(OIER);
109 oscr = timer_readl(OSCR);
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700110}
111
112static void pxa_timer_resume(struct clock_event_device *cedev)
113{
114 /*
115 * Ensure that we have at least MIN_OSCR_DELTA between match
116 * register 0 and the OSCR, to guarantee that we will receive
117 * the one-shot timer interrupt. We adjust OSMR0 in preference
118 * to OSCR to guarantee that OSCR is monotonically incrementing.
119 */
120 if (osmr[0] - oscr < MIN_OSCR_DELTA)
121 osmr[0] += MIN_OSCR_DELTA;
122
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200123 timer_writel(osmr[0], OSMR0);
124 timer_writel(osmr[1], OSMR1);
125 timer_writel(osmr[2], OSMR2);
126 timer_writel(osmr[3], OSMR3);
127 timer_writel(oier, OIER);
128 timer_writel(oscr, OSCR);
Stephen Warren5b30d5b2012-11-07 16:34:13 -0700129}
130#else
131#define pxa_timer_suspend NULL
132#define pxa_timer_resume NULL
133#endif
134
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100135static struct clock_event_device ckevt_pxa_osmr0 = {
Viresh Kumar47d490e2015-06-18 16:24:30 +0530136 .name = "osmr0",
137 .features = CLOCK_EVT_FEAT_ONESHOT,
138 .rating = 200,
139 .set_next_event = pxa_osmr0_set_next_event,
140 .set_state_shutdown = pxa_osmr0_shutdown,
141 .set_state_oneshot = pxa_osmr0_shutdown,
142 .suspend = pxa_timer_suspend,
143 .resume = pxa_timer_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144};
145
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100146static struct irqaction pxa_ost0_irq = {
147 .name = "ost0",
Michael Opdenackered7936f2013-12-09 11:22:22 +0100148 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100149 .handler = pxa_ost0_interrupt,
150 .dev_id = &ckevt_pxa_osmr0,
151};
152
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200153static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154{
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200155 int ret;
156
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200157 timer_writel(0, OIER);
158 timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159
Stephen Boyd364ed1e2013-11-15 15:26:19 -0800160 sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
Nicolas Pitre6c3a1582007-08-17 16:55:22 +0100161
Rusty Russell320ab2b2008-12-13 21:20:26 +1030162 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200164 ret = setup_irq(irq, &pxa_ost0_irq);
165 if (ret) {
166 pr_err("Failed to setup irq");
167 return ret;
168 }
Bill Gatliff7bbb18c2007-07-21 03:39:36 +0100169
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200170 ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
171 32, clocksource_mmio_readl_up);
172 if (ret) {
173 pr_err("Failed to init clocksource");
174 return ret;
175 }
176
Olof Johansson8d849812013-01-14 10:20:02 -0800177 clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200178 MIN_OSCR_DELTA * 2, 0x7fffffff);
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200179
180 return 0;
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200181}
182
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200183static int __init pxa_timer_dt_init(struct device_node *np)
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200184{
185 struct clk *clk;
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200186 int irq, ret;
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200187
188 /* timer registers are shared with watchdog timer */
189 timer_base = of_iomap(np, 0);
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200190 if (!timer_base) {
191 pr_err("%s: unable to map resource\n", np->name);
192 return -ENXIO;
193 }
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200194
195 clk = of_clk_get(np, 0);
196 if (IS_ERR(clk)) {
197 pr_crit("%s: unable to get clk\n", np->name);
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200198 return PTR_ERR(clk);
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200199 }
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200200
201 ret = clk_prepare_enable(clk);
202 if (ret) {
203 pr_crit("Failed to prepare clock");
204 return ret;
205 }
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200206
207 /* we are only interested in OS-timer0 irq */
208 irq = irq_of_parse_and_map(np, 0);
209 if (irq <= 0) {
210 pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200211 return -EINVAL;
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200212 }
213
Daniel Lezcanobe3aff82016-06-06 17:58:27 +0200214 return pxa_timer_common_init(irq, clk_get_rate(clk));
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200215}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200216CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
Robert Jarzmikab5354c2014-07-14 18:52:02 +0200217
218/*
219 * Legacy timer init for non device-tree boards.
220 */
221void __init pxa_timer_nodt_init(int irq, void __iomem *base,
222 unsigned long clock_tick_rate)
223{
224 struct clk *clk;
225
226 timer_base = base;
227 clk = clk_get(NULL, "OSTIMER0");
228 if (clk && !IS_ERR(clk))
229 clk_prepare_enable(clk);
230 else
231 pr_crit("%s: unable to get clk\n", __func__);
232
233 pxa_timer_common_init(irq, clock_tick_rate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234}