Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1 | /* |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 2 | * Intel I/OAT DMA Linux driver |
Dave Jiang | 85596a1 | 2015-08-11 08:48:10 -0700 | [diff] [blame] | 3 | * Copyright(c) 2004 - 2015 Intel Corporation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 14 | * The full GNU General Public License is included in this distribution in |
| 15 | * the file called "COPYING". |
| 16 | * |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | /* |
| 20 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous |
| 21 | * copy operations. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 26 | #include <linux/slab.h> |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 27 | #include <linux/pci.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/dmaengine.h> |
| 30 | #include <linux/delay.h> |
David S. Miller | 6b00c92 | 2006-05-23 17:37:58 -0700 | [diff] [blame] | 31 | #include <linux/dma-mapping.h> |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 32 | #include <linux/workqueue.h> |
Paul Gortmaker | 70c7160 | 2011-05-22 16:47:17 -0400 | [diff] [blame] | 33 | #include <linux/prefetch.h> |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 34 | #include <linux/sizes.h> |
Dan Williams | 584ec22 | 2009-07-28 14:32:12 -0700 | [diff] [blame] | 35 | #include "dma.h" |
| 36 | #include "registers.h" |
| 37 | #include "hw.h" |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 38 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 39 | #include "../dmaengine.h" |
| 40 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 41 | static void ioat_eh(struct ioatdma_chan *ioat_chan); |
| 42 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 43 | /** |
| 44 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode |
| 45 | * @irq: interrupt id |
| 46 | * @data: interrupt data |
| 47 | */ |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 48 | irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 49 | { |
| 50 | struct ioatdma_device *instance = data; |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 51 | struct ioatdma_chan *ioat_chan; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 52 | unsigned long attnstatus; |
| 53 | int bit; |
| 54 | u8 intrctrl; |
| 55 | |
| 56 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 57 | |
| 58 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) |
| 59 | return IRQ_NONE; |
| 60 | |
| 61 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { |
| 62 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 63 | return IRQ_NONE; |
| 64 | } |
| 65 | |
| 66 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 67 | for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 68 | ioat_chan = ioat_chan_by_index(instance, bit); |
| 69 | if (test_bit(IOAT_RUN, &ioat_chan->state)) |
| 70 | tasklet_schedule(&ioat_chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 74 | return IRQ_HANDLED; |
| 75 | } |
| 76 | |
| 77 | /** |
| 78 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode |
| 79 | * @irq: interrupt id |
| 80 | * @data: interrupt data |
| 81 | */ |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 82 | irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 83 | { |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 84 | struct ioatdma_chan *ioat_chan = data; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 85 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 86 | if (test_bit(IOAT_RUN, &ioat_chan->state)) |
| 87 | tasklet_schedule(&ioat_chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 88 | |
| 89 | return IRQ_HANDLED; |
| 90 | } |
| 91 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 92 | void ioat_stop(struct ioatdma_chan *ioat_chan) |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 93 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 94 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
| 95 | struct pci_dev *pdev = ioat_dma->pdev; |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 96 | int chan_id = chan_num(ioat_chan); |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 97 | struct msix_entry *msix; |
| 98 | |
| 99 | /* 1/ stop irq from firing tasklets |
| 100 | * 2/ stop the tasklet from re-arming irqs |
| 101 | */ |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 102 | clear_bit(IOAT_RUN, &ioat_chan->state); |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 103 | |
| 104 | /* flush inflight interrupts */ |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 105 | switch (ioat_dma->irq_mode) { |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 106 | case IOAT_MSIX: |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 107 | msix = &ioat_dma->msix_entries[chan_id]; |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 108 | synchronize_irq(msix->vector); |
| 109 | break; |
| 110 | case IOAT_MSI: |
| 111 | case IOAT_INTX: |
| 112 | synchronize_irq(pdev->irq); |
| 113 | break; |
| 114 | default: |
| 115 | break; |
| 116 | } |
| 117 | |
| 118 | /* flush inflight timers */ |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 119 | del_timer_sync(&ioat_chan->timer); |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 120 | |
| 121 | /* flush inflight tasklet runs */ |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 122 | tasklet_kill(&ioat_chan->cleanup_task); |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 123 | |
| 124 | /* final cleanup now that everything is quiesced and can't re-arm */ |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 125 | ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan); |
Dan Williams | da87ca4 | 2014-02-19 16:19:35 -0800 | [diff] [blame] | 126 | } |
| 127 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 128 | static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 129 | { |
| 130 | ioat_chan->dmacount += ioat_ring_pending(ioat_chan); |
| 131 | ioat_chan->issued = ioat_chan->head; |
| 132 | writew(ioat_chan->dmacount, |
| 133 | ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); |
| 134 | dev_dbg(to_dev(ioat_chan), |
| 135 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", |
| 136 | __func__, ioat_chan->head, ioat_chan->tail, |
| 137 | ioat_chan->issued, ioat_chan->dmacount); |
| 138 | } |
| 139 | |
| 140 | void ioat_issue_pending(struct dma_chan *c) |
| 141 | { |
| 142 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
| 143 | |
| 144 | if (ioat_ring_pending(ioat_chan)) { |
| 145 | spin_lock_bh(&ioat_chan->prep_lock); |
| 146 | __ioat_issue_pending(ioat_chan); |
| 147 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | /** |
| 152 | * ioat_update_pending - log pending descriptors |
| 153 | * @ioat: ioat+ channel |
| 154 | * |
| 155 | * Check if the number of unsubmitted descriptors has exceeded the |
| 156 | * watermark. Called with prep_lock held |
| 157 | */ |
| 158 | static void ioat_update_pending(struct ioatdma_chan *ioat_chan) |
| 159 | { |
| 160 | if (ioat_ring_pending(ioat_chan) > ioat_pending_level) |
| 161 | __ioat_issue_pending(ioat_chan); |
| 162 | } |
| 163 | |
| 164 | static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan) |
| 165 | { |
| 166 | struct ioat_ring_ent *desc; |
| 167 | struct ioat_dma_descriptor *hw; |
| 168 | |
| 169 | if (ioat_ring_space(ioat_chan) < 1) { |
| 170 | dev_err(to_dev(ioat_chan), |
| 171 | "Unable to start null desc - ring full\n"); |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | dev_dbg(to_dev(ioat_chan), |
| 176 | "%s: head: %#x tail: %#x issued: %#x\n", |
| 177 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); |
| 178 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); |
| 179 | |
| 180 | hw = desc->hw; |
| 181 | hw->ctl = 0; |
| 182 | hw->ctl_f.null = 1; |
| 183 | hw->ctl_f.int_en = 1; |
| 184 | hw->ctl_f.compl_write = 1; |
| 185 | /* set size to non-zero value (channel returns error when size is 0) */ |
| 186 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 187 | hw->src_addr = 0; |
| 188 | hw->dst_addr = 0; |
| 189 | async_tx_ack(&desc->txd); |
| 190 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); |
| 191 | dump_desc_dbg(ioat_chan, desc); |
| 192 | /* make sure descriptors are written before we submit */ |
| 193 | wmb(); |
| 194 | ioat_chan->head += 1; |
| 195 | __ioat_issue_pending(ioat_chan); |
| 196 | } |
| 197 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 198 | void ioat_start_null_desc(struct ioatdma_chan *ioat_chan) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 199 | { |
| 200 | spin_lock_bh(&ioat_chan->prep_lock); |
Dave Jiang | ad4a7b5 | 2015-08-26 13:17:24 -0700 | [diff] [blame] | 201 | if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
| 202 | __ioat_start_null_desc(ioat_chan); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 203 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 204 | } |
| 205 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 206 | static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 207 | { |
| 208 | /* set the tail to be re-issued */ |
| 209 | ioat_chan->issued = ioat_chan->tail; |
| 210 | ioat_chan->dmacount = 0; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 211 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 212 | |
| 213 | dev_dbg(to_dev(ioat_chan), |
| 214 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", |
| 215 | __func__, ioat_chan->head, ioat_chan->tail, |
| 216 | ioat_chan->issued, ioat_chan->dmacount); |
| 217 | |
| 218 | if (ioat_ring_pending(ioat_chan)) { |
| 219 | struct ioat_ring_ent *desc; |
| 220 | |
| 221 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); |
| 222 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); |
| 223 | __ioat_issue_pending(ioat_chan); |
| 224 | } else |
| 225 | __ioat_start_null_desc(ioat_chan); |
| 226 | } |
| 227 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 228 | static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 229 | { |
| 230 | unsigned long end = jiffies + tmo; |
| 231 | int err = 0; |
| 232 | u32 status; |
| 233 | |
| 234 | status = ioat_chansts(ioat_chan); |
| 235 | if (is_ioat_active(status) || is_ioat_idle(status)) |
| 236 | ioat_suspend(ioat_chan); |
| 237 | while (is_ioat_active(status) || is_ioat_idle(status)) { |
| 238 | if (tmo && time_after(jiffies, end)) { |
| 239 | err = -ETIMEDOUT; |
| 240 | break; |
| 241 | } |
| 242 | status = ioat_chansts(ioat_chan); |
| 243 | cpu_relax(); |
| 244 | } |
| 245 | |
| 246 | return err; |
| 247 | } |
| 248 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 249 | static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 250 | { |
| 251 | unsigned long end = jiffies + tmo; |
| 252 | int err = 0; |
| 253 | |
| 254 | ioat_reset(ioat_chan); |
| 255 | while (ioat_reset_pending(ioat_chan)) { |
| 256 | if (end && time_after(jiffies, end)) { |
| 257 | err = -ETIMEDOUT; |
| 258 | break; |
| 259 | } |
| 260 | cpu_relax(); |
| 261 | } |
| 262 | |
| 263 | return err; |
| 264 | } |
| 265 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 266 | static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx) |
Dave Jiang | 5c65cb9 | 2015-08-25 12:58:05 -0700 | [diff] [blame] | 267 | __releases(&ioat_chan->prep_lock) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 268 | { |
| 269 | struct dma_chan *c = tx->chan; |
| 270 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
| 271 | dma_cookie_t cookie; |
| 272 | |
| 273 | cookie = dma_cookie_assign(tx); |
| 274 | dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie); |
| 275 | |
| 276 | if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) |
| 277 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 278 | |
| 279 | /* make descriptor updates visible before advancing ioat->head, |
| 280 | * this is purposefully not smp_wmb() since we are also |
| 281 | * publishing the descriptor updates to a dma device |
| 282 | */ |
| 283 | wmb(); |
| 284 | |
| 285 | ioat_chan->head += ioat_chan->produce; |
| 286 | |
| 287 | ioat_update_pending(ioat_chan); |
| 288 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 289 | |
| 290 | return cookie; |
| 291 | } |
| 292 | |
| 293 | static struct ioat_ring_ent * |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 294 | ioat_alloc_ring_ent(struct dma_chan *chan, int idx, gfp_t flags) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 295 | { |
| 296 | struct ioat_dma_descriptor *hw; |
| 297 | struct ioat_ring_ent *desc; |
| 298 | struct ioatdma_device *ioat_dma; |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 299 | struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
| 300 | int chunk; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 301 | dma_addr_t phys; |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 302 | u8 *pos; |
| 303 | off_t offs; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 304 | |
| 305 | ioat_dma = to_ioatdma_device(chan->device); |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 306 | |
| 307 | chunk = idx / IOAT_DESCS_PER_2M; |
| 308 | idx &= (IOAT_DESCS_PER_2M - 1); |
| 309 | offs = idx * IOAT_DESC_SZ; |
| 310 | pos = (u8 *)ioat_chan->descs[chunk].virt + offs; |
| 311 | phys = ioat_chan->descs[chunk].hw + offs; |
| 312 | hw = (struct ioat_dma_descriptor *)pos; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 313 | memset(hw, 0, sizeof(*hw)); |
| 314 | |
| 315 | desc = kmem_cache_zalloc(ioat_cache, flags); |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 316 | if (!desc) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 317 | return NULL; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 318 | |
| 319 | dma_async_tx_descriptor_init(&desc->txd, chan); |
| 320 | desc->txd.tx_submit = ioat_tx_submit_unlock; |
| 321 | desc->hw = hw; |
| 322 | desc->txd.phys = phys; |
| 323 | return desc; |
| 324 | } |
| 325 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 326 | void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 327 | { |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 328 | kmem_cache_free(ioat_cache, desc); |
| 329 | } |
| 330 | |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 331 | struct ioat_ring_ent ** |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 332 | ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags) |
| 333 | { |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 334 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 335 | struct ioat_ring_ent **ring; |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 336 | int total_descs = 1 << order; |
| 337 | int i, chunks; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 338 | |
| 339 | /* allocate the array to hold the software ring */ |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 340 | ring = kcalloc(total_descs, sizeof(*ring), flags); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 341 | if (!ring) |
| 342 | return NULL; |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 343 | |
| 344 | ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M; |
| 345 | |
| 346 | for (i = 0; i < chunks; i++) { |
| 347 | struct ioat_descs *descs = &ioat_chan->descs[i]; |
| 348 | |
| 349 | descs->virt = dma_alloc_coherent(to_dev(ioat_chan), |
| 350 | SZ_2M, &descs->hw, flags); |
| 351 | if (!descs->virt && (i > 0)) { |
| 352 | int idx; |
| 353 | |
| 354 | for (idx = 0; idx < i; idx++) { |
| 355 | dma_free_coherent(to_dev(ioat_chan), SZ_2M, |
| 356 | descs->virt, descs->hw); |
| 357 | descs->virt = NULL; |
| 358 | descs->hw = 0; |
| 359 | } |
| 360 | |
| 361 | ioat_chan->desc_chunks = 0; |
| 362 | kfree(ring); |
| 363 | return NULL; |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | for (i = 0; i < total_descs; i++) { |
| 368 | ring[i] = ioat_alloc_ring_ent(c, i, flags); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 369 | if (!ring[i]) { |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 370 | int idx; |
| 371 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 372 | while (i--) |
| 373 | ioat_free_ring_ent(ring[i], c); |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 374 | |
| 375 | for (idx = 0; idx < ioat_chan->desc_chunks; idx++) { |
| 376 | dma_free_coherent(to_dev(ioat_chan), |
| 377 | SZ_2M, |
| 378 | ioat_chan->descs[idx].virt, |
| 379 | ioat_chan->descs[idx].hw); |
| 380 | ioat_chan->descs[idx].virt = NULL; |
| 381 | ioat_chan->descs[idx].hw = 0; |
| 382 | } |
| 383 | |
| 384 | ioat_chan->desc_chunks = 0; |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 385 | kfree(ring); |
| 386 | return NULL; |
| 387 | } |
| 388 | set_desc_id(ring[i], i); |
| 389 | } |
| 390 | |
| 391 | /* link descs */ |
Dave Jiang | dd4645e | 2016-02-10 15:00:32 -0700 | [diff] [blame] | 392 | for (i = 0; i < total_descs-1; i++) { |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 393 | struct ioat_ring_ent *next = ring[i+1]; |
| 394 | struct ioat_dma_descriptor *hw = ring[i]->hw; |
| 395 | |
| 396 | hw->next = next->txd.phys; |
| 397 | } |
| 398 | ring[i]->hw->next = ring[0]->txd.phys; |
| 399 | |
| 400 | return ring; |
| 401 | } |
| 402 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 403 | /** |
| 404 | * ioat_check_space_lock - verify space and grab ring producer lock |
| 405 | * @ioat: ioat,3 channel (ring) to operate on |
| 406 | * @num_descs: allocation length |
| 407 | */ |
| 408 | int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs) |
Dave Jiang | 5c65cb9 | 2015-08-25 12:58:05 -0700 | [diff] [blame] | 409 | __acquires(&ioat_chan->prep_lock) |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 410 | { |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 411 | spin_lock_bh(&ioat_chan->prep_lock); |
| 412 | /* never allow the last descriptor to be consumed, we need at |
| 413 | * least one free at all times to allow for on-the-fly ring |
| 414 | * resizing. |
| 415 | */ |
| 416 | if (likely(ioat_ring_space(ioat_chan) > num_descs)) { |
| 417 | dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n", |
| 418 | __func__, num_descs, ioat_chan->head, |
| 419 | ioat_chan->tail, ioat_chan->issued); |
| 420 | ioat_chan->produce = num_descs; |
| 421 | return 0; /* with ioat->prep_lock held */ |
| 422 | } |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 423 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 424 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 425 | dev_dbg_ratelimited(to_dev(ioat_chan), |
| 426 | "%s: ring full! num_descs: %d (%x:%x:%x)\n", |
| 427 | __func__, num_descs, ioat_chan->head, |
| 428 | ioat_chan->tail, ioat_chan->issued); |
| 429 | |
| 430 | /* progress reclaim in the allocation failure case we may be |
| 431 | * called under bh_disabled so we need to trigger the timer |
| 432 | * event directly |
| 433 | */ |
| 434 | if (time_is_before_jiffies(ioat_chan->timer.expires) |
| 435 | && timer_pending(&ioat_chan->timer)) { |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 436 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
Dave Jiang | ef97bd0f | 2015-08-11 08:49:00 -0700 | [diff] [blame] | 437 | ioat_timer_event((unsigned long)ioat_chan); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 438 | } |
| 439 | |
| 440 | return -ENOMEM; |
| 441 | } |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 442 | |
| 443 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
| 444 | { |
| 445 | struct ioat_dma_descriptor *hw = desc->hw; |
| 446 | |
| 447 | if (hw->ctl_f.op == IOAT_OP_XOR || |
| 448 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { |
| 449 | struct ioat_xor_descriptor *xor = desc->xor; |
| 450 | |
| 451 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
| 452 | return true; |
| 453 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
| 454 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { |
| 455 | struct ioat_pq_descriptor *pq = desc->pq; |
| 456 | |
| 457 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) |
| 458 | return true; |
| 459 | } |
| 460 | |
| 461 | return false; |
| 462 | } |
| 463 | |
| 464 | static void |
| 465 | ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed) |
| 466 | { |
| 467 | if (!sed) |
| 468 | return; |
| 469 | |
| 470 | dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); |
| 471 | kmem_cache_free(ioat_sed_cache, sed); |
| 472 | } |
| 473 | |
| 474 | static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan) |
| 475 | { |
| 476 | u64 phys_complete; |
| 477 | u64 completion; |
| 478 | |
| 479 | completion = *ioat_chan->completion; |
| 480 | phys_complete = ioat_chansts_to_addr(completion); |
| 481 | |
| 482 | dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__, |
| 483 | (unsigned long long) phys_complete); |
| 484 | |
| 485 | return phys_complete; |
| 486 | } |
| 487 | |
| 488 | static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, |
| 489 | u64 *phys_complete) |
| 490 | { |
| 491 | *phys_complete = ioat_get_current_completion(ioat_chan); |
| 492 | if (*phys_complete == ioat_chan->last_completion) |
| 493 | return false; |
| 494 | |
| 495 | clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); |
| 496 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 497 | |
| 498 | return true; |
| 499 | } |
| 500 | |
| 501 | static void |
| 502 | desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc) |
| 503 | { |
| 504 | struct ioat_dma_descriptor *hw = desc->hw; |
| 505 | |
| 506 | switch (hw->ctl_f.op) { |
| 507 | case IOAT_OP_PQ_VAL: |
| 508 | case IOAT_OP_PQ_VAL_16S: |
| 509 | { |
| 510 | struct ioat_pq_descriptor *pq = desc->pq; |
| 511 | |
| 512 | /* check if there's error written */ |
| 513 | if (!pq->dwbes_f.wbes) |
| 514 | return; |
| 515 | |
| 516 | /* need to set a chanerr var for checking to clear later */ |
| 517 | |
| 518 | if (pq->dwbes_f.p_val_err) |
| 519 | *desc->result |= SUM_CHECK_P_RESULT; |
| 520 | |
| 521 | if (pq->dwbes_f.q_val_err) |
| 522 | *desc->result |= SUM_CHECK_Q_RESULT; |
| 523 | |
| 524 | return; |
| 525 | } |
| 526 | default: |
| 527 | return; |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | /** |
| 532 | * __cleanup - reclaim used descriptors |
| 533 | * @ioat: channel (ring) to clean |
| 534 | */ |
| 535 | static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete) |
| 536 | { |
| 537 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
| 538 | struct ioat_ring_ent *desc; |
| 539 | bool seen_current = false; |
| 540 | int idx = ioat_chan->tail, i; |
| 541 | u16 active; |
| 542 | |
| 543 | dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n", |
| 544 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); |
| 545 | |
| 546 | /* |
| 547 | * At restart of the channel, the completion address and the |
| 548 | * channel status will be 0 due to starting a new chain. Since |
| 549 | * it's new chain and the first descriptor "fails", there is |
| 550 | * nothing to clean up. We do not want to reap the entire submitted |
| 551 | * chain due to this 0 address value and then BUG. |
| 552 | */ |
| 553 | if (!phys_complete) |
| 554 | return; |
| 555 | |
| 556 | active = ioat_ring_active(ioat_chan); |
| 557 | for (i = 0; i < active && !seen_current; i++) { |
| 558 | struct dma_async_tx_descriptor *tx; |
| 559 | |
| 560 | smp_read_barrier_depends(); |
| 561 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); |
| 562 | desc = ioat_get_ring_ent(ioat_chan, idx + i); |
| 563 | dump_desc_dbg(ioat_chan, desc); |
| 564 | |
| 565 | /* set err stat if we are using dwbes */ |
| 566 | if (ioat_dma->cap & IOAT_CAP_DWBES) |
| 567 | desc_get_errstat(ioat_chan, desc); |
| 568 | |
| 569 | tx = &desc->txd; |
| 570 | if (tx->cookie) { |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 571 | struct dmaengine_result res; |
| 572 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 573 | dma_cookie_complete(tx); |
| 574 | dma_descriptor_unmap(tx); |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 575 | res.result = DMA_TRANS_NOERROR; |
Dave Jiang | 6399286 | 2016-07-20 13:11:33 -0700 | [diff] [blame] | 576 | dmaengine_desc_get_callback_invoke(tx, NULL); |
| 577 | tx->callback = NULL; |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 578 | tx->callback_result = NULL; |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | if (tx->phys == phys_complete) |
| 582 | seen_current = true; |
| 583 | |
| 584 | /* skip extended descriptors */ |
| 585 | if (desc_has_ext(desc)) { |
| 586 | BUG_ON(i + 1 >= active); |
| 587 | i++; |
| 588 | } |
| 589 | |
| 590 | /* cleanup super extended descriptors */ |
| 591 | if (desc->sed) { |
| 592 | ioat_free_sed(ioat_dma, desc->sed); |
| 593 | desc->sed = NULL; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | /* finish all descriptor reads before incrementing tail */ |
| 598 | smp_mb(); |
| 599 | ioat_chan->tail = idx + i; |
| 600 | /* no active descs have written a completion? */ |
| 601 | BUG_ON(active && !seen_current); |
| 602 | ioat_chan->last_completion = phys_complete; |
| 603 | |
| 604 | if (active - i == 0) { |
| 605 | dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n", |
| 606 | __func__); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 607 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
| 608 | } |
| 609 | |
| 610 | /* 5 microsecond delay per pending descriptor */ |
| 611 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), |
| 612 | ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET); |
| 613 | } |
| 614 | |
| 615 | static void ioat_cleanup(struct ioatdma_chan *ioat_chan) |
| 616 | { |
| 617 | u64 phys_complete; |
| 618 | |
| 619 | spin_lock_bh(&ioat_chan->cleanup_lock); |
| 620 | |
| 621 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
| 622 | __cleanup(ioat_chan, phys_complete); |
| 623 | |
| 624 | if (is_ioat_halted(*ioat_chan->completion)) { |
| 625 | u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 626 | |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 627 | if (chanerr & |
| 628 | (IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) { |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 629 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
| 630 | ioat_eh(ioat_chan); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 635 | } |
| 636 | |
| 637 | void ioat_cleanup_event(unsigned long data) |
| 638 | { |
| 639 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); |
| 640 | |
| 641 | ioat_cleanup(ioat_chan); |
| 642 | if (!test_bit(IOAT_RUN, &ioat_chan->state)) |
| 643 | return; |
| 644 | writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); |
| 645 | } |
| 646 | |
| 647 | static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) |
| 648 | { |
| 649 | u64 phys_complete; |
| 650 | |
| 651 | ioat_quiesce(ioat_chan, 0); |
| 652 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
| 653 | __cleanup(ioat_chan, phys_complete); |
| 654 | |
| 655 | __ioat_restart_chan(ioat_chan); |
| 656 | } |
| 657 | |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 658 | |
| 659 | static void ioat_abort_descs(struct ioatdma_chan *ioat_chan) |
| 660 | { |
| 661 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
| 662 | struct ioat_ring_ent *desc; |
| 663 | u16 active; |
| 664 | int idx = ioat_chan->tail, i; |
| 665 | |
| 666 | /* |
| 667 | * We assume that the failed descriptor has been processed. |
| 668 | * Now we are just returning all the remaining submitted |
| 669 | * descriptors to abort. |
| 670 | */ |
| 671 | active = ioat_ring_active(ioat_chan); |
| 672 | |
| 673 | /* we skip the failed descriptor that tail points to */ |
| 674 | for (i = 1; i < active; i++) { |
| 675 | struct dma_async_tx_descriptor *tx; |
| 676 | |
| 677 | smp_read_barrier_depends(); |
| 678 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); |
| 679 | desc = ioat_get_ring_ent(ioat_chan, idx + i); |
| 680 | |
| 681 | tx = &desc->txd; |
| 682 | if (tx->cookie) { |
| 683 | struct dmaengine_result res; |
| 684 | |
| 685 | dma_cookie_complete(tx); |
| 686 | dma_descriptor_unmap(tx); |
| 687 | res.result = DMA_TRANS_ABORTED; |
| 688 | dmaengine_desc_get_callback_invoke(tx, &res); |
| 689 | tx->callback = NULL; |
| 690 | tx->callback_result = NULL; |
| 691 | } |
| 692 | |
| 693 | /* skip extended descriptors */ |
| 694 | if (desc_has_ext(desc)) { |
| 695 | WARN_ON(i + 1 >= active); |
| 696 | i++; |
| 697 | } |
| 698 | |
| 699 | /* cleanup super extended descriptors */ |
| 700 | if (desc->sed) { |
| 701 | ioat_free_sed(ioat_dma, desc->sed); |
| 702 | desc->sed = NULL; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | smp_mb(); /* finish all descriptor reads before incrementing tail */ |
| 707 | ioat_chan->tail = idx + active; |
| 708 | |
| 709 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); |
| 710 | ioat_chan->last_completion = *ioat_chan->completion = desc->txd.phys; |
| 711 | } |
| 712 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 713 | static void ioat_eh(struct ioatdma_chan *ioat_chan) |
| 714 | { |
| 715 | struct pci_dev *pdev = to_pdev(ioat_chan); |
| 716 | struct ioat_dma_descriptor *hw; |
| 717 | struct dma_async_tx_descriptor *tx; |
| 718 | u64 phys_complete; |
| 719 | struct ioat_ring_ent *desc; |
| 720 | u32 err_handled = 0; |
| 721 | u32 chanerr_int; |
| 722 | u32 chanerr; |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 723 | bool abort = false; |
| 724 | struct dmaengine_result res; |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 725 | |
| 726 | /* cleanup so tail points to descriptor that caused the error */ |
| 727 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
| 728 | __cleanup(ioat_chan, phys_complete); |
| 729 | |
| 730 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 731 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); |
| 732 | |
| 733 | dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n", |
| 734 | __func__, chanerr, chanerr_int); |
| 735 | |
| 736 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); |
| 737 | hw = desc->hw; |
| 738 | dump_desc_dbg(ioat_chan, desc); |
| 739 | |
| 740 | switch (hw->ctl_f.op) { |
| 741 | case IOAT_OP_XOR_VAL: |
| 742 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { |
| 743 | *desc->result |= SUM_CHECK_P_RESULT; |
| 744 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; |
| 745 | } |
| 746 | break; |
| 747 | case IOAT_OP_PQ_VAL: |
| 748 | case IOAT_OP_PQ_VAL_16S: |
| 749 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { |
| 750 | *desc->result |= SUM_CHECK_P_RESULT; |
| 751 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; |
| 752 | } |
| 753 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { |
| 754 | *desc->result |= SUM_CHECK_Q_RESULT; |
| 755 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; |
| 756 | } |
| 757 | break; |
| 758 | } |
| 759 | |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 760 | if (chanerr & IOAT_CHANERR_RECOVER_MASK) { |
| 761 | if (chanerr & IOAT_CHANERR_READ_DATA_ERR) { |
| 762 | res.result = DMA_TRANS_READ_FAILED; |
| 763 | err_handled |= IOAT_CHANERR_READ_DATA_ERR; |
| 764 | } else if (chanerr & IOAT_CHANERR_WRITE_DATA_ERR) { |
| 765 | res.result = DMA_TRANS_WRITE_FAILED; |
| 766 | err_handled |= IOAT_CHANERR_WRITE_DATA_ERR; |
| 767 | } |
| 768 | |
| 769 | abort = true; |
| 770 | } else |
| 771 | res.result = DMA_TRANS_NOERROR; |
| 772 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 773 | /* fault on unhandled error or spurious halt */ |
| 774 | if (chanerr ^ err_handled || chanerr == 0) { |
| 775 | dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n", |
| 776 | __func__, chanerr, err_handled); |
| 777 | BUG(); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 778 | } |
| 779 | |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 780 | /* cleanup the faulty descriptor since we are continuing */ |
| 781 | tx = &desc->txd; |
| 782 | if (tx->cookie) { |
| 783 | dma_cookie_complete(tx); |
| 784 | dma_descriptor_unmap(tx); |
| 785 | dmaengine_desc_get_callback_invoke(tx, &res); |
| 786 | tx->callback = NULL; |
| 787 | tx->callback_result = NULL; |
| 788 | } |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 789 | |
| 790 | /* mark faulting descriptor as complete */ |
| 791 | *ioat_chan->completion = desc->txd.phys; |
| 792 | |
| 793 | spin_lock_bh(&ioat_chan->prep_lock); |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 794 | /* we need abort all descriptors */ |
| 795 | if (abort) { |
| 796 | ioat_abort_descs(ioat_chan); |
| 797 | /* clean up the channel, we could be in weird state */ |
| 798 | ioat_reset_hw(ioat_chan); |
| 799 | } |
| 800 | |
| 801 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 802 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); |
| 803 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 804 | ioat_restart_channel(ioat_chan); |
| 805 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 806 | } |
| 807 | |
| 808 | static void check_active(struct ioatdma_chan *ioat_chan) |
| 809 | { |
| 810 | if (ioat_ring_active(ioat_chan)) { |
| 811 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 812 | return; |
| 813 | } |
| 814 | |
| 815 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) |
| 816 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 817 | } |
| 818 | |
| 819 | void ioat_timer_event(unsigned long data) |
| 820 | { |
| 821 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); |
| 822 | dma_addr_t phys_complete; |
| 823 | u64 status; |
| 824 | |
| 825 | status = ioat_chansts(ioat_chan); |
| 826 | |
| 827 | /* when halted due to errors check for channel |
| 828 | * programming errors before advancing the completion state |
| 829 | */ |
| 830 | if (is_ioat_halted(status)) { |
| 831 | u32 chanerr; |
| 832 | |
| 833 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 834 | dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n", |
| 835 | __func__, chanerr); |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 836 | if (test_bit(IOAT_RUN, &ioat_chan->state)) { |
| 837 | spin_lock_bh(&ioat_chan->cleanup_lock); |
| 838 | spin_lock_bh(&ioat_chan->prep_lock); |
| 839 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
| 840 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 841 | |
| 842 | ioat_abort_descs(ioat_chan); |
| 843 | dev_warn(to_dev(ioat_chan), "Reset channel...\n"); |
| 844 | ioat_reset_hw(ioat_chan); |
| 845 | dev_warn(to_dev(ioat_chan), "Restart channel...\n"); |
| 846 | ioat_restart_channel(ioat_chan); |
| 847 | |
| 848 | spin_lock_bh(&ioat_chan->prep_lock); |
| 849 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
| 850 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 851 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 852 | } |
| 853 | |
| 854 | return; |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 855 | } |
| 856 | |
Dave Jiang | 8a695db | 2016-01-19 08:57:48 -0700 | [diff] [blame] | 857 | spin_lock_bh(&ioat_chan->cleanup_lock); |
| 858 | |
| 859 | /* handle the no-actives case */ |
| 860 | if (!ioat_ring_active(ioat_chan)) { |
| 861 | spin_lock_bh(&ioat_chan->prep_lock); |
| 862 | check_active(ioat_chan); |
| 863 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 864 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 865 | return; |
| 866 | } |
| 867 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 868 | /* if we haven't made progress and we have already |
| 869 | * acknowledged a pending completion once, then be more |
| 870 | * forceful with a restart |
| 871 | */ |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 872 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
| 873 | __cleanup(ioat_chan, phys_complete); |
| 874 | else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) { |
Dave Jiang | 8a695db | 2016-01-19 08:57:48 -0700 | [diff] [blame] | 875 | u32 chanerr; |
| 876 | |
| 877 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
Dave Jiang | 8a695db | 2016-01-19 08:57:48 -0700 | [diff] [blame] | 878 | dev_warn(to_dev(ioat_chan), "CHANSTS: %#Lx CHANERR: %#x\n", |
| 879 | status, chanerr); |
| 880 | dev_warn(to_dev(ioat_chan), "Active descriptors: %d\n", |
| 881 | ioat_ring_active(ioat_chan)); |
| 882 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 883 | spin_lock_bh(&ioat_chan->prep_lock); |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 884 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
| 885 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 886 | |
| 887 | ioat_abort_descs(ioat_chan); |
| 888 | dev_warn(to_dev(ioat_chan), "Resetting channel...\n"); |
| 889 | ioat_reset_hw(ioat_chan); |
| 890 | dev_warn(to_dev(ioat_chan), "Restarting channel...\n"); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 891 | ioat_restart_channel(ioat_chan); |
Dave Jiang | 9546d4c | 2016-07-20 13:13:55 -0700 | [diff] [blame^] | 892 | |
| 893 | spin_lock_bh(&ioat_chan->prep_lock); |
| 894 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 895 | spin_unlock_bh(&ioat_chan->prep_lock); |
| 896 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 897 | return; |
Dave Jiang | 8a695db | 2016-01-19 08:57:48 -0700 | [diff] [blame] | 898 | } else |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 899 | set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 900 | |
Dave Jiang | 8a695db | 2016-01-19 08:57:48 -0700 | [diff] [blame] | 901 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 902 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
| 903 | } |
| 904 | |
| 905 | enum dma_status |
| 906 | ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
| 907 | struct dma_tx_state *txstate) |
| 908 | { |
| 909 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
| 910 | enum dma_status ret; |
| 911 | |
| 912 | ret = dma_cookie_status(c, cookie, txstate); |
| 913 | if (ret == DMA_COMPLETE) |
| 914 | return ret; |
| 915 | |
| 916 | ioat_cleanup(ioat_chan); |
| 917 | |
| 918 | return dma_cookie_status(c, cookie, txstate); |
| 919 | } |
| 920 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 921 | int ioat_reset_hw(struct ioatdma_chan *ioat_chan) |
| 922 | { |
| 923 | /* throw away whatever the channel was doing and get it |
| 924 | * initialized, with ioat3 specific workarounds |
| 925 | */ |
| 926 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
| 927 | struct pci_dev *pdev = ioat_dma->pdev; |
| 928 | u32 chanerr; |
| 929 | u16 dev_id; |
| 930 | int err; |
| 931 | |
| 932 | ioat_quiesce(ioat_chan, msecs_to_jiffies(100)); |
| 933 | |
| 934 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 935 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
| 936 | |
| 937 | if (ioat_dma->version < IOAT_VER_3_3) { |
| 938 | /* clear any pending errors */ |
| 939 | err = pci_read_config_dword(pdev, |
| 940 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); |
| 941 | if (err) { |
| 942 | dev_err(&pdev->dev, |
| 943 | "channel error register unreachable\n"); |
| 944 | return err; |
| 945 | } |
| 946 | pci_write_config_dword(pdev, |
| 947 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); |
| 948 | |
| 949 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit |
| 950 | * (workaround for spurious config parity error after restart) |
| 951 | */ |
| 952 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); |
| 953 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { |
| 954 | pci_write_config_dword(pdev, |
| 955 | IOAT_PCI_DMAUNCERRSTS_OFFSET, |
| 956 | 0x10); |
| 957 | } |
| 958 | } |
| 959 | |
Dave Jiang | c997e30 | 2016-03-10 16:18:40 -0700 | [diff] [blame] | 960 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { |
| 961 | ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000); |
| 962 | ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008); |
| 963 | ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800); |
| 964 | } |
| 965 | |
| 966 | |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 967 | err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200)); |
Dave Jiang | c997e30 | 2016-03-10 16:18:40 -0700 | [diff] [blame] | 968 | if (!err) { |
| 969 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { |
| 970 | writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000); |
| 971 | writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008); |
| 972 | writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800); |
| 973 | } |
| 974 | } |
Dave Jiang | 3372de5 | 2015-08-11 08:48:55 -0700 | [diff] [blame] | 975 | |
| 976 | if (err) |
| 977 | dev_err(&pdev->dev, "Failed to reset: %d\n", err); |
| 978 | |
| 979 | return err; |
| 980 | } |