blob: 3244df9c1e92bd4e0ba0690314b0094d9fd8c7b8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ALSA modem driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
Sasha Khapyorskyf01cc522005-10-10 11:45:31 +02006 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * of ALSA ICH sound driver intel8x0.c .
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <sound/driver.h>
27#include <asm/io.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/slab.h>
33#include <linux/moduleparam.h>
34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/ac97_codec.h>
37#include <sound/info.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <sound/initval.h>
39
40MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
44 "{Intel,82901AB-ICH0},"
45 "{Intel,82801BA-ICH2},"
46 "{Intel,82801CA-ICH3},"
47 "{Intel,82801DB-ICH4},"
48 "{Intel,ICH5},"
49 "{Intel,ICH6},"
50 "{Intel,ICH7},"
51 "{Intel,MX440},"
52 "{SiS,7013},"
53 "{NVidia,NForce Modem},"
54 "{NVidia,NForce2 Modem},"
55 "{NVidia,NForce2s Modem},"
56 "{NVidia,NForce3 Modem},"
57 "{AMD,AMD768}}");
58
Clemens Ladischb7fe4622005-10-04 08:46:51 +020059static int index = -2; /* Exclude the first card */
60static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
61static int ac97_clock = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
Clemens Ladischb7fe4622005-10-04 08:46:51 +020063module_param(index, int, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070064MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
Clemens Ladischb7fe4622005-10-04 08:46:51 +020065module_param(id, charp, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070066MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
Clemens Ladischb7fe4622005-10-04 08:46:51 +020067module_param(ac97_clock, int, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070068MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
69
Takashi Iwai2b3e5842005-10-06 13:47:23 +020070/* just for backward compatibility */
71static int enable;
Takashi Iwai698444f2005-10-20 16:53:49 +020072module_param(enable, bool, 0444);
Takashi Iwai2b3e5842005-10-06 13:47:23 +020073
Linus Torvalds1da177e2005-04-16 15:20:36 -070074/*
75 * Direct registers
76 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070077enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
78
79#define ICHREG(x) ICH_REG_##x
80
81#define DEFINE_REGSET(name,base) \
82enum { \
83 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
84 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
85 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
86 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
87 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
88 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
89 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
90};
91
92/* busmaster blocks */
93DEFINE_REGSET(OFF, 0); /* offset */
94
95/* values for each busmaster block */
96
97/* LVI */
98#define ICH_REG_LVI_MASK 0x1f
99
100/* SR */
101#define ICH_FIFOE 0x10 /* FIFO error */
102#define ICH_BCIS 0x08 /* buffer completion interrupt status */
103#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
104#define ICH_CELV 0x02 /* current equals last valid */
105#define ICH_DCH 0x01 /* DMA controller halted */
106
107/* PIV */
108#define ICH_REG_PIV_MASK 0x1f /* mask */
109
110/* CR */
111#define ICH_IOCE 0x10 /* interrupt on completion enable */
112#define ICH_FEIE 0x08 /* fifo error interrupt enable */
113#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
114#define ICH_RESETREGS 0x02 /* reset busmaster registers */
115#define ICH_STARTBM 0x01 /* start busmaster operation */
116
117
118/* global block */
119#define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
120#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
121#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
122#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
123#define ICH_ACLINK 0x00000008 /* AClink shut off */
124#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
125#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
126#define ICH_GIE 0x00000001 /* GPI interrupt enable */
127#define ICH_REG_GLOB_STA 0x40 /* dword - global status */
128#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
129#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
130#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
131#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
132#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
133#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
134#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
135#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
136#define ICH_MD3 0x00020000 /* modem power down semaphore */
137#define ICH_AD3 0x00010000 /* audio power down semaphore */
138#define ICH_RCS 0x00008000 /* read completion status */
139#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
140#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
141#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
142#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
143#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
144#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
145#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
146#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
147#define ICH_POINT 0x00000040 /* playback interrupt */
148#define ICH_PIINT 0x00000020 /* capture interrupt */
149#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
150#define ICH_MOINT 0x00000004 /* modem playback interrupt */
151#define ICH_MIINT 0x00000002 /* modem capture interrupt */
152#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
153#define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
154#define ICH_CAS 0x01 /* codec access semaphore */
155
156#define ICH_MAX_FRAGS 32 /* max hw frags */
157
158
159/*
160 *
161 */
162
163enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
164enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
165
166#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
167
168typedef struct {
169 unsigned int ichd; /* ich device number */
170 unsigned long reg_offset; /* offset to bmaddr */
171 u32 *bdbar; /* CPU address (32bit) */
172 unsigned int bdbar_addr; /* PCI bus address (32bit) */
173 snd_pcm_substream_t *substream;
174 unsigned int physbuf; /* physical address (32bit) */
175 unsigned int size;
176 unsigned int fragsize;
177 unsigned int fragsize1;
178 unsigned int position;
179 int frags;
180 int lvi;
181 int lvi_frag;
182 int civ;
183 int ack;
184 int ack_reload;
185 unsigned int ack_bit;
186 unsigned int roff_sr;
187 unsigned int roff_picb;
188 unsigned int int_sta_mask; /* interrupt status mask */
189 unsigned int ali_slot; /* ALI DMA slot */
190 ac97_t *ac97;
191} ichdev_t;
192
193typedef struct _snd_intel8x0m intel8x0_t;
194
195struct _snd_intel8x0m {
196 unsigned int device_type;
197
198 int irq;
199
200 unsigned int mmio;
201 unsigned long addr;
202 void __iomem *remap_addr;
203 unsigned int bm_mmio;
204 unsigned long bmaddr;
205 void __iomem *remap_bmaddr;
206
207 struct pci_dev *pci;
208 snd_card_t *card;
209
210 int pcm_devs;
211 snd_pcm_t *pcm[2];
212 ichdev_t ichd[2];
213
214 unsigned int in_ac97_init: 1;
215
216 ac97_bus_t *ac97_bus;
217 ac97_t *ac97;
218
219 spinlock_t reg_lock;
220
221 struct snd_dma_buffer bdbars;
222 u32 bdbars_count;
223 u32 int_sta_reg; /* interrupt status register */
224 u32 int_sta_mask; /* interrupt status mask */
225 unsigned int pcm_pos_shift;
226};
227
228static struct pci_device_id snd_intel8x0m_ids[] = {
229 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
230 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
231 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
232 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
233 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
234 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
235 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */
236 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */
237 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
238 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
239 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */
240 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
241 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
242 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
243 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
244#if 0
245 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
246 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
247#endif
248 { 0, }
249};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
251MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253/*
254 * Lowlevel I/O - busmaster
255 */
256
257static u8 igetbyte(intel8x0_t *chip, u32 offset)
258{
259 if (chip->bm_mmio)
260 return readb(chip->remap_bmaddr + offset);
261 else
262 return inb(chip->bmaddr + offset);
263}
264
265static u16 igetword(intel8x0_t *chip, u32 offset)
266{
267 if (chip->bm_mmio)
268 return readw(chip->remap_bmaddr + offset);
269 else
270 return inw(chip->bmaddr + offset);
271}
272
273static u32 igetdword(intel8x0_t *chip, u32 offset)
274{
275 if (chip->bm_mmio)
276 return readl(chip->remap_bmaddr + offset);
277 else
278 return inl(chip->bmaddr + offset);
279}
280
281static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
282{
283 if (chip->bm_mmio)
284 writeb(val, chip->remap_bmaddr + offset);
285 else
286 outb(val, chip->bmaddr + offset);
287}
288
289static void iputword(intel8x0_t *chip, u32 offset, u16 val)
290{
291 if (chip->bm_mmio)
292 writew(val, chip->remap_bmaddr + offset);
293 else
294 outw(val, chip->bmaddr + offset);
295}
296
297static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
298{
299 if (chip->bm_mmio)
300 writel(val, chip->remap_bmaddr + offset);
301 else
302 outl(val, chip->bmaddr + offset);
303}
304
305/*
306 * Lowlevel I/O - AC'97 registers
307 */
308
309static u16 iagetword(intel8x0_t *chip, u32 offset)
310{
311 if (chip->mmio)
312 return readw(chip->remap_addr + offset);
313 else
314 return inw(chip->addr + offset);
315}
316
317static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
318{
319 if (chip->mmio)
320 writew(val, chip->remap_addr + offset);
321 else
322 outw(val, chip->addr + offset);
323}
324
325/*
326 * Basic I/O
327 */
328
329/*
330 * access to AC97 codec via normal i/o (for ICH and SIS7013)
331 */
332
333/* return the GLOB_STA bit for the corresponding codec */
334static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
335{
336 static unsigned int codec_bit[3] = {
337 ICH_PCR, ICH_SCR, ICH_TCR
338 };
339 snd_assert(codec < 3, return ICH_PCR);
340 return codec_bit[codec];
341}
342
343static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
344{
345 int time;
346
347 if (codec > 1)
348 return -EIO;
349 codec = get_ich_codec_bit(chip, codec);
350
351 /* codec ready ? */
352 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
353 return -EIO;
354
355 /* Anyone holding a semaphore for 1 msec should be shot... */
356 time = 100;
357 do {
358 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
359 return 0;
360 udelay(10);
361 } while (time--);
362
363 /* access to some forbidden (non existant) ac97 registers will not
364 * reset the semaphore. So even if you don't get the semaphore, still
365 * continue the access. We don't need the semaphore anyway. */
Takashi Iwai99b359b2005-10-20 18:26:44 +0200366 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
368 iagetword(chip, 0); /* clear semaphore flag */
369 /* I don't care about the semaphore */
370 return -EBUSY;
371}
372
373static void snd_intel8x0_codec_write(ac97_t *ac97,
374 unsigned short reg,
375 unsigned short val)
376{
377 intel8x0_t *chip = ac97->private_data;
378
379 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
380 if (! chip->in_ac97_init)
Takashi Iwai99b359b2005-10-20 18:26:44 +0200381 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 }
383 iaputword(chip, reg + ac97->num * 0x80, val);
384}
385
386static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
387 unsigned short reg)
388{
389 intel8x0_t *chip = ac97->private_data;
390 unsigned short res;
391 unsigned int tmp;
392
393 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
394 if (! chip->in_ac97_init)
Takashi Iwai99b359b2005-10-20 18:26:44 +0200395 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 res = 0xffff;
397 } else {
398 res = iagetword(chip, reg + ac97->num * 0x80);
399 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
400 /* reset RCS and preserve other R/WC bits */
401 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
402 if (! chip->in_ac97_init)
Takashi Iwai99b359b2005-10-20 18:26:44 +0200403 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 res = 0xffff;
405 }
406 }
Sasha Khapyorsky2c56c472005-04-07 20:21:21 +0200407 if (reg == AC97_GPIO_STATUS)
408 iagetword(chip, 0); /* clear semaphore */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 return res;
410}
411
412
413/*
414 * DMA I/O
415 */
416static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
417{
418 int idx;
419 u32 *bdbar = ichdev->bdbar;
420 unsigned long port = ichdev->reg_offset;
421
422 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
423 if (ichdev->size == ichdev->fragsize) {
424 ichdev->ack_reload = ichdev->ack = 2;
425 ichdev->fragsize1 = ichdev->fragsize >> 1;
426 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
427 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
428 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
429 ichdev->fragsize1 >> chip->pcm_pos_shift);
430 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
431 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
432 ichdev->fragsize1 >> chip->pcm_pos_shift);
433 }
434 ichdev->frags = 2;
435 } else {
436 ichdev->ack_reload = ichdev->ack = 1;
437 ichdev->fragsize1 = ichdev->fragsize;
438 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
439 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
440 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
441 ichdev->fragsize >> chip->pcm_pos_shift);
442 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
443 }
444 ichdev->frags = ichdev->size / ichdev->fragsize;
445 }
446 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
447 ichdev->civ = 0;
448 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
449 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
450 ichdev->position = 0;
451#if 0
452 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
453 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
454#endif
455 /* clear interrupts */
456 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
457}
458
459/*
460 * Interrupt handler
461 */
462
463static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
464{
465 unsigned long port = ichdev->reg_offset;
466 int civ, i, step;
467 int ack = 0;
468
469 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
470 if (civ == ichdev->civ) {
471 // snd_printd("civ same %d\n", civ);
472 step = 1;
473 ichdev->civ++;
474 ichdev->civ &= ICH_REG_LVI_MASK;
475 } else {
476 step = civ - ichdev->civ;
477 if (step < 0)
478 step += ICH_REG_LVI_MASK + 1;
479 // if (step != 1)
480 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
481 ichdev->civ = civ;
482 }
483
484 ichdev->position += step * ichdev->fragsize1;
485 ichdev->position %= ichdev->size;
486 ichdev->lvi += step;
487 ichdev->lvi &= ICH_REG_LVI_MASK;
488 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
489 for (i = 0; i < step; i++) {
490 ichdev->lvi_frag++;
491 ichdev->lvi_frag %= ichdev->frags;
492 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
493 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
494 if (--ichdev->ack == 0) {
495 ichdev->ack = ichdev->ack_reload;
496 ack = 1;
497 }
498 }
499 if (ack && ichdev->substream) {
500 spin_unlock(&chip->reg_lock);
501 snd_pcm_period_elapsed(ichdev->substream);
502 spin_lock(&chip->reg_lock);
503 }
504 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
505}
506
507static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
508{
509 intel8x0_t *chip = dev_id;
510 ichdev_t *ichdev;
511 unsigned int status;
512 unsigned int i;
513
514 spin_lock(&chip->reg_lock);
515 status = igetdword(chip, chip->int_sta_reg);
516 if (status == 0xffffffff) { /* we are not yet resumed */
517 spin_unlock(&chip->reg_lock);
518 return IRQ_NONE;
519 }
520 if ((status & chip->int_sta_mask) == 0) {
521 if (status)
522 iputdword(chip, chip->int_sta_reg, status);
523 spin_unlock(&chip->reg_lock);
524 return IRQ_NONE;
525 }
526
527 for (i = 0; i < chip->bdbars_count; i++) {
528 ichdev = &chip->ichd[i];
529 if (status & ichdev->int_sta_mask)
530 snd_intel8x0_update(chip, ichdev);
531 }
532
533 /* ack them */
534 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
535 spin_unlock(&chip->reg_lock);
536
537 return IRQ_HANDLED;
538}
539
540/*
541 * PCM part
542 */
543
544static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
545{
546 intel8x0_t *chip = snd_pcm_substream_chip(substream);
547 ichdev_t *ichdev = get_ichdev(substream);
548 unsigned char val = 0;
549 unsigned long port = ichdev->reg_offset;
550
551 switch (cmd) {
552 case SNDRV_PCM_TRIGGER_START:
553 case SNDRV_PCM_TRIGGER_RESUME:
554 val = ICH_IOCE | ICH_STARTBM;
555 break;
556 case SNDRV_PCM_TRIGGER_STOP:
557 case SNDRV_PCM_TRIGGER_SUSPEND:
558 val = 0;
559 break;
560 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
561 val = ICH_IOCE;
562 break;
563 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
564 val = ICH_IOCE | ICH_STARTBM;
565 break;
566 default:
567 return -EINVAL;
568 }
569 iputbyte(chip, port + ICH_REG_OFF_CR, val);
570 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
571 /* wait until DMA stopped */
572 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
573 /* reset whole DMA things */
574 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
575 }
576 return 0;
577}
578
579static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
580 snd_pcm_hw_params_t * hw_params)
581{
582 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
583}
584
585static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
586{
587 return snd_pcm_lib_free_pages(substream);
588}
589
590static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
591{
592 intel8x0_t *chip = snd_pcm_substream_chip(substream);
593 ichdev_t *ichdev = get_ichdev(substream);
594 size_t ptr1, ptr;
595
596 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
597 if (ptr1 != 0)
598 ptr = ichdev->fragsize1 - ptr1;
599 else
600 ptr = 0;
601 ptr += ichdev->position;
602 if (ptr >= ichdev->size)
603 return 0;
604 return bytes_to_frames(substream->runtime, ptr);
605}
606
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
608{
609 intel8x0_t *chip = snd_pcm_substream_chip(substream);
610 snd_pcm_runtime_t *runtime = substream->runtime;
611 ichdev_t *ichdev = get_ichdev(substream);
612
613 ichdev->physbuf = runtime->dma_addr;
614 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
615 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
616 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
617 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
618 snd_intel8x0_setup_periods(chip, ichdev);
619 return 0;
620}
621
622static snd_pcm_hardware_t snd_intel8x0m_stream =
623{
624 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
625 SNDRV_PCM_INFO_BLOCK_TRANSFER |
626 SNDRV_PCM_INFO_MMAP_VALID |
627 SNDRV_PCM_INFO_PAUSE |
628 SNDRV_PCM_INFO_RESUME),
629 .formats = SNDRV_PCM_FMTBIT_S16_LE,
630 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
631 .rate_min = 8000,
632 .rate_max = 16000,
633 .channels_min = 1,
634 .channels_max = 1,
635 .buffer_bytes_max = 64 * 1024,
636 .period_bytes_min = 32,
637 .period_bytes_max = 64 * 1024,
638 .periods_min = 1,
639 .periods_max = 1024,
640 .fifo_size = 0,
641};
642
643
644static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
645{
646 static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
647 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
648 .count = ARRAY_SIZE(rates),
649 .list = rates,
650 .mask = 0,
651 };
652 snd_pcm_runtime_t *runtime = substream->runtime;
653 int err;
654
655 ichdev->substream = substream;
656 runtime->hw = snd_intel8x0m_stream;
657 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
658 if ( err < 0 )
659 return err;
660 runtime->private_data = ichdev;
661 return 0;
662}
663
664static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
665{
666 intel8x0_t *chip = snd_pcm_substream_chip(substream);
667
668 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
669}
670
671static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
672{
673 intel8x0_t *chip = snd_pcm_substream_chip(substream);
674
675 chip->ichd[ICHD_MDMOUT].substream = NULL;
676 return 0;
677}
678
679static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
680{
681 intel8x0_t *chip = snd_pcm_substream_chip(substream);
682
683 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
684}
685
686static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
687{
688 intel8x0_t *chip = snd_pcm_substream_chip(substream);
689
690 chip->ichd[ICHD_MDMIN].substream = NULL;
691 return 0;
692}
693
694
695static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
696 .open = snd_intel8x0m_playback_open,
697 .close = snd_intel8x0m_playback_close,
698 .ioctl = snd_pcm_lib_ioctl,
699 .hw_params = snd_intel8x0_hw_params,
700 .hw_free = snd_intel8x0_hw_free,
701 .prepare = snd_intel8x0m_pcm_prepare,
Sasha Khapyorsky83a5b722005-05-29 15:10:07 +0200702 .trigger = snd_intel8x0_pcm_trigger,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 .pointer = snd_intel8x0_pcm_pointer,
704};
705
706static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
707 .open = snd_intel8x0m_capture_open,
708 .close = snd_intel8x0m_capture_close,
709 .ioctl = snd_pcm_lib_ioctl,
710 .hw_params = snd_intel8x0_hw_params,
711 .hw_free = snd_intel8x0_hw_free,
712 .prepare = snd_intel8x0m_pcm_prepare,
Sasha Khapyorsky83a5b722005-05-29 15:10:07 +0200713 .trigger = snd_intel8x0_pcm_trigger,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 .pointer = snd_intel8x0_pcm_pointer,
715};
716
717
718struct ich_pcm_table {
719 char *suffix;
720 snd_pcm_ops_t *playback_ops;
721 snd_pcm_ops_t *capture_ops;
722 size_t prealloc_size;
723 size_t prealloc_max_size;
724 int ac97_idx;
725};
726
727static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
728{
729 snd_pcm_t *pcm;
730 int err;
731 char name[32];
732
733 if (rec->suffix)
734 sprintf(name, "Intel ICH - %s", rec->suffix);
735 else
736 strcpy(name, "Intel ICH");
737 err = snd_pcm_new(chip->card, name, device,
738 rec->playback_ops ? 1 : 0,
739 rec->capture_ops ? 1 : 0, &pcm);
740 if (err < 0)
741 return err;
742
743 if (rec->playback_ops)
744 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
745 if (rec->capture_ops)
746 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
747
748 pcm->private_data = chip;
749 pcm->info_flags = 0;
Sasha Khapyorsky6632d192005-09-29 11:48:17 +0200750 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 if (rec->suffix)
752 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
753 else
754 strcpy(pcm->name, chip->card->shortname);
755 chip->pcm[device] = pcm;
756
757 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
758 snd_dma_pci_data(chip->pci),
759 rec->prealloc_size,
760 rec->prealloc_max_size);
761
762 return 0;
763}
764
765static struct ich_pcm_table intel_pcms[] __devinitdata = {
766 {
767 .suffix = "Modem",
768 .playback_ops = &snd_intel8x0m_playback_ops,
769 .capture_ops = &snd_intel8x0m_capture_ops,
770 .prealloc_size = 32 * 1024,
771 .prealloc_max_size = 64 * 1024,
772 },
773};
774
775static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
776{
777 int i, tblsize, device, err;
778 struct ich_pcm_table *tbl, *rec;
779
780#if 1
781 tbl = intel_pcms;
782 tblsize = 1;
783#else
784 switch (chip->device_type) {
785 case DEVICE_NFORCE:
786 tbl = nforce_pcms;
787 tblsize = ARRAY_SIZE(nforce_pcms);
788 break;
789 case DEVICE_ALI:
790 tbl = ali_pcms;
791 tblsize = ARRAY_SIZE(ali_pcms);
792 break;
793 default:
794 tbl = intel_pcms;
795 tblsize = 2;
796 break;
797 }
798#endif
799 device = 0;
800 for (i = 0; i < tblsize; i++) {
801 rec = tbl + i;
802 if (i > 0 && rec->ac97_idx) {
803 /* activate PCM only when associated AC'97 codec */
804 if (! chip->ichd[rec->ac97_idx].ac97)
805 continue;
806 }
807 err = snd_intel8x0_pcm1(chip, device, rec);
808 if (err < 0)
809 return err;
810 device++;
811 }
812
813 chip->pcm_devs = device;
814 return 0;
815}
816
817
818/*
819 * Mixer part
820 */
821
822static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
823{
824 intel8x0_t *chip = bus->private_data;
825 chip->ac97_bus = NULL;
826}
827
828static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
829{
830 intel8x0_t *chip = ac97->private_data;
831 chip->ac97 = NULL;
832}
833
834
835static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
836{
837 ac97_bus_t *pbus;
838 ac97_template_t ac97;
839 ac97_t *x97;
840 int err;
841 unsigned int glob_sta = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 static ac97_bus_ops_t ops = {
843 .write = snd_intel8x0_codec_write,
844 .read = snd_intel8x0_codec_read,
845 };
846
847 chip->in_ac97_init = 1;
848
849 memset(&ac97, 0, sizeof(ac97));
850 ac97.private_data = chip;
851 ac97.private_free = snd_intel8x0_mixer_free_ac97;
852 ac97.scaps = AC97_SCAP_SKIP_AUDIO;
853
854 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
855
856 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
857 goto __err;
858 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 if (ac97_clock >= 8000 && ac97_clock <= 48000)
860 pbus->clock = ac97_clock;
861 chip->ac97_bus = pbus;
862
863 ac97.pci = chip->pci;
864 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
865 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
866 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
867 if (ac97.num == 0)
868 goto __err;
869 return err;
870 }
871 chip->ac97 = x97;
872 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
873 chip->ichd[ICHD_MDMIN].ac97 = x97;
874 chip->ichd[ICHD_MDMOUT].ac97 = x97;
875 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876
877 chip->in_ac97_init = 0;
878 return 0;
879
880 __err:
881 /* clear the cold-reset bit for the next chance */
882 if (chip->device_type != DEVICE_ALI)
883 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
884 return err;
885}
886
887
888/*
889 *
890 */
891
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
893{
894 unsigned long end_time;
895 unsigned int cnt, status, nstatus;
896
897 /* put logic to right state */
898 /* first clear status bits */
899 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
900 cnt = igetdword(chip, ICHREG(GLOB_STA));
901 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
902
903 /* ACLink on, 2 channels */
904 cnt = igetdword(chip, ICHREG(GLOB_CNT));
905 cnt &= ~(ICH_ACLINK);
906 /* finish cold or do warm reset */
907 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
908 iputdword(chip, ICHREG(GLOB_CNT), cnt);
909 end_time = (jiffies + (HZ / 4)) + 1;
910 do {
911 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
912 goto __ok;
Takashi Iwai954bea32005-11-17 10:37:40 +0100913 schedule_timeout_uninterruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 } while (time_after_eq(end_time, jiffies));
Takashi Iwai99b359b2005-10-20 18:26:44 +0200915 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 return -EIO;
917
918 __ok:
919 if (probing) {
920 /* wait for any codec ready status.
921 * Once it becomes ready it should remain ready
922 * as long as we do not disable the ac97 link.
923 */
924 end_time = jiffies + HZ;
925 do {
926 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
927 if (status)
928 break;
Takashi Iwai954bea32005-11-17 10:37:40 +0100929 schedule_timeout_uninterruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 } while (time_after_eq(end_time, jiffies));
931 if (! status) {
932 /* no codec is found */
933 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
934 return -EIO;
935 }
936
937 /* up to two codecs (modem cannot be tertiary with ICH4) */
938 nstatus = ICH_PCR | ICH_SCR;
939
940 /* wait for other codecs ready status. */
941 end_time = jiffies + HZ / 4;
942 while (status != nstatus && time_after_eq(end_time, jiffies)) {
Takashi Iwai954bea32005-11-17 10:37:40 +0100943 schedule_timeout_uninterruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
945 }
946
947 } else {
948 /* resume phase */
949 status = 0;
950 if (chip->ac97)
951 status |= get_ich_codec_bit(chip, chip->ac97->num);
952 /* wait until all the probed codecs are ready */
953 end_time = jiffies + HZ;
954 do {
955 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
956 if (status == nstatus)
957 break;
Takashi Iwai954bea32005-11-17 10:37:40 +0100958 schedule_timeout_uninterruptible(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 } while (time_after_eq(end_time, jiffies));
960 }
961
962 if (chip->device_type == DEVICE_SIS) {
963 /* unmute the output on SIS7012 */
964 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
965 }
966
967 return 0;
968}
969
970static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
971{
972 unsigned int i;
973 int err;
974
975 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
976 return err;
977 iagetword(chip, 0); /* clear semaphore flag */
978
979 /* disable interrupts */
980 for (i = 0; i < chip->bdbars_count; i++)
981 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
982 /* reset channels */
983 for (i = 0; i < chip->bdbars_count; i++)
984 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
985 /* initialize Buffer Descriptor Lists */
986 for (i = 0; i < chip->bdbars_count; i++)
987 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
988 return 0;
989}
990
991static int snd_intel8x0_free(intel8x0_t *chip)
992{
993 unsigned int i;
994
995 if (chip->irq < 0)
996 goto __hw_end;
997 /* disable interrupts */
998 for (i = 0; i < chip->bdbars_count; i++)
999 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1000 /* reset channels */
1001 for (i = 0; i < chip->bdbars_count; i++)
1002 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1003 /* --- */
1004 synchronize_irq(chip->irq);
1005 __hw_end:
1006 if (chip->bdbars.area)
1007 snd_dma_free_pages(&chip->bdbars);
1008 if (chip->remap_addr)
1009 iounmap(chip->remap_addr);
1010 if (chip->remap_bmaddr)
1011 iounmap(chip->remap_bmaddr);
1012 if (chip->irq >= 0)
1013 free_irq(chip->irq, (void *)chip);
1014 pci_release_regions(chip->pci);
1015 pci_disable_device(chip->pci);
1016 kfree(chip);
1017 return 0;
1018}
1019
1020#ifdef CONFIG_PM
1021/*
1022 * power management
1023 */
1024static int intel8x0m_suspend(snd_card_t *card, pm_message_t state)
1025{
1026 intel8x0_t *chip = card->pm_private_data;
1027 int i;
1028
1029 for (i = 0; i < chip->pcm_devs; i++)
1030 snd_pcm_suspend_all(chip->pcm[i]);
1031 if (chip->ac97)
1032 snd_ac97_suspend(chip->ac97);
1033 pci_disable_device(chip->pci);
1034 return 0;
1035}
1036
1037static int intel8x0m_resume(snd_card_t *card)
1038{
1039 intel8x0_t *chip = card->pm_private_data;
1040 pci_enable_device(chip->pci);
1041 pci_set_master(chip->pci);
1042 snd_intel8x0_chip_init(chip, 0);
1043 if (chip->ac97)
1044 snd_ac97_resume(chip->ac97);
1045
1046 return 0;
1047}
1048#endif /* CONFIG_PM */
1049
1050static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1051 snd_info_buffer_t * buffer)
1052{
1053 intel8x0_t *chip = entry->private_data;
1054 unsigned int tmp;
1055
1056 snd_iprintf(buffer, "Intel8x0m\n\n");
1057 if (chip->device_type == DEVICE_ALI)
1058 return;
1059 tmp = igetdword(chip, ICHREG(GLOB_STA));
1060 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1061 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1062 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1063 tmp & ICH_PCR ? " primary" : "",
1064 tmp & ICH_SCR ? " secondary" : "",
1065 tmp & ICH_TCR ? " tertiary" : "",
1066 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1067}
1068
1069static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1070{
1071 snd_info_entry_t *entry;
1072
1073 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1074 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1075}
1076
1077static int snd_intel8x0_dev_free(snd_device_t *device)
1078{
1079 intel8x0_t *chip = device->device_data;
1080 return snd_intel8x0_free(chip);
1081}
1082
1083struct ich_reg_info {
1084 unsigned int int_sta_mask;
1085 unsigned int offset;
1086};
1087
1088static int __devinit snd_intel8x0m_create(snd_card_t * card,
1089 struct pci_dev *pci,
1090 unsigned long device_type,
1091 intel8x0_t ** r_intel8x0)
1092{
1093 intel8x0_t *chip;
1094 int err;
1095 unsigned int i;
1096 unsigned int int_sta_masks;
1097 ichdev_t *ichdev;
1098 static snd_device_ops_t ops = {
1099 .dev_free = snd_intel8x0_dev_free,
1100 };
1101 static struct ich_reg_info intel_regs[2] = {
1102 { ICH_MIINT, 0 },
1103 { ICH_MOINT, 0x10 },
1104 };
1105 struct ich_reg_info *tbl;
1106
1107 *r_intel8x0 = NULL;
1108
1109 if ((err = pci_enable_device(pci)) < 0)
1110 return err;
1111
Takashi Iwaie560d8d2005-09-09 14:21:46 +02001112 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 if (chip == NULL) {
1114 pci_disable_device(pci);
1115 return -ENOMEM;
1116 }
1117 spin_lock_init(&chip->reg_lock);
1118 chip->device_type = device_type;
1119 chip->card = card;
1120 chip->pci = pci;
1121 chip->irq = -1;
1122
1123 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1124 kfree(chip);
1125 pci_disable_device(pci);
1126 return err;
1127 }
1128
1129 if (device_type == DEVICE_ALI) {
1130 /* ALI5455 has no ac97 region */
1131 chip->bmaddr = pci_resource_start(pci, 0);
1132 goto port_inited;
1133 }
1134
1135 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
1136 chip->mmio = 1;
1137 chip->addr = pci_resource_start(pci, 2);
1138 chip->remap_addr = ioremap_nocache(chip->addr,
1139 pci_resource_len(pci, 2));
1140 if (chip->remap_addr == NULL) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02001141 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 snd_intel8x0_free(chip);
1143 return -EIO;
1144 }
1145 } else {
1146 chip->addr = pci_resource_start(pci, 0);
1147 }
1148 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
1149 chip->bm_mmio = 1;
1150 chip->bmaddr = pci_resource_start(pci, 3);
1151 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
1152 pci_resource_len(pci, 3));
1153 if (chip->remap_bmaddr == NULL) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02001154 snd_printk(KERN_ERR "Controller space ioremap problem\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155 snd_intel8x0_free(chip);
1156 return -EIO;
1157 }
1158 } else {
1159 chip->bmaddr = pci_resource_start(pci, 1);
1160 }
1161
1162 port_inited:
1163 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02001164 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001165 snd_intel8x0_free(chip);
1166 return -EBUSY;
1167 }
1168 chip->irq = pci->irq;
1169 pci_set_master(pci);
1170 synchronize_irq(chip->irq);
1171
1172 /* initialize offsets */
1173 chip->bdbars_count = 2;
1174 tbl = intel_regs;
1175
1176 for (i = 0; i < chip->bdbars_count; i++) {
1177 ichdev = &chip->ichd[i];
1178 ichdev->ichd = i;
1179 ichdev->reg_offset = tbl[i].offset;
1180 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1181 if (device_type == DEVICE_SIS) {
1182 /* SiS 7013 swaps the registers */
1183 ichdev->roff_sr = ICH_REG_OFF_PICB;
1184 ichdev->roff_picb = ICH_REG_OFF_SR;
1185 } else {
1186 ichdev->roff_sr = ICH_REG_OFF_SR;
1187 ichdev->roff_picb = ICH_REG_OFF_PICB;
1188 }
1189 if (device_type == DEVICE_ALI)
1190 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1191 }
1192 /* SIS7013 handles the pcm data in bytes, others are in words */
1193 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1194
1195 /* allocate buffer descriptor lists */
1196 /* the start of each lists must be aligned to 8 bytes */
1197 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1198 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1199 &chip->bdbars) < 0) {
1200 snd_intel8x0_free(chip);
1201 return -ENOMEM;
1202 }
1203 /* tables must be aligned to 8 bytes here, but the kernel pages
1204 are much bigger, so we don't care (on i386) */
1205 int_sta_masks = 0;
1206 for (i = 0; i < chip->bdbars_count; i++) {
1207 ichdev = &chip->ichd[i];
1208 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1209 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1210 int_sta_masks |= ichdev->int_sta_mask;
1211 }
1212 chip->int_sta_reg = ICH_REG_GLOB_STA;
1213 chip->int_sta_mask = int_sta_masks;
1214
1215 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1216 snd_intel8x0_free(chip);
1217 return err;
1218 }
1219
1220 snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1221
1222 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1223 snd_intel8x0_free(chip);
1224 return err;
1225 }
1226
1227 snd_card_set_dev(card, &pci->dev);
1228
1229 *r_intel8x0 = chip;
1230 return 0;
1231}
1232
1233static struct shortname_table {
1234 unsigned int id;
1235 const char *s;
1236} shortnames[] __devinitdata = {
Takashi Iwai8cdfd252005-09-07 14:08:11 +02001237 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1238 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1240 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
Takashi Iwai8cdfd252005-09-07 14:08:11 +02001241 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1242 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1243 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1244 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1245 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 { 0x7446, "AMD AMD768" },
1247 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
Takashi Iwai8cdfd252005-09-07 14:08:11 +02001248 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1250 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1251 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1252#if 0
1253 { 0x5455, "ALi M5455" },
1254 { 0x746d, "AMD AMD8111" },
1255#endif
1256 { 0 },
1257};
1258
1259static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1260 const struct pci_device_id *pci_id)
1261{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262 snd_card_t *card;
1263 intel8x0_t *chip;
1264 int err;
1265 struct shortname_table *name;
1266
Clemens Ladischb7fe4622005-10-04 08:46:51 +02001267 card = snd_card_new(index, id, THIS_MODULE, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 if (card == NULL)
1269 return -ENOMEM;
1270
1271 strcpy(card->driver, "ICH-MODEM");
1272 strcpy(card->shortname, "Intel ICH");
1273 for (name = shortnames; name->id; name++) {
1274 if (pci->device == name->id) {
1275 strcpy(card->shortname, name->s);
1276 break;
1277 }
1278 }
1279 strcat(card->shortname," Modem");
1280
1281 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1282 snd_card_free(card);
1283 return err;
1284 }
1285
Clemens Ladischb7fe4622005-10-04 08:46:51 +02001286 if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 snd_card_free(card);
1288 return err;
1289 }
1290 if ((err = snd_intel8x0_pcm(chip)) < 0) {
1291 snd_card_free(card);
1292 return err;
1293 }
1294
1295 snd_intel8x0m_proc_init(chip);
1296
1297 sprintf(card->longname, "%s at 0x%lx, irq %i",
1298 card->shortname, chip->addr, chip->irq);
1299
1300 if ((err = snd_card_register(card)) < 0) {
1301 snd_card_free(card);
1302 return err;
1303 }
1304 pci_set_drvdata(pci, card);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 return 0;
1306}
1307
1308static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1309{
1310 snd_card_free(pci_get_drvdata(pci));
1311 pci_set_drvdata(pci, NULL);
1312}
1313
1314static struct pci_driver driver = {
1315 .name = "Intel ICH Modem",
1316 .id_table = snd_intel8x0m_ids,
1317 .probe = snd_intel8x0m_probe,
1318 .remove = __devexit_p(snd_intel8x0m_remove),
1319 SND_PCI_PM_CALLBACKS
1320};
1321
1322
1323static int __init alsa_card_intel8x0m_init(void)
1324{
Takashi Iwai01d25d42005-04-11 16:58:24 +02001325 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326}
1327
1328static void __exit alsa_card_intel8x0m_exit(void)
1329{
1330 pci_unregister_driver(&driver);
1331}
1332
1333module_init(alsa_card_intel8x0m_init)
1334module_exit(alsa_card_intel8x0m_exit)