Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1 | /* |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 2 | * Intel 5400 class Memory Controllers kernel module (Seaburg) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 3 | * |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * Copyright (c) 2008 by: |
| 8 | * Ben Woodard <woodard@redhat.com> |
| 9 | * Mauro Carvalho Chehab <mchehab@redhat.com> |
| 10 | * |
| 11 | * Red Hat Inc. http://www.redhat.com |
| 12 | * |
| 13 | * Forked and adapted from the i5000_edac driver which was |
| 14 | * written by Douglas Thompson Linux Networx <norsk5@xmission.com> |
| 15 | * |
| 16 | * This module is based on the following document: |
| 17 | * |
| 18 | * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet |
| 19 | * http://developer.intel.com/design/chipsets/datashts/313070.htm |
| 20 | * |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 21 | * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with |
| 22 | * 2 channels operating in lockstep no-mirror mode. Each channel can have up to |
| 23 | * 4 dimm's, each with up to 8GB. |
| 24 | * |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 25 | */ |
| 26 | |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/pci.h> |
| 30 | #include <linux/pci_ids.h> |
| 31 | #include <linux/slab.h> |
| 32 | #include <linux/edac.h> |
| 33 | #include <linux/mmzone.h> |
| 34 | |
| 35 | #include "edac_core.h" |
| 36 | |
| 37 | /* |
| 38 | * Alter this version for the I5400 module when modifications are made |
| 39 | */ |
Michal Marek | 152ba39 | 2011-04-01 12:41:20 +0200 | [diff] [blame] | 40 | #define I5400_REVISION " Ver: 1.0.0" |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 41 | |
| 42 | #define EDAC_MOD_STR "i5400_edac" |
| 43 | |
| 44 | #define i5400_printk(level, fmt, arg...) \ |
| 45 | edac_printk(level, "i5400", fmt, ##arg) |
| 46 | |
| 47 | #define i5400_mc_printk(mci, level, fmt, arg...) \ |
| 48 | edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg) |
| 49 | |
| 50 | /* Limits for i5400 */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 51 | #define MAX_BRANCHES 2 |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 52 | #define CHANNELS_PER_BRANCH 2 |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 53 | #define DIMMS_PER_CHANNEL 4 |
| 54 | #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 55 | |
| 56 | /* Device 16, |
| 57 | * Function 0: System Address |
| 58 | * Function 1: Memory Branch Map, Control, Errors Register |
| 59 | * Function 2: FSB Error Registers |
| 60 | * |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 61 | * All 3 functions of Device 16 (0,1,2) share the SAME DID and |
| 62 | * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2), |
| 63 | * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1 |
| 64 | * for device 21 (0,1). |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 65 | */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 66 | |
| 67 | /* OFFSETS for Function 0 */ |
| 68 | #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ |
| 69 | #define MAXCH 0x56 /* Max Channel Number */ |
| 70 | #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ |
| 71 | |
| 72 | /* OFFSETS for Function 1 */ |
| 73 | #define TOLM 0x6C |
| 74 | #define REDMEMB 0x7C |
| 75 | #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ |
| 76 | #define MIR0 0x80 |
| 77 | #define MIR1 0x84 |
| 78 | #define AMIR0 0x8c |
| 79 | #define AMIR1 0x90 |
| 80 | |
| 81 | /* Fatal error registers */ |
| 82 | #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */ |
| 83 | #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ |
| 84 | |
| 85 | #define NERR_FAT_FBD 0x9c |
| 86 | #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */ |
| 87 | |
| 88 | /* Non-fatal error register */ |
| 89 | #define NERR_NF_FBD 0xa4 |
| 90 | |
| 91 | /* Enable error mask */ |
| 92 | #define EMASK_FBD 0xa8 |
| 93 | |
| 94 | #define ERR0_FBD 0xac |
| 95 | #define ERR1_FBD 0xb0 |
| 96 | #define ERR2_FBD 0xb4 |
| 97 | #define MCERR_FBD 0xb8 |
| 98 | |
| 99 | /* No OFFSETS for Device 16 Function 2 */ |
| 100 | |
| 101 | /* |
| 102 | * Device 21, |
| 103 | * Function 0: Memory Map Branch 0 |
| 104 | * |
| 105 | * Device 22, |
| 106 | * Function 0: Memory Map Branch 1 |
| 107 | */ |
| 108 | |
| 109 | /* OFFSETS for Function 0 */ |
| 110 | #define AMBPRESENT_0 0x64 |
| 111 | #define AMBPRESENT_1 0x66 |
| 112 | #define MTR0 0x80 |
| 113 | #define MTR1 0x82 |
| 114 | #define MTR2 0x84 |
| 115 | #define MTR3 0x86 |
| 116 | |
| 117 | /* OFFSETS for Function 1 */ |
| 118 | #define NRECFGLOG 0x74 |
| 119 | #define RECFGLOG 0x78 |
| 120 | #define NRECMEMA 0xbe |
| 121 | #define NRECMEMB 0xc0 |
| 122 | #define NRECFB_DIMMA 0xc4 |
| 123 | #define NRECFB_DIMMB 0xc8 |
| 124 | #define NRECFB_DIMMC 0xcc |
| 125 | #define NRECFB_DIMMD 0xd0 |
| 126 | #define NRECFB_DIMME 0xd4 |
| 127 | #define NRECFB_DIMMF 0xd8 |
| 128 | #define REDMEMA 0xdC |
| 129 | #define RECMEMA 0xf0 |
| 130 | #define RECMEMB 0xf4 |
| 131 | #define RECFB_DIMMA 0xf8 |
| 132 | #define RECFB_DIMMB 0xec |
| 133 | #define RECFB_DIMMC 0xf0 |
| 134 | #define RECFB_DIMMD 0xf4 |
| 135 | #define RECFB_DIMME 0xf8 |
| 136 | #define RECFB_DIMMF 0xfC |
| 137 | |
| 138 | /* |
| 139 | * Error indicator bits and masks |
| 140 | * Error masks are according with Table 5-17 of i5400 datasheet |
| 141 | */ |
| 142 | |
| 143 | enum error_mask { |
| 144 | EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */ |
| 145 | EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */ |
| 146 | EMASK_M3 = 1<<2, /* Reserved */ |
| 147 | EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */ |
| 148 | EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */ |
| 149 | EMASK_M6 = 1<<5, /* Unsupported on i5400 */ |
| 150 | EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ |
| 151 | EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */ |
| 152 | EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */ |
| 153 | EMASK_M10 = 1<<9, /* Unsupported on i5400 */ |
| 154 | EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ |
| 155 | EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */ |
| 156 | EMASK_M13 = 1<<12, /* Memory Write error on first attempt */ |
| 157 | EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */ |
| 158 | EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */ |
| 159 | EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */ |
| 160 | EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */ |
| 161 | EMASK_M18 = 1<<17, /* Unsupported on i5400 */ |
| 162 | EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */ |
| 163 | EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */ |
| 164 | EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */ |
| 165 | EMASK_M22 = 1<<21, /* SPD protocol Error */ |
| 166 | EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */ |
| 167 | EMASK_M24 = 1<<23, /* Refresh error */ |
| 168 | EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */ |
| 169 | EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */ |
| 170 | EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */ |
| 171 | EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */ |
| 172 | EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */ |
| 173 | }; |
| 174 | |
| 175 | /* |
| 176 | * Names to translate bit error into something useful |
| 177 | */ |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 178 | static const char *error_name[] = { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 179 | [0] = "Memory Write error on non-redundant retry", |
| 180 | [1] = "Memory or FB-DIMM configuration CRC read error", |
| 181 | /* Reserved */ |
| 182 | [3] = "Uncorrectable Data ECC on Replay", |
| 183 | [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 184 | /* M6 Unsupported on i5400 */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 185 | [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", |
| 186 | [7] = "Aliased Uncorrectable Patrol Data ECC", |
| 187 | [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 188 | /* M10 Unsupported on i5400 */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 189 | [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", |
| 190 | [11] = "Non-Aliased Uncorrectable Patrol Data ECC", |
| 191 | [12] = "Memory Write error on first attempt", |
| 192 | [13] = "FB-DIMM Configuration Write error on first attempt", |
| 193 | [14] = "Memory or FB-DIMM configuration CRC read error", |
| 194 | [15] = "Channel Failed-Over Occurred", |
| 195 | [16] = "Correctable Non-Mirrored Demand Data ECC", |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 196 | /* M18 Unsupported on i5400 */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 197 | [18] = "Correctable Resilver- or Spare-Copy Data ECC", |
| 198 | [19] = "Correctable Patrol Data ECC", |
| 199 | [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status", |
| 200 | [21] = "SPD protocol Error", |
| 201 | [22] = "Non-Redundant Fast Reset Timeout", |
| 202 | [23] = "Refresh error", |
| 203 | [24] = "Memory Write error on redundant retry", |
| 204 | [25] = "Redundant Fast Reset Timeout", |
| 205 | [26] = "Correctable Counter Threshold Exceeded", |
| 206 | [27] = "DIMM-Spare Copy Completed", |
| 207 | [28] = "DIMM-Isolation Completed", |
| 208 | }; |
| 209 | |
| 210 | /* Fatal errors */ |
| 211 | #define ERROR_FAT_MASK (EMASK_M1 | \ |
| 212 | EMASK_M2 | \ |
| 213 | EMASK_M23) |
| 214 | |
| 215 | /* Correctable errors */ |
| 216 | #define ERROR_NF_CORRECTABLE (EMASK_M27 | \ |
| 217 | EMASK_M20 | \ |
| 218 | EMASK_M19 | \ |
| 219 | EMASK_M18 | \ |
| 220 | EMASK_M17 | \ |
| 221 | EMASK_M16) |
| 222 | #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \ |
| 223 | EMASK_M28) |
| 224 | #define ERROR_NF_SPD_PROTOCOL (EMASK_M22) |
| 225 | #define ERROR_NF_NORTH_CRC (EMASK_M21) |
| 226 | |
| 227 | /* Recoverable errors */ |
| 228 | #define ERROR_NF_RECOVERABLE (EMASK_M26 | \ |
| 229 | EMASK_M25 | \ |
| 230 | EMASK_M24 | \ |
| 231 | EMASK_M15 | \ |
| 232 | EMASK_M14 | \ |
| 233 | EMASK_M13 | \ |
| 234 | EMASK_M12 | \ |
| 235 | EMASK_M11 | \ |
| 236 | EMASK_M9 | \ |
| 237 | EMASK_M8 | \ |
| 238 | EMASK_M7 | \ |
| 239 | EMASK_M5) |
| 240 | |
| 241 | /* uncorrectable errors */ |
| 242 | #define ERROR_NF_UNCORRECTABLE (EMASK_M4) |
| 243 | |
| 244 | /* mask to all non-fatal errors */ |
| 245 | #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \ |
| 246 | ERROR_NF_UNCORRECTABLE | \ |
| 247 | ERROR_NF_RECOVERABLE | \ |
| 248 | ERROR_NF_DIMM_SPARE | \ |
| 249 | ERROR_NF_SPD_PROTOCOL | \ |
| 250 | ERROR_NF_NORTH_CRC) |
| 251 | |
| 252 | /* |
| 253 | * Define error masks for the several registers |
| 254 | */ |
| 255 | |
| 256 | /* Enable all fatal and non fatal errors */ |
| 257 | #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK) |
| 258 | |
| 259 | /* mask for fatal error registers */ |
| 260 | #define FERR_FAT_MASK ERROR_FAT_MASK |
| 261 | |
| 262 | /* masks for non-fatal error register */ |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 263 | static inline int to_nf_mask(unsigned int mask) |
| 264 | { |
| 265 | return (mask & EMASK_M29) | (mask >> 3); |
| 266 | }; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 267 | |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 268 | static inline int from_nf_ferr(unsigned int mask) |
| 269 | { |
| 270 | return (mask & EMASK_M29) | /* Bit 28 */ |
| 271 | (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ |
| 272 | }; |
| 273 | |
| 274 | #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK) |
| 275 | #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE) |
| 276 | #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE) |
| 277 | #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL) |
| 278 | #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC) |
| 279 | #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE) |
| 280 | #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 281 | |
| 282 | /* Defines to extract the vaious fields from the |
| 283 | * MTRx - Memory Technology Registers |
| 284 | */ |
| 285 | #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) |
| 286 | #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 287 | #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) |
| 288 | #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 289 | #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) |
| 290 | #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) |
| 291 | #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) |
| 292 | #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) |
| 293 | #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) |
| 294 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) |
| 295 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) |
| 296 | |
| 297 | /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ |
| 298 | static inline int extract_fbdchan_indx(u32 x) |
| 299 | { |
| 300 | return (x>>28) & 0x3; |
| 301 | } |
| 302 | |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 303 | /* Device name and register DID (Device ID) */ |
| 304 | struct i5400_dev_info { |
| 305 | const char *ctl_name; /* name for this device */ |
| 306 | u16 fsb_mapping_errors; /* DID for the branchmap,control */ |
| 307 | }; |
| 308 | |
| 309 | /* Table of devices attributes supported by this driver */ |
| 310 | static const struct i5400_dev_info i5400_devs[] = { |
| 311 | { |
| 312 | .ctl_name = "I5400", |
| 313 | .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR, |
| 314 | }, |
| 315 | }; |
| 316 | |
| 317 | struct i5400_dimm_info { |
| 318 | int megabytes; /* size, 0 means not present */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 319 | }; |
| 320 | |
| 321 | /* driver private data structure */ |
| 322 | struct i5400_pvt { |
| 323 | struct pci_dev *system_address; /* 16.0 */ |
| 324 | struct pci_dev *branchmap_werrors; /* 16.1 */ |
| 325 | struct pci_dev *fsb_error_regs; /* 16.2 */ |
| 326 | struct pci_dev *branch_0; /* 21.0 */ |
| 327 | struct pci_dev *branch_1; /* 22.0 */ |
| 328 | |
| 329 | u16 tolm; /* top of low memory */ |
| 330 | u64 ambase; /* AMB BAR */ |
| 331 | |
| 332 | u16 mir0, mir1; |
| 333 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 334 | u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 335 | u16 b0_ambpresent0; /* Branch 0, Channel 0 */ |
| 336 | u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ |
| 337 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 338 | u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 339 | u16 b1_ambpresent0; /* Branch 1, Channel 8 */ |
| 340 | u16 b1_ambpresent1; /* Branch 1, Channel 1 */ |
| 341 | |
| 342 | /* DIMM information matrix, allocating architecture maximums */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 343 | struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS]; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 344 | |
| 345 | /* Actual values for this controller */ |
| 346 | int maxch; /* Max channels */ |
| 347 | int maxdimmperch; /* Max DIMMs per channel */ |
| 348 | }; |
| 349 | |
| 350 | /* I5400 MCH error information retrieved from Hardware */ |
| 351 | struct i5400_error_info { |
| 352 | /* These registers are always read from the MC */ |
| 353 | u32 ferr_fat_fbd; /* First Errors Fatal */ |
| 354 | u32 nerr_fat_fbd; /* Next Errors Fatal */ |
| 355 | u32 ferr_nf_fbd; /* First Errors Non-Fatal */ |
| 356 | u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ |
| 357 | |
| 358 | /* These registers are input ONLY if there was a Recoverable Error */ |
| 359 | u32 redmemb; /* Recoverable Mem Data Error log B */ |
| 360 | u16 recmema; /* Recoverable Mem Error log A */ |
| 361 | u32 recmemb; /* Recoverable Mem Error log B */ |
| 362 | |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 363 | /* These registers are input ONLY if there was a Non-Rec Error */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 364 | u16 nrecmema; /* Non-Recoverable Mem log A */ |
| 365 | u16 nrecmemb; /* Non-Recoverable Mem log B */ |
| 366 | |
| 367 | }; |
| 368 | |
| 369 | /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and |
| 370 | 5400 better to use an inline function than a macro in this case */ |
| 371 | static inline int nrec_bank(struct i5400_error_info *info) |
| 372 | { |
| 373 | return ((info->nrecmema) >> 12) & 0x7; |
| 374 | } |
| 375 | static inline int nrec_rank(struct i5400_error_info *info) |
| 376 | { |
| 377 | return ((info->nrecmema) >> 8) & 0xf; |
| 378 | } |
| 379 | static inline int nrec_buf_id(struct i5400_error_info *info) |
| 380 | { |
| 381 | return ((info->nrecmema)) & 0xff; |
| 382 | } |
| 383 | static inline int nrec_rdwr(struct i5400_error_info *info) |
| 384 | { |
| 385 | return (info->nrecmemb) >> 31; |
| 386 | } |
| 387 | /* This applies to both NREC and REC string so it can be used with nrec_rdwr |
| 388 | and rec_rdwr */ |
| 389 | static inline const char *rdwr_str(int rdwr) |
| 390 | { |
| 391 | return rdwr ? "Write" : "Read"; |
| 392 | } |
| 393 | static inline int nrec_cas(struct i5400_error_info *info) |
| 394 | { |
| 395 | return ((info->nrecmemb) >> 16) & 0x1fff; |
| 396 | } |
| 397 | static inline int nrec_ras(struct i5400_error_info *info) |
| 398 | { |
| 399 | return (info->nrecmemb) & 0xffff; |
| 400 | } |
| 401 | static inline int rec_bank(struct i5400_error_info *info) |
| 402 | { |
| 403 | return ((info->recmema) >> 12) & 0x7; |
| 404 | } |
| 405 | static inline int rec_rank(struct i5400_error_info *info) |
| 406 | { |
| 407 | return ((info->recmema) >> 8) & 0xf; |
| 408 | } |
| 409 | static inline int rec_rdwr(struct i5400_error_info *info) |
| 410 | { |
| 411 | return (info->recmemb) >> 31; |
| 412 | } |
| 413 | static inline int rec_cas(struct i5400_error_info *info) |
| 414 | { |
| 415 | return ((info->recmemb) >> 16) & 0x1fff; |
| 416 | } |
| 417 | static inline int rec_ras(struct i5400_error_info *info) |
| 418 | { |
| 419 | return (info->recmemb) & 0xffff; |
| 420 | } |
| 421 | |
| 422 | static struct edac_pci_ctl_info *i5400_pci; |
| 423 | |
| 424 | /* |
| 425 | * i5400_get_error_info Retrieve the hardware error information from |
| 426 | * the hardware and cache it in the 'info' |
| 427 | * structure |
| 428 | */ |
| 429 | static void i5400_get_error_info(struct mem_ctl_info *mci, |
| 430 | struct i5400_error_info *info) |
| 431 | { |
| 432 | struct i5400_pvt *pvt; |
| 433 | u32 value; |
| 434 | |
| 435 | pvt = mci->pvt_info; |
| 436 | |
| 437 | /* read in the 1st FATAL error register */ |
| 438 | pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); |
| 439 | |
| 440 | /* Mask only the bits that the doc says are valid |
| 441 | */ |
| 442 | value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); |
| 443 | |
| 444 | /* If there is an error, then read in the |
| 445 | NEXT FATAL error register and the Memory Error Log Register A |
| 446 | */ |
| 447 | if (value & FERR_FAT_MASK) { |
| 448 | info->ferr_fat_fbd = value; |
| 449 | |
| 450 | /* harvest the various error data we need */ |
| 451 | pci_read_config_dword(pvt->branchmap_werrors, |
| 452 | NERR_FAT_FBD, &info->nerr_fat_fbd); |
| 453 | pci_read_config_word(pvt->branchmap_werrors, |
| 454 | NRECMEMA, &info->nrecmema); |
| 455 | pci_read_config_word(pvt->branchmap_werrors, |
| 456 | NRECMEMB, &info->nrecmemb); |
| 457 | |
| 458 | /* Clear the error bits, by writing them back */ |
| 459 | pci_write_config_dword(pvt->branchmap_werrors, |
| 460 | FERR_FAT_FBD, value); |
| 461 | } else { |
| 462 | info->ferr_fat_fbd = 0; |
| 463 | info->nerr_fat_fbd = 0; |
| 464 | info->nrecmema = 0; |
| 465 | info->nrecmemb = 0; |
| 466 | } |
| 467 | |
| 468 | /* read in the 1st NON-FATAL error register */ |
| 469 | pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); |
| 470 | |
| 471 | /* If there is an error, then read in the 1st NON-FATAL error |
| 472 | * register as well */ |
| 473 | if (value & FERR_NF_MASK) { |
| 474 | info->ferr_nf_fbd = value; |
| 475 | |
| 476 | /* harvest the various error data we need */ |
| 477 | pci_read_config_dword(pvt->branchmap_werrors, |
| 478 | NERR_NF_FBD, &info->nerr_nf_fbd); |
| 479 | pci_read_config_word(pvt->branchmap_werrors, |
| 480 | RECMEMA, &info->recmema); |
| 481 | pci_read_config_dword(pvt->branchmap_werrors, |
| 482 | RECMEMB, &info->recmemb); |
| 483 | pci_read_config_dword(pvt->branchmap_werrors, |
| 484 | REDMEMB, &info->redmemb); |
| 485 | |
| 486 | /* Clear the error bits, by writing them back */ |
| 487 | pci_write_config_dword(pvt->branchmap_werrors, |
| 488 | FERR_NF_FBD, value); |
| 489 | } else { |
| 490 | info->ferr_nf_fbd = 0; |
| 491 | info->nerr_nf_fbd = 0; |
| 492 | info->recmema = 0; |
| 493 | info->recmemb = 0; |
| 494 | info->redmemb = 0; |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | /* |
| 499 | * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, |
| 500 | * struct i5400_error_info *info, |
| 501 | * int handle_errors); |
| 502 | * |
| 503 | * handle the Intel FATAL and unrecoverable errors, if any |
| 504 | */ |
| 505 | static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, |
| 506 | struct i5400_error_info *info, |
| 507 | unsigned long allErrors) |
| 508 | { |
| 509 | char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; |
| 510 | int branch; |
| 511 | int channel; |
| 512 | int bank; |
| 513 | int buf_id; |
| 514 | int rank; |
| 515 | int rdwr; |
| 516 | int ras, cas; |
| 517 | int errnum; |
| 518 | char *type = NULL; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 519 | enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 520 | |
| 521 | if (!allErrors) |
| 522 | return; /* if no error, return now */ |
| 523 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 524 | if (allErrors & ERROR_FAT_MASK) { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 525 | type = "FATAL"; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 526 | tp_event = HW_EVENT_ERR_FATAL; |
| 527 | } else if (allErrors & FERR_NF_UNCORRECTABLE) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 528 | type = "NON-FATAL uncorrected"; |
| 529 | else |
| 530 | type = "NON-FATAL recoverable"; |
| 531 | |
| 532 | /* ONLY ONE of the possible error bits will be set, as per the docs */ |
| 533 | |
| 534 | branch = extract_fbdchan_indx(info->ferr_fat_fbd); |
| 535 | channel = branch; |
| 536 | |
| 537 | /* Use the NON-Recoverable macros to extract data */ |
| 538 | bank = nrec_bank(info); |
| 539 | rank = nrec_rank(info); |
| 540 | buf_id = nrec_buf_id(info); |
| 541 | rdwr = nrec_rdwr(info); |
| 542 | ras = nrec_ras(info); |
| 543 | cas = nrec_cas(info); |
| 544 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 545 | edac_dbg(0, "\t\tDIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", |
| 546 | rank, channel, channel + 1, branch >> 1, bank, |
| 547 | buf_id, rdwr_str(rdwr), ras, cas); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 548 | |
| 549 | /* Only 1 bit will be on */ |
| 550 | errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); |
| 551 | |
| 552 | /* Form out message */ |
| 553 | snprintf(msg, sizeof(msg), |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 554 | "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", |
| 555 | bank, buf_id, ras, cas, allErrors, error_name[errnum]); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 556 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 557 | edac_mc_handle_error(tp_event, mci, 0, 0, 0, |
| 558 | branch >> 1, -1, rank, |
| 559 | rdwr ? "Write error" : "Read error", |
| 560 | msg, NULL); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | /* |
| 564 | * i5400_process_fatal_error_info(struct mem_ctl_info *mci, |
| 565 | * struct i5400_error_info *info, |
| 566 | * int handle_errors); |
| 567 | * |
| 568 | * handle the Intel NON-FATAL errors, if any |
| 569 | */ |
| 570 | static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci, |
| 571 | struct i5400_error_info *info) |
| 572 | { |
| 573 | char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; |
| 574 | unsigned long allErrors; |
| 575 | int branch; |
| 576 | int channel; |
| 577 | int bank; |
| 578 | int rank; |
| 579 | int rdwr; |
| 580 | int ras, cas; |
| 581 | int errnum; |
| 582 | |
| 583 | /* mask off the Error bits that are possible */ |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 584 | allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 585 | if (!allErrors) |
| 586 | return; /* if no error, return now */ |
| 587 | |
| 588 | /* ONLY ONE of the possible error bits will be set, as per the docs */ |
| 589 | |
| 590 | if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) { |
| 591 | i5400_proccess_non_recoverable_info(mci, info, allErrors); |
| 592 | return; |
| 593 | } |
| 594 | |
| 595 | /* Correctable errors */ |
| 596 | if (allErrors & ERROR_NF_CORRECTABLE) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 597 | edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 598 | |
| 599 | branch = extract_fbdchan_indx(info->ferr_nf_fbd); |
| 600 | |
| 601 | channel = 0; |
| 602 | if (REC_ECC_LOCATOR_ODD(info->redmemb)) |
| 603 | channel = 1; |
| 604 | |
| 605 | /* Convert channel to be based from zero, instead of |
| 606 | * from branch base of 0 */ |
| 607 | channel += branch; |
| 608 | |
| 609 | bank = rec_bank(info); |
| 610 | rank = rec_rank(info); |
| 611 | rdwr = rec_rdwr(info); |
| 612 | ras = rec_ras(info); |
| 613 | cas = rec_cas(info); |
| 614 | |
| 615 | /* Only 1 bit will be on */ |
| 616 | errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); |
| 617 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 618 | edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", |
| 619 | rank, channel, branch >> 1, bank, |
| 620 | rdwr_str(rdwr), ras, cas); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 621 | |
| 622 | /* Form out message */ |
| 623 | snprintf(msg, sizeof(msg), |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 624 | "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " |
| 625 | "RAS=%d CAS=%d, CE Err=0x%lx (%s))", |
| 626 | branch >> 1, bank, rdwr_str(rdwr), ras, cas, |
| 627 | allErrors, error_name[errnum]); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 628 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 629 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0, |
| 630 | branch >> 1, channel % 2, rank, |
| 631 | rdwr ? "Write error" : "Read error", |
| 632 | msg, NULL); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 633 | |
| 634 | return; |
| 635 | } |
| 636 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 637 | /* Miscellaneous errors */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 638 | errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); |
| 639 | |
| 640 | branch = extract_fbdchan_indx(info->ferr_nf_fbd); |
| 641 | |
| 642 | i5400_mc_printk(mci, KERN_EMERG, |
| 643 | "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", |
| 644 | branch >> 1, allErrors, error_name[errnum]); |
| 645 | } |
| 646 | |
| 647 | /* |
| 648 | * i5400_process_error_info Process the error info that is |
| 649 | * in the 'info' structure, previously retrieved from hardware |
| 650 | */ |
| 651 | static void i5400_process_error_info(struct mem_ctl_info *mci, |
| 652 | struct i5400_error_info *info) |
| 653 | { u32 allErrors; |
| 654 | |
| 655 | /* First handle any fatal errors that occurred */ |
| 656 | allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); |
| 657 | i5400_proccess_non_recoverable_info(mci, info, allErrors); |
| 658 | |
| 659 | /* now handle any non-fatal errors that occurred */ |
| 660 | i5400_process_nonfatal_error_info(mci, info); |
| 661 | } |
| 662 | |
| 663 | /* |
| 664 | * i5400_clear_error Retrieve any error from the hardware |
| 665 | * but do NOT process that error. |
| 666 | * Used for 'clearing' out of previous errors |
| 667 | * Called by the Core module. |
| 668 | */ |
| 669 | static void i5400_clear_error(struct mem_ctl_info *mci) |
| 670 | { |
| 671 | struct i5400_error_info info; |
| 672 | |
| 673 | i5400_get_error_info(mci, &info); |
| 674 | } |
| 675 | |
| 676 | /* |
| 677 | * i5400_check_error Retrieve and process errors reported by the |
| 678 | * hardware. Called by the Core module. |
| 679 | */ |
| 680 | static void i5400_check_error(struct mem_ctl_info *mci) |
| 681 | { |
| 682 | struct i5400_error_info info; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 683 | edac_dbg(4, "MC%d\n", mci->mc_idx); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 684 | i5400_get_error_info(mci, &info); |
| 685 | i5400_process_error_info(mci, &info); |
| 686 | } |
| 687 | |
| 688 | /* |
| 689 | * i5400_put_devices 'put' all the devices that we have |
| 690 | * reserved via 'get' |
| 691 | */ |
| 692 | static void i5400_put_devices(struct mem_ctl_info *mci) |
| 693 | { |
| 694 | struct i5400_pvt *pvt; |
| 695 | |
| 696 | pvt = mci->pvt_info; |
| 697 | |
| 698 | /* Decrement usage count for devices */ |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 699 | pci_dev_put(pvt->branch_1); |
| 700 | pci_dev_put(pvt->branch_0); |
| 701 | pci_dev_put(pvt->fsb_error_regs); |
| 702 | pci_dev_put(pvt->branchmap_werrors); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 703 | } |
| 704 | |
| 705 | /* |
| 706 | * i5400_get_devices Find and perform 'get' operation on the MCH's |
| 707 | * device/functions we want to reference for this driver |
| 708 | * |
| 709 | * Need to 'get' device 16 func 1 and func 2 |
| 710 | */ |
| 711 | static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx) |
| 712 | { |
| 713 | struct i5400_pvt *pvt; |
| 714 | struct pci_dev *pdev; |
| 715 | |
| 716 | pvt = mci->pvt_info; |
| 717 | pvt->branchmap_werrors = NULL; |
| 718 | pvt->fsb_error_regs = NULL; |
| 719 | pvt->branch_0 = NULL; |
| 720 | pvt->branch_1 = NULL; |
| 721 | |
| 722 | /* Attempt to 'get' the MCH register we want */ |
| 723 | pdev = NULL; |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 724 | while (1) { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 725 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 726 | PCI_DEVICE_ID_INTEL_5400_ERR, pdev); |
| 727 | if (!pdev) { |
| 728 | /* End of list, leave */ |
| 729 | i5400_printk(KERN_ERR, |
| 730 | "'system address,Process Bus' " |
| 731 | "device not found:" |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 732 | "vendor 0x%x device 0x%x ERR func 1 " |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 733 | "(broken BIOS?)\n", |
| 734 | PCI_VENDOR_ID_INTEL, |
| 735 | PCI_DEVICE_ID_INTEL_5400_ERR); |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 736 | return -ENODEV; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 737 | } |
| 738 | |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 739 | /* Store device 16 func 1 */ |
| 740 | if (PCI_FUNC(pdev->devfn) == 1) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 741 | break; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 742 | } |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 743 | pvt->branchmap_werrors = pdev; |
| 744 | |
| 745 | pdev = NULL; |
| 746 | while (1) { |
| 747 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 748 | PCI_DEVICE_ID_INTEL_5400_ERR, pdev); |
| 749 | if (!pdev) { |
| 750 | /* End of list, leave */ |
| 751 | i5400_printk(KERN_ERR, |
| 752 | "'system address,Process Bus' " |
| 753 | "device not found:" |
| 754 | "vendor 0x%x device 0x%x ERR func 2 " |
| 755 | "(broken BIOS?)\n", |
| 756 | PCI_VENDOR_ID_INTEL, |
| 757 | PCI_DEVICE_ID_INTEL_5400_ERR); |
| 758 | |
| 759 | pci_dev_put(pvt->branchmap_werrors); |
| 760 | return -ENODEV; |
| 761 | } |
| 762 | |
| 763 | /* Store device 16 func 2 */ |
| 764 | if (PCI_FUNC(pdev->devfn) == 2) |
| 765 | break; |
| 766 | } |
| 767 | pvt->fsb_error_regs = pdev; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 768 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 769 | edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", |
| 770 | pci_name(pvt->system_address), |
| 771 | pvt->system_address->vendor, pvt->system_address->device); |
| 772 | edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", |
| 773 | pci_name(pvt->branchmap_werrors), |
| 774 | pvt->branchmap_werrors->vendor, |
| 775 | pvt->branchmap_werrors->device); |
| 776 | edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", |
| 777 | pci_name(pvt->fsb_error_regs), |
| 778 | pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 779 | |
| 780 | pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 781 | PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); |
| 782 | if (!pvt->branch_0) { |
| 783 | i5400_printk(KERN_ERR, |
| 784 | "MC: 'BRANCH 0' device not found:" |
| 785 | "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", |
| 786 | PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0); |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 787 | |
| 788 | pci_dev_put(pvt->fsb_error_regs); |
| 789 | pci_dev_put(pvt->branchmap_werrors); |
| 790 | return -ENODEV; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 791 | } |
| 792 | |
| 793 | /* If this device claims to have more than 2 channels then |
| 794 | * fetch Branch 1's information |
| 795 | */ |
| 796 | if (pvt->maxch < CHANNELS_PER_BRANCH) |
| 797 | return 0; |
| 798 | |
| 799 | pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 800 | PCI_DEVICE_ID_INTEL_5400_FBD1, NULL); |
| 801 | if (!pvt->branch_1) { |
| 802 | i5400_printk(KERN_ERR, |
| 803 | "MC: 'BRANCH 1' device not found:" |
| 804 | "vendor 0x%x device 0x%x Func 0 " |
| 805 | "(broken BIOS?)\n", |
| 806 | PCI_VENDOR_ID_INTEL, |
| 807 | PCI_DEVICE_ID_INTEL_5400_FBD1); |
Mauro Carvalho Chehab | 0142877 | 2012-02-12 08:21:34 -0300 | [diff] [blame] | 808 | |
| 809 | pci_dev_put(pvt->branch_0); |
| 810 | pci_dev_put(pvt->fsb_error_regs); |
| 811 | pci_dev_put(pvt->branchmap_werrors); |
| 812 | return -ENODEV; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 813 | } |
| 814 | |
| 815 | return 0; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 816 | } |
| 817 | |
| 818 | /* |
| 819 | * determine_amb_present |
| 820 | * |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 821 | * the information is contained in DIMMS_PER_CHANNEL different |
| 822 | * registers determining which of the DIMMS_PER_CHANNEL requires |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 823 | * knowing which channel is in question |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 824 | * |
| 825 | * 2 branches, each with 2 channels |
| 826 | * b0_ambpresent0 for channel '0' |
| 827 | * b0_ambpresent1 for channel '1' |
| 828 | * b1_ambpresent0 for channel '2' |
| 829 | * b1_ambpresent1 for channel '3' |
| 830 | */ |
| 831 | static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) |
| 832 | { |
| 833 | int amb_present; |
| 834 | |
| 835 | if (channel < CHANNELS_PER_BRANCH) { |
| 836 | if (channel & 0x1) |
| 837 | amb_present = pvt->b0_ambpresent1; |
| 838 | else |
| 839 | amb_present = pvt->b0_ambpresent0; |
| 840 | } else { |
| 841 | if (channel & 0x1) |
| 842 | amb_present = pvt->b1_ambpresent1; |
| 843 | else |
| 844 | amb_present = pvt->b1_ambpresent0; |
| 845 | } |
| 846 | |
| 847 | return amb_present; |
| 848 | } |
| 849 | |
| 850 | /* |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 851 | * determine_mtr(pvt, dimm, channel) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 852 | * |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 853 | * return the proper MTR register as determine by the dimm and desired channel |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 854 | */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 855 | static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 856 | { |
| 857 | int mtr; |
| 858 | int n; |
| 859 | |
| 860 | /* There is one MTR for each slot pair of FB-DIMMs, |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 861 | Each slot pair may be at branch 0 or branch 1. |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 862 | */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 863 | n = dimm; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 864 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 865 | if (n >= DIMMS_PER_CHANNEL) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 866 | edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n", |
| 867 | dimm); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | if (channel < CHANNELS_PER_BRANCH) |
| 872 | mtr = pvt->b0_mtr[n]; |
| 873 | else |
| 874 | mtr = pvt->b1_mtr[n]; |
| 875 | |
| 876 | return mtr; |
| 877 | } |
| 878 | |
| 879 | /* |
| 880 | */ |
| 881 | static void decode_mtr(int slot_row, u16 mtr) |
| 882 | { |
| 883 | int ans; |
| 884 | |
| 885 | ans = MTR_DIMMS_PRESENT(mtr); |
| 886 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 887 | edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n", |
| 888 | slot_row, mtr, ans ? "" : "NOT "); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 889 | if (!ans) |
| 890 | return; |
| 891 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 892 | edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 893 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 894 | edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n", |
| 895 | MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 896 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 897 | edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); |
| 898 | edac_dbg(2, "\t\tNUMRANK: %s\n", |
| 899 | MTR_DIMM_RANK(mtr) ? "double" : "single"); |
| 900 | edac_dbg(2, "\t\tNUMROW: %s\n", |
| 901 | MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : |
| 902 | MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : |
| 903 | MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : |
| 904 | "65,536 - 16 rows"); |
| 905 | edac_dbg(2, "\t\tNUMCOL: %s\n", |
| 906 | MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : |
| 907 | MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : |
| 908 | MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : |
| 909 | "reserved"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 910 | } |
| 911 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 912 | static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 913 | struct i5400_dimm_info *dinfo) |
| 914 | { |
| 915 | int mtr; |
| 916 | int amb_present_reg; |
| 917 | int addrBits; |
| 918 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 919 | mtr = determine_mtr(pvt, dimm, channel); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 920 | if (MTR_DIMMS_PRESENT(mtr)) { |
| 921 | amb_present_reg = determine_amb_present_reg(pvt, channel); |
| 922 | |
| 923 | /* Determine if there is a DIMM present in this DIMM slot */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 924 | if (amb_present_reg & (1 << dimm)) { |
Jeff Roberson | 156edd4 | 2009-10-26 16:50:09 -0700 | [diff] [blame] | 925 | /* Start with the number of bits for a Bank |
| 926 | * on the DRAM */ |
| 927 | addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); |
| 928 | /* Add thenumber of ROW bits */ |
| 929 | addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); |
| 930 | /* add the number of COLUMN bits */ |
| 931 | addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); |
| 932 | /* add the number of RANK bits */ |
| 933 | addrBits += MTR_DIMM_RANK(mtr); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 934 | |
Jeff Roberson | 156edd4 | 2009-10-26 16:50:09 -0700 | [diff] [blame] | 935 | addrBits += 6; /* add 64 bits per DIMM */ |
| 936 | addrBits -= 20; /* divide by 2^^20 */ |
| 937 | addrBits -= 3; /* 8 bits per bytes */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 938 | |
Jeff Roberson | 156edd4 | 2009-10-26 16:50:09 -0700 | [diff] [blame] | 939 | dinfo->megabytes = 1 << addrBits; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 940 | } |
| 941 | } |
| 942 | } |
| 943 | |
| 944 | /* |
| 945 | * calculate_dimm_size |
| 946 | * |
| 947 | * also will output a DIMM matrix map, if debug is enabled, for viewing |
| 948 | * how the DIMMs are populated |
| 949 | */ |
| 950 | static void calculate_dimm_size(struct i5400_pvt *pvt) |
| 951 | { |
| 952 | struct i5400_dimm_info *dinfo; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 953 | int dimm, max_dimms; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 954 | char *p, *mem_buffer; |
| 955 | int space, n; |
Mauro Carvalho Chehab | 68d086f | 2012-02-12 17:18:06 -0300 | [diff] [blame] | 956 | int channel, branch; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 957 | |
| 958 | /* ================= Generate some debug output ================= */ |
| 959 | space = PAGE_SIZE; |
| 960 | mem_buffer = p = kmalloc(space, GFP_KERNEL); |
| 961 | if (p == NULL) { |
| 962 | i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", |
| 963 | __FILE__, __func__); |
| 964 | return; |
| 965 | } |
| 966 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 967 | /* Scan all the actual DIMMS |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 968 | * and calculate the information for each DIMM |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 969 | * Start with the highest dimm first, to display it first |
| 970 | * and work toward the 0th dimm |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 971 | */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 972 | max_dimms = pvt->maxdimmperch; |
| 973 | for (dimm = max_dimms - 1; dimm >= 0; dimm--) { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 974 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 975 | /* on an odd dimm, first output a 'boundary' marker, |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 976 | * then reset the message buffer */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 977 | if (dimm & 0x1) { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 978 | n = snprintf(p, space, "---------------------------" |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 979 | "-------------------------------"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 980 | p += n; |
| 981 | space -= n; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 982 | edac_dbg(2, "%s\n", mem_buffer); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 983 | p = mem_buffer; |
| 984 | space = PAGE_SIZE; |
| 985 | } |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 986 | n = snprintf(p, space, "dimm %2d ", dimm); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 987 | p += n; |
| 988 | space -= n; |
| 989 | |
| 990 | for (channel = 0; channel < pvt->maxch; channel++) { |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 991 | dinfo = &pvt->dimm_info[dimm][channel]; |
| 992 | handle_channel(pvt, dimm, channel, dinfo); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 993 | n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); |
| 994 | p += n; |
| 995 | space -= n; |
| 996 | } |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 997 | edac_dbg(2, "%s\n", mem_buffer); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 998 | p = mem_buffer; |
| 999 | space = PAGE_SIZE; |
| 1000 | } |
| 1001 | |
| 1002 | /* Output the last bottom 'boundary' marker */ |
| 1003 | n = snprintf(p, space, "---------------------------" |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1004 | "-------------------------------"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1005 | p += n; |
| 1006 | space -= n; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1007 | edac_dbg(2, "%s\n", mem_buffer); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1008 | p = mem_buffer; |
| 1009 | space = PAGE_SIZE; |
| 1010 | |
| 1011 | /* now output the 'channel' labels */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1012 | n = snprintf(p, space, " "); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1013 | p += n; |
| 1014 | space -= n; |
| 1015 | for (channel = 0; channel < pvt->maxch; channel++) { |
| 1016 | n = snprintf(p, space, "channel %d | ", channel); |
| 1017 | p += n; |
| 1018 | space -= n; |
| 1019 | } |
| 1020 | |
Mauro Carvalho Chehab | 68d086f | 2012-02-12 17:18:06 -0300 | [diff] [blame] | 1021 | space -= n; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1022 | edac_dbg(2, "%s\n", mem_buffer); |
Mauro Carvalho Chehab | 68d086f | 2012-02-12 17:18:06 -0300 | [diff] [blame] | 1023 | p = mem_buffer; |
| 1024 | space = PAGE_SIZE; |
| 1025 | |
| 1026 | n = snprintf(p, space, " "); |
| 1027 | p += n; |
| 1028 | for (branch = 0; branch < MAX_BRANCHES; branch++) { |
| 1029 | n = snprintf(p, space, " branch %d | ", branch); |
| 1030 | p += n; |
| 1031 | space -= n; |
| 1032 | } |
| 1033 | |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1034 | /* output the last message and free buffer */ |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1035 | edac_dbg(2, "%s\n", mem_buffer); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1036 | kfree(mem_buffer); |
| 1037 | } |
| 1038 | |
| 1039 | /* |
| 1040 | * i5400_get_mc_regs read in the necessary registers and |
| 1041 | * cache locally |
| 1042 | * |
| 1043 | * Fills in the private data members |
| 1044 | */ |
| 1045 | static void i5400_get_mc_regs(struct mem_ctl_info *mci) |
| 1046 | { |
| 1047 | struct i5400_pvt *pvt; |
| 1048 | u32 actual_tolm; |
| 1049 | u16 limit; |
| 1050 | int slot_row; |
| 1051 | int maxch; |
| 1052 | int maxdimmperch; |
| 1053 | int way0, way1; |
| 1054 | |
| 1055 | pvt = mci->pvt_info; |
| 1056 | |
| 1057 | pci_read_config_dword(pvt->system_address, AMBASE, |
| 1058 | (u32 *) &pvt->ambase); |
| 1059 | pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), |
| 1060 | ((u32 *) &pvt->ambase) + sizeof(u32)); |
| 1061 | |
| 1062 | maxdimmperch = pvt->maxdimmperch; |
| 1063 | maxch = pvt->maxch; |
| 1064 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1065 | edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", |
| 1066 | (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1067 | |
| 1068 | /* Get the Branch Map regs */ |
| 1069 | pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); |
| 1070 | pvt->tolm >>= 12; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1071 | edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n", |
| 1072 | pvt->tolm, pvt->tolm); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1073 | |
| 1074 | actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1075 | edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n", |
| 1076 | actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1077 | |
| 1078 | pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); |
| 1079 | pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); |
| 1080 | |
| 1081 | /* Get the MIR[0-1] regs */ |
| 1082 | limit = (pvt->mir0 >> 4) & 0x0fff; |
| 1083 | way0 = pvt->mir0 & 0x1; |
| 1084 | way1 = pvt->mir0 & 0x2; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1085 | edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", |
| 1086 | limit, way1, way0); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1087 | limit = (pvt->mir1 >> 4) & 0xfff; |
| 1088 | way0 = pvt->mir1 & 0x1; |
| 1089 | way1 = pvt->mir1 & 0x2; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1090 | edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", |
| 1091 | limit, way1, way0); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1092 | |
| 1093 | /* Get the set of MTR[0-3] regs by each branch */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1094 | for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { |
Jeff Roberson | 156edd4 | 2009-10-26 16:50:09 -0700 | [diff] [blame] | 1095 | int where = MTR0 + (slot_row * sizeof(u16)); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1096 | |
| 1097 | /* Branch 0 set of MTR registers */ |
| 1098 | pci_read_config_word(pvt->branch_0, where, |
| 1099 | &pvt->b0_mtr[slot_row]); |
| 1100 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1101 | edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n", |
| 1102 | slot_row, where, pvt->b0_mtr[slot_row]); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1103 | |
| 1104 | if (pvt->maxch < CHANNELS_PER_BRANCH) { |
| 1105 | pvt->b1_mtr[slot_row] = 0; |
| 1106 | continue; |
| 1107 | } |
| 1108 | |
| 1109 | /* Branch 1 set of MTR registers */ |
| 1110 | pci_read_config_word(pvt->branch_1, where, |
| 1111 | &pvt->b1_mtr[slot_row]); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1112 | edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n", |
| 1113 | slot_row, where, pvt->b1_mtr[slot_row]); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1114 | } |
| 1115 | |
| 1116 | /* Read and dump branch 0's MTRs */ |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1117 | edac_dbg(2, "Memory Technology Registers:\n"); |
| 1118 | edac_dbg(2, " Branch 0:\n"); |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1119 | for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1120 | decode_mtr(slot_row, pvt->b0_mtr[slot_row]); |
| 1121 | |
| 1122 | pci_read_config_word(pvt->branch_0, AMBPRESENT_0, |
| 1123 | &pvt->b0_ambpresent0); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1124 | edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1125 | pci_read_config_word(pvt->branch_0, AMBPRESENT_1, |
| 1126 | &pvt->b0_ambpresent1); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1127 | edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1128 | |
| 1129 | /* Only if we have 2 branchs (4 channels) */ |
| 1130 | if (pvt->maxch < CHANNELS_PER_BRANCH) { |
| 1131 | pvt->b1_ambpresent0 = 0; |
| 1132 | pvt->b1_ambpresent1 = 0; |
| 1133 | } else { |
| 1134 | /* Read and dump branch 1's MTRs */ |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1135 | edac_dbg(2, " Branch 1:\n"); |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1136 | for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1137 | decode_mtr(slot_row, pvt->b1_mtr[slot_row]); |
| 1138 | |
| 1139 | pci_read_config_word(pvt->branch_1, AMBPRESENT_0, |
| 1140 | &pvt->b1_ambpresent0); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1141 | edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", |
| 1142 | pvt->b1_ambpresent0); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1143 | pci_read_config_word(pvt->branch_1, AMBPRESENT_1, |
| 1144 | &pvt->b1_ambpresent1); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1145 | edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", |
| 1146 | pvt->b1_ambpresent1); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | /* Go and determine the size of each DIMM and place in an |
| 1150 | * orderly matrix */ |
| 1151 | calculate_dimm_size(pvt); |
| 1152 | } |
| 1153 | |
| 1154 | /* |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1155 | * i5400_init_dimms Initialize the 'dimms' table within |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1156 | * the mci control structure with the |
| 1157 | * addressing of memory. |
| 1158 | * |
| 1159 | * return: |
| 1160 | * 0 success |
| 1161 | * 1 no actual memory found on this MC |
| 1162 | */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1163 | static int i5400_init_dimms(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1164 | { |
| 1165 | struct i5400_pvt *pvt; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1166 | struct dimm_info *dimm; |
| 1167 | int ndimms, channel_count; |
| 1168 | int max_dimms; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1169 | int mtr; |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 1170 | int size_mb; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1171 | int channel, slot; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1172 | |
| 1173 | pvt = mci->pvt_info; |
| 1174 | |
| 1175 | channel_count = pvt->maxch; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1176 | max_dimms = pvt->maxdimmperch; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1177 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1178 | ndimms = 0; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1179 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1180 | /* |
| 1181 | * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 |
| 1182 | * layers here. |
| 1183 | */ |
| 1184 | for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; |
| 1185 | channel++) { |
| 1186 | for (slot = 0; slot < mci->layers[2].size; slot++) { |
| 1187 | mtr = determine_mtr(pvt, slot, channel); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1188 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1189 | /* if no DIMMS on this slot, continue */ |
| 1190 | if (!MTR_DIMMS_PRESENT(mtr)) |
| 1191 | continue; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1192 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1193 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
| 1194 | channel / 2, channel % 2, slot); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1195 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1196 | size_mb = pvt->dimm_info[slot][channel].megabytes; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1197 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1198 | edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n", |
| 1199 | channel / 2, channel % 2, slot, |
| 1200 | size_mb / 1000, size_mb % 1000); |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1201 | |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 1202 | dimm->nr_pages = size_mb << 8; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 1203 | dimm->grain = 8; |
| 1204 | dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1205 | dimm->mtype = MEM_FB_DDR2; |
| 1206 | /* |
| 1207 | * The eccc mechanism is SDDC (aka SECC), with |
| 1208 | * is similar to Chipkill. |
| 1209 | */ |
| 1210 | dimm->edac_mode = MTR_DRAM_WIDTH(mtr) ? |
| 1211 | EDAC_S8ECD8ED : EDAC_S4ECD4ED; |
| 1212 | ndimms++; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 1213 | } |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1214 | } |
| 1215 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1216 | /* |
| 1217 | * When just one memory is provided, it should be at location (0,0,0). |
| 1218 | * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. |
| 1219 | */ |
| 1220 | if (ndimms == 1) |
Mauro Carvalho Chehab | de3910eb | 2012-04-24 15:05:43 -0300 | [diff] [blame] | 1221 | mci->dimms[0]->edac_mode = EDAC_SECDED; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1222 | |
| 1223 | return (ndimms == 0); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1224 | } |
| 1225 | |
| 1226 | /* |
| 1227 | * i5400_enable_error_reporting |
| 1228 | * Turn on the memory reporting features of the hardware |
| 1229 | */ |
| 1230 | static void i5400_enable_error_reporting(struct mem_ctl_info *mci) |
| 1231 | { |
| 1232 | struct i5400_pvt *pvt; |
| 1233 | u32 fbd_error_mask; |
| 1234 | |
| 1235 | pvt = mci->pvt_info; |
| 1236 | |
| 1237 | /* Read the FBD Error Mask Register */ |
| 1238 | pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, |
| 1239 | &fbd_error_mask); |
| 1240 | |
| 1241 | /* Enable with a '0' */ |
| 1242 | fbd_error_mask &= ~(ENABLE_EMASK_ALL); |
| 1243 | |
| 1244 | pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, |
| 1245 | fbd_error_mask); |
| 1246 | } |
| 1247 | |
| 1248 | /* |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1249 | * i5400_probe1 Probe for ONE instance of device to see if it is |
| 1250 | * present. |
| 1251 | * return: |
| 1252 | * 0 for FOUND a device |
| 1253 | * < 0 for error code |
| 1254 | */ |
| 1255 | static int i5400_probe1(struct pci_dev *pdev, int dev_idx) |
| 1256 | { |
| 1257 | struct mem_ctl_info *mci; |
| 1258 | struct i5400_pvt *pvt; |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1259 | struct edac_mc_layer layers[3]; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1260 | |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1261 | if (dev_idx >= ARRAY_SIZE(i5400_devs)) |
| 1262 | return -EINVAL; |
| 1263 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1264 | edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n", |
| 1265 | pdev->bus->number, |
| 1266 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1267 | |
| 1268 | /* We only are looking for func 0 of the set */ |
| 1269 | if (PCI_FUNC(pdev->devfn) != 0) |
| 1270 | return -ENODEV; |
| 1271 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1272 | /* |
| 1273 | * allocate a new MC control structure |
| 1274 | * |
| 1275 | * This drivers uses the DIMM slot as "csrow" and the rest as "channel". |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1276 | */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1277 | layers[0].type = EDAC_MC_LAYER_BRANCH; |
| 1278 | layers[0].size = MAX_BRANCHES; |
| 1279 | layers[0].is_virt_csrow = false; |
| 1280 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
| 1281 | layers[1].size = CHANNELS_PER_BRANCH; |
| 1282 | layers[1].is_virt_csrow = false; |
| 1283 | layers[2].type = EDAC_MC_LAYER_SLOT; |
| 1284 | layers[2].size = DIMMS_PER_CHANNEL; |
| 1285 | layers[2].is_virt_csrow = true; |
Mauro Carvalho Chehab | ca0907b | 2012-05-02 14:37:00 -0300 | [diff] [blame] | 1286 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1287 | if (mci == NULL) |
| 1288 | return -ENOMEM; |
| 1289 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1290 | edac_dbg(0, "MC: mci = %p\n", mci); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1291 | |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 1292 | mci->pdev = &pdev->dev; /* record ptr to the generic device */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1293 | |
| 1294 | pvt = mci->pvt_info; |
| 1295 | pvt->system_address = pdev; /* Record this device in our private */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1296 | pvt->maxch = MAX_CHANNELS; |
| 1297 | pvt->maxdimmperch = DIMMS_PER_CHANNEL; |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1298 | |
| 1299 | /* 'get' the pci devices we want to reserve for our use */ |
| 1300 | if (i5400_get_devices(mci, dev_idx)) |
| 1301 | goto fail0; |
| 1302 | |
| 1303 | /* Time to get serious */ |
| 1304 | i5400_get_mc_regs(mci); /* retrieve the hardware registers */ |
| 1305 | |
| 1306 | mci->mc_idx = 0; |
| 1307 | mci->mtype_cap = MEM_FLAG_FB_DDR2; |
| 1308 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 1309 | mci->edac_cap = EDAC_FLAG_NONE; |
| 1310 | mci->mod_name = "i5400_edac.c"; |
| 1311 | mci->mod_ver = I5400_REVISION; |
| 1312 | mci->ctl_name = i5400_devs[dev_idx].ctl_name; |
| 1313 | mci->dev_name = pci_name(pdev); |
| 1314 | mci->ctl_page_to_phys = NULL; |
| 1315 | |
| 1316 | /* Set the function pointer to an actual operation function */ |
| 1317 | mci->edac_check = i5400_check_error; |
| 1318 | |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1319 | /* initialize the MC control structure 'dimms' table |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1320 | * with the mapping and control information */ |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1321 | if (i5400_init_dimms(mci)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1322 | edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n"); |
Mauro Carvalho Chehab | 296da59 | 2012-04-16 15:09:58 -0300 | [diff] [blame] | 1323 | mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1324 | } else { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1325 | edac_dbg(1, "MC: Enable error reporting now\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1326 | i5400_enable_error_reporting(mci); |
| 1327 | } |
| 1328 | |
| 1329 | /* add this new MC control structure to EDAC's list of MCs */ |
| 1330 | if (edac_mc_add_mc(mci)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1331 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1332 | /* FIXME: perhaps some code should go here that disables error |
| 1333 | * reporting if we just enabled it |
| 1334 | */ |
| 1335 | goto fail1; |
| 1336 | } |
| 1337 | |
| 1338 | i5400_clear_error(mci); |
| 1339 | |
| 1340 | /* allocating generic PCI control info */ |
| 1341 | i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
| 1342 | if (!i5400_pci) { |
| 1343 | printk(KERN_WARNING |
| 1344 | "%s(): Unable to create PCI control\n", |
| 1345 | __func__); |
| 1346 | printk(KERN_WARNING |
| 1347 | "%s(): PCI error report via EDAC not setup\n", |
| 1348 | __func__); |
| 1349 | } |
| 1350 | |
| 1351 | return 0; |
| 1352 | |
| 1353 | /* Error exit unwinding stack */ |
| 1354 | fail1: |
| 1355 | |
| 1356 | i5400_put_devices(mci); |
| 1357 | |
| 1358 | fail0: |
| 1359 | edac_mc_free(mci); |
| 1360 | return -ENODEV; |
| 1361 | } |
| 1362 | |
| 1363 | /* |
| 1364 | * i5400_init_one constructor for one instance of device |
| 1365 | * |
| 1366 | * returns: |
| 1367 | * negative on error |
| 1368 | * count (>= 0) |
| 1369 | */ |
| 1370 | static int __devinit i5400_init_one(struct pci_dev *pdev, |
| 1371 | const struct pci_device_id *id) |
| 1372 | { |
| 1373 | int rc; |
| 1374 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1375 | edac_dbg(0, "MC:\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1376 | |
| 1377 | /* wake up device */ |
| 1378 | rc = pci_enable_device(pdev); |
Kulikov Vasiliy | b425d5c | 2010-08-10 18:03:20 -0700 | [diff] [blame] | 1379 | if (rc) |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1380 | return rc; |
| 1381 | |
| 1382 | /* now probe and enable the device */ |
| 1383 | return i5400_probe1(pdev, id->driver_data); |
| 1384 | } |
| 1385 | |
| 1386 | /* |
| 1387 | * i5400_remove_one destructor for one instance of device |
| 1388 | * |
| 1389 | */ |
| 1390 | static void __devexit i5400_remove_one(struct pci_dev *pdev) |
| 1391 | { |
| 1392 | struct mem_ctl_info *mci; |
| 1393 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1394 | edac_dbg(0, "\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1395 | |
| 1396 | if (i5400_pci) |
| 1397 | edac_pci_release_generic_ctl(i5400_pci); |
| 1398 | |
| 1399 | mci = edac_mc_del_mc(&pdev->dev); |
| 1400 | if (!mci) |
| 1401 | return; |
| 1402 | |
| 1403 | /* retrieve references to resources, and free those resources */ |
| 1404 | i5400_put_devices(mci); |
| 1405 | |
| 1406 | edac_mc_free(mci); |
| 1407 | } |
| 1408 | |
| 1409 | /* |
| 1410 | * pci_device_id table for which devices we are looking for |
| 1411 | * |
| 1412 | * The "E500P" device is the first device supported. |
| 1413 | */ |
Lionel Debroux | 36c46f3 | 2012-02-27 07:41:47 +0100 | [diff] [blame] | 1414 | static DEFINE_PCI_DEVICE_TABLE(i5400_pci_tbl) = { |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1415 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)}, |
| 1416 | {0,} /* 0 terminated list. */ |
| 1417 | }; |
| 1418 | |
| 1419 | MODULE_DEVICE_TABLE(pci, i5400_pci_tbl); |
| 1420 | |
| 1421 | /* |
| 1422 | * i5400_driver pci_driver structure for this module |
| 1423 | * |
| 1424 | */ |
| 1425 | static struct pci_driver i5400_driver = { |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1426 | .name = "i5400_edac", |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1427 | .probe = i5400_init_one, |
| 1428 | .remove = __devexit_p(i5400_remove_one), |
| 1429 | .id_table = i5400_pci_tbl, |
| 1430 | }; |
| 1431 | |
| 1432 | /* |
| 1433 | * i5400_init Module entry function |
| 1434 | * Try to initialize this module for its devices |
| 1435 | */ |
| 1436 | static int __init i5400_init(void) |
| 1437 | { |
| 1438 | int pci_rc; |
| 1439 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1440 | edac_dbg(2, "MC:\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1441 | |
| 1442 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 1443 | opstate_init(); |
| 1444 | |
| 1445 | pci_rc = pci_register_driver(&i5400_driver); |
| 1446 | |
| 1447 | return (pci_rc < 0) ? pci_rc : 0; |
| 1448 | } |
| 1449 | |
| 1450 | /* |
| 1451 | * i5400_exit() Module exit function |
| 1452 | * Unregister the driver |
| 1453 | */ |
| 1454 | static void __exit i5400_exit(void) |
| 1455 | { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame^] | 1456 | edac_dbg(2, "MC:\n"); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1457 | pci_unregister_driver(&i5400_driver); |
| 1458 | } |
| 1459 | |
| 1460 | module_init(i5400_init); |
| 1461 | module_exit(i5400_exit); |
| 1462 | |
| 1463 | MODULE_LICENSE("GPL"); |
Mauro Carvalho Chehab | 8375d49 | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1464 | MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>"); |
| 1465 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); |
| 1466 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
| 1467 | MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " |
| 1468 | I5400_REVISION); |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 1469 | |
| 1470 | module_param(edac_op_state, int, 0444); |
| 1471 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |