Tony Truong | 349ee49 | 2014-10-01 17:35:56 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * MSM PCIe controller driver. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/bitops.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/debugfs.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/iopoll.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/of_pci.h> |
| 26 | #include <linux/pci.h> |
| 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/regulator/consumer.h> |
| 29 | #include <linux/regulator/rpm-smd-regulator.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/types.h> |
| 32 | #include <linux/of_gpio.h> |
| 33 | #include <linux/clk/msm-clk.h> |
| 34 | #include <linux/reset.h> |
| 35 | #include <linux/msm-bus.h> |
| 36 | #include <linux/msm-bus-board.h> |
| 37 | #include <linux/debugfs.h> |
| 38 | #include <linux/uaccess.h> |
| 39 | #include <linux/io.h> |
| 40 | #include <linux/msi.h> |
| 41 | #include <linux/interrupt.h> |
| 42 | #include <linux/irq.h> |
| 43 | #include <linux/irqdomain.h> |
| 44 | #include <linux/pm_wakeup.h> |
| 45 | #include <linux/compiler.h> |
| 46 | #include <soc/qcom/scm.h> |
| 47 | #include <linux/ipc_logging.h> |
| 48 | #include <linux/msm_pcie.h> |
| 49 | |
| 50 | #ifdef CONFIG_ARCH_MDMCALIFORNIUM |
| 51 | #define PCIE_VENDOR_ID_RCP 0x17cb |
| 52 | #define PCIE_DEVICE_ID_RCP 0x0302 |
| 53 | |
| 54 | #define PCIE20_L1SUB_CONTROL1 0x158 |
| 55 | #define PCIE20_PARF_DBI_BASE_ADDR 0x350 |
| 56 | #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358 |
| 57 | |
| 58 | #define TX_BASE 0x200 |
| 59 | #define RX_BASE 0x400 |
| 60 | #define PCS_BASE 0x800 |
| 61 | #define PCS_MISC_BASE 0x600 |
| 62 | |
| 63 | #elif defined(CONFIG_ARCH_MSM8998) |
| 64 | #define PCIE_VENDOR_ID_RCP 0x17cb |
| 65 | #define PCIE_DEVICE_ID_RCP 0x0105 |
| 66 | |
| 67 | #define PCIE20_L1SUB_CONTROL1 0x1E4 |
| 68 | #define PCIE20_PARF_DBI_BASE_ADDR 0x350 |
| 69 | #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358 |
| 70 | |
| 71 | #define TX_BASE 0 |
| 72 | #define RX_BASE 0 |
| 73 | #define PCS_BASE 0x800 |
| 74 | #define PCS_MISC_BASE 0 |
| 75 | |
| 76 | #else |
| 77 | #define PCIE_VENDOR_ID_RCP 0x17cb |
| 78 | #define PCIE_DEVICE_ID_RCP 0x0104 |
| 79 | |
| 80 | #define PCIE20_L1SUB_CONTROL1 0x158 |
| 81 | #define PCIE20_PARF_DBI_BASE_ADDR 0x168 |
| 82 | #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C |
| 83 | |
| 84 | #define TX_BASE 0x1000 |
| 85 | #define RX_BASE 0x1200 |
| 86 | #define PCS_BASE 0x1400 |
| 87 | #define PCS_MISC_BASE 0 |
| 88 | #endif |
| 89 | |
| 90 | #define TX(n, m) (TX_BASE + n * m * 0x1000) |
| 91 | #define RX(n, m) (RX_BASE + n * m * 0x1000) |
| 92 | #define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000) |
| 93 | #define PCS_MISC_PORT(n, m) (PCS_MISC_BASE + n * m * 0x1000) |
| 94 | |
| 95 | #define QSERDES_COM_BG_TIMER 0x00C |
| 96 | #define QSERDES_COM_SSC_EN_CENTER 0x010 |
| 97 | #define QSERDES_COM_SSC_ADJ_PER1 0x014 |
| 98 | #define QSERDES_COM_SSC_ADJ_PER2 0x018 |
| 99 | #define QSERDES_COM_SSC_PER1 0x01C |
| 100 | #define QSERDES_COM_SSC_PER2 0x020 |
| 101 | #define QSERDES_COM_SSC_STEP_SIZE1 0x024 |
| 102 | #define QSERDES_COM_SSC_STEP_SIZE2 0x028 |
| 103 | #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 |
| 104 | #define QSERDES_COM_CLK_ENABLE1 0x038 |
| 105 | #define QSERDES_COM_SYS_CLK_CTRL 0x03C |
| 106 | #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 |
| 107 | #define QSERDES_COM_PLL_IVCO 0x048 |
| 108 | #define QSERDES_COM_LOCK_CMP1_MODE0 0x04C |
| 109 | #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 |
| 110 | #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 |
| 111 | #define QSERDES_COM_BG_TRIM 0x070 |
| 112 | #define QSERDES_COM_CLK_EP_DIV 0x074 |
| 113 | #define QSERDES_COM_CP_CTRL_MODE0 0x078 |
| 114 | #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 |
| 115 | #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 |
| 116 | #define QSERDES_COM_SYSCLK_EN_SEL 0x0AC |
| 117 | #define QSERDES_COM_RESETSM_CNTRL 0x0B4 |
| 118 | #define QSERDES_COM_RESTRIM_CTRL 0x0BC |
| 119 | #define QSERDES_COM_RESCODE_DIV_NUM 0x0C4 |
| 120 | #define QSERDES_COM_LOCK_CMP_EN 0x0C8 |
| 121 | #define QSERDES_COM_DEC_START_MODE0 0x0D0 |
| 122 | #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0DC |
| 123 | #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0E0 |
| 124 | #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0E4 |
| 125 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 |
| 126 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10C |
| 127 | #define QSERDES_COM_VCO_TUNE_CTRL 0x124 |
| 128 | #define QSERDES_COM_VCO_TUNE_MAP 0x128 |
| 129 | #define QSERDES_COM_VCO_TUNE1_MODE0 0x12C |
| 130 | #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 |
| 131 | #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 |
| 132 | #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 |
| 133 | #define QSERDES_COM_BG_CTRL 0x170 |
| 134 | #define QSERDES_COM_CLK_SELECT 0x174 |
| 135 | #define QSERDES_COM_HSCLK_SEL 0x178 |
| 136 | #define QSERDES_COM_CORECLK_DIV 0x184 |
| 137 | #define QSERDES_COM_CORE_CLK_EN 0x18C |
| 138 | #define QSERDES_COM_C_READY_STATUS 0x190 |
| 139 | #define QSERDES_COM_CMN_CONFIG 0x194 |
| 140 | #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19C |
| 141 | #define QSERDES_COM_DEBUG_BUS0 0x1A0 |
| 142 | #define QSERDES_COM_DEBUG_BUS1 0x1A4 |
| 143 | #define QSERDES_COM_DEBUG_BUS2 0x1A8 |
| 144 | #define QSERDES_COM_DEBUG_BUS3 0x1AC |
| 145 | #define QSERDES_COM_DEBUG_BUS_SEL 0x1B0 |
| 146 | |
| 147 | #define QSERDES_TX_N_RES_CODE_LANE_OFFSET(n, m) (TX(n, m) + 0x4C) |
| 148 | #define QSERDES_TX_N_DEBUG_BUS_SEL(n, m) (TX(n, m) + 0x64) |
| 149 | #define QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(n, m) (TX(n, m) + 0x68) |
| 150 | #define QSERDES_TX_N_LANE_MODE(n, m) (TX(n, m) + 0x94) |
| 151 | #define QSERDES_TX_N_RCV_DETECT_LVL_2(n, m) (TX(n, m) + 0xAC) |
| 152 | |
| 153 | #define QSERDES_RX_N_UCDR_SO_GAIN_HALF(n, m) (RX(n, m) + 0x010) |
| 154 | #define QSERDES_RX_N_UCDR_SO_GAIN(n, m) (RX(n, m) + 0x01C) |
| 155 | #define QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(n, m) (RX(n, m) + 0x048) |
| 156 | #define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(n, m) (RX(n, m) + 0x0D8) |
| 157 | #define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(n, m) (RX(n, m) + 0x0DC) |
| 158 | #define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(n, m) (RX(n, m) + 0x0E0) |
| 159 | #define QSERDES_RX_N_SIGDET_ENABLES(n, m) (RX(n, m) + 0x110) |
| 160 | #define QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(n, m) (RX(n, m) + 0x11C) |
| 161 | #define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118) |
| 162 | #define QSERDES_RX_N_RX_BAND(n, m) (RX(n, m) + 0x120) |
| 163 | |
| 164 | #define PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x00) |
| 165 | #define PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x04) |
| 166 | #define PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x08) |
| 167 | #define PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x0C) |
| 168 | #define PCIE_MISC_N_DEBUG_BUS_0_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x14) |
| 169 | #define PCIE_MISC_N_DEBUG_BUS_1_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x18) |
| 170 | #define PCIE_MISC_N_DEBUG_BUS_2_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x1C) |
| 171 | #define PCIE_MISC_N_DEBUG_BUS_3_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x20) |
| 172 | |
| 173 | #define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00) |
| 174 | #define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04) |
| 175 | #define PCIE_N_START_CONTROL(n, m) (PCS_PORT(n, m) + 0x08) |
| 176 | #define PCIE_N_TXDEEMPH_M6DB_V0(n, m) (PCS_PORT(n, m) + 0x24) |
| 177 | #define PCIE_N_TXDEEMPH_M3P5DB_V0(n, m) (PCS_PORT(n, m) + 0x28) |
| 178 | #define PCIE_N_ENDPOINT_REFCLK_DRIVE(n, m) (PCS_PORT(n, m) + 0x54) |
| 179 | #define PCIE_N_RX_IDLE_DTCT_CNTRL(n, m) (PCS_PORT(n, m) + 0x58) |
| 180 | #define PCIE_N_POWER_STATE_CONFIG1(n, m) (PCS_PORT(n, m) + 0x60) |
| 181 | #define PCIE_N_POWER_STATE_CONFIG4(n, m) (PCS_PORT(n, m) + 0x6C) |
| 182 | #define PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(n, m) (PCS_PORT(n, m) + 0xA0) |
| 183 | #define PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(n, m) (PCS_PORT(n, m) + 0xA4) |
| 184 | #define PCIE_N_PLL_LOCK_CHK_DLY_TIME(n, m) (PCS_PORT(n, m) + 0xA8) |
| 185 | #define PCIE_N_TEST_CONTROL4(n, m) (PCS_PORT(n, m) + 0x11C) |
| 186 | #define PCIE_N_TEST_CONTROL5(n, m) (PCS_PORT(n, m) + 0x120) |
| 187 | #define PCIE_N_TEST_CONTROL6(n, m) (PCS_PORT(n, m) + 0x124) |
| 188 | #define PCIE_N_TEST_CONTROL7(n, m) (PCS_PORT(n, m) + 0x128) |
| 189 | #define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174) |
| 190 | #define PCIE_N_DEBUG_BUS_0_STATUS(n, m) (PCS_PORT(n, m) + 0x198) |
| 191 | #define PCIE_N_DEBUG_BUS_1_STATUS(n, m) (PCS_PORT(n, m) + 0x19C) |
| 192 | #define PCIE_N_DEBUG_BUS_2_STATUS(n, m) (PCS_PORT(n, m) + 0x1A0) |
| 193 | #define PCIE_N_DEBUG_BUS_3_STATUS(n, m) (PCS_PORT(n, m) + 0x1A4) |
| 194 | #define PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK_MSB(n, m) (PCS_PORT(n, m) + 0x1A8) |
| 195 | #define PCIE_N_OSC_DTCT_ACTIONS(n, m) (PCS_PORT(n, m) + 0x1AC) |
| 196 | #define PCIE_N_SIGDET_CNTRL(n, m) (PCS_PORT(n, m) + 0x1B0) |
| 197 | #define PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB(n, m) (PCS_PORT(n, m) + 0x1DC) |
| 198 | #define PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB(n, m) (PCS_PORT(n, m) + 0x1E0) |
| 199 | |
| 200 | #define PCIE_COM_SW_RESET 0x400 |
| 201 | #define PCIE_COM_POWER_DOWN_CONTROL 0x404 |
| 202 | #define PCIE_COM_START_CONTROL 0x408 |
| 203 | #define PCIE_COM_DEBUG_BUS_BYTE0_INDEX 0x438 |
| 204 | #define PCIE_COM_DEBUG_BUS_BYTE1_INDEX 0x43C |
| 205 | #define PCIE_COM_DEBUG_BUS_BYTE2_INDEX 0x440 |
| 206 | #define PCIE_COM_DEBUG_BUS_BYTE3_INDEX 0x444 |
| 207 | #define PCIE_COM_PCS_READY_STATUS 0x448 |
| 208 | #define PCIE_COM_DEBUG_BUS_0_STATUS 0x45C |
| 209 | #define PCIE_COM_DEBUG_BUS_1_STATUS 0x460 |
| 210 | #define PCIE_COM_DEBUG_BUS_2_STATUS 0x464 |
| 211 | #define PCIE_COM_DEBUG_BUS_3_STATUS 0x468 |
| 212 | |
| 213 | #define PCIE20_PARF_SYS_CTRL 0x00 |
| 214 | #define PCIE20_PARF_PM_STTS 0x24 |
| 215 | #define PCIE20_PARF_PCS_DEEMPH 0x34 |
| 216 | #define PCIE20_PARF_PCS_SWING 0x38 |
| 217 | #define PCIE20_PARF_PHY_CTRL 0x40 |
| 218 | #define PCIE20_PARF_PHY_REFCLK 0x4C |
| 219 | #define PCIE20_PARF_CONFIG_BITS 0x50 |
| 220 | #define PCIE20_PARF_TEST_BUS 0xE4 |
| 221 | #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 |
| 222 | #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8 |
| 223 | #define PCIE20_PARF_LTSSM 0x1B0 |
| 224 | #define PCIE20_PARF_INT_ALL_STATUS 0x224 |
| 225 | #define PCIE20_PARF_INT_ALL_CLEAR 0x228 |
| 226 | #define PCIE20_PARF_INT_ALL_MASK 0x22C |
| 227 | #define PCIE20_PARF_SID_OFFSET 0x234 |
| 228 | #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C |
| 229 | #define PCIE20_PARF_BDF_TRANSLATE_N 0x250 |
| 230 | |
| 231 | #define PCIE20_ELBI_VERSION 0x00 |
| 232 | #define PCIE20_ELBI_SYS_CTRL 0x04 |
| 233 | #define PCIE20_ELBI_SYS_STTS 0x08 |
| 234 | |
| 235 | #define PCIE20_CAP 0x70 |
| 236 | #define PCIE20_CAP_DEVCTRLSTATUS (PCIE20_CAP + 0x08) |
| 237 | #define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) |
| 238 | |
| 239 | #define PCIE20_COMMAND_STATUS 0x04 |
| 240 | #define PCIE20_HEADER_TYPE 0x0C |
| 241 | #define PCIE20_BUSNUMBERS 0x18 |
| 242 | #define PCIE20_MEMORY_BASE_LIMIT 0x20 |
| 243 | #define PCIE20_BRIDGE_CTRL 0x3C |
| 244 | #define PCIE20_DEVICE_CONTROL_STATUS 0x78 |
| 245 | #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 |
| 246 | |
| 247 | #define PCIE20_AUX_CLK_FREQ_REG 0xB40 |
| 248 | #define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C |
| 249 | #define PCIE20_ACK_N_FTS 0xff00 |
| 250 | |
| 251 | #define PCIE20_PLR_IATU_VIEWPORT 0x900 |
| 252 | #define PCIE20_PLR_IATU_CTRL1 0x904 |
| 253 | #define PCIE20_PLR_IATU_CTRL2 0x908 |
| 254 | #define PCIE20_PLR_IATU_LBAR 0x90C |
| 255 | #define PCIE20_PLR_IATU_UBAR 0x910 |
| 256 | #define PCIE20_PLR_IATU_LAR 0x914 |
| 257 | #define PCIE20_PLR_IATU_LTAR 0x918 |
| 258 | #define PCIE20_PLR_IATU_UTAR 0x91c |
| 259 | |
| 260 | #define PCIE20_CTRL1_TYPE_CFG0 0x04 |
| 261 | #define PCIE20_CTRL1_TYPE_CFG1 0x05 |
| 262 | |
| 263 | #define PCIE20_CAP_ID 0x10 |
| 264 | #define L1SUB_CAP_ID 0x1E |
| 265 | |
| 266 | #define PCIE_CAP_PTR_OFFSET 0x34 |
| 267 | #define PCIE_EXT_CAP_OFFSET 0x100 |
| 268 | |
| 269 | #define PCIE20_AER_UNCORR_ERR_STATUS_REG 0x104 |
| 270 | #define PCIE20_AER_CORR_ERR_STATUS_REG 0x110 |
| 271 | #define PCIE20_AER_ROOT_ERR_STATUS_REG 0x130 |
| 272 | #define PCIE20_AER_ERR_SRC_ID_REG 0x134 |
| 273 | |
| 274 | #define RD 0 |
| 275 | #define WR 1 |
| 276 | #define MSM_PCIE_ERROR -1 |
| 277 | |
| 278 | #define PERST_PROPAGATION_DELAY_US_MIN 1000 |
| 279 | #define PERST_PROPAGATION_DELAY_US_MAX 1005 |
| 280 | #define REFCLK_STABILIZATION_DELAY_US_MIN 1000 |
| 281 | #define REFCLK_STABILIZATION_DELAY_US_MAX 1005 |
| 282 | #define LINK_UP_TIMEOUT_US_MIN 5000 |
| 283 | #define LINK_UP_TIMEOUT_US_MAX 5100 |
| 284 | #define LINK_UP_CHECK_MAX_COUNT 20 |
| 285 | #define PHY_STABILIZATION_DELAY_US_MIN 995 |
| 286 | #define PHY_STABILIZATION_DELAY_US_MAX 1005 |
| 287 | #define POWER_DOWN_DELAY_US_MIN 10 |
| 288 | #define POWER_DOWN_DELAY_US_MAX 11 |
| 289 | #define LINKDOWN_INIT_WAITING_US_MIN 995 |
| 290 | #define LINKDOWN_INIT_WAITING_US_MAX 1005 |
| 291 | #define LINKDOWN_WAITING_US_MIN 4900 |
| 292 | #define LINKDOWN_WAITING_US_MAX 5100 |
| 293 | #define LINKDOWN_WAITING_COUNT 200 |
| 294 | |
| 295 | #define PHY_READY_TIMEOUT_COUNT 10 |
| 296 | #define XMLH_LINK_UP 0x400 |
| 297 | #define MAX_LINK_RETRIES 5 |
| 298 | #define MAX_BUS_NUM 3 |
| 299 | #define MAX_PROP_SIZE 32 |
| 300 | #define MAX_RC_NAME_LEN 15 |
| 301 | #define MSM_PCIE_MAX_VREG 4 |
| 302 | #define MSM_PCIE_MAX_CLK 9 |
| 303 | #define MSM_PCIE_MAX_PIPE_CLK 1 |
| 304 | #define MAX_RC_NUM 3 |
| 305 | #define MAX_DEVICE_NUM 20 |
| 306 | #define MAX_SHORT_BDF_NUM 16 |
| 307 | #define PCIE_TLP_RD_SIZE 0x5 |
| 308 | #define PCIE_MSI_NR_IRQS 256 |
| 309 | #define MSM_PCIE_MAX_MSI 32 |
| 310 | #define MAX_MSG_LEN 80 |
| 311 | #define PCIE_LOG_PAGES (50) |
| 312 | #define PCIE_CONF_SPACE_DW 1024 |
| 313 | #define PCIE_CLEAR 0xDEADBEEF |
| 314 | #define PCIE_LINK_DOWN 0xFFFFFFFF |
| 315 | |
| 316 | #define MSM_PCIE_MAX_RESET 4 |
| 317 | #define MSM_PCIE_MAX_PIPE_RESET 1 |
| 318 | |
| 319 | #define MSM_PCIE_MSI_PHY 0xa0000000 |
| 320 | #define PCIE20_MSI_CTRL_ADDR (0x820) |
| 321 | #define PCIE20_MSI_CTRL_UPPER_ADDR (0x824) |
| 322 | #define PCIE20_MSI_CTRL_INTR_EN (0x828) |
| 323 | #define PCIE20_MSI_CTRL_INTR_MASK (0x82C) |
| 324 | #define PCIE20_MSI_CTRL_INTR_STATUS (0x830) |
| 325 | #define PCIE20_MSI_CTRL_MAX 8 |
| 326 | |
| 327 | /* PM control options */ |
| 328 | #define PM_IRQ 0x1 |
| 329 | #define PM_CLK 0x2 |
| 330 | #define PM_GPIO 0x4 |
| 331 | #define PM_VREG 0x8 |
| 332 | #define PM_PIPE_CLK 0x10 |
| 333 | #define PM_ALL (PM_IRQ | PM_CLK | PM_GPIO | PM_VREG | PM_PIPE_CLK) |
| 334 | |
| 335 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
| 336 | #define PCIE_UPPER_ADDR(addr) ((u32)((addr) >> 32)) |
| 337 | #else |
| 338 | #define PCIE_UPPER_ADDR(addr) (0x0) |
| 339 | #endif |
| 340 | #define PCIE_LOWER_ADDR(addr) ((u32)((addr) & 0xffffffff)) |
| 341 | |
| 342 | /* Config Space Offsets */ |
| 343 | #define BDF_OFFSET(bus, devfn) \ |
| 344 | ((bus << 24) | (devfn << 16)) |
| 345 | |
| 346 | #define PCIE_GEN_DBG(x...) do { \ |
| 347 | if (msm_pcie_debug_mask) \ |
| 348 | pr_alert(x); \ |
| 349 | } while (0) |
| 350 | |
| 351 | #define PCIE_DBG(dev, fmt, arg...) do { \ |
| 352 | if ((dev) && (dev)->ipc_log_long) \ |
| 353 | ipc_log_string((dev)->ipc_log_long, \ |
| 354 | "DBG1:%s: " fmt, __func__, arg); \ |
| 355 | if ((dev) && (dev)->ipc_log) \ |
| 356 | ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \ |
| 357 | if (msm_pcie_debug_mask) \ |
| 358 | pr_alert("%s: " fmt, __func__, arg); \ |
| 359 | } while (0) |
| 360 | |
| 361 | #define PCIE_DBG2(dev, fmt, arg...) do { \ |
| 362 | if ((dev) && (dev)->ipc_log) \ |
| 363 | ipc_log_string((dev)->ipc_log, "DBG2:%s: " fmt, __func__, arg);\ |
| 364 | if (msm_pcie_debug_mask) \ |
| 365 | pr_alert("%s: " fmt, __func__, arg); \ |
| 366 | } while (0) |
| 367 | |
| 368 | #define PCIE_DBG3(dev, fmt, arg...) do { \ |
| 369 | if ((dev) && (dev)->ipc_log) \ |
| 370 | ipc_log_string((dev)->ipc_log, "DBG3:%s: " fmt, __func__, arg);\ |
| 371 | if (msm_pcie_debug_mask) \ |
| 372 | pr_alert("%s: " fmt, __func__, arg); \ |
| 373 | } while (0) |
| 374 | |
| 375 | #define PCIE_DUMP(dev, fmt, arg...) do { \ |
| 376 | if ((dev) && (dev)->ipc_log_dump) \ |
| 377 | ipc_log_string((dev)->ipc_log_dump, \ |
| 378 | "DUMP:%s: " fmt, __func__, arg); \ |
| 379 | } while (0) |
| 380 | |
| 381 | #define PCIE_DBG_FS(dev, fmt, arg...) do { \ |
| 382 | if ((dev) && (dev)->ipc_log_dump) \ |
| 383 | ipc_log_string((dev)->ipc_log_dump, \ |
| 384 | "DBG_FS:%s: " fmt, __func__, arg); \ |
| 385 | pr_alert("%s: " fmt, __func__, arg); \ |
| 386 | } while (0) |
| 387 | |
| 388 | #define PCIE_INFO(dev, fmt, arg...) do { \ |
| 389 | if ((dev) && (dev)->ipc_log_long) \ |
| 390 | ipc_log_string((dev)->ipc_log_long, \ |
| 391 | "INFO:%s: " fmt, __func__, arg); \ |
| 392 | if ((dev) && (dev)->ipc_log) \ |
| 393 | ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \ |
| 394 | pr_info("%s: " fmt, __func__, arg); \ |
| 395 | } while (0) |
| 396 | |
| 397 | #define PCIE_ERR(dev, fmt, arg...) do { \ |
| 398 | if ((dev) && (dev)->ipc_log_long) \ |
| 399 | ipc_log_string((dev)->ipc_log_long, \ |
| 400 | "ERR:%s: " fmt, __func__, arg); \ |
| 401 | if ((dev) && (dev)->ipc_log) \ |
| 402 | ipc_log_string((dev)->ipc_log, "%s: " fmt, __func__, arg); \ |
| 403 | pr_err("%s: " fmt, __func__, arg); \ |
| 404 | } while (0) |
| 405 | |
| 406 | |
| 407 | enum msm_pcie_res { |
| 408 | MSM_PCIE_RES_PARF, |
| 409 | MSM_PCIE_RES_PHY, |
| 410 | MSM_PCIE_RES_DM_CORE, |
| 411 | MSM_PCIE_RES_ELBI, |
| 412 | MSM_PCIE_RES_CONF, |
| 413 | MSM_PCIE_RES_IO, |
| 414 | MSM_PCIE_RES_BARS, |
| 415 | MSM_PCIE_RES_TCSR, |
| 416 | MSM_PCIE_MAX_RES, |
| 417 | }; |
| 418 | |
| 419 | enum msm_pcie_irq { |
| 420 | MSM_PCIE_INT_MSI, |
| 421 | MSM_PCIE_INT_A, |
| 422 | MSM_PCIE_INT_B, |
| 423 | MSM_PCIE_INT_C, |
| 424 | MSM_PCIE_INT_D, |
| 425 | MSM_PCIE_INT_PLS_PME, |
| 426 | MSM_PCIE_INT_PME_LEGACY, |
| 427 | MSM_PCIE_INT_PLS_ERR, |
| 428 | MSM_PCIE_INT_AER_LEGACY, |
| 429 | MSM_PCIE_INT_LINK_UP, |
| 430 | MSM_PCIE_INT_LINK_DOWN, |
| 431 | MSM_PCIE_INT_BRIDGE_FLUSH_N, |
| 432 | MSM_PCIE_INT_GLOBAL_INT, |
| 433 | MSM_PCIE_MAX_IRQ, |
| 434 | }; |
| 435 | |
| 436 | enum msm_pcie_irq_event { |
| 437 | MSM_PCIE_INT_EVT_LINK_DOWN = 1, |
| 438 | MSM_PCIE_INT_EVT_BME, |
| 439 | MSM_PCIE_INT_EVT_PM_TURNOFF, |
| 440 | MSM_PCIE_INT_EVT_DEBUG, |
| 441 | MSM_PCIE_INT_EVT_LTR, |
| 442 | MSM_PCIE_INT_EVT_MHI_Q6, |
| 443 | MSM_PCIE_INT_EVT_MHI_A7, |
| 444 | MSM_PCIE_INT_EVT_DSTATE_CHANGE, |
| 445 | MSM_PCIE_INT_EVT_L1SUB_TIMEOUT, |
| 446 | MSM_PCIE_INT_EVT_MMIO_WRITE, |
| 447 | MSM_PCIE_INT_EVT_CFG_WRITE, |
| 448 | MSM_PCIE_INT_EVT_BRIDGE_FLUSH_N, |
| 449 | MSM_PCIE_INT_EVT_LINK_UP, |
| 450 | MSM_PCIE_INT_EVT_AER_LEGACY, |
| 451 | MSM_PCIE_INT_EVT_AER_ERR, |
| 452 | MSM_PCIE_INT_EVT_PME_LEGACY, |
| 453 | MSM_PCIE_INT_EVT_PLS_PME, |
| 454 | MSM_PCIE_INT_EVT_INTD, |
| 455 | MSM_PCIE_INT_EVT_INTC, |
| 456 | MSM_PCIE_INT_EVT_INTB, |
| 457 | MSM_PCIE_INT_EVT_INTA, |
| 458 | MSM_PCIE_INT_EVT_EDMA, |
| 459 | MSM_PCIE_INT_EVT_MSI_0, |
| 460 | MSM_PCIE_INT_EVT_MSI_1, |
| 461 | MSM_PCIE_INT_EVT_MSI_2, |
| 462 | MSM_PCIE_INT_EVT_MSI_3, |
| 463 | MSM_PCIE_INT_EVT_MSI_4, |
| 464 | MSM_PCIE_INT_EVT_MSI_5, |
| 465 | MSM_PCIE_INT_EVT_MSI_6, |
| 466 | MSM_PCIE_INT_EVT_MSI_7, |
| 467 | MSM_PCIE_INT_EVT_MAX = 30, |
| 468 | }; |
| 469 | |
| 470 | enum msm_pcie_gpio { |
| 471 | MSM_PCIE_GPIO_PERST, |
| 472 | MSM_PCIE_GPIO_WAKE, |
| 473 | MSM_PCIE_GPIO_EP, |
| 474 | MSM_PCIE_MAX_GPIO |
| 475 | }; |
| 476 | |
| 477 | enum msm_pcie_link_status { |
| 478 | MSM_PCIE_LINK_DEINIT, |
| 479 | MSM_PCIE_LINK_ENABLED, |
| 480 | MSM_PCIE_LINK_DISABLED |
| 481 | }; |
| 482 | |
| 483 | /* gpio info structure */ |
| 484 | struct msm_pcie_gpio_info_t { |
| 485 | char *name; |
| 486 | uint32_t num; |
| 487 | bool out; |
| 488 | uint32_t on; |
| 489 | uint32_t init; |
| 490 | bool required; |
| 491 | }; |
| 492 | |
| 493 | /* voltage regulator info structrue */ |
| 494 | struct msm_pcie_vreg_info_t { |
| 495 | struct regulator *hdl; |
| 496 | char *name; |
| 497 | uint32_t max_v; |
| 498 | uint32_t min_v; |
| 499 | uint32_t opt_mode; |
| 500 | bool required; |
| 501 | }; |
| 502 | |
| 503 | /* reset info structure */ |
| 504 | struct msm_pcie_reset_info_t { |
| 505 | struct reset_control *hdl; |
| 506 | char *name; |
| 507 | bool required; |
| 508 | }; |
| 509 | |
| 510 | /* clock info structure */ |
| 511 | struct msm_pcie_clk_info_t { |
| 512 | struct clk *hdl; |
| 513 | char *name; |
| 514 | u32 freq; |
| 515 | bool config_mem; |
| 516 | bool required; |
| 517 | }; |
| 518 | |
| 519 | /* resource info structure */ |
| 520 | struct msm_pcie_res_info_t { |
| 521 | char *name; |
| 522 | struct resource *resource; |
| 523 | void __iomem *base; |
| 524 | }; |
| 525 | |
| 526 | /* irq info structrue */ |
| 527 | struct msm_pcie_irq_info_t { |
| 528 | char *name; |
| 529 | uint32_t num; |
| 530 | }; |
| 531 | |
| 532 | /* phy info structure */ |
| 533 | struct msm_pcie_phy_info_t { |
| 534 | u32 offset; |
| 535 | u32 val; |
| 536 | u32 delay; |
| 537 | }; |
| 538 | |
| 539 | /* PCIe device info structure */ |
| 540 | struct msm_pcie_device_info { |
| 541 | u32 bdf; |
| 542 | struct pci_dev *dev; |
| 543 | short short_bdf; |
| 544 | u32 sid; |
| 545 | int domain; |
| 546 | void __iomem *conf_base; |
| 547 | unsigned long phy_address; |
| 548 | u32 dev_ctrlstts_offset; |
| 549 | struct msm_pcie_register_event *event_reg; |
| 550 | bool registered; |
| 551 | }; |
| 552 | |
| 553 | /* msm pcie device structure */ |
| 554 | struct msm_pcie_dev_t { |
| 555 | struct platform_device *pdev; |
| 556 | struct pci_dev *dev; |
| 557 | struct regulator *gdsc; |
| 558 | struct regulator *gdsc_smmu; |
| 559 | struct msm_pcie_vreg_info_t vreg[MSM_PCIE_MAX_VREG]; |
| 560 | struct msm_pcie_gpio_info_t gpio[MSM_PCIE_MAX_GPIO]; |
| 561 | struct msm_pcie_clk_info_t clk[MSM_PCIE_MAX_CLK]; |
| 562 | struct msm_pcie_clk_info_t pipeclk[MSM_PCIE_MAX_PIPE_CLK]; |
| 563 | struct msm_pcie_res_info_t res[MSM_PCIE_MAX_RES]; |
| 564 | struct msm_pcie_irq_info_t irq[MSM_PCIE_MAX_IRQ]; |
| 565 | struct msm_pcie_irq_info_t msi[MSM_PCIE_MAX_MSI]; |
| 566 | struct msm_pcie_reset_info_t reset[MSM_PCIE_MAX_RESET]; |
| 567 | struct msm_pcie_reset_info_t pipe_reset[MSM_PCIE_MAX_PIPE_RESET]; |
| 568 | |
| 569 | void __iomem *parf; |
| 570 | void __iomem *phy; |
| 571 | void __iomem *elbi; |
| 572 | void __iomem *dm_core; |
| 573 | void __iomem *conf; |
| 574 | void __iomem *bars; |
| 575 | void __iomem *tcsr; |
| 576 | |
| 577 | uint32_t axi_bar_start; |
| 578 | uint32_t axi_bar_end; |
| 579 | |
| 580 | struct resource *dev_mem_res; |
| 581 | struct resource *dev_io_res; |
| 582 | |
| 583 | uint32_t wake_n; |
| 584 | uint32_t vreg_n; |
| 585 | uint32_t gpio_n; |
| 586 | uint32_t parf_deemph; |
| 587 | uint32_t parf_swing; |
| 588 | |
| 589 | bool cfg_access; |
| 590 | spinlock_t cfg_lock; |
| 591 | unsigned long irqsave_flags; |
| 592 | struct mutex enumerate_lock; |
| 593 | struct mutex setup_lock; |
| 594 | |
| 595 | struct irq_domain *irq_domain; |
| 596 | DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_NR_IRQS); |
| 597 | uint32_t msi_gicm_addr; |
| 598 | uint32_t msi_gicm_base; |
| 599 | bool use_msi; |
| 600 | |
| 601 | enum msm_pcie_link_status link_status; |
| 602 | bool user_suspend; |
| 603 | bool disable_pc; |
| 604 | struct pci_saved_state *saved_state; |
| 605 | |
| 606 | struct wakeup_source ws; |
| 607 | struct msm_bus_scale_pdata *bus_scale_table; |
| 608 | uint32_t bus_client; |
| 609 | |
| 610 | bool l0s_supported; |
| 611 | bool l1_supported; |
| 612 | bool l1ss_supported; |
| 613 | bool common_clk_en; |
| 614 | bool clk_power_manage_en; |
| 615 | bool aux_clk_sync; |
| 616 | bool aer_enable; |
| 617 | bool smmu_exist; |
| 618 | uint32_t smmu_sid_base; |
| 619 | uint32_t n_fts; |
| 620 | bool ext_ref_clk; |
| 621 | bool common_phy; |
| 622 | uint32_t ep_latency; |
| 623 | uint32_t wr_halt_size; |
| 624 | uint32_t cpl_timeout; |
| 625 | uint32_t current_bdf; |
| 626 | short current_short_bdf; |
| 627 | uint32_t perst_delay_us_min; |
| 628 | uint32_t perst_delay_us_max; |
| 629 | uint32_t tlp_rd_size; |
| 630 | bool linkdown_panic; |
| 631 | bool ep_wakeirq; |
| 632 | |
| 633 | uint32_t rc_idx; |
| 634 | uint32_t phy_ver; |
| 635 | bool drv_ready; |
| 636 | bool enumerated; |
| 637 | struct work_struct handle_wake_work; |
| 638 | struct mutex recovery_lock; |
| 639 | spinlock_t linkdown_lock; |
| 640 | spinlock_t wakeup_lock; |
| 641 | spinlock_t global_irq_lock; |
| 642 | spinlock_t aer_lock; |
| 643 | ulong linkdown_counter; |
| 644 | ulong link_turned_on_counter; |
| 645 | ulong link_turned_off_counter; |
| 646 | ulong rc_corr_counter; |
| 647 | ulong rc_non_fatal_counter; |
| 648 | ulong rc_fatal_counter; |
| 649 | ulong ep_corr_counter; |
| 650 | ulong ep_non_fatal_counter; |
| 651 | ulong ep_fatal_counter; |
| 652 | bool suspending; |
| 653 | ulong wake_counter; |
| 654 | u32 num_active_ep; |
| 655 | u32 num_ep; |
| 656 | bool pending_ep_reg; |
| 657 | u32 phy_len; |
| 658 | u32 port_phy_len; |
| 659 | struct msm_pcie_phy_info_t *phy_sequence; |
| 660 | struct msm_pcie_phy_info_t *port_phy_sequence; |
| 661 | u32 ep_shadow[MAX_DEVICE_NUM][PCIE_CONF_SPACE_DW]; |
| 662 | u32 rc_shadow[PCIE_CONF_SPACE_DW]; |
| 663 | bool shadow_en; |
| 664 | bool bridge_found; |
| 665 | struct msm_pcie_register_event *event_reg; |
| 666 | unsigned int scm_dev_id; |
| 667 | bool power_on; |
| 668 | void *ipc_log; |
| 669 | void *ipc_log_long; |
| 670 | void *ipc_log_dump; |
| 671 | bool use_19p2mhz_aux_clk; |
| 672 | bool use_pinctrl; |
| 673 | struct pinctrl *pinctrl; |
| 674 | struct pinctrl_state *pins_default; |
| 675 | struct pinctrl_state *pins_sleep; |
| 676 | struct msm_pcie_device_info pcidev_table[MAX_DEVICE_NUM]; |
| 677 | }; |
| 678 | |
| 679 | |
| 680 | /* debug mask sys interface */ |
| 681 | static int msm_pcie_debug_mask; |
| 682 | module_param_named(debug_mask, msm_pcie_debug_mask, |
| 683 | int, 0644); |
| 684 | |
| 685 | /* debugfs values */ |
| 686 | static u32 rc_sel; |
| 687 | static u32 base_sel; |
| 688 | static u32 wr_offset; |
| 689 | static u32 wr_mask; |
| 690 | static u32 wr_value; |
| 691 | static ulong corr_counter_limit = 5; |
| 692 | |
| 693 | /* counter to keep track if common PHY needs to be configured */ |
| 694 | static u32 num_rc_on; |
| 695 | |
| 696 | /* global lock for PCIe common PHY */ |
| 697 | static struct mutex com_phy_lock; |
| 698 | |
| 699 | /* Table to track info of PCIe devices */ |
| 700 | static struct msm_pcie_device_info |
| 701 | msm_pcie_dev_tbl[MAX_RC_NUM * MAX_DEVICE_NUM]; |
| 702 | |
| 703 | /* PCIe driver state */ |
| 704 | struct pcie_drv_sta { |
| 705 | u32 rc_num; |
| 706 | struct mutex drv_lock; |
| 707 | } pcie_drv; |
| 708 | |
| 709 | /* msm pcie device data */ |
| 710 | static struct msm_pcie_dev_t msm_pcie_dev[MAX_RC_NUM]; |
| 711 | |
| 712 | /* regulators */ |
| 713 | static struct msm_pcie_vreg_info_t msm_pcie_vreg_info[MSM_PCIE_MAX_VREG] = { |
| 714 | {NULL, "vreg-3.3", 0, 0, 0, false}, |
| 715 | {NULL, "vreg-1.8", 1800000, 1800000, 14000, true}, |
| 716 | {NULL, "vreg-0.9", 1000000, 1000000, 40000, true}, |
| 717 | {NULL, "vreg-cx", 0, 0, 0, false} |
| 718 | }; |
| 719 | |
| 720 | /* GPIOs */ |
| 721 | static struct msm_pcie_gpio_info_t msm_pcie_gpio_info[MSM_PCIE_MAX_GPIO] = { |
| 722 | {"perst-gpio", 0, 1, 0, 0, 1}, |
| 723 | {"wake-gpio", 0, 0, 0, 0, 0}, |
| 724 | {"qcom,ep-gpio", 0, 1, 1, 0, 0} |
| 725 | }; |
| 726 | |
| 727 | /* resets */ |
| 728 | static struct msm_pcie_reset_info_t |
| 729 | msm_pcie_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_RESET] = { |
| 730 | { |
| 731 | {NULL, "pcie_phy_reset", false}, |
| 732 | {NULL, "pcie_phy_com_reset", false}, |
| 733 | {NULL, "pcie_phy_nocsr_com_phy_reset", false}, |
| 734 | {NULL, "pcie_0_phy_reset", false} |
| 735 | }, |
| 736 | { |
| 737 | {NULL, "pcie_phy_reset", false}, |
| 738 | {NULL, "pcie_phy_com_reset", false}, |
| 739 | {NULL, "pcie_phy_nocsr_com_phy_reset", false}, |
| 740 | {NULL, "pcie_1_phy_reset", false} |
| 741 | }, |
| 742 | { |
| 743 | {NULL, "pcie_phy_reset", false}, |
| 744 | {NULL, "pcie_phy_com_reset", false}, |
| 745 | {NULL, "pcie_phy_nocsr_com_phy_reset", false}, |
| 746 | {NULL, "pcie_2_phy_reset", false} |
| 747 | } |
| 748 | }; |
| 749 | |
| 750 | /* pipe reset */ |
| 751 | static struct msm_pcie_reset_info_t |
| 752 | msm_pcie_pipe_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_RESET] = { |
| 753 | { |
| 754 | {NULL, "pcie_0_phy_pipe_reset", false} |
| 755 | }, |
| 756 | { |
| 757 | {NULL, "pcie_1_phy_pipe_reset", false} |
| 758 | }, |
| 759 | { |
| 760 | {NULL, "pcie_2_phy_pipe_reset", false} |
| 761 | } |
| 762 | }; |
| 763 | |
| 764 | /* clocks */ |
| 765 | static struct msm_pcie_clk_info_t |
| 766 | msm_pcie_clk_info[MAX_RC_NUM][MSM_PCIE_MAX_CLK] = { |
| 767 | { |
| 768 | {NULL, "pcie_0_ref_clk_src", 0, false, false}, |
| 769 | {NULL, "pcie_0_aux_clk", 1010000, false, true}, |
| 770 | {NULL, "pcie_0_cfg_ahb_clk", 0, false, true}, |
| 771 | {NULL, "pcie_0_mstr_axi_clk", 0, true, true}, |
| 772 | {NULL, "pcie_0_slv_axi_clk", 0, true, true}, |
| 773 | {NULL, "pcie_0_ldo", 0, false, true}, |
| 774 | {NULL, "pcie_0_smmu_clk", 0, false, false}, |
| 775 | {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, |
| 776 | {NULL, "pcie_phy_aux_clk", 0, false, false} |
| 777 | }, |
| 778 | { |
| 779 | {NULL, "pcie_1_ref_clk_src", 0, false, false}, |
| 780 | {NULL, "pcie_1_aux_clk", 1010000, false, true}, |
| 781 | {NULL, "pcie_1_cfg_ahb_clk", 0, false, true}, |
| 782 | {NULL, "pcie_1_mstr_axi_clk", 0, true, true}, |
| 783 | {NULL, "pcie_1_slv_axi_clk", 0, true, true}, |
| 784 | {NULL, "pcie_1_ldo", 0, false, true}, |
| 785 | {NULL, "pcie_1_smmu_clk", 0, false, false}, |
| 786 | {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, |
| 787 | {NULL, "pcie_phy_aux_clk", 0, false, false} |
| 788 | }, |
| 789 | { |
| 790 | {NULL, "pcie_2_ref_clk_src", 0, false, false}, |
| 791 | {NULL, "pcie_2_aux_clk", 1010000, false, true}, |
| 792 | {NULL, "pcie_2_cfg_ahb_clk", 0, false, true}, |
| 793 | {NULL, "pcie_2_mstr_axi_clk", 0, true, true}, |
| 794 | {NULL, "pcie_2_slv_axi_clk", 0, true, true}, |
| 795 | {NULL, "pcie_2_ldo", 0, false, true}, |
| 796 | {NULL, "pcie_2_smmu_clk", 0, false, false}, |
| 797 | {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, |
| 798 | {NULL, "pcie_phy_aux_clk", 0, false, false} |
| 799 | } |
| 800 | }; |
| 801 | |
| 802 | /* Pipe Clocks */ |
| 803 | static struct msm_pcie_clk_info_t |
| 804 | msm_pcie_pipe_clk_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_CLK] = { |
| 805 | { |
| 806 | {NULL, "pcie_0_pipe_clk", 125000000, true, true}, |
| 807 | }, |
| 808 | { |
| 809 | {NULL, "pcie_1_pipe_clk", 125000000, true, true}, |
| 810 | }, |
| 811 | { |
| 812 | {NULL, "pcie_2_pipe_clk", 125000000, true, true}, |
| 813 | } |
| 814 | }; |
| 815 | |
| 816 | /* resources */ |
| 817 | static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { |
| 818 | {"parf", 0, 0}, |
| 819 | {"phy", 0, 0}, |
| 820 | {"dm_core", 0, 0}, |
| 821 | {"elbi", 0, 0}, |
| 822 | {"conf", 0, 0}, |
| 823 | {"io", 0, 0}, |
| 824 | {"bars", 0, 0}, |
| 825 | {"tcsr", 0, 0} |
| 826 | }; |
| 827 | |
| 828 | /* irqs */ |
| 829 | static const struct msm_pcie_irq_info_t msm_pcie_irq_info[MSM_PCIE_MAX_IRQ] = { |
| 830 | {"int_msi", 0}, |
| 831 | {"int_a", 0}, |
| 832 | {"int_b", 0}, |
| 833 | {"int_c", 0}, |
| 834 | {"int_d", 0}, |
| 835 | {"int_pls_pme", 0}, |
| 836 | {"int_pme_legacy", 0}, |
| 837 | {"int_pls_err", 0}, |
| 838 | {"int_aer_legacy", 0}, |
| 839 | {"int_pls_link_up", 0}, |
| 840 | {"int_pls_link_down", 0}, |
| 841 | {"int_bridge_flush_n", 0}, |
| 842 | {"int_global_int", 0} |
| 843 | }; |
| 844 | |
| 845 | /* MSIs */ |
| 846 | static const struct msm_pcie_irq_info_t msm_pcie_msi_info[MSM_PCIE_MAX_MSI] = { |
| 847 | {"msi_0", 0}, {"msi_1", 0}, {"msi_2", 0}, {"msi_3", 0}, |
| 848 | {"msi_4", 0}, {"msi_5", 0}, {"msi_6", 0}, {"msi_7", 0}, |
| 849 | {"msi_8", 0}, {"msi_9", 0}, {"msi_10", 0}, {"msi_11", 0}, |
| 850 | {"msi_12", 0}, {"msi_13", 0}, {"msi_14", 0}, {"msi_15", 0}, |
| 851 | {"msi_16", 0}, {"msi_17", 0}, {"msi_18", 0}, {"msi_19", 0}, |
| 852 | {"msi_20", 0}, {"msi_21", 0}, {"msi_22", 0}, {"msi_23", 0}, |
| 853 | {"msi_24", 0}, {"msi_25", 0}, {"msi_26", 0}, {"msi_27", 0}, |
| 854 | {"msi_28", 0}, {"msi_29", 0}, {"msi_30", 0}, {"msi_31", 0} |
| 855 | }; |
| 856 | |
| 857 | #ifdef CONFIG_ARM |
| 858 | #define PCIE_BUS_PRIV_DATA(bus) \ |
| 859 | (((struct pci_sys_data *)bus->sysdata)->private_data) |
| 860 | |
| 861 | static struct pci_sys_data msm_pcie_sys_data[MAX_RC_NUM]; |
| 862 | |
| 863 | static inline void *msm_pcie_setup_sys_data(struct msm_pcie_dev_t *dev) |
| 864 | { |
| 865 | msm_pcie_sys_data[dev->rc_idx].domain = dev->rc_idx; |
| 866 | msm_pcie_sys_data[dev->rc_idx].private_data = dev; |
| 867 | |
| 868 | return &msm_pcie_sys_data[dev->rc_idx]; |
| 869 | } |
| 870 | |
| 871 | static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev) |
| 872 | { |
| 873 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); |
| 874 | } |
| 875 | #else |
| 876 | #define PCIE_BUS_PRIV_DATA(bus) \ |
| 877 | (struct msm_pcie_dev_t *)(bus->sysdata) |
| 878 | |
| 879 | static inline void *msm_pcie_setup_sys_data(struct msm_pcie_dev_t *dev) |
| 880 | { |
| 881 | return dev; |
| 882 | } |
| 883 | |
| 884 | static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev) |
| 885 | { |
| 886 | } |
| 887 | #endif |
| 888 | |
| 889 | static inline void msm_pcie_write_reg(void *base, u32 offset, u32 value) |
| 890 | { |
| 891 | writel_relaxed(value, base + offset); |
| 892 | /* ensure that changes propagated to the hardware */ |
| 893 | wmb(); |
| 894 | } |
| 895 | |
| 896 | static inline void msm_pcie_write_reg_field(void *base, u32 offset, |
| 897 | const u32 mask, u32 val) |
| 898 | { |
| 899 | u32 shift = find_first_bit((void *)&mask, 32); |
| 900 | u32 tmp = readl_relaxed(base + offset); |
| 901 | |
| 902 | tmp &= ~mask; /* clear written bits */ |
| 903 | val = tmp | (val << shift); |
| 904 | writel_relaxed(val, base + offset); |
| 905 | /* ensure that changes propagated to the hardware */ |
| 906 | wmb(); |
| 907 | } |
| 908 | |
| 909 | static inline void msm_pcie_config_clock_mem(struct msm_pcie_dev_t *dev, |
| 910 | struct msm_pcie_clk_info_t *info) |
| 911 | { |
| 912 | int ret; |
| 913 | |
| 914 | ret = clk_set_flags(info->hdl, CLKFLAG_NORETAIN_MEM); |
| 915 | if (ret) |
| 916 | PCIE_ERR(dev, |
| 917 | "PCIe: RC%d can't configure core memory for clk %s: %d.\n", |
| 918 | dev->rc_idx, info->name, ret); |
| 919 | else |
| 920 | PCIE_DBG2(dev, |
| 921 | "PCIe: RC%d configured core memory for clk %s.\n", |
| 922 | dev->rc_idx, info->name); |
| 923 | |
| 924 | ret = clk_set_flags(info->hdl, CLKFLAG_NORETAIN_PERIPH); |
| 925 | if (ret) |
| 926 | PCIE_ERR(dev, |
| 927 | "PCIe: RC%d can't configure peripheral memory for clk %s: %d.\n", |
| 928 | dev->rc_idx, info->name, ret); |
| 929 | else |
| 930 | PCIE_DBG2(dev, |
| 931 | "PCIe: RC%d configured peripheral memory for clk %s.\n", |
| 932 | dev->rc_idx, info->name); |
| 933 | } |
| 934 | |
| 935 | #if defined(CONFIG_ARCH_FSM9010) |
| 936 | #define PCIE20_PARF_PHY_STTS 0x3c |
| 937 | #define PCIE2_PHY_RESET_CTRL 0x44 |
| 938 | #define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0 |
| 939 | #define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4 |
| 940 | #define PCIE20_PARF_PCS_SWING_CTRL1 0x88 |
| 941 | #define PCIE20_PARF_PCS_SWING_CTRL2 0x8c |
| 942 | #define PCIE20_PARF_PCS_DEEMPH1 0x74 |
| 943 | #define PCIE20_PARF_PCS_DEEMPH2 0x78 |
| 944 | #define PCIE20_PARF_PCS_DEEMPH3 0x7c |
| 945 | #define PCIE20_PARF_CONFIGBITS 0x84 |
| 946 | #define PCIE20_PARF_PHY_CTRL3 0x94 |
| 947 | #define PCIE20_PARF_PCS_CTRL 0x80 |
| 948 | |
| 949 | #define TX_AMP_VAL 127 |
| 950 | #define PHY_RX0_EQ_GEN1_VAL 0 |
| 951 | #define PHY_RX0_EQ_GEN2_VAL 4 |
| 952 | #define TX_DEEMPH_GEN1_VAL 24 |
| 953 | #define TX_DEEMPH_GEN2_3_5DB_VAL 24 |
| 954 | #define TX_DEEMPH_GEN2_6DB_VAL 34 |
| 955 | #define PHY_TX0_TERM_OFFST_VAL 0 |
| 956 | |
| 957 | static inline void pcie_phy_dump(struct msm_pcie_dev_t *dev) |
| 958 | { |
| 959 | } |
| 960 | |
| 961 | static inline void pcie20_phy_reset(struct msm_pcie_dev_t *dev, uint32_t assert) |
| 962 | { |
| 963 | msm_pcie_write_reg_field(dev->phy, PCIE2_PHY_RESET_CTRL, |
| 964 | BIT(0), (assert) ? 1 : 0); |
| 965 | } |
| 966 | |
| 967 | static void pcie_phy_init(struct msm_pcie_dev_t *dev) |
| 968 | { |
| 969 | PCIE_DBG(dev, "RC%d: Initializing 28LP SNS phy - 100MHz\n", |
| 970 | dev->rc_idx); |
| 971 | |
| 972 | /* De-assert Phy SW Reset */ |
| 973 | pcie20_phy_reset(dev, 1); |
| 974 | |
| 975 | /* Program SSP ENABLE */ |
| 976 | if (readl_relaxed(dev->phy + PCIE20_PARF_PHY_REFCLK_CTRL2) & BIT(0)) |
| 977 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL2, |
| 978 | BIT(0), 0); |
| 979 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PHY_REFCLK_CTRL3) & |
| 980 | BIT(0)) == 0) |
| 981 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL3, |
| 982 | BIT(0), 1); |
| 983 | /* Program Tx Amplitude */ |
| 984 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_SWING_CTRL1) & |
| 985 | (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 986 | TX_AMP_VAL) |
| 987 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_SWING_CTRL1, |
| 988 | BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 989 | TX_AMP_VAL); |
| 990 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_SWING_CTRL2) & |
| 991 | (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 992 | TX_AMP_VAL) |
| 993 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_SWING_CTRL2, |
| 994 | BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 995 | TX_AMP_VAL); |
| 996 | /* Program De-Emphasis */ |
| 997 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH1) & |
| 998 | (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 999 | TX_DEEMPH_GEN2_6DB_VAL) |
| 1000 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH1, |
| 1001 | BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 1002 | TX_DEEMPH_GEN2_6DB_VAL); |
| 1003 | |
| 1004 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH2) & |
| 1005 | (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 1006 | TX_DEEMPH_GEN2_3_5DB_VAL) |
| 1007 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH2, |
| 1008 | BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 1009 | TX_DEEMPH_GEN2_3_5DB_VAL); |
| 1010 | |
| 1011 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH3) & |
| 1012 | (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 1013 | TX_DEEMPH_GEN1_VAL) |
| 1014 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH3, |
| 1015 | BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 1016 | TX_DEEMPH_GEN1_VAL); |
| 1017 | |
| 1018 | /* Program Rx_Eq */ |
| 1019 | if ((readl_relaxed(dev->phy + PCIE20_PARF_CONFIGBITS) & |
| 1020 | (BIT(2)|BIT(1)|BIT(0))) != PHY_RX0_EQ_GEN1_VAL) |
| 1021 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_CONFIGBITS, |
| 1022 | BIT(2)|BIT(1)|BIT(0), PHY_RX0_EQ_GEN1_VAL); |
| 1023 | |
| 1024 | /* Program Tx0_term_offset */ |
| 1025 | if ((readl_relaxed(dev->phy + PCIE20_PARF_PHY_CTRL3) & |
| 1026 | (BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) != |
| 1027 | PHY_TX0_TERM_OFFST_VAL) |
| 1028 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_CTRL3, |
| 1029 | BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0), |
| 1030 | PHY_TX0_TERM_OFFST_VAL); |
| 1031 | |
| 1032 | /* Program REF_CLK source */ |
| 1033 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL2, BIT(1), |
| 1034 | (dev->ext_ref_clk) ? 1 : 0); |
| 1035 | /* disable Tx2Rx Loopback */ |
| 1036 | if (readl_relaxed(dev->phy + PCIE20_PARF_PCS_CTRL) & BIT(1)) |
| 1037 | msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_CTRL, |
| 1038 | BIT(1), 0); |
| 1039 | /* De-assert Phy SW Reset */ |
| 1040 | pcie20_phy_reset(dev, 0); |
| 1041 | } |
| 1042 | |
| 1043 | static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) |
| 1044 | { |
| 1045 | |
| 1046 | /* read PCIE20_PARF_PHY_STTS twice */ |
| 1047 | readl_relaxed(dev->phy + PCIE20_PARF_PHY_STTS); |
| 1048 | if (readl_relaxed(dev->phy + PCIE20_PARF_PHY_STTS) & BIT(0)) |
| 1049 | return false; |
| 1050 | else |
| 1051 | return true; |
| 1052 | } |
| 1053 | #else |
| 1054 | static void pcie_phy_dump_test_cntrl(struct msm_pcie_dev_t *dev, |
| 1055 | u32 cntrl4_val, u32 cntrl5_val, |
| 1056 | u32 cntrl6_val, u32 cntrl7_val) |
| 1057 | { |
| 1058 | msm_pcie_write_reg(dev->phy, |
| 1059 | PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), cntrl4_val); |
| 1060 | msm_pcie_write_reg(dev->phy, |
| 1061 | PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), cntrl5_val); |
| 1062 | msm_pcie_write_reg(dev->phy, |
| 1063 | PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), cntrl6_val); |
| 1064 | msm_pcie_write_reg(dev->phy, |
| 1065 | PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), cntrl7_val); |
| 1066 | |
| 1067 | PCIE_DUMP(dev, |
| 1068 | "PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", dev->rc_idx, |
| 1069 | readl_relaxed(dev->phy + |
| 1070 | PCIE_N_TEST_CONTROL4(dev->rc_idx, |
| 1071 | dev->common_phy))); |
| 1072 | PCIE_DUMP(dev, |
| 1073 | "PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", dev->rc_idx, |
| 1074 | readl_relaxed(dev->phy + |
| 1075 | PCIE_N_TEST_CONTROL5(dev->rc_idx, |
| 1076 | dev->common_phy))); |
| 1077 | PCIE_DUMP(dev, |
| 1078 | "PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", dev->rc_idx, |
| 1079 | readl_relaxed(dev->phy + |
| 1080 | PCIE_N_TEST_CONTROL6(dev->rc_idx, |
| 1081 | dev->common_phy))); |
| 1082 | PCIE_DUMP(dev, |
| 1083 | "PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", dev->rc_idx, |
| 1084 | readl_relaxed(dev->phy + |
| 1085 | PCIE_N_TEST_CONTROL7(dev->rc_idx, |
| 1086 | dev->common_phy))); |
| 1087 | PCIE_DUMP(dev, |
| 1088 | "PCIe: RC%d PCIE_N_DEBUG_BUS_0_STATUS: 0x%x\n", dev->rc_idx, |
| 1089 | readl_relaxed(dev->phy + |
| 1090 | PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx, |
| 1091 | dev->common_phy))); |
| 1092 | PCIE_DUMP(dev, |
| 1093 | "PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", dev->rc_idx, |
| 1094 | readl_relaxed(dev->phy + |
| 1095 | PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx, |
| 1096 | dev->common_phy))); |
| 1097 | PCIE_DUMP(dev, |
| 1098 | "PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", dev->rc_idx, |
| 1099 | readl_relaxed(dev->phy + |
| 1100 | PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx, |
| 1101 | dev->common_phy))); |
| 1102 | PCIE_DUMP(dev, |
| 1103 | "PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", dev->rc_idx, |
| 1104 | readl_relaxed(dev->phy + |
| 1105 | PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx, |
| 1106 | dev->common_phy))); |
| 1107 | } |
| 1108 | |
| 1109 | static void pcie_phy_dump(struct msm_pcie_dev_t *dev) |
| 1110 | { |
| 1111 | int i, size; |
| 1112 | u32 write_val; |
| 1113 | |
| 1114 | if (dev->phy_ver >= 0x20) { |
| 1115 | PCIE_DUMP(dev, "PCIe: RC%d PHY dump is not supported\n", |
| 1116 | dev->rc_idx); |
| 1117 | return; |
| 1118 | } |
| 1119 | |
| 1120 | PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx); |
| 1121 | |
| 1122 | pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B); |
| 1123 | pcie_phy_dump_test_cntrl(dev, 0x1C, 0x1D, 0x1E, 0x1F); |
| 1124 | pcie_phy_dump_test_cntrl(dev, 0x20, 0x21, 0x22, 0x23); |
| 1125 | |
| 1126 | for (i = 0; i < 3; i++) { |
| 1127 | write_val = 0x1 + i; |
| 1128 | msm_pcie_write_reg(dev->phy, |
| 1129 | QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx, |
| 1130 | dev->common_phy), write_val); |
| 1131 | PCIE_DUMP(dev, |
| 1132 | "PCIe: RC%d QSERDES_TX_N_DEBUG_BUS_SEL: 0x%x\n", |
| 1133 | dev->rc_idx, |
| 1134 | readl_relaxed(dev->phy + |
| 1135 | QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx, |
| 1136 | dev->common_phy))); |
| 1137 | |
| 1138 | pcie_phy_dump_test_cntrl(dev, 0x30, 0x31, 0x32, 0x33); |
| 1139 | } |
| 1140 | |
| 1141 | pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0); |
| 1142 | |
| 1143 | if (dev->phy_ver >= 0x10 && dev->phy_ver < 0x20) { |
| 1144 | pcie_phy_dump_test_cntrl(dev, 0x01, 0x02, 0x03, 0x0A); |
| 1145 | pcie_phy_dump_test_cntrl(dev, 0x0E, 0x0F, 0x12, 0x13); |
| 1146 | pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0); |
| 1147 | |
| 1148 | for (i = 0; i < 8; i += 4) { |
| 1149 | write_val = 0x1 + i; |
| 1150 | msm_pcie_write_reg(dev->phy, |
| 1151 | PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(dev->rc_idx, |
| 1152 | dev->common_phy), write_val); |
| 1153 | msm_pcie_write_reg(dev->phy, |
| 1154 | PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(dev->rc_idx, |
| 1155 | dev->common_phy), write_val + 1); |
| 1156 | msm_pcie_write_reg(dev->phy, |
| 1157 | PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(dev->rc_idx, |
| 1158 | dev->common_phy), write_val + 2); |
| 1159 | msm_pcie_write_reg(dev->phy, |
| 1160 | PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(dev->rc_idx, |
| 1161 | dev->common_phy), write_val + 3); |
| 1162 | |
| 1163 | PCIE_DUMP(dev, |
| 1164 | "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX: 0x%x\n", |
| 1165 | dev->rc_idx, |
| 1166 | readl_relaxed(dev->phy + |
| 1167 | PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX( |
| 1168 | dev->rc_idx, dev->common_phy))); |
| 1169 | PCIE_DUMP(dev, |
| 1170 | "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX: 0x%x\n", |
| 1171 | dev->rc_idx, |
| 1172 | readl_relaxed(dev->phy + |
| 1173 | PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX( |
| 1174 | dev->rc_idx, dev->common_phy))); |
| 1175 | PCIE_DUMP(dev, |
| 1176 | "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX: 0x%x\n", |
| 1177 | dev->rc_idx, |
| 1178 | readl_relaxed(dev->phy + |
| 1179 | PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX( |
| 1180 | dev->rc_idx, dev->common_phy))); |
| 1181 | PCIE_DUMP(dev, |
| 1182 | "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX: 0x%x\n", |
| 1183 | dev->rc_idx, |
| 1184 | readl_relaxed(dev->phy + |
| 1185 | PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX( |
| 1186 | dev->rc_idx, dev->common_phy))); |
| 1187 | PCIE_DUMP(dev, |
| 1188 | "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_0_STATUS: 0x%x\n", |
| 1189 | dev->rc_idx, |
| 1190 | readl_relaxed(dev->phy + |
| 1191 | PCIE_MISC_N_DEBUG_BUS_0_STATUS( |
| 1192 | dev->rc_idx, dev->common_phy))); |
| 1193 | PCIE_DUMP(dev, |
| 1194 | "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_1_STATUS: 0x%x\n", |
| 1195 | dev->rc_idx, |
| 1196 | readl_relaxed(dev->phy + |
| 1197 | PCIE_MISC_N_DEBUG_BUS_1_STATUS( |
| 1198 | dev->rc_idx, dev->common_phy))); |
| 1199 | PCIE_DUMP(dev, |
| 1200 | "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_2_STATUS: 0x%x\n", |
| 1201 | dev->rc_idx, |
| 1202 | readl_relaxed(dev->phy + |
| 1203 | PCIE_MISC_N_DEBUG_BUS_2_STATUS( |
| 1204 | dev->rc_idx, dev->common_phy))); |
| 1205 | PCIE_DUMP(dev, |
| 1206 | "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_3_STATUS: 0x%x\n", |
| 1207 | dev->rc_idx, |
| 1208 | readl_relaxed(dev->phy + |
| 1209 | PCIE_MISC_N_DEBUG_BUS_3_STATUS( |
| 1210 | dev->rc_idx, dev->common_phy))); |
| 1211 | } |
| 1212 | |
| 1213 | msm_pcie_write_reg(dev->phy, |
| 1214 | PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX( |
| 1215 | dev->rc_idx, dev->common_phy), 0); |
| 1216 | msm_pcie_write_reg(dev->phy, |
| 1217 | PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX( |
| 1218 | dev->rc_idx, dev->common_phy), 0); |
| 1219 | msm_pcie_write_reg(dev->phy, |
| 1220 | PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX( |
| 1221 | dev->rc_idx, dev->common_phy), 0); |
| 1222 | msm_pcie_write_reg(dev->phy, |
| 1223 | PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX( |
| 1224 | dev->rc_idx, dev->common_phy), 0); |
| 1225 | } |
| 1226 | |
| 1227 | for (i = 0; i < 2; i++) { |
| 1228 | write_val = 0x2 + i; |
| 1229 | |
| 1230 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, |
| 1231 | write_val); |
| 1232 | |
| 1233 | PCIE_DUMP(dev, |
| 1234 | "PCIe: RC%d to QSERDES_COM_DEBUG_BUS_SEL: 0x%x\n", |
| 1235 | dev->rc_idx, |
| 1236 | readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS_SEL)); |
| 1237 | PCIE_DUMP(dev, |
| 1238 | "PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n", |
| 1239 | dev->rc_idx, |
| 1240 | readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS0)); |
| 1241 | PCIE_DUMP(dev, |
| 1242 | "PCIe: RC%d QSERDES_COM_DEBUG_BUS1: 0x%x\n", |
| 1243 | dev->rc_idx, |
| 1244 | readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS1)); |
| 1245 | PCIE_DUMP(dev, |
| 1246 | "PCIe: RC%d QSERDES_COM_DEBUG_BUS2: 0x%x\n", |
| 1247 | dev->rc_idx, |
| 1248 | readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS2)); |
| 1249 | PCIE_DUMP(dev, |
| 1250 | "PCIe: RC%d QSERDES_COM_DEBUG_BUS3: 0x%x\n\n", |
| 1251 | dev->rc_idx, |
| 1252 | readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3)); |
| 1253 | } |
| 1254 | |
| 1255 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, 0); |
| 1256 | |
| 1257 | if (dev->common_phy) { |
| 1258 | msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX, |
| 1259 | 0x01); |
| 1260 | msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE1_INDEX, |
| 1261 | 0x02); |
| 1262 | msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE2_INDEX, |
| 1263 | 0x03); |
| 1264 | msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE3_INDEX, |
| 1265 | 0x04); |
| 1266 | |
| 1267 | PCIE_DUMP(dev, |
| 1268 | "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n", |
| 1269 | dev->rc_idx, |
| 1270 | readl_relaxed(dev->phy + |
| 1271 | PCIE_COM_DEBUG_BUS_BYTE0_INDEX)); |
| 1272 | PCIE_DUMP(dev, |
| 1273 | "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE1_INDEX: 0x%x\n", |
| 1274 | dev->rc_idx, |
| 1275 | readl_relaxed(dev->phy + |
| 1276 | PCIE_COM_DEBUG_BUS_BYTE1_INDEX)); |
| 1277 | PCIE_DUMP(dev, |
| 1278 | "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE2_INDEX: 0x%x\n", |
| 1279 | dev->rc_idx, |
| 1280 | readl_relaxed(dev->phy + |
| 1281 | PCIE_COM_DEBUG_BUS_BYTE2_INDEX)); |
| 1282 | PCIE_DUMP(dev, |
| 1283 | "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE3_INDEX: 0x%x\n", |
| 1284 | dev->rc_idx, |
| 1285 | readl_relaxed(dev->phy + |
| 1286 | PCIE_COM_DEBUG_BUS_BYTE3_INDEX)); |
| 1287 | PCIE_DUMP(dev, |
| 1288 | "PCIe: RC%d PCIE_COM_DEBUG_BUS_0_STATUS: 0x%x\n", |
| 1289 | dev->rc_idx, |
| 1290 | readl_relaxed(dev->phy + |
| 1291 | PCIE_COM_DEBUG_BUS_0_STATUS)); |
| 1292 | PCIE_DUMP(dev, |
| 1293 | "PCIe: RC%d PCIE_COM_DEBUG_BUS_1_STATUS: 0x%x\n", |
| 1294 | dev->rc_idx, |
| 1295 | readl_relaxed(dev->phy + |
| 1296 | PCIE_COM_DEBUG_BUS_1_STATUS)); |
| 1297 | PCIE_DUMP(dev, |
| 1298 | "PCIe: RC%d PCIE_COM_DEBUG_BUS_2_STATUS: 0x%x\n", |
| 1299 | dev->rc_idx, |
| 1300 | readl_relaxed(dev->phy + |
| 1301 | PCIE_COM_DEBUG_BUS_2_STATUS)); |
| 1302 | PCIE_DUMP(dev, |
| 1303 | "PCIe: RC%d PCIE_COM_DEBUG_BUS_3_STATUS: 0x%x\n", |
| 1304 | dev->rc_idx, |
| 1305 | readl_relaxed(dev->phy + |
| 1306 | PCIE_COM_DEBUG_BUS_3_STATUS)); |
| 1307 | |
| 1308 | msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX, |
| 1309 | 0x05); |
| 1310 | |
| 1311 | PCIE_DUMP(dev, |
| 1312 | "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n", |
| 1313 | dev->rc_idx, |
| 1314 | readl_relaxed(dev->phy + |
| 1315 | PCIE_COM_DEBUG_BUS_BYTE0_INDEX)); |
| 1316 | PCIE_DUMP(dev, |
| 1317 | "PCIe: RC%d PCIE_COM_DEBUG_BUS_0_STATUS: 0x%x\n\n", |
| 1318 | dev->rc_idx, |
| 1319 | readl_relaxed(dev->phy + |
| 1320 | PCIE_COM_DEBUG_BUS_0_STATUS)); |
| 1321 | } |
| 1322 | |
| 1323 | size = resource_size(dev->res[MSM_PCIE_RES_PHY].resource); |
| 1324 | for (i = 0; i < size; i += 32) { |
| 1325 | PCIE_DUMP(dev, |
| 1326 | "PCIe PHY of RC%d: 0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n", |
| 1327 | dev->rc_idx, i, |
| 1328 | readl_relaxed(dev->phy + i), |
| 1329 | readl_relaxed(dev->phy + (i + 4)), |
| 1330 | readl_relaxed(dev->phy + (i + 8)), |
| 1331 | readl_relaxed(dev->phy + (i + 12)), |
| 1332 | readl_relaxed(dev->phy + (i + 16)), |
| 1333 | readl_relaxed(dev->phy + (i + 20)), |
| 1334 | readl_relaxed(dev->phy + (i + 24)), |
| 1335 | readl_relaxed(dev->phy + (i + 28))); |
| 1336 | } |
| 1337 | } |
| 1338 | |
| 1339 | #ifdef CONFIG_ARCH_MDMCALIFORNIUM |
| 1340 | static void pcie_phy_init(struct msm_pcie_dev_t *dev) |
| 1341 | { |
| 1342 | u8 common_phy; |
| 1343 | |
| 1344 | PCIE_DBG(dev, |
| 1345 | "RC%d: Initializing MDM 14nm QMP phy - 19.2MHz with Common Mode Clock (SSC ON)\n", |
| 1346 | dev->rc_idx); |
| 1347 | |
| 1348 | if (dev->common_phy) |
| 1349 | common_phy = 1; |
| 1350 | else |
| 1351 | common_phy = 0; |
| 1352 | |
| 1353 | msm_pcie_write_reg(dev->phy, |
| 1354 | PCIE_N_SW_RESET(dev->rc_idx, common_phy), |
| 1355 | 0x01); |
| 1356 | msm_pcie_write_reg(dev->phy, |
| 1357 | PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy), |
| 1358 | 0x03); |
| 1359 | |
| 1360 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18); |
| 1361 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10); |
| 1362 | |
| 1363 | msm_pcie_write_reg(dev->phy, |
| 1364 | QSERDES_TX_N_LANE_MODE(dev->rc_idx, common_phy), 0x06); |
| 1365 | |
| 1366 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x01); |
| 1367 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00); |
| 1368 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF); |
| 1369 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F); |
| 1370 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F); |
| 1371 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F); |
| 1372 | msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x00); |
| 1373 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); |
| 1374 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x20); |
| 1375 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A); |
| 1376 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x09); |
| 1377 | |
| 1378 | if (dev->tcsr) { |
| 1379 | PCIE_DBG(dev, "RC%d: TCSR PHY clock scheme is 0x%x\n", |
| 1380 | dev->rc_idx, readl_relaxed(dev->tcsr)); |
| 1381 | |
| 1382 | if (readl_relaxed(dev->tcsr) & (BIT(1) | BIT(0))) |
| 1383 | msm_pcie_write_reg(dev->phy, |
| 1384 | QSERDES_COM_SYSCLK_EN_SEL, 0x0A); |
| 1385 | else |
| 1386 | msm_pcie_write_reg(dev->phy, |
| 1387 | QSERDES_COM_SYSCLK_EN_SEL, 0x04); |
| 1388 | } |
| 1389 | |
| 1390 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x82); |
| 1391 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03); |
| 1392 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55); |
| 1393 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55); |
| 1394 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00); |
| 1395 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x0D); |
| 1396 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x04); |
| 1397 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33); |
| 1398 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x02); |
| 1399 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1F); |
| 1400 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x0B); |
| 1401 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); |
| 1402 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x28); |
| 1403 | msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00); |
| 1404 | msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80); |
| 1405 | |
| 1406 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_EN_CENTER, 0x01); |
| 1407 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER1, 0x31); |
| 1408 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER2, 0x01); |
| 1409 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER1, 0x02); |
| 1410 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER2, 0x00); |
| 1411 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE1, 0x2f); |
| 1412 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE2, 0x19); |
| 1413 | |
| 1414 | msm_pcie_write_reg(dev->phy, |
| 1415 | QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(dev->rc_idx, |
| 1416 | common_phy), 0x45); |
| 1417 | |
| 1418 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06); |
| 1419 | |
| 1420 | msm_pcie_write_reg(dev->phy, |
| 1421 | QSERDES_TX_N_RES_CODE_LANE_OFFSET(dev->rc_idx, common_phy), |
| 1422 | 0x02); |
| 1423 | msm_pcie_write_reg(dev->phy, |
| 1424 | QSERDES_TX_N_RCV_DETECT_LVL_2(dev->rc_idx, common_phy), |
| 1425 | 0x12); |
| 1426 | |
| 1427 | msm_pcie_write_reg(dev->phy, |
| 1428 | QSERDES_RX_N_SIGDET_ENABLES(dev->rc_idx, common_phy), |
| 1429 | 0x1C); |
| 1430 | msm_pcie_write_reg(dev->phy, |
| 1431 | QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(dev->rc_idx, common_phy), |
| 1432 | 0x14); |
| 1433 | msm_pcie_write_reg(dev->phy, |
| 1434 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(dev->rc_idx, common_phy), |
| 1435 | 0x01); |
| 1436 | msm_pcie_write_reg(dev->phy, |
| 1437 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(dev->rc_idx, common_phy), |
| 1438 | 0x00); |
| 1439 | msm_pcie_write_reg(dev->phy, |
| 1440 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy), |
| 1441 | 0xDB); |
| 1442 | msm_pcie_write_reg(dev->phy, |
| 1443 | QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(dev->rc_idx, |
| 1444 | common_phy), |
| 1445 | 0x4B); |
| 1446 | msm_pcie_write_reg(dev->phy, |
| 1447 | QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy), |
| 1448 | 0x04); |
| 1449 | msm_pcie_write_reg(dev->phy, |
| 1450 | QSERDES_RX_N_UCDR_SO_GAIN_HALF(dev->rc_idx, common_phy), |
| 1451 | 0x04); |
| 1452 | |
| 1453 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19); |
| 1454 | |
| 1455 | msm_pcie_write_reg(dev->phy, |
| 1456 | PCIE_N_ENDPOINT_REFCLK_DRIVE(dev->rc_idx, common_phy), |
| 1457 | 0x04); |
| 1458 | msm_pcie_write_reg(dev->phy, |
| 1459 | PCIE_N_OSC_DTCT_ACTIONS(dev->rc_idx, common_phy), |
| 1460 | 0x00); |
| 1461 | msm_pcie_write_reg(dev->phy, |
| 1462 | PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(dev->rc_idx, common_phy), |
| 1463 | 0x40); |
| 1464 | msm_pcie_write_reg(dev->phy, |
| 1465 | PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB(dev->rc_idx, common_phy), |
| 1466 | 0x00); |
| 1467 | msm_pcie_write_reg(dev->phy, |
| 1468 | PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB(dev->rc_idx, common_phy), |
| 1469 | 0x40); |
| 1470 | msm_pcie_write_reg(dev->phy, |
| 1471 | PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK_MSB(dev->rc_idx, common_phy), |
| 1472 | 0x00); |
| 1473 | msm_pcie_write_reg(dev->phy, |
| 1474 | PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(dev->rc_idx, common_phy), |
| 1475 | 0x40); |
| 1476 | msm_pcie_write_reg(dev->phy, |
| 1477 | PCIE_N_PLL_LOCK_CHK_DLY_TIME(dev->rc_idx, common_phy), |
| 1478 | 0x73); |
| 1479 | msm_pcie_write_reg(dev->phy, |
| 1480 | QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy), |
| 1481 | 0x99); |
| 1482 | msm_pcie_write_reg(dev->phy, |
| 1483 | PCIE_N_TXDEEMPH_M6DB_V0(dev->rc_idx, common_phy), |
| 1484 | 0x15); |
| 1485 | msm_pcie_write_reg(dev->phy, |
| 1486 | PCIE_N_TXDEEMPH_M3P5DB_V0(dev->rc_idx, common_phy), |
| 1487 | 0x0E); |
| 1488 | |
| 1489 | msm_pcie_write_reg(dev->phy, |
| 1490 | PCIE_N_SIGDET_CNTRL(dev->rc_idx, common_phy), |
| 1491 | 0x07); |
| 1492 | |
| 1493 | msm_pcie_write_reg(dev->phy, |
| 1494 | PCIE_N_SW_RESET(dev->rc_idx, common_phy), |
| 1495 | 0x00); |
| 1496 | msm_pcie_write_reg(dev->phy, |
| 1497 | PCIE_N_START_CONTROL(dev->rc_idx, common_phy), |
| 1498 | 0x03); |
| 1499 | } |
| 1500 | |
| 1501 | static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) |
| 1502 | { |
| 1503 | } |
| 1504 | |
| 1505 | static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) |
| 1506 | { |
| 1507 | if (readl_relaxed(dev->phy + |
| 1508 | PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) & BIT(6)) |
| 1509 | return false; |
| 1510 | else |
| 1511 | return true; |
| 1512 | } |
| 1513 | #else |
| 1514 | static void pcie_phy_init(struct msm_pcie_dev_t *dev) |
| 1515 | { |
| 1516 | int i; |
| 1517 | struct msm_pcie_phy_info_t *phy_seq; |
| 1518 | |
| 1519 | PCIE_DBG(dev, |
| 1520 | "RC%d: Initializing 14nm QMP phy - 19.2MHz with Common Mode Clock (SSC ON)\n", |
| 1521 | dev->rc_idx); |
| 1522 | |
| 1523 | if (dev->phy_sequence) { |
| 1524 | i = dev->phy_len; |
| 1525 | phy_seq = dev->phy_sequence; |
| 1526 | while (i--) { |
| 1527 | msm_pcie_write_reg(dev->phy, |
| 1528 | phy_seq->offset, |
| 1529 | phy_seq->val); |
| 1530 | if (phy_seq->delay) |
| 1531 | usleep_range(phy_seq->delay, |
| 1532 | phy_seq->delay + 1); |
| 1533 | phy_seq++; |
| 1534 | } |
| 1535 | return; |
| 1536 | } |
| 1537 | |
| 1538 | if (dev->common_phy) |
| 1539 | msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0x01); |
| 1540 | |
| 1541 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1C); |
| 1542 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10); |
| 1543 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33); |
| 1544 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06); |
| 1545 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x42); |
| 1546 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00); |
| 1547 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF); |
| 1548 | msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F); |
| 1549 | msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x01); |
| 1550 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); |
| 1551 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x00); |
| 1552 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A); |
| 1553 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x09); |
| 1554 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x82); |
| 1555 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03); |
| 1556 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55); |
| 1557 | msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55); |
| 1558 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00); |
| 1559 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A); |
| 1560 | msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A); |
| 1561 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33); |
| 1562 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x02); |
| 1563 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1F); |
| 1564 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_EN_SEL, 0x04); |
| 1565 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x0B); |
| 1566 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); |
| 1567 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x28); |
| 1568 | msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00); |
| 1569 | msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80); |
| 1570 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_EN_CENTER, 0x01); |
| 1571 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER1, 0x31); |
| 1572 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER2, 0x01); |
| 1573 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER1, 0x02); |
| 1574 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER2, 0x00); |
| 1575 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE1, 0x2f); |
| 1576 | msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE2, 0x19); |
| 1577 | |
| 1578 | msm_pcie_write_reg(dev->phy, QSERDES_COM_RESCODE_DIV_NUM, 0x15); |
| 1579 | msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F); |
| 1580 | msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F); |
| 1581 | |
| 1582 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19); |
| 1583 | msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10); |
| 1584 | |
| 1585 | if (dev->phy_ver == 0x3) { |
| 1586 | msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x00); |
| 1587 | msm_pcie_write_reg(dev->phy, QSERDES_COM_RESCODE_DIV_NUM, 0x40); |
| 1588 | } |
| 1589 | |
| 1590 | if (dev->common_phy) { |
| 1591 | msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x00); |
| 1592 | msm_pcie_write_reg(dev->phy, PCIE_COM_START_CONTROL, 0x03); |
| 1593 | } |
| 1594 | } |
| 1595 | |
| 1596 | static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) |
| 1597 | { |
| 1598 | int i; |
| 1599 | struct msm_pcie_phy_info_t *phy_seq; |
| 1600 | u8 common_phy; |
| 1601 | |
| 1602 | if (dev->phy_ver >= 0x20) |
| 1603 | return; |
| 1604 | |
| 1605 | PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx); |
| 1606 | |
| 1607 | if (dev->common_phy) |
| 1608 | common_phy = 1; |
| 1609 | else |
| 1610 | common_phy = 0; |
| 1611 | |
| 1612 | if (dev->port_phy_sequence) { |
| 1613 | i = dev->port_phy_len; |
| 1614 | phy_seq = dev->port_phy_sequence; |
| 1615 | while (i--) { |
| 1616 | msm_pcie_write_reg(dev->phy, |
| 1617 | phy_seq->offset, |
| 1618 | phy_seq->val); |
| 1619 | if (phy_seq->delay) |
| 1620 | usleep_range(phy_seq->delay, |
| 1621 | phy_seq->delay + 1); |
| 1622 | phy_seq++; |
| 1623 | } |
| 1624 | return; |
| 1625 | } |
| 1626 | |
| 1627 | msm_pcie_write_reg(dev->phy, |
| 1628 | QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(dev->rc_idx, |
| 1629 | common_phy), 0x45); |
| 1630 | msm_pcie_write_reg(dev->phy, |
| 1631 | QSERDES_TX_N_LANE_MODE(dev->rc_idx, common_phy), |
| 1632 | 0x06); |
| 1633 | |
| 1634 | msm_pcie_write_reg(dev->phy, |
| 1635 | QSERDES_RX_N_SIGDET_ENABLES(dev->rc_idx, common_phy), |
| 1636 | 0x1C); |
| 1637 | msm_pcie_write_reg(dev->phy, |
| 1638 | QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy), |
| 1639 | 0x17); |
| 1640 | msm_pcie_write_reg(dev->phy, |
| 1641 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(dev->rc_idx, common_phy), |
| 1642 | 0x01); |
| 1643 | msm_pcie_write_reg(dev->phy, |
| 1644 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(dev->rc_idx, common_phy), |
| 1645 | 0x00); |
| 1646 | msm_pcie_write_reg(dev->phy, |
| 1647 | QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy), |
| 1648 | 0xDB); |
| 1649 | msm_pcie_write_reg(dev->phy, |
| 1650 | QSERDES_RX_N_RX_BAND(dev->rc_idx, common_phy), |
| 1651 | 0x18); |
| 1652 | msm_pcie_write_reg(dev->phy, |
| 1653 | QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy), |
| 1654 | 0x04); |
| 1655 | msm_pcie_write_reg(dev->phy, |
| 1656 | QSERDES_RX_N_UCDR_SO_GAIN_HALF(dev->rc_idx, common_phy), |
| 1657 | 0x04); |
| 1658 | msm_pcie_write_reg(dev->phy, |
| 1659 | PCIE_N_RX_IDLE_DTCT_CNTRL(dev->rc_idx, common_phy), |
| 1660 | 0x4C); |
| 1661 | msm_pcie_write_reg(dev->phy, |
| 1662 | PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(dev->rc_idx, common_phy), |
| 1663 | 0x00); |
| 1664 | msm_pcie_write_reg(dev->phy, |
| 1665 | PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(dev->rc_idx, common_phy), |
| 1666 | 0x01); |
| 1667 | msm_pcie_write_reg(dev->phy, |
| 1668 | PCIE_N_PLL_LOCK_CHK_DLY_TIME(dev->rc_idx, common_phy), |
| 1669 | 0x05); |
| 1670 | msm_pcie_write_reg(dev->phy, |
| 1671 | QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(dev->rc_idx, |
| 1672 | common_phy), 0x4B); |
| 1673 | msm_pcie_write_reg(dev->phy, |
| 1674 | QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(dev->rc_idx, common_phy), |
| 1675 | 0x14); |
| 1676 | |
| 1677 | msm_pcie_write_reg(dev->phy, |
| 1678 | PCIE_N_ENDPOINT_REFCLK_DRIVE(dev->rc_idx, common_phy), |
| 1679 | 0x05); |
| 1680 | msm_pcie_write_reg(dev->phy, |
| 1681 | PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy), |
| 1682 | 0x02); |
| 1683 | msm_pcie_write_reg(dev->phy, |
| 1684 | PCIE_N_POWER_STATE_CONFIG4(dev->rc_idx, common_phy), |
| 1685 | 0x00); |
| 1686 | msm_pcie_write_reg(dev->phy, |
| 1687 | PCIE_N_POWER_STATE_CONFIG1(dev->rc_idx, common_phy), |
| 1688 | 0xA3); |
| 1689 | |
| 1690 | if (dev->phy_ver == 0x3) { |
| 1691 | msm_pcie_write_reg(dev->phy, |
| 1692 | QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy), |
| 1693 | 0x19); |
| 1694 | |
| 1695 | msm_pcie_write_reg(dev->phy, |
| 1696 | PCIE_N_TXDEEMPH_M3P5DB_V0(dev->rc_idx, common_phy), |
| 1697 | 0x0E); |
| 1698 | } |
| 1699 | |
| 1700 | msm_pcie_write_reg(dev->phy, |
| 1701 | PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy), |
| 1702 | 0x03); |
| 1703 | usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); |
| 1704 | |
| 1705 | msm_pcie_write_reg(dev->phy, |
| 1706 | PCIE_N_SW_RESET(dev->rc_idx, common_phy), |
| 1707 | 0x00); |
| 1708 | msm_pcie_write_reg(dev->phy, |
| 1709 | PCIE_N_START_CONTROL(dev->rc_idx, common_phy), |
| 1710 | 0x0A); |
| 1711 | } |
| 1712 | |
| 1713 | static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) |
| 1714 | { |
| 1715 | if (dev->phy_ver >= 0x20) { |
| 1716 | if (readl_relaxed(dev->phy + |
| 1717 | PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) & |
| 1718 | BIT(6)) |
| 1719 | return false; |
| 1720 | else |
| 1721 | return true; |
| 1722 | } |
| 1723 | |
| 1724 | if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1)) |
| 1725 | return false; |
| 1726 | else |
| 1727 | return true; |
| 1728 | } |
| 1729 | #endif |
| 1730 | #endif |
| 1731 | |
| 1732 | static int msm_pcie_restore_sec_config(struct msm_pcie_dev_t *dev) |
| 1733 | { |
| 1734 | int ret, scm_ret; |
| 1735 | |
| 1736 | if (!dev) { |
| 1737 | pr_err("PCIe: the input pcie dev is NULL.\n"); |
| 1738 | return -ENODEV; |
| 1739 | } |
| 1740 | |
| 1741 | ret = scm_restore_sec_cfg(dev->scm_dev_id, 0, &scm_ret); |
| 1742 | if (ret || scm_ret) { |
| 1743 | PCIE_ERR(dev, |
| 1744 | "PCIe: RC%d failed(%d) to restore sec config, scm_ret=%d\n", |
| 1745 | dev->rc_idx, ret, scm_ret); |
| 1746 | return ret ? ret : -EINVAL; |
| 1747 | } |
| 1748 | |
| 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | static inline int msm_pcie_check_align(struct msm_pcie_dev_t *dev, |
| 1753 | u32 offset) |
| 1754 | { |
| 1755 | if (offset % 4) { |
| 1756 | PCIE_ERR(dev, |
| 1757 | "PCIe: RC%d: offset 0x%x is not correctly aligned\n", |
| 1758 | dev->rc_idx, offset); |
| 1759 | return MSM_PCIE_ERROR; |
| 1760 | } |
| 1761 | |
| 1762 | return 0; |
| 1763 | } |
| 1764 | |
| 1765 | static bool msm_pcie_confirm_linkup(struct msm_pcie_dev_t *dev, |
| 1766 | bool check_sw_stts, |
| 1767 | bool check_ep, |
| 1768 | void __iomem *ep_conf) |
| 1769 | { |
| 1770 | u32 val; |
| 1771 | |
| 1772 | if (check_sw_stts && (dev->link_status != MSM_PCIE_LINK_ENABLED)) { |
| 1773 | PCIE_DBG(dev, "PCIe: The link of RC %d is not enabled.\n", |
| 1774 | dev->rc_idx); |
| 1775 | return false; |
| 1776 | } |
| 1777 | |
| 1778 | if (!(readl_relaxed(dev->dm_core + 0x80) & BIT(29))) { |
| 1779 | PCIE_DBG(dev, "PCIe: The link of RC %d is not up.\n", |
| 1780 | dev->rc_idx); |
| 1781 | return false; |
| 1782 | } |
| 1783 | |
| 1784 | val = readl_relaxed(dev->dm_core); |
| 1785 | PCIE_DBG(dev, "PCIe: device ID and vender ID of RC %d are 0x%x.\n", |
| 1786 | dev->rc_idx, val); |
| 1787 | if (val == PCIE_LINK_DOWN) { |
| 1788 | PCIE_ERR(dev, |
| 1789 | "PCIe: The link of RC %d is not really up; device ID and vender ID of RC %d are 0x%x.\n", |
| 1790 | dev->rc_idx, dev->rc_idx, val); |
| 1791 | return false; |
| 1792 | } |
| 1793 | |
| 1794 | if (check_ep) { |
| 1795 | val = readl_relaxed(ep_conf); |
| 1796 | PCIE_DBG(dev, |
| 1797 | "PCIe: device ID and vender ID of EP of RC %d are 0x%x.\n", |
| 1798 | dev->rc_idx, val); |
| 1799 | if (val == PCIE_LINK_DOWN) { |
| 1800 | PCIE_ERR(dev, |
| 1801 | "PCIe: The link of RC %d is not really up; device ID and vender ID of EP of RC %d are 0x%x.\n", |
| 1802 | dev->rc_idx, dev->rc_idx, val); |
| 1803 | return false; |
| 1804 | } |
| 1805 | } |
| 1806 | |
| 1807 | return true; |
| 1808 | } |
| 1809 | |
| 1810 | static void msm_pcie_cfg_recover(struct msm_pcie_dev_t *dev, bool rc) |
| 1811 | { |
| 1812 | int i, j; |
| 1813 | u32 val = 0; |
| 1814 | u32 *shadow; |
| 1815 | void *cfg = dev->conf; |
| 1816 | |
| 1817 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 1818 | if (!rc && !dev->pcidev_table[i].bdf) |
| 1819 | break; |
| 1820 | if (rc) { |
| 1821 | cfg = dev->dm_core; |
| 1822 | shadow = dev->rc_shadow; |
| 1823 | } else { |
| 1824 | if (!msm_pcie_confirm_linkup(dev, false, true, |
| 1825 | dev->pcidev_table[i].conf_base)) |
| 1826 | continue; |
| 1827 | |
| 1828 | shadow = dev->ep_shadow[i]; |
| 1829 | PCIE_DBG(dev, |
| 1830 | "PCIe Device: %02x:%02x.%01x\n", |
| 1831 | dev->pcidev_table[i].bdf >> 24, |
| 1832 | dev->pcidev_table[i].bdf >> 19 & 0x1f, |
| 1833 | dev->pcidev_table[i].bdf >> 16 & 0x07); |
| 1834 | } |
| 1835 | for (j = PCIE_CONF_SPACE_DW - 1; j >= 0; j--) { |
| 1836 | val = shadow[j]; |
| 1837 | if (val != PCIE_CLEAR) { |
| 1838 | PCIE_DBG3(dev, |
| 1839 | "PCIe: before recovery:cfg 0x%x:0x%x\n", |
| 1840 | j * 4, readl_relaxed(cfg + j * 4)); |
| 1841 | PCIE_DBG3(dev, |
| 1842 | "PCIe: shadow_dw[%d]:cfg 0x%x:0x%x\n", |
| 1843 | j, j * 4, val); |
| 1844 | writel_relaxed(val, cfg + j * 4); |
| 1845 | /* ensure changes propagated to the hardware */ |
| 1846 | wmb(); |
| 1847 | PCIE_DBG3(dev, |
| 1848 | "PCIe: after recovery:cfg 0x%x:0x%x\n\n", |
| 1849 | j * 4, readl_relaxed(cfg + j * 4)); |
| 1850 | } |
| 1851 | } |
| 1852 | if (rc) |
| 1853 | break; |
| 1854 | |
| 1855 | pci_save_state(dev->pcidev_table[i].dev); |
| 1856 | cfg += SZ_4K; |
| 1857 | } |
| 1858 | } |
| 1859 | |
| 1860 | static void msm_pcie_write_mask(void __iomem *addr, |
| 1861 | uint32_t clear_mask, uint32_t set_mask) |
| 1862 | { |
| 1863 | uint32_t val; |
| 1864 | |
| 1865 | val = (readl_relaxed(addr) & ~clear_mask) | set_mask; |
| 1866 | writel_relaxed(val, addr); |
| 1867 | wmb(); /* ensure data is written to hardware register */ |
| 1868 | } |
| 1869 | |
| 1870 | static void pcie_parf_dump(struct msm_pcie_dev_t *dev) |
| 1871 | { |
| 1872 | int i, size; |
| 1873 | u32 original; |
| 1874 | |
| 1875 | PCIE_DUMP(dev, "PCIe: RC%d PARF testbus\n", dev->rc_idx); |
| 1876 | |
| 1877 | original = readl_relaxed(dev->parf + PCIE20_PARF_SYS_CTRL); |
| 1878 | for (i = 1; i <= 0x1A; i++) { |
| 1879 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, |
| 1880 | 0xFF0000, i << 16); |
| 1881 | PCIE_DUMP(dev, |
| 1882 | "RC%d: PARF_SYS_CTRL: 0%08x PARF_TEST_BUS: 0%08x\n", |
| 1883 | dev->rc_idx, |
| 1884 | readl_relaxed(dev->parf + PCIE20_PARF_SYS_CTRL), |
| 1885 | readl_relaxed(dev->parf + PCIE20_PARF_TEST_BUS)); |
| 1886 | } |
| 1887 | writel_relaxed(original, dev->parf + PCIE20_PARF_SYS_CTRL); |
| 1888 | |
| 1889 | PCIE_DUMP(dev, "PCIe: RC%d PARF register dump\n", dev->rc_idx); |
| 1890 | |
| 1891 | size = resource_size(dev->res[MSM_PCIE_RES_PARF].resource); |
| 1892 | for (i = 0; i < size; i += 32) { |
| 1893 | PCIE_DUMP(dev, |
| 1894 | "RC%d: 0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n", |
| 1895 | dev->rc_idx, i, |
| 1896 | readl_relaxed(dev->parf + i), |
| 1897 | readl_relaxed(dev->parf + (i + 4)), |
| 1898 | readl_relaxed(dev->parf + (i + 8)), |
| 1899 | readl_relaxed(dev->parf + (i + 12)), |
| 1900 | readl_relaxed(dev->parf + (i + 16)), |
| 1901 | readl_relaxed(dev->parf + (i + 20)), |
| 1902 | readl_relaxed(dev->parf + (i + 24)), |
| 1903 | readl_relaxed(dev->parf + (i + 28))); |
| 1904 | } |
| 1905 | } |
| 1906 | |
| 1907 | static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) |
| 1908 | { |
| 1909 | PCIE_DBG_FS(dev, "PCIe: RC%d is %s enumerated\n", |
| 1910 | dev->rc_idx, dev->enumerated ? "" : "not"); |
| 1911 | PCIE_DBG_FS(dev, "PCIe: link is %s\n", |
| 1912 | (dev->link_status == MSM_PCIE_LINK_ENABLED) |
| 1913 | ? "enabled" : "disabled"); |
| 1914 | PCIE_DBG_FS(dev, "cfg_access is %s allowed\n", |
| 1915 | dev->cfg_access ? "" : "not"); |
| 1916 | PCIE_DBG_FS(dev, "use_msi is %d\n", |
| 1917 | dev->use_msi); |
| 1918 | PCIE_DBG_FS(dev, "use_pinctrl is %d\n", |
| 1919 | dev->use_pinctrl); |
| 1920 | PCIE_DBG_FS(dev, "use_19p2mhz_aux_clk is %d\n", |
| 1921 | dev->use_19p2mhz_aux_clk); |
| 1922 | PCIE_DBG_FS(dev, "user_suspend is %d\n", |
| 1923 | dev->user_suspend); |
| 1924 | PCIE_DBG_FS(dev, "num_ep: %d\n", |
| 1925 | dev->num_ep); |
| 1926 | PCIE_DBG_FS(dev, "num_active_ep: %d\n", |
| 1927 | dev->num_active_ep); |
| 1928 | PCIE_DBG_FS(dev, "pending_ep_reg: %s\n", |
| 1929 | dev->pending_ep_reg ? "true" : "false"); |
| 1930 | PCIE_DBG_FS(dev, "phy_len is %d", |
| 1931 | dev->phy_len); |
| 1932 | PCIE_DBG_FS(dev, "port_phy_len is %d", |
| 1933 | dev->port_phy_len); |
| 1934 | PCIE_DBG_FS(dev, "disable_pc is %d", |
| 1935 | dev->disable_pc); |
| 1936 | PCIE_DBG_FS(dev, "l0s_supported is %s supported\n", |
| 1937 | dev->l0s_supported ? "" : "not"); |
| 1938 | PCIE_DBG_FS(dev, "l1_supported is %s supported\n", |
| 1939 | dev->l1_supported ? "" : "not"); |
| 1940 | PCIE_DBG_FS(dev, "l1ss_supported is %s supported\n", |
| 1941 | dev->l1ss_supported ? "" : "not"); |
| 1942 | PCIE_DBG_FS(dev, "common_clk_en is %d\n", |
| 1943 | dev->common_clk_en); |
| 1944 | PCIE_DBG_FS(dev, "clk_power_manage_en is %d\n", |
| 1945 | dev->clk_power_manage_en); |
| 1946 | PCIE_DBG_FS(dev, "aux_clk_sync is %d\n", |
| 1947 | dev->aux_clk_sync); |
| 1948 | PCIE_DBG_FS(dev, "AER is %s enable\n", |
| 1949 | dev->aer_enable ? "" : "not"); |
| 1950 | PCIE_DBG_FS(dev, "ext_ref_clk is %d\n", |
| 1951 | dev->ext_ref_clk); |
| 1952 | PCIE_DBG_FS(dev, "ep_wakeirq is %d\n", |
| 1953 | dev->ep_wakeirq); |
| 1954 | PCIE_DBG_FS(dev, "phy_ver is %d\n", |
| 1955 | dev->phy_ver); |
| 1956 | PCIE_DBG_FS(dev, "drv_ready is %d\n", |
| 1957 | dev->drv_ready); |
| 1958 | PCIE_DBG_FS(dev, "linkdown_panic is %d\n", |
| 1959 | dev->linkdown_panic); |
| 1960 | PCIE_DBG_FS(dev, "the link is %s suspending\n", |
| 1961 | dev->suspending ? "" : "not"); |
| 1962 | PCIE_DBG_FS(dev, "shadow is %s enabled\n", |
| 1963 | dev->shadow_en ? "" : "not"); |
| 1964 | PCIE_DBG_FS(dev, "the power of RC is %s on\n", |
| 1965 | dev->power_on ? "" : "not"); |
| 1966 | PCIE_DBG_FS(dev, "msi_gicm_addr: 0x%x\n", |
| 1967 | dev->msi_gicm_addr); |
| 1968 | PCIE_DBG_FS(dev, "msi_gicm_base: 0x%x\n", |
| 1969 | dev->msi_gicm_base); |
| 1970 | PCIE_DBG_FS(dev, "bus_client: %d\n", |
| 1971 | dev->bus_client); |
| 1972 | PCIE_DBG_FS(dev, "current short bdf: %d\n", |
| 1973 | dev->current_short_bdf); |
| 1974 | PCIE_DBG_FS(dev, "smmu does %s exist\n", |
| 1975 | dev->smmu_exist ? "" : "not"); |
| 1976 | PCIE_DBG_FS(dev, "smmu_sid_base: 0x%x\n", |
| 1977 | dev->smmu_sid_base); |
| 1978 | PCIE_DBG_FS(dev, "n_fts: %d\n", |
| 1979 | dev->n_fts); |
| 1980 | PCIE_DBG_FS(dev, "common_phy: %d\n", |
| 1981 | dev->common_phy); |
| 1982 | PCIE_DBG_FS(dev, "ep_latency: %dms\n", |
| 1983 | dev->ep_latency); |
| 1984 | PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n", |
| 1985 | dev->wr_halt_size); |
| 1986 | PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n", |
| 1987 | dev->cpl_timeout); |
| 1988 | PCIE_DBG_FS(dev, "current_bdf: 0x%x\n", |
| 1989 | dev->current_bdf); |
| 1990 | PCIE_DBG_FS(dev, "perst_delay_us_min: %dus\n", |
| 1991 | dev->perst_delay_us_min); |
| 1992 | PCIE_DBG_FS(dev, "perst_delay_us_max: %dus\n", |
| 1993 | dev->perst_delay_us_max); |
| 1994 | PCIE_DBG_FS(dev, "tlp_rd_size: 0x%x\n", |
| 1995 | dev->tlp_rd_size); |
| 1996 | PCIE_DBG_FS(dev, "rc_corr_counter: %lu\n", |
| 1997 | dev->rc_corr_counter); |
| 1998 | PCIE_DBG_FS(dev, "rc_non_fatal_counter: %lu\n", |
| 1999 | dev->rc_non_fatal_counter); |
| 2000 | PCIE_DBG_FS(dev, "rc_fatal_counter: %lu\n", |
| 2001 | dev->rc_fatal_counter); |
| 2002 | PCIE_DBG_FS(dev, "ep_corr_counter: %lu\n", |
| 2003 | dev->ep_corr_counter); |
| 2004 | PCIE_DBG_FS(dev, "ep_non_fatal_counter: %lu\n", |
| 2005 | dev->ep_non_fatal_counter); |
| 2006 | PCIE_DBG_FS(dev, "ep_fatal_counter: %lu\n", |
| 2007 | dev->ep_fatal_counter); |
| 2008 | PCIE_DBG_FS(dev, "linkdown_counter: %lu\n", |
| 2009 | dev->linkdown_counter); |
| 2010 | PCIE_DBG_FS(dev, "wake_counter: %lu\n", |
| 2011 | dev->wake_counter); |
| 2012 | PCIE_DBG_FS(dev, "link_turned_on_counter: %lu\n", |
| 2013 | dev->link_turned_on_counter); |
| 2014 | PCIE_DBG_FS(dev, "link_turned_off_counter: %lu\n", |
| 2015 | dev->link_turned_off_counter); |
| 2016 | } |
| 2017 | |
| 2018 | static void msm_pcie_shadow_dump(struct msm_pcie_dev_t *dev, bool rc) |
| 2019 | { |
| 2020 | int i, j; |
| 2021 | u32 val = 0; |
| 2022 | u32 *shadow; |
| 2023 | |
| 2024 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 2025 | if (!rc && !dev->pcidev_table[i].bdf) |
| 2026 | break; |
| 2027 | if (rc) { |
| 2028 | shadow = dev->rc_shadow; |
| 2029 | } else { |
| 2030 | shadow = dev->ep_shadow[i]; |
| 2031 | PCIE_DBG_FS(dev, "PCIe Device: %02x:%02x.%01x\n", |
| 2032 | dev->pcidev_table[i].bdf >> 24, |
| 2033 | dev->pcidev_table[i].bdf >> 19 & 0x1f, |
| 2034 | dev->pcidev_table[i].bdf >> 16 & 0x07); |
| 2035 | } |
| 2036 | for (j = 0; j < PCIE_CONF_SPACE_DW; j++) { |
| 2037 | val = shadow[j]; |
| 2038 | if (val != PCIE_CLEAR) { |
| 2039 | PCIE_DBG_FS(dev, |
| 2040 | "PCIe: shadow_dw[%d]:cfg 0x%x:0x%x\n", |
| 2041 | j, j * 4, val); |
| 2042 | } |
| 2043 | } |
| 2044 | if (rc) |
| 2045 | break; |
| 2046 | } |
| 2047 | } |
| 2048 | |
| 2049 | static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, |
| 2050 | u32 testcase) |
| 2051 | { |
| 2052 | int ret, i; |
| 2053 | u32 base_sel_size = 0; |
| 2054 | u32 val = 0; |
| 2055 | u32 current_offset = 0; |
| 2056 | u32 ep_l1sub_ctrl1_offset = 0; |
| 2057 | u32 ep_l1sub_cap_reg1_offset = 0; |
| 2058 | u32 ep_link_ctrlstts_offset = 0; |
| 2059 | u32 ep_dev_ctrl2stts2_offset = 0; |
| 2060 | |
| 2061 | if (testcase >= 5 && testcase <= 10) { |
| 2062 | current_offset = |
| 2063 | readl_relaxed(dev->conf + PCIE_CAP_PTR_OFFSET) & 0xff; |
| 2064 | |
| 2065 | while (current_offset) { |
| 2066 | val = readl_relaxed(dev->conf + current_offset); |
| 2067 | if ((val & 0xff) == PCIE20_CAP_ID) { |
| 2068 | ep_link_ctrlstts_offset = current_offset + |
| 2069 | 0x10; |
| 2070 | ep_dev_ctrl2stts2_offset = current_offset + |
| 2071 | 0x28; |
| 2072 | break; |
| 2073 | } |
| 2074 | current_offset = (val >> 8) & 0xff; |
| 2075 | } |
| 2076 | |
| 2077 | if (!ep_link_ctrlstts_offset) |
| 2078 | PCIE_DBG(dev, |
| 2079 | "RC%d endpoint does not support PCIe capability registers\n", |
| 2080 | dev->rc_idx); |
| 2081 | else |
| 2082 | PCIE_DBG(dev, |
| 2083 | "RC%d: ep_link_ctrlstts_offset: 0x%x\n", |
| 2084 | dev->rc_idx, ep_link_ctrlstts_offset); |
| 2085 | } |
| 2086 | |
| 2087 | switch (testcase) { |
| 2088 | case 0: /* output status */ |
| 2089 | PCIE_DBG_FS(dev, "\n\nPCIe: Status for RC%d:\n", |
| 2090 | dev->rc_idx); |
| 2091 | msm_pcie_show_status(dev); |
| 2092 | break; |
| 2093 | case 1: /* disable link */ |
| 2094 | PCIE_DBG_FS(dev, |
| 2095 | "\n\nPCIe: RC%d: disable link\n\n", dev->rc_idx); |
| 2096 | ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0, |
| 2097 | dev->dev, NULL, |
| 2098 | MSM_PCIE_CONFIG_NO_CFG_RESTORE); |
| 2099 | if (ret) |
| 2100 | PCIE_DBG_FS(dev, "PCIe:%s:failed to disable link\n", |
| 2101 | __func__); |
| 2102 | else |
| 2103 | PCIE_DBG_FS(dev, "PCIe:%s:disabled link\n", |
| 2104 | __func__); |
| 2105 | break; |
| 2106 | case 2: /* enable link and recover config space for RC and EP */ |
| 2107 | PCIE_DBG_FS(dev, |
| 2108 | "\n\nPCIe: RC%d: enable link and recover config space\n\n", |
| 2109 | dev->rc_idx); |
| 2110 | ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0, |
| 2111 | dev->dev, NULL, |
| 2112 | MSM_PCIE_CONFIG_NO_CFG_RESTORE); |
| 2113 | if (ret) |
| 2114 | PCIE_DBG_FS(dev, "PCIe:%s:failed to enable link\n", |
| 2115 | __func__); |
| 2116 | else { |
| 2117 | PCIE_DBG_FS(dev, "PCIe:%s:enabled link\n", __func__); |
| 2118 | msm_pcie_recover_config(dev->dev); |
| 2119 | } |
| 2120 | break; |
| 2121 | case 3: /* |
| 2122 | * disable and enable link, recover config space for |
| 2123 | * RC and EP |
| 2124 | */ |
| 2125 | PCIE_DBG_FS(dev, |
| 2126 | "\n\nPCIe: RC%d: disable and enable link then recover config space\n\n", |
| 2127 | dev->rc_idx); |
| 2128 | ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0, |
| 2129 | dev->dev, NULL, |
| 2130 | MSM_PCIE_CONFIG_NO_CFG_RESTORE); |
| 2131 | if (ret) |
| 2132 | PCIE_DBG_FS(dev, "PCIe:%s:failed to disable link\n", |
| 2133 | __func__); |
| 2134 | else |
| 2135 | PCIE_DBG_FS(dev, "PCIe:%s:disabled link\n", __func__); |
| 2136 | ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0, |
| 2137 | dev->dev, NULL, |
| 2138 | MSM_PCIE_CONFIG_NO_CFG_RESTORE); |
| 2139 | if (ret) |
| 2140 | PCIE_DBG_FS(dev, "PCIe:%s:failed to enable link\n", |
| 2141 | __func__); |
| 2142 | else { |
| 2143 | PCIE_DBG_FS(dev, "PCIe:%s:enabled link\n", __func__); |
| 2144 | msm_pcie_recover_config(dev->dev); |
| 2145 | } |
| 2146 | break; |
| 2147 | case 4: /* dump shadow registers for RC and EP */ |
| 2148 | PCIE_DBG_FS(dev, |
| 2149 | "\n\nPCIe: RC%d: dumping RC shadow registers\n", |
| 2150 | dev->rc_idx); |
| 2151 | msm_pcie_shadow_dump(dev, true); |
| 2152 | |
| 2153 | PCIE_DBG_FS(dev, |
| 2154 | "\n\nPCIe: RC%d: dumping EP shadow registers\n", |
| 2155 | dev->rc_idx); |
| 2156 | msm_pcie_shadow_dump(dev, false); |
| 2157 | break; |
| 2158 | case 5: /* disable L0s */ |
| 2159 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L0s\n\n", |
| 2160 | dev->rc_idx); |
| 2161 | msm_pcie_write_mask(dev->dm_core + |
| 2162 | PCIE20_CAP_LINKCTRLSTATUS, |
| 2163 | BIT(0), 0); |
| 2164 | msm_pcie_write_mask(dev->conf + |
| 2165 | ep_link_ctrlstts_offset, |
| 2166 | BIT(0), 0); |
| 2167 | if (dev->shadow_en) { |
| 2168 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 2169 | readl_relaxed(dev->dm_core + |
| 2170 | PCIE20_CAP_LINKCTRLSTATUS); |
| 2171 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 2172 | readl_relaxed(dev->conf + |
| 2173 | ep_link_ctrlstts_offset); |
| 2174 | } |
| 2175 | PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2176 | readl_relaxed(dev->dm_core + |
| 2177 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 2178 | PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2179 | readl_relaxed(dev->conf + |
| 2180 | ep_link_ctrlstts_offset)); |
| 2181 | break; |
| 2182 | case 6: /* enable L0s */ |
| 2183 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L0s\n\n", |
| 2184 | dev->rc_idx); |
| 2185 | msm_pcie_write_mask(dev->dm_core + |
| 2186 | PCIE20_CAP_LINKCTRLSTATUS, |
| 2187 | 0, BIT(0)); |
| 2188 | msm_pcie_write_mask(dev->conf + |
| 2189 | ep_link_ctrlstts_offset, |
| 2190 | 0, BIT(0)); |
| 2191 | if (dev->shadow_en) { |
| 2192 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 2193 | readl_relaxed(dev->dm_core + |
| 2194 | PCIE20_CAP_LINKCTRLSTATUS); |
| 2195 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 2196 | readl_relaxed(dev->conf + |
| 2197 | ep_link_ctrlstts_offset); |
| 2198 | } |
| 2199 | PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2200 | readl_relaxed(dev->dm_core + |
| 2201 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 2202 | PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2203 | readl_relaxed(dev->conf + |
| 2204 | ep_link_ctrlstts_offset)); |
| 2205 | break; |
| 2206 | case 7: /* disable L1 */ |
| 2207 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L1\n\n", |
| 2208 | dev->rc_idx); |
| 2209 | msm_pcie_write_mask(dev->dm_core + |
| 2210 | PCIE20_CAP_LINKCTRLSTATUS, |
| 2211 | BIT(1), 0); |
| 2212 | msm_pcie_write_mask(dev->conf + |
| 2213 | ep_link_ctrlstts_offset, |
| 2214 | BIT(1), 0); |
| 2215 | if (dev->shadow_en) { |
| 2216 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 2217 | readl_relaxed(dev->dm_core + |
| 2218 | PCIE20_CAP_LINKCTRLSTATUS); |
| 2219 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 2220 | readl_relaxed(dev->conf + |
| 2221 | ep_link_ctrlstts_offset); |
| 2222 | } |
| 2223 | PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2224 | readl_relaxed(dev->dm_core + |
| 2225 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 2226 | PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2227 | readl_relaxed(dev->conf + |
| 2228 | ep_link_ctrlstts_offset)); |
| 2229 | break; |
| 2230 | case 8: /* enable L1 */ |
| 2231 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L1\n\n", |
| 2232 | dev->rc_idx); |
| 2233 | msm_pcie_write_mask(dev->dm_core + |
| 2234 | PCIE20_CAP_LINKCTRLSTATUS, |
| 2235 | 0, BIT(1)); |
| 2236 | msm_pcie_write_mask(dev->conf + |
| 2237 | ep_link_ctrlstts_offset, |
| 2238 | 0, BIT(1)); |
| 2239 | if (dev->shadow_en) { |
| 2240 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 2241 | readl_relaxed(dev->dm_core + |
| 2242 | PCIE20_CAP_LINKCTRLSTATUS); |
| 2243 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 2244 | readl_relaxed(dev->conf + |
| 2245 | ep_link_ctrlstts_offset); |
| 2246 | } |
| 2247 | PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2248 | readl_relaxed(dev->dm_core + |
| 2249 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 2250 | PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 2251 | readl_relaxed(dev->conf + |
| 2252 | ep_link_ctrlstts_offset)); |
| 2253 | break; |
| 2254 | case 9: /* disable L1ss */ |
| 2255 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L1ss\n\n", |
| 2256 | dev->rc_idx); |
| 2257 | current_offset = PCIE_EXT_CAP_OFFSET; |
| 2258 | while (current_offset) { |
| 2259 | val = readl_relaxed(dev->conf + current_offset); |
| 2260 | if ((val & 0xffff) == L1SUB_CAP_ID) { |
| 2261 | ep_l1sub_ctrl1_offset = |
| 2262 | current_offset + 0x8; |
| 2263 | break; |
| 2264 | } |
| 2265 | current_offset = val >> 20; |
| 2266 | } |
| 2267 | if (!ep_l1sub_ctrl1_offset) { |
| 2268 | PCIE_DBG_FS(dev, |
| 2269 | "PCIe: RC%d endpoint does not support l1ss registers\n", |
| 2270 | dev->rc_idx); |
| 2271 | break; |
| 2272 | } |
| 2273 | |
| 2274 | PCIE_DBG_FS(dev, "PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n", |
| 2275 | dev->rc_idx, ep_l1sub_ctrl1_offset); |
| 2276 | |
| 2277 | msm_pcie_write_reg_field(dev->dm_core, |
| 2278 | PCIE20_L1SUB_CONTROL1, |
| 2279 | 0xf, 0); |
| 2280 | msm_pcie_write_mask(dev->dm_core + |
| 2281 | PCIE20_DEVICE_CONTROL2_STATUS2, |
| 2282 | BIT(10), 0); |
| 2283 | msm_pcie_write_reg_field(dev->conf, |
| 2284 | ep_l1sub_ctrl1_offset, |
| 2285 | 0xf, 0); |
| 2286 | msm_pcie_write_mask(dev->conf + |
| 2287 | ep_dev_ctrl2stts2_offset, |
| 2288 | BIT(10), 0); |
| 2289 | if (dev->shadow_en) { |
| 2290 | dev->rc_shadow[PCIE20_L1SUB_CONTROL1 / 4] = |
| 2291 | readl_relaxed(dev->dm_core + |
| 2292 | PCIE20_L1SUB_CONTROL1); |
| 2293 | dev->rc_shadow[PCIE20_DEVICE_CONTROL2_STATUS2 / 4] = |
| 2294 | readl_relaxed(dev->dm_core + |
| 2295 | PCIE20_DEVICE_CONTROL2_STATUS2); |
| 2296 | dev->ep_shadow[0][ep_l1sub_ctrl1_offset / 4] = |
| 2297 | readl_relaxed(dev->conf + |
| 2298 | ep_l1sub_ctrl1_offset); |
| 2299 | dev->ep_shadow[0][ep_dev_ctrl2stts2_offset / 4] = |
| 2300 | readl_relaxed(dev->conf + |
| 2301 | ep_dev_ctrl2stts2_offset); |
| 2302 | } |
| 2303 | PCIE_DBG_FS(dev, "PCIe: RC's L1SUB_CONTROL1:0x%x\n", |
| 2304 | readl_relaxed(dev->dm_core + |
| 2305 | PCIE20_L1SUB_CONTROL1)); |
| 2306 | PCIE_DBG_FS(dev, "PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 2307 | readl_relaxed(dev->dm_core + |
| 2308 | PCIE20_DEVICE_CONTROL2_STATUS2)); |
| 2309 | PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CONTROL1:0x%x\n", |
| 2310 | readl_relaxed(dev->conf + |
| 2311 | ep_l1sub_ctrl1_offset)); |
| 2312 | PCIE_DBG_FS(dev, "PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 2313 | readl_relaxed(dev->conf + |
| 2314 | ep_dev_ctrl2stts2_offset)); |
| 2315 | break; |
| 2316 | case 10: /* enable L1ss */ |
| 2317 | PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L1ss\n\n", |
| 2318 | dev->rc_idx); |
| 2319 | current_offset = PCIE_EXT_CAP_OFFSET; |
| 2320 | while (current_offset) { |
| 2321 | val = readl_relaxed(dev->conf + current_offset); |
| 2322 | if ((val & 0xffff) == L1SUB_CAP_ID) { |
| 2323 | ep_l1sub_cap_reg1_offset = |
| 2324 | current_offset + 0x4; |
| 2325 | ep_l1sub_ctrl1_offset = |
| 2326 | current_offset + 0x8; |
| 2327 | break; |
| 2328 | } |
| 2329 | current_offset = val >> 20; |
| 2330 | } |
| 2331 | if (!ep_l1sub_ctrl1_offset) { |
| 2332 | PCIE_DBG_FS(dev, |
| 2333 | "PCIe: RC%d endpoint does not support l1ss registers\n", |
| 2334 | dev->rc_idx); |
| 2335 | break; |
| 2336 | } |
| 2337 | |
| 2338 | val = readl_relaxed(dev->conf + |
| 2339 | ep_l1sub_cap_reg1_offset); |
| 2340 | |
| 2341 | PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CAPABILITY_REG_1: 0x%x\n", |
| 2342 | val); |
| 2343 | PCIE_DBG_FS(dev, "PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n", |
| 2344 | dev->rc_idx, ep_l1sub_ctrl1_offset); |
| 2345 | |
| 2346 | val &= 0xf; |
| 2347 | |
| 2348 | msm_pcie_write_reg_field(dev->dm_core, |
| 2349 | PCIE20_L1SUB_CONTROL1, |
| 2350 | 0xf, val); |
| 2351 | msm_pcie_write_mask(dev->dm_core + |
| 2352 | PCIE20_DEVICE_CONTROL2_STATUS2, |
| 2353 | 0, BIT(10)); |
| 2354 | msm_pcie_write_reg_field(dev->conf, |
| 2355 | ep_l1sub_ctrl1_offset, |
| 2356 | 0xf, val); |
| 2357 | msm_pcie_write_mask(dev->conf + |
| 2358 | ep_dev_ctrl2stts2_offset, |
| 2359 | 0, BIT(10)); |
| 2360 | if (dev->shadow_en) { |
| 2361 | dev->rc_shadow[PCIE20_L1SUB_CONTROL1 / 4] = |
| 2362 | readl_relaxed(dev->dm_core + |
| 2363 | PCIE20_L1SUB_CONTROL1); |
| 2364 | dev->rc_shadow[PCIE20_DEVICE_CONTROL2_STATUS2 / 4] = |
| 2365 | readl_relaxed(dev->dm_core + |
| 2366 | PCIE20_DEVICE_CONTROL2_STATUS2); |
| 2367 | dev->ep_shadow[0][ep_l1sub_ctrl1_offset / 4] = |
| 2368 | readl_relaxed(dev->conf + |
| 2369 | ep_l1sub_ctrl1_offset); |
| 2370 | dev->ep_shadow[0][ep_dev_ctrl2stts2_offset / 4] = |
| 2371 | readl_relaxed(dev->conf + |
| 2372 | ep_dev_ctrl2stts2_offset); |
| 2373 | } |
| 2374 | PCIE_DBG_FS(dev, "PCIe: RC's L1SUB_CONTROL1:0x%x\n", |
| 2375 | readl_relaxed(dev->dm_core + |
| 2376 | PCIE20_L1SUB_CONTROL1)); |
| 2377 | PCIE_DBG_FS(dev, "PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 2378 | readl_relaxed(dev->dm_core + |
| 2379 | PCIE20_DEVICE_CONTROL2_STATUS2)); |
| 2380 | PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CONTROL1:0x%x\n", |
| 2381 | readl_relaxed(dev->conf + |
| 2382 | ep_l1sub_ctrl1_offset)); |
| 2383 | PCIE_DBG_FS(dev, "PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 2384 | readl_relaxed(dev->conf + |
| 2385 | ep_dev_ctrl2stts2_offset)); |
| 2386 | break; |
| 2387 | case 11: /* enumerate PCIe */ |
| 2388 | PCIE_DBG_FS(dev, "\n\nPCIe: attempting to enumerate RC%d\n\n", |
| 2389 | dev->rc_idx); |
| 2390 | if (dev->enumerated) |
| 2391 | PCIE_DBG_FS(dev, "PCIe: RC%d is already enumerated\n", |
| 2392 | dev->rc_idx); |
| 2393 | else { |
| 2394 | if (!msm_pcie_enumerate(dev->rc_idx)) |
| 2395 | PCIE_DBG_FS(dev, |
| 2396 | "PCIe: RC%d is successfully enumerated\n", |
| 2397 | dev->rc_idx); |
| 2398 | else |
| 2399 | PCIE_DBG_FS(dev, |
| 2400 | "PCIe: RC%d enumeration failed\n", |
| 2401 | dev->rc_idx); |
| 2402 | } |
| 2403 | break; |
| 2404 | case 12: /* write a value to a register */ |
| 2405 | PCIE_DBG_FS(dev, |
| 2406 | "\n\nPCIe: RC%d: writing a value to a register\n\n", |
| 2407 | dev->rc_idx); |
| 2408 | |
| 2409 | if (!base_sel) { |
| 2410 | PCIE_DBG_FS(dev, "Invalid base_sel: 0x%x\n", base_sel); |
| 2411 | break; |
| 2412 | } |
| 2413 | |
| 2414 | PCIE_DBG_FS(dev, |
| 2415 | "base: %s: 0x%p\nwr_offset: 0x%x\nwr_mask: 0x%x\nwr_value: 0x%x\n", |
| 2416 | dev->res[base_sel - 1].name, |
| 2417 | dev->res[base_sel - 1].base, |
| 2418 | wr_offset, wr_mask, wr_value); |
| 2419 | |
Tony Truong | 9574738 | 2017-01-06 14:03:03 -0800 | [diff] [blame^] | 2420 | base_sel_size = resource_size(dev->res[base_sel - 1].resource); |
| 2421 | |
| 2422 | if (wr_offset > base_sel_size - 4 || |
| 2423 | msm_pcie_check_align(dev, wr_offset)) |
| 2424 | PCIE_DBG_FS(dev, |
| 2425 | "PCIe: RC%d: Invalid wr_offset: 0x%x. wr_offset should be no more than 0x%x\n", |
| 2426 | dev->rc_idx, wr_offset, base_sel_size - 4); |
| 2427 | else |
| 2428 | msm_pcie_write_reg_field(dev->res[base_sel - 1].base, |
| 2429 | wr_offset, wr_mask, wr_value); |
Tony Truong | 349ee49 | 2014-10-01 17:35:56 -0700 | [diff] [blame] | 2430 | |
| 2431 | break; |
| 2432 | case 13: /* dump all registers of base_sel */ |
| 2433 | if (!base_sel) { |
| 2434 | PCIE_DBG_FS(dev, "Invalid base_sel: 0x%x\n", base_sel); |
| 2435 | break; |
| 2436 | } else if (base_sel - 1 == MSM_PCIE_RES_PARF) { |
| 2437 | pcie_parf_dump(dev); |
| 2438 | break; |
| 2439 | } else if (base_sel - 1 == MSM_PCIE_RES_PHY) { |
| 2440 | pcie_phy_dump(dev); |
| 2441 | break; |
| 2442 | } else if (base_sel - 1 == MSM_PCIE_RES_CONF) { |
| 2443 | base_sel_size = 0x1000; |
| 2444 | } else { |
| 2445 | base_sel_size = resource_size( |
| 2446 | dev->res[base_sel - 1].resource); |
| 2447 | } |
| 2448 | |
| 2449 | PCIE_DBG_FS(dev, "\n\nPCIe: Dumping %s Registers for RC%d\n\n", |
| 2450 | dev->res[base_sel - 1].name, dev->rc_idx); |
| 2451 | |
| 2452 | for (i = 0; i < base_sel_size; i += 32) { |
| 2453 | PCIE_DBG_FS(dev, |
| 2454 | "0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n", |
| 2455 | i, readl_relaxed(dev->res[base_sel - 1].base + i), |
| 2456 | readl_relaxed(dev->res[base_sel - 1].base + (i + 4)), |
| 2457 | readl_relaxed(dev->res[base_sel - 1].base + (i + 8)), |
| 2458 | readl_relaxed(dev->res[base_sel - 1].base + (i + 12)), |
| 2459 | readl_relaxed(dev->res[base_sel - 1].base + (i + 16)), |
| 2460 | readl_relaxed(dev->res[base_sel - 1].base + (i + 20)), |
| 2461 | readl_relaxed(dev->res[base_sel - 1].base + (i + 24)), |
| 2462 | readl_relaxed(dev->res[base_sel - 1].base + (i + 28))); |
| 2463 | } |
| 2464 | break; |
| 2465 | default: |
| 2466 | PCIE_DBG_FS(dev, "Invalid testcase: %d.\n", testcase); |
| 2467 | break; |
| 2468 | } |
| 2469 | } |
| 2470 | |
| 2471 | int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base, |
| 2472 | u32 offset, u32 mask, u32 value) |
| 2473 | { |
| 2474 | int ret = 0; |
| 2475 | struct msm_pcie_dev_t *pdev = NULL; |
| 2476 | |
| 2477 | if (!dev) { |
| 2478 | pr_err("PCIe: the input pci dev is NULL.\n"); |
| 2479 | return -ENODEV; |
| 2480 | } |
| 2481 | |
| 2482 | if (option == 12 || option == 13) { |
| 2483 | if (!base || base > 5) { |
| 2484 | PCIE_DBG_FS(pdev, "Invalid base_sel: 0x%x\n", base); |
| 2485 | PCIE_DBG_FS(pdev, |
| 2486 | "PCIe: base_sel is still 0x%x\n", base_sel); |
| 2487 | return -EINVAL; |
| 2488 | } |
| 2489 | |
| 2490 | base_sel = base; |
| 2491 | PCIE_DBG_FS(pdev, "PCIe: base_sel is now 0x%x\n", base_sel); |
| 2492 | |
| 2493 | if (option == 12) { |
| 2494 | wr_offset = offset; |
| 2495 | wr_mask = mask; |
| 2496 | wr_value = value; |
| 2497 | |
| 2498 | PCIE_DBG_FS(pdev, |
| 2499 | "PCIe: wr_offset is now 0x%x\n", wr_offset); |
| 2500 | PCIE_DBG_FS(pdev, |
| 2501 | "PCIe: wr_mask is now 0x%x\n", wr_mask); |
| 2502 | PCIE_DBG_FS(pdev, |
| 2503 | "PCIe: wr_value is now 0x%x\n", wr_value); |
| 2504 | } |
| 2505 | } |
| 2506 | |
| 2507 | pdev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 2508 | rc_sel = 1 << pdev->rc_idx; |
| 2509 | |
| 2510 | msm_pcie_sel_debug_testcase(pdev, option); |
| 2511 | |
| 2512 | return ret; |
| 2513 | } |
| 2514 | EXPORT_SYMBOL(msm_pcie_debug_info); |
| 2515 | |
| 2516 | #ifdef CONFIG_DEBUG_FS |
| 2517 | static struct dentry *dent_msm_pcie; |
| 2518 | static struct dentry *dfile_rc_sel; |
| 2519 | static struct dentry *dfile_case; |
| 2520 | static struct dentry *dfile_base_sel; |
| 2521 | static struct dentry *dfile_linkdown_panic; |
| 2522 | static struct dentry *dfile_wr_offset; |
| 2523 | static struct dentry *dfile_wr_mask; |
| 2524 | static struct dentry *dfile_wr_value; |
| 2525 | static struct dentry *dfile_ep_wakeirq; |
| 2526 | static struct dentry *dfile_aer_enable; |
| 2527 | static struct dentry *dfile_corr_counter_limit; |
| 2528 | |
| 2529 | static u32 rc_sel_max; |
| 2530 | |
| 2531 | static ssize_t msm_pcie_cmd_debug(struct file *file, |
| 2532 | const char __user *buf, |
| 2533 | size_t count, loff_t *ppos) |
| 2534 | { |
| 2535 | unsigned long ret; |
| 2536 | char str[MAX_MSG_LEN]; |
| 2537 | unsigned int testcase = 0; |
| 2538 | int i; |
| 2539 | |
| 2540 | memset(str, 0, sizeof(str)); |
| 2541 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2542 | if (ret) |
| 2543 | return -EFAULT; |
| 2544 | |
| 2545 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2546 | testcase = (testcase * 10) + (str[i] - '0'); |
| 2547 | |
| 2548 | if (!rc_sel) |
| 2549 | rc_sel = 1; |
| 2550 | |
| 2551 | pr_alert("PCIe: TEST: %d\n", testcase); |
| 2552 | |
| 2553 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 2554 | if (!((rc_sel >> i) & 0x1)) |
| 2555 | continue; |
| 2556 | msm_pcie_sel_debug_testcase(&msm_pcie_dev[i], testcase); |
| 2557 | } |
| 2558 | |
| 2559 | return count; |
| 2560 | } |
| 2561 | |
| 2562 | const struct file_operations msm_pcie_cmd_debug_ops = { |
| 2563 | .write = msm_pcie_cmd_debug, |
| 2564 | }; |
| 2565 | |
| 2566 | static ssize_t msm_pcie_set_rc_sel(struct file *file, |
| 2567 | const char __user *buf, |
| 2568 | size_t count, loff_t *ppos) |
| 2569 | { |
| 2570 | unsigned long ret; |
| 2571 | char str[MAX_MSG_LEN]; |
| 2572 | int i; |
| 2573 | u32 new_rc_sel = 0; |
| 2574 | |
| 2575 | memset(str, 0, sizeof(str)); |
| 2576 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2577 | if (ret) |
| 2578 | return -EFAULT; |
| 2579 | |
| 2580 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2581 | new_rc_sel = (new_rc_sel * 10) + (str[i] - '0'); |
| 2582 | |
| 2583 | if ((!new_rc_sel) || (new_rc_sel > rc_sel_max)) { |
| 2584 | pr_alert("PCIe: invalid value for rc_sel: 0x%x\n", new_rc_sel); |
| 2585 | pr_alert("PCIe: rc_sel is still 0x%x\n", rc_sel ? rc_sel : 0x1); |
| 2586 | } else { |
| 2587 | rc_sel = new_rc_sel; |
| 2588 | pr_alert("PCIe: rc_sel is now: 0x%x\n", rc_sel); |
| 2589 | } |
| 2590 | |
| 2591 | pr_alert("PCIe: the following RC(s) will be tested:\n"); |
| 2592 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 2593 | if (!rc_sel) { |
| 2594 | pr_alert("RC %d\n", i); |
| 2595 | break; |
| 2596 | } else if (rc_sel & (1 << i)) { |
| 2597 | pr_alert("RC %d\n", i); |
| 2598 | } |
| 2599 | } |
| 2600 | |
| 2601 | return count; |
| 2602 | } |
| 2603 | |
| 2604 | const struct file_operations msm_pcie_rc_sel_ops = { |
| 2605 | .write = msm_pcie_set_rc_sel, |
| 2606 | }; |
| 2607 | |
| 2608 | static ssize_t msm_pcie_set_base_sel(struct file *file, |
| 2609 | const char __user *buf, |
| 2610 | size_t count, loff_t *ppos) |
| 2611 | { |
| 2612 | unsigned long ret; |
| 2613 | char str[MAX_MSG_LEN]; |
| 2614 | int i; |
| 2615 | u32 new_base_sel = 0; |
| 2616 | char *base_sel_name; |
| 2617 | |
| 2618 | memset(str, 0, sizeof(str)); |
| 2619 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2620 | if (ret) |
| 2621 | return -EFAULT; |
| 2622 | |
| 2623 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2624 | new_base_sel = (new_base_sel * 10) + (str[i] - '0'); |
| 2625 | |
| 2626 | if (!new_base_sel || new_base_sel > 5) { |
| 2627 | pr_alert("PCIe: invalid value for base_sel: 0x%x\n", |
| 2628 | new_base_sel); |
| 2629 | pr_alert("PCIe: base_sel is still 0x%x\n", base_sel); |
| 2630 | } else { |
| 2631 | base_sel = new_base_sel; |
| 2632 | pr_alert("PCIe: base_sel is now 0x%x\n", base_sel); |
| 2633 | } |
| 2634 | |
| 2635 | switch (base_sel) { |
| 2636 | case 1: |
| 2637 | base_sel_name = "PARF"; |
| 2638 | break; |
| 2639 | case 2: |
| 2640 | base_sel_name = "PHY"; |
| 2641 | break; |
| 2642 | case 3: |
| 2643 | base_sel_name = "RC CONFIG SPACE"; |
| 2644 | break; |
| 2645 | case 4: |
| 2646 | base_sel_name = "ELBI"; |
| 2647 | break; |
| 2648 | case 5: |
| 2649 | base_sel_name = "EP CONFIG SPACE"; |
| 2650 | break; |
| 2651 | default: |
| 2652 | base_sel_name = "INVALID"; |
| 2653 | break; |
| 2654 | } |
| 2655 | |
| 2656 | pr_alert("%s\n", base_sel_name); |
| 2657 | |
| 2658 | return count; |
| 2659 | } |
| 2660 | |
| 2661 | const struct file_operations msm_pcie_base_sel_ops = { |
| 2662 | .write = msm_pcie_set_base_sel, |
| 2663 | }; |
| 2664 | |
| 2665 | static ssize_t msm_pcie_set_linkdown_panic(struct file *file, |
| 2666 | const char __user *buf, |
| 2667 | size_t count, loff_t *ppos) |
| 2668 | { |
| 2669 | unsigned long ret; |
| 2670 | char str[MAX_MSG_LEN]; |
| 2671 | u32 new_linkdown_panic = 0; |
| 2672 | int i; |
| 2673 | |
| 2674 | memset(str, 0, sizeof(str)); |
| 2675 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2676 | if (ret) |
| 2677 | return -EFAULT; |
| 2678 | |
| 2679 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2680 | new_linkdown_panic = (new_linkdown_panic * 10) + (str[i] - '0'); |
| 2681 | |
| 2682 | if (new_linkdown_panic <= 1) { |
| 2683 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 2684 | if (!rc_sel) { |
| 2685 | msm_pcie_dev[0].linkdown_panic = |
| 2686 | new_linkdown_panic; |
| 2687 | PCIE_DBG_FS(&msm_pcie_dev[0], |
| 2688 | "PCIe: RC0: linkdown_panic is now %d\n", |
| 2689 | msm_pcie_dev[0].linkdown_panic); |
| 2690 | break; |
| 2691 | } else if (rc_sel & (1 << i)) { |
| 2692 | msm_pcie_dev[i].linkdown_panic = |
| 2693 | new_linkdown_panic; |
| 2694 | PCIE_DBG_FS(&msm_pcie_dev[i], |
| 2695 | "PCIe: RC%d: linkdown_panic is now %d\n", |
| 2696 | i, msm_pcie_dev[i].linkdown_panic); |
| 2697 | } |
| 2698 | } |
| 2699 | } else { |
| 2700 | pr_err("PCIe: Invalid input for linkdown_panic: %d. Please enter 0 or 1.\n", |
| 2701 | new_linkdown_panic); |
| 2702 | } |
| 2703 | |
| 2704 | return count; |
| 2705 | } |
| 2706 | |
| 2707 | const struct file_operations msm_pcie_linkdown_panic_ops = { |
| 2708 | .write = msm_pcie_set_linkdown_panic, |
| 2709 | }; |
| 2710 | |
| 2711 | static ssize_t msm_pcie_set_wr_offset(struct file *file, |
| 2712 | const char __user *buf, |
| 2713 | size_t count, loff_t *ppos) |
| 2714 | { |
| 2715 | unsigned long ret; |
| 2716 | char str[MAX_MSG_LEN]; |
| 2717 | int i; |
| 2718 | |
| 2719 | memset(str, 0, sizeof(str)); |
| 2720 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2721 | if (ret) |
| 2722 | return -EFAULT; |
| 2723 | |
| 2724 | wr_offset = 0; |
| 2725 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2726 | wr_offset = (wr_offset * 10) + (str[i] - '0'); |
| 2727 | |
| 2728 | pr_alert("PCIe: wr_offset is now 0x%x\n", wr_offset); |
| 2729 | |
| 2730 | return count; |
| 2731 | } |
| 2732 | |
| 2733 | const struct file_operations msm_pcie_wr_offset_ops = { |
| 2734 | .write = msm_pcie_set_wr_offset, |
| 2735 | }; |
| 2736 | |
| 2737 | static ssize_t msm_pcie_set_wr_mask(struct file *file, |
| 2738 | const char __user *buf, |
| 2739 | size_t count, loff_t *ppos) |
| 2740 | { |
| 2741 | unsigned long ret; |
| 2742 | char str[MAX_MSG_LEN]; |
| 2743 | int i; |
| 2744 | |
| 2745 | memset(str, 0, sizeof(str)); |
| 2746 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2747 | if (ret) |
| 2748 | return -EFAULT; |
| 2749 | |
| 2750 | wr_mask = 0; |
| 2751 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2752 | wr_mask = (wr_mask * 10) + (str[i] - '0'); |
| 2753 | |
| 2754 | pr_alert("PCIe: wr_mask is now 0x%x\n", wr_mask); |
| 2755 | |
| 2756 | return count; |
| 2757 | } |
| 2758 | |
| 2759 | const struct file_operations msm_pcie_wr_mask_ops = { |
| 2760 | .write = msm_pcie_set_wr_mask, |
| 2761 | }; |
| 2762 | static ssize_t msm_pcie_set_wr_value(struct file *file, |
| 2763 | const char __user *buf, |
| 2764 | size_t count, loff_t *ppos) |
| 2765 | { |
| 2766 | unsigned long ret; |
| 2767 | char str[MAX_MSG_LEN]; |
| 2768 | int i; |
| 2769 | |
| 2770 | memset(str, 0, sizeof(str)); |
| 2771 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2772 | if (ret) |
| 2773 | return -EFAULT; |
| 2774 | |
| 2775 | wr_value = 0; |
| 2776 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2777 | wr_value = (wr_value * 10) + (str[i] - '0'); |
| 2778 | |
| 2779 | pr_alert("PCIe: wr_value is now 0x%x\n", wr_value); |
| 2780 | |
| 2781 | return count; |
| 2782 | } |
| 2783 | |
| 2784 | const struct file_operations msm_pcie_wr_value_ops = { |
| 2785 | .write = msm_pcie_set_wr_value, |
| 2786 | }; |
| 2787 | |
| 2788 | static ssize_t msm_pcie_set_ep_wakeirq(struct file *file, |
| 2789 | const char __user *buf, |
| 2790 | size_t count, loff_t *ppos) |
| 2791 | { |
| 2792 | unsigned long ret; |
| 2793 | char str[MAX_MSG_LEN]; |
| 2794 | u32 new_ep_wakeirq = 0; |
| 2795 | int i; |
| 2796 | |
| 2797 | memset(str, 0, sizeof(str)); |
| 2798 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2799 | if (ret) |
| 2800 | return -EFAULT; |
| 2801 | |
| 2802 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2803 | new_ep_wakeirq = (new_ep_wakeirq * 10) + (str[i] - '0'); |
| 2804 | |
| 2805 | if (new_ep_wakeirq <= 1) { |
| 2806 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 2807 | if (!rc_sel) { |
| 2808 | msm_pcie_dev[0].ep_wakeirq = new_ep_wakeirq; |
| 2809 | PCIE_DBG_FS(&msm_pcie_dev[0], |
| 2810 | "PCIe: RC0: ep_wakeirq is now %d\n", |
| 2811 | msm_pcie_dev[0].ep_wakeirq); |
| 2812 | break; |
| 2813 | } else if (rc_sel & (1 << i)) { |
| 2814 | msm_pcie_dev[i].ep_wakeirq = new_ep_wakeirq; |
| 2815 | PCIE_DBG_FS(&msm_pcie_dev[i], |
| 2816 | "PCIe: RC%d: ep_wakeirq is now %d\n", |
| 2817 | i, msm_pcie_dev[i].ep_wakeirq); |
| 2818 | } |
| 2819 | } |
| 2820 | } else { |
| 2821 | pr_err("PCIe: Invalid input for ep_wakeirq: %d. Please enter 0 or 1.\n", |
| 2822 | new_ep_wakeirq); |
| 2823 | } |
| 2824 | |
| 2825 | return count; |
| 2826 | } |
| 2827 | |
| 2828 | const struct file_operations msm_pcie_ep_wakeirq_ops = { |
| 2829 | .write = msm_pcie_set_ep_wakeirq, |
| 2830 | }; |
| 2831 | |
| 2832 | static ssize_t msm_pcie_set_aer_enable(struct file *file, |
| 2833 | const char __user *buf, |
| 2834 | size_t count, loff_t *ppos) |
| 2835 | { |
| 2836 | unsigned long ret; |
| 2837 | char str[MAX_MSG_LEN]; |
| 2838 | u32 new_aer_enable = 0; |
| 2839 | u32 temp_rc_sel; |
| 2840 | int i; |
| 2841 | |
| 2842 | memset(str, 0, sizeof(str)); |
| 2843 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2844 | if (ret) |
| 2845 | return -EFAULT; |
| 2846 | |
| 2847 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2848 | new_aer_enable = (new_aer_enable * 10) + (str[i] - '0'); |
| 2849 | |
| 2850 | if (new_aer_enable > 1) { |
| 2851 | pr_err( |
| 2852 | "PCIe: Invalid input for aer_enable: %d. Please enter 0 or 1.\n", |
| 2853 | new_aer_enable); |
| 2854 | return count; |
| 2855 | } |
| 2856 | |
| 2857 | if (rc_sel) |
| 2858 | temp_rc_sel = rc_sel; |
| 2859 | else |
| 2860 | temp_rc_sel = 0x1; |
| 2861 | |
| 2862 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 2863 | if (temp_rc_sel & (1 << i)) { |
| 2864 | msm_pcie_dev[i].aer_enable = new_aer_enable; |
| 2865 | PCIE_DBG_FS(&msm_pcie_dev[i], |
| 2866 | "PCIe: RC%d: aer_enable is now %d\n", |
| 2867 | i, msm_pcie_dev[i].aer_enable); |
| 2868 | |
| 2869 | msm_pcie_write_mask(msm_pcie_dev[i].dm_core + |
| 2870 | PCIE20_BRIDGE_CTRL, |
| 2871 | new_aer_enable ? 0 : BIT(16), |
| 2872 | new_aer_enable ? BIT(16) : 0); |
| 2873 | |
| 2874 | PCIE_DBG_FS(&msm_pcie_dev[i], |
| 2875 | "RC%d: PCIE20_BRIDGE_CTRL: 0x%x\n", i, |
| 2876 | readl_relaxed(msm_pcie_dev[i].dm_core + |
| 2877 | PCIE20_BRIDGE_CTRL)); |
| 2878 | } |
| 2879 | } |
| 2880 | |
| 2881 | return count; |
| 2882 | } |
| 2883 | |
| 2884 | const struct file_operations msm_pcie_aer_enable_ops = { |
| 2885 | .write = msm_pcie_set_aer_enable, |
| 2886 | }; |
| 2887 | |
| 2888 | static ssize_t msm_pcie_set_corr_counter_limit(struct file *file, |
| 2889 | const char __user *buf, |
| 2890 | size_t count, loff_t *ppos) |
| 2891 | { |
| 2892 | unsigned long ret; |
| 2893 | char str[MAX_MSG_LEN]; |
| 2894 | int i; |
| 2895 | |
| 2896 | memset(str, 0, sizeof(str)); |
| 2897 | ret = copy_from_user(str, buf, sizeof(str)); |
| 2898 | if (ret) |
| 2899 | return -EFAULT; |
| 2900 | |
| 2901 | corr_counter_limit = 0; |
| 2902 | for (i = 0; i < sizeof(str) && (str[i] >= '0') && (str[i] <= '9'); ++i) |
| 2903 | corr_counter_limit = (corr_counter_limit * 10) + (str[i] - '0'); |
| 2904 | |
| 2905 | pr_info("PCIe: corr_counter_limit is now %lu\n", corr_counter_limit); |
| 2906 | |
| 2907 | return count; |
| 2908 | } |
| 2909 | |
| 2910 | const struct file_operations msm_pcie_corr_counter_limit_ops = { |
| 2911 | .write = msm_pcie_set_corr_counter_limit, |
| 2912 | }; |
| 2913 | |
| 2914 | static void msm_pcie_debugfs_init(void) |
| 2915 | { |
| 2916 | rc_sel_max = (0x1 << MAX_RC_NUM) - 1; |
| 2917 | wr_mask = 0xffffffff; |
| 2918 | |
| 2919 | dent_msm_pcie = debugfs_create_dir("pci-msm", 0); |
| 2920 | if (IS_ERR(dent_msm_pcie)) { |
| 2921 | pr_err("PCIe: fail to create the folder for debug_fs.\n"); |
| 2922 | return; |
| 2923 | } |
| 2924 | |
| 2925 | dfile_rc_sel = debugfs_create_file("rc_sel", 0664, |
| 2926 | dent_msm_pcie, 0, |
| 2927 | &msm_pcie_rc_sel_ops); |
| 2928 | if (!dfile_rc_sel || IS_ERR(dfile_rc_sel)) { |
| 2929 | pr_err("PCIe: fail to create the file for debug_fs rc_sel.\n"); |
| 2930 | goto rc_sel_error; |
| 2931 | } |
| 2932 | |
| 2933 | dfile_case = debugfs_create_file("case", 0664, |
| 2934 | dent_msm_pcie, 0, |
| 2935 | &msm_pcie_cmd_debug_ops); |
| 2936 | if (!dfile_case || IS_ERR(dfile_case)) { |
| 2937 | pr_err("PCIe: fail to create the file for debug_fs case.\n"); |
| 2938 | goto case_error; |
| 2939 | } |
| 2940 | |
| 2941 | dfile_base_sel = debugfs_create_file("base_sel", 0664, |
| 2942 | dent_msm_pcie, 0, |
| 2943 | &msm_pcie_base_sel_ops); |
| 2944 | if (!dfile_base_sel || IS_ERR(dfile_base_sel)) { |
| 2945 | pr_err("PCIe: fail to create the file for debug_fs base_sel.\n"); |
| 2946 | goto base_sel_error; |
| 2947 | } |
| 2948 | |
| 2949 | dfile_linkdown_panic = debugfs_create_file("linkdown_panic", 0644, |
| 2950 | dent_msm_pcie, 0, |
| 2951 | &msm_pcie_linkdown_panic_ops); |
| 2952 | if (!dfile_linkdown_panic || IS_ERR(dfile_linkdown_panic)) { |
| 2953 | pr_err("PCIe: fail to create the file for debug_fs linkdown_panic.\n"); |
| 2954 | goto linkdown_panic_error; |
| 2955 | } |
| 2956 | |
| 2957 | dfile_wr_offset = debugfs_create_file("wr_offset", 0664, |
| 2958 | dent_msm_pcie, 0, |
| 2959 | &msm_pcie_wr_offset_ops); |
| 2960 | if (!dfile_wr_offset || IS_ERR(dfile_wr_offset)) { |
| 2961 | pr_err("PCIe: fail to create the file for debug_fs wr_offset.\n"); |
| 2962 | goto wr_offset_error; |
| 2963 | } |
| 2964 | |
| 2965 | dfile_wr_mask = debugfs_create_file("wr_mask", 0664, |
| 2966 | dent_msm_pcie, 0, |
| 2967 | &msm_pcie_wr_mask_ops); |
| 2968 | if (!dfile_wr_mask || IS_ERR(dfile_wr_mask)) { |
| 2969 | pr_err("PCIe: fail to create the file for debug_fs wr_mask.\n"); |
| 2970 | goto wr_mask_error; |
| 2971 | } |
| 2972 | |
| 2973 | dfile_wr_value = debugfs_create_file("wr_value", 0664, |
| 2974 | dent_msm_pcie, 0, |
| 2975 | &msm_pcie_wr_value_ops); |
| 2976 | if (!dfile_wr_value || IS_ERR(dfile_wr_value)) { |
| 2977 | pr_err("PCIe: fail to create the file for debug_fs wr_value.\n"); |
| 2978 | goto wr_value_error; |
| 2979 | } |
| 2980 | |
| 2981 | dfile_ep_wakeirq = debugfs_create_file("ep_wakeirq", 0664, |
| 2982 | dent_msm_pcie, 0, |
| 2983 | &msm_pcie_ep_wakeirq_ops); |
| 2984 | if (!dfile_ep_wakeirq || IS_ERR(dfile_ep_wakeirq)) { |
| 2985 | pr_err("PCIe: fail to create the file for debug_fs ep_wakeirq.\n"); |
| 2986 | goto ep_wakeirq_error; |
| 2987 | } |
| 2988 | |
| 2989 | dfile_aer_enable = debugfs_create_file("aer_enable", 0664, |
| 2990 | dent_msm_pcie, 0, |
| 2991 | &msm_pcie_aer_enable_ops); |
| 2992 | if (!dfile_aer_enable || IS_ERR(dfile_aer_enable)) { |
| 2993 | pr_err("PCIe: fail to create the file for debug_fs aer_enable.\n"); |
| 2994 | goto aer_enable_error; |
| 2995 | } |
| 2996 | |
| 2997 | dfile_corr_counter_limit = debugfs_create_file("corr_counter_limit", |
| 2998 | 0664, dent_msm_pcie, 0, |
| 2999 | &msm_pcie_corr_counter_limit_ops); |
| 3000 | if (!dfile_corr_counter_limit || IS_ERR(dfile_corr_counter_limit)) { |
| 3001 | pr_err("PCIe: fail to create the file for debug_fs corr_counter_limit.\n"); |
| 3002 | goto corr_counter_limit_error; |
| 3003 | } |
| 3004 | return; |
| 3005 | |
| 3006 | corr_counter_limit_error: |
| 3007 | debugfs_remove(dfile_aer_enable); |
| 3008 | aer_enable_error: |
| 3009 | debugfs_remove(dfile_ep_wakeirq); |
| 3010 | ep_wakeirq_error: |
| 3011 | debugfs_remove(dfile_wr_value); |
| 3012 | wr_value_error: |
| 3013 | debugfs_remove(dfile_wr_mask); |
| 3014 | wr_mask_error: |
| 3015 | debugfs_remove(dfile_wr_offset); |
| 3016 | wr_offset_error: |
| 3017 | debugfs_remove(dfile_linkdown_panic); |
| 3018 | linkdown_panic_error: |
| 3019 | debugfs_remove(dfile_base_sel); |
| 3020 | base_sel_error: |
| 3021 | debugfs_remove(dfile_case); |
| 3022 | case_error: |
| 3023 | debugfs_remove(dfile_rc_sel); |
| 3024 | rc_sel_error: |
| 3025 | debugfs_remove(dent_msm_pcie); |
| 3026 | } |
| 3027 | |
| 3028 | static void msm_pcie_debugfs_exit(void) |
| 3029 | { |
| 3030 | debugfs_remove(dfile_rc_sel); |
| 3031 | debugfs_remove(dfile_case); |
| 3032 | debugfs_remove(dfile_base_sel); |
| 3033 | debugfs_remove(dfile_linkdown_panic); |
| 3034 | debugfs_remove(dfile_wr_offset); |
| 3035 | debugfs_remove(dfile_wr_mask); |
| 3036 | debugfs_remove(dfile_wr_value); |
| 3037 | debugfs_remove(dfile_ep_wakeirq); |
| 3038 | debugfs_remove(dfile_aer_enable); |
| 3039 | debugfs_remove(dfile_corr_counter_limit); |
| 3040 | } |
| 3041 | #else |
| 3042 | static void msm_pcie_debugfs_init(void) |
| 3043 | { |
| 3044 | } |
| 3045 | |
| 3046 | static void msm_pcie_debugfs_exit(void) |
| 3047 | { |
| 3048 | } |
| 3049 | #endif |
| 3050 | |
| 3051 | static inline int msm_pcie_is_link_up(struct msm_pcie_dev_t *dev) |
| 3052 | { |
| 3053 | return readl_relaxed(dev->dm_core + |
| 3054 | PCIE20_CAP_LINKCTRLSTATUS) & BIT(29); |
| 3055 | } |
| 3056 | |
| 3057 | /** |
| 3058 | * msm_pcie_iatu_config - configure outbound address translation region |
| 3059 | * @dev: root commpex |
| 3060 | * @nr: region number |
| 3061 | * @type: target transaction type, see PCIE20_CTRL1_TYPE_xxx |
| 3062 | * @host_addr: - region start address on host |
| 3063 | * @host_end: - region end address (low 32 bit) on host, |
| 3064 | * upper 32 bits are same as for @host_addr |
| 3065 | * @target_addr: - region start address on target |
| 3066 | */ |
| 3067 | static void msm_pcie_iatu_config(struct msm_pcie_dev_t *dev, int nr, u8 type, |
| 3068 | unsigned long host_addr, u32 host_end, |
| 3069 | unsigned long target_addr) |
| 3070 | { |
| 3071 | void __iomem *pcie20 = dev->dm_core; |
| 3072 | |
| 3073 | if (dev->shadow_en) { |
| 3074 | dev->rc_shadow[PCIE20_PLR_IATU_VIEWPORT / 4] = |
| 3075 | nr; |
| 3076 | dev->rc_shadow[PCIE20_PLR_IATU_CTRL1 / 4] = |
| 3077 | type; |
| 3078 | dev->rc_shadow[PCIE20_PLR_IATU_LBAR / 4] = |
| 3079 | lower_32_bits(host_addr); |
| 3080 | dev->rc_shadow[PCIE20_PLR_IATU_UBAR / 4] = |
| 3081 | upper_32_bits(host_addr); |
| 3082 | dev->rc_shadow[PCIE20_PLR_IATU_LAR / 4] = |
| 3083 | host_end; |
| 3084 | dev->rc_shadow[PCIE20_PLR_IATU_LTAR / 4] = |
| 3085 | lower_32_bits(target_addr); |
| 3086 | dev->rc_shadow[PCIE20_PLR_IATU_UTAR / 4] = |
| 3087 | upper_32_bits(target_addr); |
| 3088 | dev->rc_shadow[PCIE20_PLR_IATU_CTRL2 / 4] = |
| 3089 | BIT(31); |
| 3090 | } |
| 3091 | |
| 3092 | /* select region */ |
| 3093 | writel_relaxed(nr, pcie20 + PCIE20_PLR_IATU_VIEWPORT); |
| 3094 | /* ensure that hardware locks it */ |
| 3095 | wmb(); |
| 3096 | |
| 3097 | /* switch off region before changing it */ |
| 3098 | writel_relaxed(0, pcie20 + PCIE20_PLR_IATU_CTRL2); |
| 3099 | /* and wait till it propagates to the hardware */ |
| 3100 | wmb(); |
| 3101 | |
| 3102 | writel_relaxed(type, pcie20 + PCIE20_PLR_IATU_CTRL1); |
| 3103 | writel_relaxed(lower_32_bits(host_addr), |
| 3104 | pcie20 + PCIE20_PLR_IATU_LBAR); |
| 3105 | writel_relaxed(upper_32_bits(host_addr), |
| 3106 | pcie20 + PCIE20_PLR_IATU_UBAR); |
| 3107 | writel_relaxed(host_end, pcie20 + PCIE20_PLR_IATU_LAR); |
| 3108 | writel_relaxed(lower_32_bits(target_addr), |
| 3109 | pcie20 + PCIE20_PLR_IATU_LTAR); |
| 3110 | writel_relaxed(upper_32_bits(target_addr), |
| 3111 | pcie20 + PCIE20_PLR_IATU_UTAR); |
| 3112 | /* ensure that changes propagated to the hardware */ |
| 3113 | wmb(); |
| 3114 | writel_relaxed(BIT(31), pcie20 + PCIE20_PLR_IATU_CTRL2); |
| 3115 | |
| 3116 | /* ensure that changes propagated to the hardware */ |
| 3117 | wmb(); |
| 3118 | |
| 3119 | if (dev->enumerated) { |
| 3120 | PCIE_DBG2(dev, "IATU for Endpoint %02x:%02x.%01x\n", |
| 3121 | dev->pcidev_table[nr].bdf >> 24, |
| 3122 | dev->pcidev_table[nr].bdf >> 19 & 0x1f, |
| 3123 | dev->pcidev_table[nr].bdf >> 16 & 0x07); |
| 3124 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_VIEWPORT:0x%x\n", |
| 3125 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_VIEWPORT)); |
| 3126 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_CTRL1:0x%x\n", |
| 3127 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_CTRL1)); |
| 3128 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_LBAR:0x%x\n", |
| 3129 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LBAR)); |
| 3130 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_UBAR:0x%x\n", |
| 3131 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_UBAR)); |
| 3132 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_LAR:0x%x\n", |
| 3133 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LAR)); |
| 3134 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_LTAR:0x%x\n", |
| 3135 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LTAR)); |
| 3136 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_UTAR:0x%x\n", |
| 3137 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_UTAR)); |
| 3138 | PCIE_DBG2(dev, "PCIE20_PLR_IATU_CTRL2:0x%x\n\n", |
| 3139 | readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_CTRL2)); |
| 3140 | } |
| 3141 | } |
| 3142 | |
| 3143 | /** |
| 3144 | * msm_pcie_cfg_bdf - configure for config access |
| 3145 | * @dev: root commpex |
| 3146 | * @bus: PCI bus number |
| 3147 | * @devfn: PCI dev and function number |
| 3148 | * |
| 3149 | * Remap if required region 0 for config access of proper type |
| 3150 | * (CFG0 for bus 1, CFG1 for other buses) |
| 3151 | * Cache current device bdf for speed-up |
| 3152 | */ |
| 3153 | static void msm_pcie_cfg_bdf(struct msm_pcie_dev_t *dev, u8 bus, u8 devfn) |
| 3154 | { |
| 3155 | struct resource *axi_conf = dev->res[MSM_PCIE_RES_CONF].resource; |
| 3156 | u32 bdf = BDF_OFFSET(bus, devfn); |
| 3157 | u8 type = bus == 1 ? PCIE20_CTRL1_TYPE_CFG0 : PCIE20_CTRL1_TYPE_CFG1; |
| 3158 | |
| 3159 | if (dev->current_bdf == bdf) |
| 3160 | return; |
| 3161 | |
| 3162 | msm_pcie_iatu_config(dev, 0, type, |
| 3163 | axi_conf->start, |
| 3164 | axi_conf->start + SZ_4K - 1, |
| 3165 | bdf); |
| 3166 | |
| 3167 | dev->current_bdf = bdf; |
| 3168 | } |
| 3169 | |
| 3170 | static inline void msm_pcie_save_shadow(struct msm_pcie_dev_t *dev, |
| 3171 | u32 word_offset, u32 wr_val, |
| 3172 | u32 bdf, bool rc) |
| 3173 | { |
| 3174 | int i, j; |
| 3175 | u32 max_dev = MAX_RC_NUM * MAX_DEVICE_NUM; |
| 3176 | |
| 3177 | if (rc) { |
| 3178 | dev->rc_shadow[word_offset / 4] = wr_val; |
| 3179 | } else { |
| 3180 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 3181 | if (!dev->pcidev_table[i].bdf) { |
| 3182 | for (j = 0; j < max_dev; j++) |
| 3183 | if (!msm_pcie_dev_tbl[j].bdf) { |
| 3184 | msm_pcie_dev_tbl[j].bdf = bdf; |
| 3185 | break; |
| 3186 | } |
| 3187 | dev->pcidev_table[i].bdf = bdf; |
| 3188 | if ((!dev->bridge_found) && (i > 0)) |
| 3189 | dev->bridge_found = true; |
| 3190 | } |
| 3191 | if (dev->pcidev_table[i].bdf == bdf) { |
| 3192 | dev->ep_shadow[i][word_offset / 4] = wr_val; |
| 3193 | break; |
| 3194 | } |
| 3195 | } |
| 3196 | } |
| 3197 | } |
| 3198 | |
| 3199 | static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, |
| 3200 | int where, int size, u32 *val) |
| 3201 | { |
| 3202 | uint32_t word_offset, byte_offset, mask; |
| 3203 | uint32_t rd_val, wr_val; |
| 3204 | struct msm_pcie_dev_t *dev; |
| 3205 | void __iomem *config_base; |
| 3206 | bool rc = false; |
| 3207 | u32 rc_idx; |
| 3208 | int rv = 0; |
| 3209 | u32 bdf = BDF_OFFSET(bus->number, devfn); |
| 3210 | int i; |
| 3211 | |
| 3212 | dev = PCIE_BUS_PRIV_DATA(bus); |
| 3213 | |
| 3214 | if (!dev) { |
| 3215 | pr_err("PCIe: No device found for this bus.\n"); |
| 3216 | *val = ~0; |
| 3217 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3218 | goto out; |
| 3219 | } |
| 3220 | |
| 3221 | rc_idx = dev->rc_idx; |
| 3222 | rc = (bus->number == 0); |
| 3223 | |
| 3224 | spin_lock_irqsave(&dev->cfg_lock, dev->irqsave_flags); |
| 3225 | |
| 3226 | if (!dev->cfg_access) { |
| 3227 | PCIE_DBG3(dev, |
| 3228 | "Access denied for RC%d %d:0x%02x + 0x%04x[%d]\n", |
| 3229 | rc_idx, bus->number, devfn, where, size); |
| 3230 | *val = ~0; |
| 3231 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3232 | goto unlock; |
| 3233 | } |
| 3234 | |
| 3235 | if (rc && (devfn != 0)) { |
| 3236 | PCIE_DBG3(dev, "RC%d invalid %s - bus %d devfn %d\n", rc_idx, |
| 3237 | (oper == RD) ? "rd" : "wr", bus->number, devfn); |
| 3238 | *val = ~0; |
| 3239 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3240 | goto unlock; |
| 3241 | } |
| 3242 | |
| 3243 | if (dev->link_status != MSM_PCIE_LINK_ENABLED) { |
| 3244 | PCIE_DBG3(dev, |
| 3245 | "Access to RC%d %d:0x%02x + 0x%04x[%d] is denied because link is down\n", |
| 3246 | rc_idx, bus->number, devfn, where, size); |
| 3247 | *val = ~0; |
| 3248 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3249 | goto unlock; |
| 3250 | } |
| 3251 | |
| 3252 | /* check if the link is up for endpoint */ |
| 3253 | if (!rc && !msm_pcie_is_link_up(dev)) { |
| 3254 | PCIE_ERR(dev, |
| 3255 | "PCIe: RC%d %s fail, link down - bus %d devfn %d\n", |
| 3256 | rc_idx, (oper == RD) ? "rd" : "wr", |
| 3257 | bus->number, devfn); |
| 3258 | *val = ~0; |
| 3259 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3260 | goto unlock; |
| 3261 | } |
| 3262 | |
| 3263 | if (!rc && !dev->enumerated) |
| 3264 | msm_pcie_cfg_bdf(dev, bus->number, devfn); |
| 3265 | |
| 3266 | word_offset = where & ~0x3; |
| 3267 | byte_offset = where & 0x3; |
| 3268 | mask = (~0 >> (8 * (4 - size))) << (8 * byte_offset); |
| 3269 | |
| 3270 | if (rc || !dev->enumerated) { |
| 3271 | config_base = rc ? dev->dm_core : dev->conf; |
| 3272 | } else { |
| 3273 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 3274 | if (dev->pcidev_table[i].bdf == bdf) { |
| 3275 | config_base = dev->pcidev_table[i].conf_base; |
| 3276 | break; |
| 3277 | } |
| 3278 | } |
| 3279 | if (i == MAX_DEVICE_NUM) { |
| 3280 | *val = ~0; |
| 3281 | rv = PCIBIOS_DEVICE_NOT_FOUND; |
| 3282 | goto unlock; |
| 3283 | } |
| 3284 | } |
| 3285 | |
| 3286 | rd_val = readl_relaxed(config_base + word_offset); |
| 3287 | |
| 3288 | if (oper == RD) { |
| 3289 | *val = ((rd_val & mask) >> (8 * byte_offset)); |
| 3290 | PCIE_DBG3(dev, |
| 3291 | "RC%d %d:0x%02x + 0x%04x[%d] -> 0x%08x; rd 0x%08x\n", |
| 3292 | rc_idx, bus->number, devfn, where, size, *val, rd_val); |
| 3293 | } else { |
| 3294 | wr_val = (rd_val & ~mask) | |
| 3295 | ((*val << (8 * byte_offset)) & mask); |
| 3296 | |
| 3297 | if ((bus->number == 0) && (where == 0x3c)) |
| 3298 | wr_val = wr_val | (3 << 16); |
| 3299 | |
| 3300 | writel_relaxed(wr_val, config_base + word_offset); |
| 3301 | wmb(); /* ensure config data is written to hardware register */ |
| 3302 | |
| 3303 | if (rd_val == PCIE_LINK_DOWN) |
| 3304 | PCIE_ERR(dev, |
| 3305 | "Read of RC%d %d:0x%02x + 0x%04x[%d] is all FFs\n", |
| 3306 | rc_idx, bus->number, devfn, where, size); |
| 3307 | else if (dev->shadow_en) |
| 3308 | msm_pcie_save_shadow(dev, word_offset, wr_val, bdf, rc); |
| 3309 | |
| 3310 | PCIE_DBG3(dev, |
| 3311 | "RC%d %d:0x%02x + 0x%04x[%d] <- 0x%08x; rd 0x%08x val 0x%08x\n", |
| 3312 | rc_idx, bus->number, devfn, where, size, |
| 3313 | wr_val, rd_val, *val); |
| 3314 | } |
| 3315 | |
| 3316 | unlock: |
| 3317 | spin_unlock_irqrestore(&dev->cfg_lock, dev->irqsave_flags); |
| 3318 | out: |
| 3319 | return rv; |
| 3320 | } |
| 3321 | |
| 3322 | static int msm_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 3323 | int size, u32 *val) |
| 3324 | { |
| 3325 | int ret = msm_pcie_oper_conf(bus, devfn, RD, where, size, val); |
| 3326 | |
| 3327 | if ((bus->number == 0) && (where == PCI_CLASS_REVISION)) { |
| 3328 | *val = (*val & 0xff) | (PCI_CLASS_BRIDGE_PCI << 16); |
| 3329 | PCIE_GEN_DBG("change class for RC:0x%x\n", *val); |
| 3330 | } |
| 3331 | |
| 3332 | return ret; |
| 3333 | } |
| 3334 | |
| 3335 | static int msm_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 3336 | int where, int size, u32 val) |
| 3337 | { |
| 3338 | return msm_pcie_oper_conf(bus, devfn, WR, where, size, &val); |
| 3339 | } |
| 3340 | |
| 3341 | static struct pci_ops msm_pcie_ops = { |
| 3342 | .read = msm_pcie_rd_conf, |
| 3343 | .write = msm_pcie_wr_conf, |
| 3344 | }; |
| 3345 | |
| 3346 | static int msm_pcie_gpio_init(struct msm_pcie_dev_t *dev) |
| 3347 | { |
| 3348 | int rc = 0, i; |
| 3349 | struct msm_pcie_gpio_info_t *info; |
| 3350 | |
| 3351 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 3352 | |
| 3353 | for (i = 0; i < dev->gpio_n; i++) { |
| 3354 | info = &dev->gpio[i]; |
| 3355 | |
| 3356 | if (!info->num) |
| 3357 | continue; |
| 3358 | |
| 3359 | rc = gpio_request(info->num, info->name); |
| 3360 | if (rc) { |
| 3361 | PCIE_ERR(dev, "PCIe: RC%d can't get gpio %s; %d\n", |
| 3362 | dev->rc_idx, info->name, rc); |
| 3363 | break; |
| 3364 | } |
| 3365 | |
| 3366 | if (info->out) |
| 3367 | rc = gpio_direction_output(info->num, info->init); |
| 3368 | else |
| 3369 | rc = gpio_direction_input(info->num); |
| 3370 | if (rc) { |
| 3371 | PCIE_ERR(dev, |
| 3372 | "PCIe: RC%d can't set direction for GPIO %s:%d\n", |
| 3373 | dev->rc_idx, info->name, rc); |
| 3374 | gpio_free(info->num); |
| 3375 | break; |
| 3376 | } |
| 3377 | } |
| 3378 | |
| 3379 | if (rc) |
| 3380 | while (i--) |
| 3381 | gpio_free(dev->gpio[i].num); |
| 3382 | |
| 3383 | return rc; |
| 3384 | } |
| 3385 | |
| 3386 | static void msm_pcie_gpio_deinit(struct msm_pcie_dev_t *dev) |
| 3387 | { |
| 3388 | int i; |
| 3389 | |
| 3390 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 3391 | |
| 3392 | for (i = 0; i < dev->gpio_n; i++) |
| 3393 | gpio_free(dev->gpio[i].num); |
| 3394 | } |
| 3395 | |
| 3396 | int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev) |
| 3397 | { |
| 3398 | int i, rc = 0; |
| 3399 | struct regulator *vreg; |
| 3400 | struct msm_pcie_vreg_info_t *info; |
| 3401 | |
| 3402 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3403 | |
| 3404 | for (i = 0; i < MSM_PCIE_MAX_VREG; i++) { |
| 3405 | info = &dev->vreg[i]; |
| 3406 | vreg = info->hdl; |
| 3407 | |
| 3408 | if (!vreg) |
| 3409 | continue; |
| 3410 | |
| 3411 | PCIE_DBG2(dev, "RC%d Vreg %s is being enabled\n", |
| 3412 | dev->rc_idx, info->name); |
| 3413 | if (info->max_v) { |
| 3414 | rc = regulator_set_voltage(vreg, |
| 3415 | info->min_v, info->max_v); |
| 3416 | if (rc) { |
| 3417 | PCIE_ERR(dev, |
| 3418 | "PCIe: RC%d can't set voltage for %s: %d\n", |
| 3419 | dev->rc_idx, info->name, rc); |
| 3420 | break; |
| 3421 | } |
| 3422 | } |
| 3423 | |
| 3424 | if (info->opt_mode) { |
| 3425 | rc = regulator_set_load(vreg, info->opt_mode); |
| 3426 | if (rc < 0) { |
| 3427 | PCIE_ERR(dev, |
| 3428 | "PCIe: RC%d can't set mode for %s: %d\n", |
| 3429 | dev->rc_idx, info->name, rc); |
| 3430 | break; |
| 3431 | } |
| 3432 | } |
| 3433 | |
| 3434 | rc = regulator_enable(vreg); |
| 3435 | if (rc) { |
| 3436 | PCIE_ERR(dev, |
| 3437 | "PCIe: RC%d can't enable regulator %s: %d\n", |
| 3438 | dev->rc_idx, info->name, rc); |
| 3439 | break; |
| 3440 | } |
| 3441 | } |
| 3442 | |
| 3443 | if (rc) |
| 3444 | while (i--) { |
| 3445 | struct regulator *hdl = dev->vreg[i].hdl; |
| 3446 | |
| 3447 | if (hdl) { |
| 3448 | regulator_disable(hdl); |
| 3449 | if (!strcmp(dev->vreg[i].name, "vreg-cx")) { |
| 3450 | PCIE_DBG(dev, |
| 3451 | "RC%d: Removing %s vote.\n", |
| 3452 | dev->rc_idx, |
| 3453 | dev->vreg[i].name); |
| 3454 | regulator_set_voltage(hdl, |
| 3455 | RPM_REGULATOR_CORNER_NONE, |
| 3456 | INT_MAX); |
| 3457 | } |
| 3458 | } |
| 3459 | |
| 3460 | } |
| 3461 | |
| 3462 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3463 | |
| 3464 | return rc; |
| 3465 | } |
| 3466 | |
| 3467 | static void msm_pcie_vreg_deinit(struct msm_pcie_dev_t *dev) |
| 3468 | { |
| 3469 | int i; |
| 3470 | |
| 3471 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3472 | |
| 3473 | for (i = MSM_PCIE_MAX_VREG - 1; i >= 0; i--) { |
| 3474 | if (dev->vreg[i].hdl) { |
| 3475 | PCIE_DBG(dev, "Vreg %s is being disabled\n", |
| 3476 | dev->vreg[i].name); |
| 3477 | regulator_disable(dev->vreg[i].hdl); |
| 3478 | |
| 3479 | if (!strcmp(dev->vreg[i].name, "vreg-cx")) { |
| 3480 | PCIE_DBG(dev, |
| 3481 | "RC%d: Removing %s vote.\n", |
| 3482 | dev->rc_idx, |
| 3483 | dev->vreg[i].name); |
| 3484 | regulator_set_voltage(dev->vreg[i].hdl, |
| 3485 | RPM_REGULATOR_CORNER_NONE, |
| 3486 | INT_MAX); |
| 3487 | } |
| 3488 | } |
| 3489 | } |
| 3490 | |
| 3491 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3492 | } |
| 3493 | |
| 3494 | static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) |
| 3495 | { |
| 3496 | int i, rc = 0; |
| 3497 | struct msm_pcie_clk_info_t *info; |
| 3498 | struct msm_pcie_reset_info_t *reset_info; |
| 3499 | |
| 3500 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3501 | |
| 3502 | rc = regulator_enable(dev->gdsc); |
| 3503 | |
| 3504 | if (rc) { |
| 3505 | PCIE_ERR(dev, "PCIe: fail to enable GDSC for RC%d (%s)\n", |
| 3506 | dev->rc_idx, dev->pdev->name); |
| 3507 | return rc; |
| 3508 | } |
| 3509 | |
| 3510 | if (dev->gdsc_smmu) { |
| 3511 | rc = regulator_enable(dev->gdsc_smmu); |
| 3512 | |
| 3513 | if (rc) { |
| 3514 | PCIE_ERR(dev, |
| 3515 | "PCIe: fail to enable SMMU GDSC for RC%d (%s)\n", |
| 3516 | dev->rc_idx, dev->pdev->name); |
| 3517 | return rc; |
| 3518 | } |
| 3519 | } |
| 3520 | |
| 3521 | PCIE_DBG(dev, "PCIe: requesting bus vote for RC%d\n", dev->rc_idx); |
| 3522 | if (dev->bus_client) { |
| 3523 | rc = msm_bus_scale_client_update_request(dev->bus_client, 1); |
| 3524 | if (rc) { |
| 3525 | PCIE_ERR(dev, |
| 3526 | "PCIe: fail to set bus bandwidth for RC%d:%d.\n", |
| 3527 | dev->rc_idx, rc); |
| 3528 | return rc; |
| 3529 | } |
| 3530 | |
| 3531 | PCIE_DBG2(dev, |
| 3532 | "PCIe: set bus bandwidth for RC%d.\n", |
| 3533 | dev->rc_idx); |
| 3534 | } |
| 3535 | |
| 3536 | for (i = 0; i < MSM_PCIE_MAX_CLK; i++) { |
| 3537 | info = &dev->clk[i]; |
| 3538 | |
| 3539 | if (!info->hdl) |
| 3540 | continue; |
| 3541 | |
| 3542 | if (info->config_mem) |
| 3543 | msm_pcie_config_clock_mem(dev, info); |
| 3544 | |
| 3545 | if (info->freq) { |
| 3546 | rc = clk_set_rate(info->hdl, info->freq); |
| 3547 | if (rc) { |
| 3548 | PCIE_ERR(dev, |
| 3549 | "PCIe: RC%d can't set rate for clk %s: %d.\n", |
| 3550 | dev->rc_idx, info->name, rc); |
| 3551 | break; |
| 3552 | } |
| 3553 | |
| 3554 | PCIE_DBG2(dev, |
| 3555 | "PCIe: RC%d set rate for clk %s.\n", |
| 3556 | dev->rc_idx, info->name); |
| 3557 | } |
| 3558 | |
| 3559 | rc = clk_prepare_enable(info->hdl); |
| 3560 | |
| 3561 | if (rc) |
| 3562 | PCIE_ERR(dev, "PCIe: RC%d failed to enable clk %s\n", |
| 3563 | dev->rc_idx, info->name); |
| 3564 | else |
| 3565 | PCIE_DBG2(dev, "enable clk %s for RC%d.\n", |
| 3566 | info->name, dev->rc_idx); |
| 3567 | } |
| 3568 | |
| 3569 | if (rc) { |
| 3570 | PCIE_DBG(dev, "RC%d disable clocks for error handling.\n", |
| 3571 | dev->rc_idx); |
| 3572 | while (i--) { |
| 3573 | struct clk *hdl = dev->clk[i].hdl; |
| 3574 | |
| 3575 | if (hdl) |
| 3576 | clk_disable_unprepare(hdl); |
| 3577 | } |
| 3578 | |
| 3579 | if (dev->gdsc_smmu) |
| 3580 | regulator_disable(dev->gdsc_smmu); |
| 3581 | |
| 3582 | regulator_disable(dev->gdsc); |
| 3583 | } |
| 3584 | |
| 3585 | for (i = 0; i < MSM_PCIE_MAX_RESET; i++) { |
| 3586 | reset_info = &dev->reset[i]; |
| 3587 | if (reset_info->hdl) { |
| 3588 | rc = reset_control_deassert(reset_info->hdl); |
| 3589 | if (rc) |
| 3590 | PCIE_ERR(dev, |
| 3591 | "PCIe: RC%d failed to deassert reset for %s.\n", |
| 3592 | dev->rc_idx, reset_info->name); |
| 3593 | else |
| 3594 | PCIE_DBG2(dev, |
| 3595 | "PCIe: RC%d successfully deasserted reset for %s.\n", |
| 3596 | dev->rc_idx, reset_info->name); |
| 3597 | } |
| 3598 | } |
| 3599 | |
| 3600 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3601 | |
| 3602 | return rc; |
| 3603 | } |
| 3604 | |
| 3605 | static void msm_pcie_clk_deinit(struct msm_pcie_dev_t *dev) |
| 3606 | { |
| 3607 | int i; |
| 3608 | int rc; |
| 3609 | |
| 3610 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3611 | |
| 3612 | for (i = 0; i < MSM_PCIE_MAX_CLK; i++) |
| 3613 | if (dev->clk[i].hdl) |
| 3614 | clk_disable_unprepare(dev->clk[i].hdl); |
| 3615 | |
| 3616 | if (dev->bus_client) { |
| 3617 | PCIE_DBG(dev, "PCIe: removing bus vote for RC%d\n", |
| 3618 | dev->rc_idx); |
| 3619 | |
| 3620 | rc = msm_bus_scale_client_update_request(dev->bus_client, 0); |
| 3621 | if (rc) |
| 3622 | PCIE_ERR(dev, |
| 3623 | "PCIe: fail to relinquish bus bandwidth for RC%d:%d.\n", |
| 3624 | dev->rc_idx, rc); |
| 3625 | else |
| 3626 | PCIE_DBG(dev, |
| 3627 | "PCIe: relinquish bus bandwidth for RC%d.\n", |
| 3628 | dev->rc_idx); |
| 3629 | } |
| 3630 | |
| 3631 | if (dev->gdsc_smmu) |
| 3632 | regulator_disable(dev->gdsc_smmu); |
| 3633 | |
| 3634 | regulator_disable(dev->gdsc); |
| 3635 | |
| 3636 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3637 | } |
| 3638 | |
| 3639 | static int msm_pcie_pipe_clk_init(struct msm_pcie_dev_t *dev) |
| 3640 | { |
| 3641 | int i, rc = 0; |
| 3642 | struct msm_pcie_clk_info_t *info; |
| 3643 | struct msm_pcie_reset_info_t *pipe_reset_info; |
| 3644 | |
| 3645 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3646 | |
| 3647 | for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++) { |
| 3648 | info = &dev->pipeclk[i]; |
| 3649 | |
| 3650 | if (!info->hdl) |
| 3651 | continue; |
| 3652 | |
| 3653 | |
| 3654 | if (info->config_mem) |
| 3655 | msm_pcie_config_clock_mem(dev, info); |
| 3656 | |
| 3657 | if (info->freq) { |
| 3658 | rc = clk_set_rate(info->hdl, info->freq); |
| 3659 | if (rc) { |
| 3660 | PCIE_ERR(dev, |
| 3661 | "PCIe: RC%d can't set rate for clk %s: %d.\n", |
| 3662 | dev->rc_idx, info->name, rc); |
| 3663 | break; |
| 3664 | } |
| 3665 | |
| 3666 | PCIE_DBG2(dev, |
| 3667 | "PCIe: RC%d set rate for clk %s: %d.\n", |
| 3668 | dev->rc_idx, info->name, rc); |
| 3669 | } |
| 3670 | |
| 3671 | rc = clk_prepare_enable(info->hdl); |
| 3672 | |
| 3673 | if (rc) |
| 3674 | PCIE_ERR(dev, "PCIe: RC%d failed to enable clk %s.\n", |
| 3675 | dev->rc_idx, info->name); |
| 3676 | else |
| 3677 | PCIE_DBG2(dev, "RC%d enabled pipe clk %s.\n", |
| 3678 | dev->rc_idx, info->name); |
| 3679 | } |
| 3680 | |
| 3681 | if (rc) { |
| 3682 | PCIE_DBG(dev, "RC%d disable pipe clocks for error handling.\n", |
| 3683 | dev->rc_idx); |
| 3684 | while (i--) |
| 3685 | if (dev->pipeclk[i].hdl) |
| 3686 | clk_disable_unprepare(dev->pipeclk[i].hdl); |
| 3687 | } |
| 3688 | |
| 3689 | for (i = 0; i < MSM_PCIE_MAX_PIPE_RESET; i++) { |
| 3690 | pipe_reset_info = &dev->pipe_reset[i]; |
| 3691 | if (pipe_reset_info->hdl) { |
| 3692 | rc = reset_control_deassert( |
| 3693 | pipe_reset_info->hdl); |
| 3694 | if (rc) |
| 3695 | PCIE_ERR(dev, |
| 3696 | "PCIe: RC%d failed to deassert pipe reset for %s.\n", |
| 3697 | dev->rc_idx, pipe_reset_info->name); |
| 3698 | else |
| 3699 | PCIE_DBG2(dev, |
| 3700 | "PCIe: RC%d successfully deasserted pipe reset for %s.\n", |
| 3701 | dev->rc_idx, pipe_reset_info->name); |
| 3702 | } |
| 3703 | } |
| 3704 | |
| 3705 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3706 | |
| 3707 | return rc; |
| 3708 | } |
| 3709 | |
| 3710 | static void msm_pcie_pipe_clk_deinit(struct msm_pcie_dev_t *dev) |
| 3711 | { |
| 3712 | int i; |
| 3713 | |
| 3714 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 3715 | |
| 3716 | for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++) |
| 3717 | if (dev->pipeclk[i].hdl) |
| 3718 | clk_disable_unprepare( |
| 3719 | dev->pipeclk[i].hdl); |
| 3720 | |
| 3721 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 3722 | } |
| 3723 | |
| 3724 | static void msm_pcie_iatu_config_all_ep(struct msm_pcie_dev_t *dev) |
| 3725 | { |
| 3726 | int i; |
| 3727 | u8 type; |
| 3728 | struct msm_pcie_device_info *dev_table = dev->pcidev_table; |
| 3729 | |
| 3730 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 3731 | if (!dev_table[i].bdf) |
| 3732 | break; |
| 3733 | |
| 3734 | type = dev_table[i].bdf >> 24 == 0x1 ? |
| 3735 | PCIE20_CTRL1_TYPE_CFG0 : PCIE20_CTRL1_TYPE_CFG1; |
| 3736 | |
| 3737 | msm_pcie_iatu_config(dev, i, type, dev_table[i].phy_address, |
| 3738 | dev_table[i].phy_address + SZ_4K - 1, |
| 3739 | dev_table[i].bdf); |
| 3740 | } |
| 3741 | } |
| 3742 | |
| 3743 | static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) |
| 3744 | { |
| 3745 | int i; |
| 3746 | |
| 3747 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 3748 | |
| 3749 | /* |
| 3750 | * program and enable address translation region 0 (device config |
| 3751 | * address space); region type config; |
| 3752 | * axi config address range to device config address range |
| 3753 | */ |
| 3754 | if (dev->enumerated) { |
| 3755 | msm_pcie_iatu_config_all_ep(dev); |
| 3756 | } else { |
| 3757 | dev->current_bdf = 0; /* to force IATU re-config */ |
| 3758 | msm_pcie_cfg_bdf(dev, 1, 0); |
| 3759 | } |
| 3760 | |
| 3761 | /* configure N_FTS */ |
| 3762 | PCIE_DBG2(dev, "Original PCIE20_ACK_F_ASPM_CTRL_REG:0x%x\n", |
| 3763 | readl_relaxed(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG)); |
| 3764 | if (!dev->n_fts) |
| 3765 | msm_pcie_write_mask(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG, |
| 3766 | 0, BIT(15)); |
| 3767 | else |
| 3768 | msm_pcie_write_mask(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG, |
| 3769 | PCIE20_ACK_N_FTS, |
| 3770 | dev->n_fts << 8); |
| 3771 | |
| 3772 | if (dev->shadow_en) |
| 3773 | dev->rc_shadow[PCIE20_ACK_F_ASPM_CTRL_REG / 4] = |
| 3774 | readl_relaxed(dev->dm_core + |
| 3775 | PCIE20_ACK_F_ASPM_CTRL_REG); |
| 3776 | |
| 3777 | PCIE_DBG2(dev, "Updated PCIE20_ACK_F_ASPM_CTRL_REG:0x%x\n", |
| 3778 | readl_relaxed(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG)); |
| 3779 | |
| 3780 | /* configure AUX clock frequency register for PCIe core */ |
| 3781 | if (dev->use_19p2mhz_aux_clk) |
| 3782 | msm_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14); |
| 3783 | else |
| 3784 | msm_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x01); |
| 3785 | |
| 3786 | /* configure the completion timeout value for PCIe core */ |
| 3787 | if (dev->cpl_timeout && dev->bridge_found) |
| 3788 | msm_pcie_write_reg_field(dev->dm_core, |
| 3789 | PCIE20_DEVICE_CONTROL2_STATUS2, |
| 3790 | 0xf, dev->cpl_timeout); |
| 3791 | |
| 3792 | /* Enable AER on RC */ |
| 3793 | if (dev->aer_enable) { |
| 3794 | msm_pcie_write_mask(dev->dm_core + PCIE20_BRIDGE_CTRL, 0, |
| 3795 | BIT(16)|BIT(17)); |
| 3796 | msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_DEVCTRLSTATUS, 0, |
| 3797 | BIT(3)|BIT(2)|BIT(1)|BIT(0)); |
| 3798 | |
| 3799 | PCIE_DBG(dev, "RC's PCIE20_CAP_DEVCTRLSTATUS:0x%x\n", |
| 3800 | readl_relaxed(dev->dm_core + PCIE20_CAP_DEVCTRLSTATUS)); |
| 3801 | } |
| 3802 | |
| 3803 | /* configure SMMU registers */ |
| 3804 | if (dev->smmu_exist) { |
| 3805 | msm_pcie_write_reg(dev->parf, |
| 3806 | PCIE20_PARF_BDF_TRANSLATE_CFG, 0); |
| 3807 | msm_pcie_write_reg(dev->parf, |
| 3808 | PCIE20_PARF_SID_OFFSET, 0); |
| 3809 | |
| 3810 | if (dev->enumerated) { |
| 3811 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 3812 | if (dev->pcidev_table[i].dev && |
| 3813 | dev->pcidev_table[i].short_bdf) { |
| 3814 | msm_pcie_write_reg(dev->parf, |
| 3815 | PCIE20_PARF_BDF_TRANSLATE_N + |
| 3816 | dev->pcidev_table[i].short_bdf |
| 3817 | * 4, |
| 3818 | dev->pcidev_table[i].bdf >> 16); |
| 3819 | } |
| 3820 | } |
| 3821 | } |
| 3822 | } |
| 3823 | } |
| 3824 | |
| 3825 | static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev) |
| 3826 | { |
| 3827 | u32 val; |
| 3828 | u32 current_offset; |
| 3829 | u32 ep_l1sub_ctrl1_offset = 0; |
| 3830 | u32 ep_l1sub_cap_reg1_offset = 0; |
| 3831 | u32 ep_link_cap_offset = 0; |
| 3832 | u32 ep_link_ctrlstts_offset = 0; |
| 3833 | u32 ep_dev_ctrl2stts2_offset = 0; |
| 3834 | |
| 3835 | /* Enable the AUX Clock and the Core Clk to be synchronous for L1SS*/ |
| 3836 | if (!dev->aux_clk_sync && dev->l1ss_supported) |
| 3837 | msm_pcie_write_mask(dev->parf + |
| 3838 | PCIE20_PARF_SYS_CTRL, BIT(3), 0); |
| 3839 | |
| 3840 | current_offset = readl_relaxed(dev->conf + PCIE_CAP_PTR_OFFSET) & 0xff; |
| 3841 | |
| 3842 | while (current_offset) { |
| 3843 | if (msm_pcie_check_align(dev, current_offset)) |
| 3844 | return; |
| 3845 | |
| 3846 | val = readl_relaxed(dev->conf + current_offset); |
| 3847 | if ((val & 0xff) == PCIE20_CAP_ID) { |
| 3848 | ep_link_cap_offset = current_offset + 0x0c; |
| 3849 | ep_link_ctrlstts_offset = current_offset + 0x10; |
| 3850 | ep_dev_ctrl2stts2_offset = current_offset + 0x28; |
| 3851 | break; |
| 3852 | } |
| 3853 | current_offset = (val >> 8) & 0xff; |
| 3854 | } |
| 3855 | |
| 3856 | if (!ep_link_cap_offset) { |
| 3857 | PCIE_DBG(dev, |
| 3858 | "RC%d endpoint does not support PCIe capability registers\n", |
| 3859 | dev->rc_idx); |
| 3860 | return; |
| 3861 | } |
| 3862 | |
| 3863 | PCIE_DBG(dev, |
| 3864 | "RC%d: ep_link_cap_offset: 0x%x\n", |
| 3865 | dev->rc_idx, ep_link_cap_offset); |
| 3866 | |
| 3867 | if (dev->common_clk_en) { |
| 3868 | msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, |
| 3869 | 0, BIT(6)); |
| 3870 | |
| 3871 | msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, |
| 3872 | 0, BIT(6)); |
| 3873 | |
| 3874 | if (dev->shadow_en) { |
| 3875 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 3876 | readl_relaxed(dev->dm_core + |
| 3877 | PCIE20_CAP_LINKCTRLSTATUS); |
| 3878 | |
| 3879 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 3880 | readl_relaxed(dev->conf + |
| 3881 | ep_link_ctrlstts_offset); |
| 3882 | } |
| 3883 | |
| 3884 | PCIE_DBG2(dev, "RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3885 | readl_relaxed(dev->dm_core + |
| 3886 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 3887 | PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3888 | readl_relaxed(dev->conf + ep_link_ctrlstts_offset)); |
| 3889 | } |
| 3890 | |
| 3891 | if (dev->clk_power_manage_en) { |
| 3892 | val = readl_relaxed(dev->conf + ep_link_cap_offset); |
| 3893 | if (val & BIT(18)) { |
| 3894 | msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, |
| 3895 | 0, BIT(8)); |
| 3896 | |
| 3897 | if (dev->shadow_en) |
| 3898 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 3899 | readl_relaxed(dev->conf + |
| 3900 | ep_link_ctrlstts_offset); |
| 3901 | |
| 3902 | PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3903 | readl_relaxed(dev->conf + |
| 3904 | ep_link_ctrlstts_offset)); |
| 3905 | } |
| 3906 | } |
| 3907 | |
| 3908 | if (dev->l0s_supported) { |
| 3909 | msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, |
| 3910 | 0, BIT(0)); |
| 3911 | msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, |
| 3912 | 0, BIT(0)); |
| 3913 | if (dev->shadow_en) { |
| 3914 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 3915 | readl_relaxed(dev->dm_core + |
| 3916 | PCIE20_CAP_LINKCTRLSTATUS); |
| 3917 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 3918 | readl_relaxed(dev->conf + |
| 3919 | ep_link_ctrlstts_offset); |
| 3920 | } |
| 3921 | PCIE_DBG2(dev, "RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3922 | readl_relaxed(dev->dm_core + |
| 3923 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 3924 | PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3925 | readl_relaxed(dev->conf + ep_link_ctrlstts_offset)); |
| 3926 | } |
| 3927 | |
| 3928 | if (dev->l1_supported) { |
| 3929 | msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, |
| 3930 | 0, BIT(1)); |
| 3931 | msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, |
| 3932 | 0, BIT(1)); |
| 3933 | if (dev->shadow_en) { |
| 3934 | dev->rc_shadow[PCIE20_CAP_LINKCTRLSTATUS / 4] = |
| 3935 | readl_relaxed(dev->dm_core + |
| 3936 | PCIE20_CAP_LINKCTRLSTATUS); |
| 3937 | dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = |
| 3938 | readl_relaxed(dev->conf + |
| 3939 | ep_link_ctrlstts_offset); |
| 3940 | } |
| 3941 | PCIE_DBG2(dev, "RC's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3942 | readl_relaxed(dev->dm_core + |
| 3943 | PCIE20_CAP_LINKCTRLSTATUS)); |
| 3944 | PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", |
| 3945 | readl_relaxed(dev->conf + ep_link_ctrlstts_offset)); |
| 3946 | } |
| 3947 | |
| 3948 | if (dev->l1ss_supported) { |
| 3949 | current_offset = PCIE_EXT_CAP_OFFSET; |
| 3950 | while (current_offset) { |
| 3951 | if (msm_pcie_check_align(dev, current_offset)) |
| 3952 | return; |
| 3953 | |
| 3954 | val = readl_relaxed(dev->conf + current_offset); |
| 3955 | if ((val & 0xffff) == L1SUB_CAP_ID) { |
| 3956 | ep_l1sub_cap_reg1_offset = current_offset + 0x4; |
| 3957 | ep_l1sub_ctrl1_offset = current_offset + 0x8; |
| 3958 | break; |
| 3959 | } |
| 3960 | current_offset = val >> 20; |
| 3961 | } |
| 3962 | if (!ep_l1sub_ctrl1_offset) { |
| 3963 | PCIE_DBG(dev, |
| 3964 | "RC%d endpoint does not support l1ss registers\n", |
| 3965 | dev->rc_idx); |
| 3966 | return; |
| 3967 | } |
| 3968 | |
| 3969 | val = readl_relaxed(dev->conf + ep_l1sub_cap_reg1_offset); |
| 3970 | |
| 3971 | PCIE_DBG2(dev, "EP's L1SUB_CAPABILITY_REG_1: 0x%x\n", val); |
| 3972 | PCIE_DBG2(dev, "RC%d: ep_l1sub_ctrl1_offset: 0x%x\n", |
| 3973 | dev->rc_idx, ep_l1sub_ctrl1_offset); |
| 3974 | |
| 3975 | val &= 0xf; |
| 3976 | |
| 3977 | msm_pcie_write_reg_field(dev->dm_core, PCIE20_L1SUB_CONTROL1, |
| 3978 | 0xf, val); |
| 3979 | msm_pcie_write_mask(dev->dm_core + |
| 3980 | PCIE20_DEVICE_CONTROL2_STATUS2, |
| 3981 | 0, BIT(10)); |
| 3982 | msm_pcie_write_reg_field(dev->conf, ep_l1sub_ctrl1_offset, |
| 3983 | 0xf, val); |
| 3984 | msm_pcie_write_mask(dev->conf + ep_dev_ctrl2stts2_offset, |
| 3985 | 0, BIT(10)); |
| 3986 | if (dev->shadow_en) { |
| 3987 | dev->rc_shadow[PCIE20_L1SUB_CONTROL1 / 4] = |
| 3988 | readl_relaxed(dev->dm_core + |
| 3989 | PCIE20_L1SUB_CONTROL1); |
| 3990 | dev->rc_shadow[PCIE20_DEVICE_CONTROL2_STATUS2 / 4] = |
| 3991 | readl_relaxed(dev->dm_core + |
| 3992 | PCIE20_DEVICE_CONTROL2_STATUS2); |
| 3993 | dev->ep_shadow[0][ep_l1sub_ctrl1_offset / 4] = |
| 3994 | readl_relaxed(dev->conf + |
| 3995 | ep_l1sub_ctrl1_offset); |
| 3996 | dev->ep_shadow[0][ep_dev_ctrl2stts2_offset / 4] = |
| 3997 | readl_relaxed(dev->conf + |
| 3998 | ep_dev_ctrl2stts2_offset); |
| 3999 | } |
| 4000 | PCIE_DBG2(dev, "RC's L1SUB_CONTROL1:0x%x\n", |
| 4001 | readl_relaxed(dev->dm_core + PCIE20_L1SUB_CONTROL1)); |
| 4002 | PCIE_DBG2(dev, "RC's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 4003 | readl_relaxed(dev->dm_core + |
| 4004 | PCIE20_DEVICE_CONTROL2_STATUS2)); |
| 4005 | PCIE_DBG2(dev, "EP's L1SUB_CONTROL1:0x%x\n", |
| 4006 | readl_relaxed(dev->conf + ep_l1sub_ctrl1_offset)); |
| 4007 | PCIE_DBG2(dev, "EP's DEVICE_CONTROL2_STATUS2:0x%x\n", |
| 4008 | readl_relaxed(dev->conf + |
| 4009 | ep_dev_ctrl2stts2_offset)); |
| 4010 | } |
| 4011 | } |
| 4012 | |
| 4013 | void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev) |
| 4014 | { |
| 4015 | int i; |
| 4016 | |
| 4017 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 4018 | |
| 4019 | /* program MSI controller and enable all interrupts */ |
| 4020 | writel_relaxed(MSM_PCIE_MSI_PHY, dev->dm_core + PCIE20_MSI_CTRL_ADDR); |
| 4021 | writel_relaxed(0, dev->dm_core + PCIE20_MSI_CTRL_UPPER_ADDR); |
| 4022 | |
| 4023 | for (i = 0; i < PCIE20_MSI_CTRL_MAX; i++) |
| 4024 | writel_relaxed(~0, dev->dm_core + |
| 4025 | PCIE20_MSI_CTRL_INTR_EN + (i * 12)); |
| 4026 | |
| 4027 | /* ensure that hardware is configured before proceeding */ |
| 4028 | wmb(); |
| 4029 | } |
| 4030 | |
| 4031 | static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, |
| 4032 | struct platform_device *pdev) |
| 4033 | { |
| 4034 | int i, len, cnt, ret = 0, size = 0; |
| 4035 | struct msm_pcie_vreg_info_t *vreg_info; |
| 4036 | struct msm_pcie_gpio_info_t *gpio_info; |
| 4037 | struct msm_pcie_clk_info_t *clk_info; |
| 4038 | struct resource *res; |
| 4039 | struct msm_pcie_res_info_t *res_info; |
| 4040 | struct msm_pcie_irq_info_t *irq_info; |
| 4041 | struct msm_pcie_irq_info_t *msi_info; |
| 4042 | struct msm_pcie_reset_info_t *reset_info; |
| 4043 | struct msm_pcie_reset_info_t *pipe_reset_info; |
| 4044 | char prop_name[MAX_PROP_SIZE]; |
| 4045 | const __be32 *prop; |
| 4046 | u32 *clkfreq = NULL; |
| 4047 | |
| 4048 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 4049 | |
| 4050 | cnt = of_property_count_strings((&pdev->dev)->of_node, |
| 4051 | "clock-names"); |
| 4052 | if (cnt > 0) { |
| 4053 | clkfreq = kzalloc((MSM_PCIE_MAX_CLK + MSM_PCIE_MAX_PIPE_CLK) * |
| 4054 | sizeof(*clkfreq), GFP_KERNEL); |
| 4055 | if (!clkfreq) { |
| 4056 | PCIE_ERR(dev, "PCIe: memory alloc failed for RC%d\n", |
| 4057 | dev->rc_idx); |
| 4058 | return -ENOMEM; |
| 4059 | } |
| 4060 | ret = of_property_read_u32_array( |
| 4061 | (&pdev->dev)->of_node, |
| 4062 | "max-clock-frequency-hz", clkfreq, cnt); |
| 4063 | if (ret) { |
| 4064 | PCIE_ERR(dev, |
| 4065 | "PCIe: invalid max-clock-frequency-hz property for RC%d:%d\n", |
| 4066 | dev->rc_idx, ret); |
| 4067 | goto out; |
| 4068 | } |
| 4069 | } |
| 4070 | |
| 4071 | for (i = 0; i < MSM_PCIE_MAX_VREG; i++) { |
| 4072 | vreg_info = &dev->vreg[i]; |
| 4073 | vreg_info->hdl = |
| 4074 | devm_regulator_get(&pdev->dev, vreg_info->name); |
| 4075 | |
| 4076 | if (PTR_ERR(vreg_info->hdl) == -EPROBE_DEFER) { |
| 4077 | PCIE_DBG(dev, "EPROBE_DEFER for VReg:%s\n", |
| 4078 | vreg_info->name); |
| 4079 | ret = PTR_ERR(vreg_info->hdl); |
| 4080 | goto out; |
| 4081 | } |
| 4082 | |
| 4083 | if (IS_ERR(vreg_info->hdl)) { |
| 4084 | if (vreg_info->required) { |
| 4085 | PCIE_DBG(dev, "Vreg %s doesn't exist\n", |
| 4086 | vreg_info->name); |
| 4087 | ret = PTR_ERR(vreg_info->hdl); |
| 4088 | goto out; |
| 4089 | } else { |
| 4090 | PCIE_DBG(dev, |
| 4091 | "Optional Vreg %s doesn't exist\n", |
| 4092 | vreg_info->name); |
| 4093 | vreg_info->hdl = NULL; |
| 4094 | } |
| 4095 | } else { |
| 4096 | dev->vreg_n++; |
| 4097 | snprintf(prop_name, MAX_PROP_SIZE, |
| 4098 | "qcom,%s-voltage-level", vreg_info->name); |
| 4099 | prop = of_get_property((&pdev->dev)->of_node, |
| 4100 | prop_name, &len); |
| 4101 | if (!prop || (len != (3 * sizeof(__be32)))) { |
| 4102 | PCIE_DBG(dev, "%s %s property\n", |
| 4103 | prop ? "invalid format" : |
| 4104 | "no", prop_name); |
| 4105 | } else { |
| 4106 | vreg_info->max_v = be32_to_cpup(&prop[0]); |
| 4107 | vreg_info->min_v = be32_to_cpup(&prop[1]); |
| 4108 | vreg_info->opt_mode = |
| 4109 | be32_to_cpup(&prop[2]); |
| 4110 | } |
| 4111 | } |
| 4112 | } |
| 4113 | |
| 4114 | dev->gdsc = devm_regulator_get(&pdev->dev, "gdsc-vdd"); |
| 4115 | |
| 4116 | if (IS_ERR(dev->gdsc)) { |
| 4117 | PCIE_ERR(dev, "PCIe: RC%d Failed to get %s GDSC:%ld\n", |
| 4118 | dev->rc_idx, dev->pdev->name, PTR_ERR(dev->gdsc)); |
| 4119 | if (PTR_ERR(dev->gdsc) == -EPROBE_DEFER) |
| 4120 | PCIE_DBG(dev, "PCIe: EPROBE_DEFER for %s GDSC\n", |
| 4121 | dev->pdev->name); |
| 4122 | ret = PTR_ERR(dev->gdsc); |
| 4123 | goto out; |
| 4124 | } |
| 4125 | |
| 4126 | dev->gdsc_smmu = devm_regulator_get(&pdev->dev, "gdsc-smmu"); |
| 4127 | |
| 4128 | if (IS_ERR(dev->gdsc_smmu)) { |
| 4129 | PCIE_DBG(dev, "PCIe: RC%d SMMU GDSC does not exist", |
| 4130 | dev->rc_idx); |
| 4131 | dev->gdsc_smmu = NULL; |
| 4132 | } |
| 4133 | |
| 4134 | dev->gpio_n = 0; |
| 4135 | for (i = 0; i < MSM_PCIE_MAX_GPIO; i++) { |
| 4136 | gpio_info = &dev->gpio[i]; |
| 4137 | ret = of_get_named_gpio((&pdev->dev)->of_node, |
| 4138 | gpio_info->name, 0); |
| 4139 | if (ret >= 0) { |
| 4140 | gpio_info->num = ret; |
| 4141 | dev->gpio_n++; |
| 4142 | PCIE_DBG(dev, "GPIO num for %s is %d\n", |
| 4143 | gpio_info->name, gpio_info->num); |
| 4144 | } else { |
| 4145 | if (gpio_info->required) { |
| 4146 | PCIE_ERR(dev, |
| 4147 | "Could not get required GPIO %s\n", |
| 4148 | gpio_info->name); |
| 4149 | goto out; |
| 4150 | } else { |
| 4151 | PCIE_DBG(dev, |
| 4152 | "Could not get optional GPIO %s\n", |
| 4153 | gpio_info->name); |
| 4154 | } |
| 4155 | } |
| 4156 | ret = 0; |
| 4157 | } |
| 4158 | |
| 4159 | of_get_property(pdev->dev.of_node, "qcom,phy-sequence", &size); |
| 4160 | if (size) { |
| 4161 | dev->phy_sequence = (struct msm_pcie_phy_info_t *) |
| 4162 | devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
| 4163 | |
| 4164 | if (dev->phy_sequence) { |
| 4165 | dev->phy_len = |
| 4166 | size / sizeof(*dev->phy_sequence); |
| 4167 | |
| 4168 | of_property_read_u32_array(pdev->dev.of_node, |
| 4169 | "qcom,phy-sequence", |
| 4170 | (unsigned int *)dev->phy_sequence, |
| 4171 | size / sizeof(dev->phy_sequence->offset)); |
| 4172 | } else { |
| 4173 | PCIE_ERR(dev, |
| 4174 | "RC%d: Could not allocate memory for phy init sequence.\n", |
| 4175 | dev->rc_idx); |
| 4176 | ret = -ENOMEM; |
| 4177 | goto out; |
| 4178 | } |
| 4179 | } else { |
| 4180 | PCIE_DBG(dev, "RC%d: phy sequence is not present in DT\n", |
| 4181 | dev->rc_idx); |
| 4182 | } |
| 4183 | |
| 4184 | of_get_property(pdev->dev.of_node, "qcom,port-phy-sequence", &size); |
| 4185 | if (size) { |
| 4186 | dev->port_phy_sequence = (struct msm_pcie_phy_info_t *) |
| 4187 | devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
| 4188 | |
| 4189 | if (dev->port_phy_sequence) { |
| 4190 | dev->port_phy_len = |
| 4191 | size / sizeof(*dev->port_phy_sequence); |
| 4192 | |
| 4193 | of_property_read_u32_array(pdev->dev.of_node, |
| 4194 | "qcom,port-phy-sequence", |
| 4195 | (unsigned int *)dev->port_phy_sequence, |
| 4196 | size / sizeof(dev->port_phy_sequence->offset)); |
| 4197 | } else { |
| 4198 | PCIE_ERR(dev, |
| 4199 | "RC%d: Could not allocate memory for port phy init sequence.\n", |
| 4200 | dev->rc_idx); |
| 4201 | ret = -ENOMEM; |
| 4202 | goto out; |
| 4203 | } |
| 4204 | } else { |
| 4205 | PCIE_DBG(dev, "RC%d: port phy sequence is not present in DT\n", |
| 4206 | dev->rc_idx); |
| 4207 | } |
| 4208 | |
| 4209 | for (i = 0; i < MSM_PCIE_MAX_CLK; i++) { |
| 4210 | clk_info = &dev->clk[i]; |
| 4211 | |
| 4212 | clk_info->hdl = devm_clk_get(&pdev->dev, clk_info->name); |
| 4213 | |
| 4214 | if (IS_ERR(clk_info->hdl)) { |
| 4215 | if (clk_info->required) { |
| 4216 | PCIE_DBG(dev, "Clock %s isn't available:%ld\n", |
| 4217 | clk_info->name, PTR_ERR(clk_info->hdl)); |
| 4218 | ret = PTR_ERR(clk_info->hdl); |
| 4219 | goto out; |
| 4220 | } else { |
| 4221 | PCIE_DBG(dev, "Ignoring Clock %s\n", |
| 4222 | clk_info->name); |
| 4223 | clk_info->hdl = NULL; |
| 4224 | } |
| 4225 | } else { |
| 4226 | if (clkfreq != NULL) { |
| 4227 | clk_info->freq = clkfreq[i + |
| 4228 | MSM_PCIE_MAX_PIPE_CLK]; |
| 4229 | PCIE_DBG(dev, "Freq of Clock %s is:%d\n", |
| 4230 | clk_info->name, clk_info->freq); |
| 4231 | } |
| 4232 | } |
| 4233 | } |
| 4234 | |
| 4235 | for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++) { |
| 4236 | clk_info = &dev->pipeclk[i]; |
| 4237 | |
| 4238 | clk_info->hdl = devm_clk_get(&pdev->dev, clk_info->name); |
| 4239 | |
| 4240 | if (IS_ERR(clk_info->hdl)) { |
| 4241 | if (clk_info->required) { |
| 4242 | PCIE_DBG(dev, "Clock %s isn't available:%ld\n", |
| 4243 | clk_info->name, PTR_ERR(clk_info->hdl)); |
| 4244 | ret = PTR_ERR(clk_info->hdl); |
| 4245 | goto out; |
| 4246 | } else { |
| 4247 | PCIE_DBG(dev, "Ignoring Clock %s\n", |
| 4248 | clk_info->name); |
| 4249 | clk_info->hdl = NULL; |
| 4250 | } |
| 4251 | } else { |
| 4252 | if (clkfreq != NULL) { |
| 4253 | clk_info->freq = clkfreq[i]; |
| 4254 | PCIE_DBG(dev, "Freq of Clock %s is:%d\n", |
| 4255 | clk_info->name, clk_info->freq); |
| 4256 | } |
| 4257 | } |
| 4258 | } |
| 4259 | |
| 4260 | for (i = 0; i < MSM_PCIE_MAX_RESET; i++) { |
| 4261 | reset_info = &dev->reset[i]; |
| 4262 | |
| 4263 | reset_info->hdl = devm_reset_control_get(&pdev->dev, |
| 4264 | reset_info->name); |
| 4265 | |
| 4266 | if (IS_ERR(reset_info->hdl)) { |
| 4267 | if (reset_info->required) { |
| 4268 | PCIE_DBG(dev, |
| 4269 | "Reset %s isn't available:%ld\n", |
| 4270 | reset_info->name, |
| 4271 | PTR_ERR(reset_info->hdl)); |
| 4272 | |
| 4273 | ret = PTR_ERR(reset_info->hdl); |
| 4274 | reset_info->hdl = NULL; |
| 4275 | goto out; |
| 4276 | } else { |
| 4277 | PCIE_DBG(dev, "Ignoring Reset %s\n", |
| 4278 | reset_info->name); |
| 4279 | reset_info->hdl = NULL; |
| 4280 | } |
| 4281 | } |
| 4282 | } |
| 4283 | |
| 4284 | for (i = 0; i < MSM_PCIE_MAX_PIPE_RESET; i++) { |
| 4285 | pipe_reset_info = &dev->pipe_reset[i]; |
| 4286 | |
| 4287 | pipe_reset_info->hdl = devm_reset_control_get(&pdev->dev, |
| 4288 | pipe_reset_info->name); |
| 4289 | |
| 4290 | if (IS_ERR(pipe_reset_info->hdl)) { |
| 4291 | if (pipe_reset_info->required) { |
| 4292 | PCIE_DBG(dev, |
| 4293 | "Pipe Reset %s isn't available:%ld\n", |
| 4294 | pipe_reset_info->name, |
| 4295 | PTR_ERR(pipe_reset_info->hdl)); |
| 4296 | |
| 4297 | ret = PTR_ERR(pipe_reset_info->hdl); |
| 4298 | pipe_reset_info->hdl = NULL; |
| 4299 | goto out; |
| 4300 | } else { |
| 4301 | PCIE_DBG(dev, "Ignoring Pipe Reset %s\n", |
| 4302 | pipe_reset_info->name); |
| 4303 | pipe_reset_info->hdl = NULL; |
| 4304 | } |
| 4305 | } |
| 4306 | } |
| 4307 | |
| 4308 | dev->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 4309 | if (!dev->bus_scale_table) { |
| 4310 | PCIE_DBG(dev, "PCIe: No bus scale table for RC%d (%s)\n", |
| 4311 | dev->rc_idx, dev->pdev->name); |
| 4312 | dev->bus_client = 0; |
| 4313 | } else { |
| 4314 | dev->bus_client = |
| 4315 | msm_bus_scale_register_client(dev->bus_scale_table); |
| 4316 | if (!dev->bus_client) { |
| 4317 | PCIE_ERR(dev, |
| 4318 | "PCIe: Failed to register bus client for RC%d (%s)\n", |
| 4319 | dev->rc_idx, dev->pdev->name); |
| 4320 | msm_bus_cl_clear_pdata(dev->bus_scale_table); |
| 4321 | ret = -ENODEV; |
| 4322 | goto out; |
| 4323 | } |
| 4324 | } |
| 4325 | |
| 4326 | for (i = 0; i < MSM_PCIE_MAX_RES; i++) { |
| 4327 | res_info = &dev->res[i]; |
| 4328 | |
| 4329 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 4330 | res_info->name); |
| 4331 | |
| 4332 | if (!res) { |
| 4333 | PCIE_ERR(dev, "PCIe: RC%d can't get %s resource.\n", |
| 4334 | dev->rc_idx, res_info->name); |
| 4335 | } else { |
| 4336 | PCIE_DBG(dev, "start addr for %s is %pa.\n", |
| 4337 | res_info->name, &res->start); |
| 4338 | |
| 4339 | res_info->base = devm_ioremap(&pdev->dev, |
| 4340 | res->start, resource_size(res)); |
| 4341 | if (!res_info->base) { |
| 4342 | PCIE_ERR(dev, "PCIe: RC%d can't remap %s.\n", |
| 4343 | dev->rc_idx, res_info->name); |
| 4344 | ret = -ENOMEM; |
| 4345 | goto out; |
| 4346 | } else { |
| 4347 | res_info->resource = res; |
| 4348 | } |
| 4349 | } |
| 4350 | } |
| 4351 | |
| 4352 | for (i = 0; i < MSM_PCIE_MAX_IRQ; i++) { |
| 4353 | irq_info = &dev->irq[i]; |
| 4354 | |
| 4355 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
| 4356 | irq_info->name); |
| 4357 | |
| 4358 | if (!res) { |
| 4359 | PCIE_DBG(dev, "PCIe: RC%d can't find IRQ # for %s.\n", |
| 4360 | dev->rc_idx, irq_info->name); |
| 4361 | } else { |
| 4362 | irq_info->num = res->start; |
| 4363 | PCIE_DBG(dev, "IRQ # for %s is %d.\n", irq_info->name, |
| 4364 | irq_info->num); |
| 4365 | } |
| 4366 | } |
| 4367 | |
| 4368 | for (i = 0; i < MSM_PCIE_MAX_MSI; i++) { |
| 4369 | msi_info = &dev->msi[i]; |
| 4370 | |
| 4371 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
| 4372 | msi_info->name); |
| 4373 | |
| 4374 | if (!res) { |
| 4375 | PCIE_DBG(dev, "PCIe: RC%d can't find IRQ # for %s.\n", |
| 4376 | dev->rc_idx, msi_info->name); |
| 4377 | } else { |
| 4378 | msi_info->num = res->start; |
| 4379 | PCIE_DBG(dev, "IRQ # for %s is %d.\n", msi_info->name, |
| 4380 | msi_info->num); |
| 4381 | } |
| 4382 | } |
| 4383 | |
| 4384 | /* All allocations succeeded */ |
| 4385 | |
| 4386 | if (dev->gpio[MSM_PCIE_GPIO_WAKE].num) |
| 4387 | dev->wake_n = gpio_to_irq(dev->gpio[MSM_PCIE_GPIO_WAKE].num); |
| 4388 | else |
| 4389 | dev->wake_n = 0; |
| 4390 | |
| 4391 | dev->parf = dev->res[MSM_PCIE_RES_PARF].base; |
| 4392 | dev->phy = dev->res[MSM_PCIE_RES_PHY].base; |
| 4393 | dev->elbi = dev->res[MSM_PCIE_RES_ELBI].base; |
| 4394 | dev->dm_core = dev->res[MSM_PCIE_RES_DM_CORE].base; |
| 4395 | dev->conf = dev->res[MSM_PCIE_RES_CONF].base; |
| 4396 | dev->bars = dev->res[MSM_PCIE_RES_BARS].base; |
| 4397 | dev->tcsr = dev->res[MSM_PCIE_RES_TCSR].base; |
| 4398 | dev->dev_mem_res = dev->res[MSM_PCIE_RES_BARS].resource; |
| 4399 | dev->dev_io_res = dev->res[MSM_PCIE_RES_IO].resource; |
| 4400 | dev->dev_io_res->flags = IORESOURCE_IO; |
| 4401 | |
| 4402 | out: |
| 4403 | kfree(clkfreq); |
| 4404 | |
| 4405 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 4406 | |
| 4407 | return ret; |
| 4408 | } |
| 4409 | |
| 4410 | static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) |
| 4411 | { |
| 4412 | dev->parf = NULL; |
| 4413 | dev->elbi = NULL; |
| 4414 | dev->dm_core = NULL; |
| 4415 | dev->conf = NULL; |
| 4416 | dev->bars = NULL; |
| 4417 | dev->tcsr = NULL; |
| 4418 | dev->dev_mem_res = NULL; |
| 4419 | dev->dev_io_res = NULL; |
| 4420 | } |
| 4421 | |
| 4422 | int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) |
| 4423 | { |
| 4424 | int ret = 0; |
| 4425 | uint32_t val; |
| 4426 | long int retries = 0; |
| 4427 | int link_check_count = 0; |
| 4428 | |
| 4429 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 4430 | |
| 4431 | mutex_lock(&dev->setup_lock); |
| 4432 | |
| 4433 | if (dev->link_status == MSM_PCIE_LINK_ENABLED) { |
| 4434 | PCIE_ERR(dev, "PCIe: the link of RC%d is already enabled\n", |
| 4435 | dev->rc_idx); |
| 4436 | goto out; |
| 4437 | } |
| 4438 | |
| 4439 | /* assert PCIe reset link to keep EP in reset */ |
| 4440 | |
| 4441 | PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n", |
| 4442 | dev->rc_idx); |
| 4443 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, |
| 4444 | dev->gpio[MSM_PCIE_GPIO_PERST].on); |
| 4445 | usleep_range(PERST_PROPAGATION_DELAY_US_MIN, |
| 4446 | PERST_PROPAGATION_DELAY_US_MAX); |
| 4447 | |
| 4448 | /* enable power */ |
| 4449 | |
| 4450 | if (options & PM_VREG) { |
| 4451 | ret = msm_pcie_vreg_init(dev); |
| 4452 | if (ret) |
| 4453 | goto out; |
| 4454 | } |
| 4455 | |
| 4456 | /* enable clocks */ |
| 4457 | if (options & PM_CLK) { |
| 4458 | ret = msm_pcie_clk_init(dev); |
| 4459 | /* ensure that changes propagated to the hardware */ |
| 4460 | wmb(); |
| 4461 | if (ret) |
| 4462 | goto clk_fail; |
| 4463 | } |
| 4464 | |
| 4465 | if (dev->scm_dev_id) { |
| 4466 | PCIE_DBG(dev, "RC%d: restoring sec config\n", dev->rc_idx); |
| 4467 | msm_pcie_restore_sec_config(dev); |
| 4468 | } |
| 4469 | |
| 4470 | /* enable PCIe clocks and resets */ |
| 4471 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); |
| 4472 | |
| 4473 | /* change DBI base address */ |
| 4474 | writel_relaxed(0, dev->parf + PCIE20_PARF_DBI_BASE_ADDR); |
| 4475 | |
| 4476 | writel_relaxed(0x365E, dev->parf + PCIE20_PARF_SYS_CTRL); |
| 4477 | |
| 4478 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL, |
| 4479 | 0, BIT(4)); |
| 4480 | |
| 4481 | /* enable selected IRQ */ |
| 4482 | if (dev->irq[MSM_PCIE_INT_GLOBAL_INT].num) { |
| 4483 | msm_pcie_write_reg(dev->parf, PCIE20_PARF_INT_ALL_MASK, 0); |
| 4484 | |
| 4485 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_INT_ALL_MASK, 0, |
| 4486 | BIT(MSM_PCIE_INT_EVT_LINK_DOWN) | |
| 4487 | BIT(MSM_PCIE_INT_EVT_AER_LEGACY) | |
| 4488 | BIT(MSM_PCIE_INT_EVT_AER_ERR) | |
| 4489 | BIT(MSM_PCIE_INT_EVT_MSI_0) | |
| 4490 | BIT(MSM_PCIE_INT_EVT_MSI_1) | |
| 4491 | BIT(MSM_PCIE_INT_EVT_MSI_2) | |
| 4492 | BIT(MSM_PCIE_INT_EVT_MSI_3) | |
| 4493 | BIT(MSM_PCIE_INT_EVT_MSI_4) | |
| 4494 | BIT(MSM_PCIE_INT_EVT_MSI_5) | |
| 4495 | BIT(MSM_PCIE_INT_EVT_MSI_6) | |
| 4496 | BIT(MSM_PCIE_INT_EVT_MSI_7)); |
| 4497 | |
| 4498 | PCIE_DBG(dev, "PCIe: RC%d: PCIE20_PARF_INT_ALL_MASK: 0x%x\n", |
| 4499 | dev->rc_idx, |
| 4500 | readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK)); |
| 4501 | } |
| 4502 | |
| 4503 | if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_16M) |
| 4504 | writel_relaxed(SZ_32M, dev->parf + |
| 4505 | PCIE20_PARF_SLV_ADDR_SPACE_SIZE); |
| 4506 | else if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M) |
| 4507 | writel_relaxed(SZ_16M, dev->parf + |
| 4508 | PCIE20_PARF_SLV_ADDR_SPACE_SIZE); |
| 4509 | else |
| 4510 | writel_relaxed(SZ_8M, dev->parf + |
| 4511 | PCIE20_PARF_SLV_ADDR_SPACE_SIZE); |
| 4512 | |
| 4513 | if (dev->use_msi) { |
| 4514 | PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx); |
| 4515 | val = dev->wr_halt_size ? dev->wr_halt_size : |
| 4516 | readl_relaxed(dev->parf + |
| 4517 | PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); |
| 4518 | |
| 4519 | msm_pcie_write_reg(dev->parf, |
| 4520 | PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, |
| 4521 | BIT(31) | val); |
| 4522 | |
| 4523 | PCIE_DBG(dev, |
| 4524 | "RC%d: PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT: 0x%x.\n", |
| 4525 | dev->rc_idx, |
| 4526 | readl_relaxed(dev->parf + |
| 4527 | PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT)); |
| 4528 | } |
| 4529 | |
| 4530 | mutex_lock(&com_phy_lock); |
| 4531 | /* init PCIe PHY */ |
| 4532 | if (!num_rc_on) |
| 4533 | pcie_phy_init(dev); |
| 4534 | |
| 4535 | num_rc_on++; |
| 4536 | mutex_unlock(&com_phy_lock); |
| 4537 | |
| 4538 | if (options & PM_PIPE_CLK) { |
| 4539 | usleep_range(PHY_STABILIZATION_DELAY_US_MIN, |
| 4540 | PHY_STABILIZATION_DELAY_US_MAX); |
| 4541 | /* Enable the pipe clock */ |
| 4542 | ret = msm_pcie_pipe_clk_init(dev); |
| 4543 | /* ensure that changes propagated to the hardware */ |
| 4544 | wmb(); |
| 4545 | if (ret) |
| 4546 | goto link_fail; |
| 4547 | } |
| 4548 | |
| 4549 | PCIE_DBG(dev, "RC%d: waiting for phy ready...\n", dev->rc_idx); |
| 4550 | |
| 4551 | do { |
| 4552 | if (pcie_phy_is_ready(dev)) |
| 4553 | break; |
| 4554 | retries++; |
| 4555 | usleep_range(REFCLK_STABILIZATION_DELAY_US_MIN, |
| 4556 | REFCLK_STABILIZATION_DELAY_US_MAX); |
| 4557 | } while (retries < PHY_READY_TIMEOUT_COUNT); |
| 4558 | |
| 4559 | PCIE_DBG(dev, "RC%d: number of PHY retries:%ld.\n", |
| 4560 | dev->rc_idx, retries); |
| 4561 | |
| 4562 | if (pcie_phy_is_ready(dev)) |
| 4563 | PCIE_INFO(dev, "PCIe RC%d PHY is ready!\n", dev->rc_idx); |
| 4564 | else { |
| 4565 | PCIE_ERR(dev, "PCIe PHY RC%d failed to come up!\n", |
| 4566 | dev->rc_idx); |
| 4567 | ret = -ENODEV; |
| 4568 | pcie_phy_dump(dev); |
| 4569 | goto link_fail; |
| 4570 | } |
| 4571 | |
| 4572 | pcie_pcs_port_phy_init(dev); |
| 4573 | |
| 4574 | if (dev->ep_latency) |
| 4575 | usleep_range(dev->ep_latency * 1000, dev->ep_latency * 1000); |
| 4576 | |
| 4577 | if (dev->gpio[MSM_PCIE_GPIO_EP].num) |
| 4578 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_EP].num, |
| 4579 | dev->gpio[MSM_PCIE_GPIO_EP].on); |
| 4580 | |
| 4581 | /* de-assert PCIe reset link to bring EP out of reset */ |
| 4582 | |
| 4583 | PCIE_INFO(dev, "PCIe: Release the reset of endpoint of RC%d.\n", |
| 4584 | dev->rc_idx); |
| 4585 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, |
| 4586 | 1 - dev->gpio[MSM_PCIE_GPIO_PERST].on); |
| 4587 | usleep_range(dev->perst_delay_us_min, dev->perst_delay_us_max); |
| 4588 | |
| 4589 | /* set max tlp read size */ |
| 4590 | msm_pcie_write_reg_field(dev->dm_core, PCIE20_DEVICE_CONTROL_STATUS, |
| 4591 | 0x7000, dev->tlp_rd_size); |
| 4592 | |
| 4593 | /* enable link training */ |
| 4594 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_LTSSM, 0, BIT(8)); |
| 4595 | |
| 4596 | PCIE_DBG(dev, "%s", "check if link is up\n"); |
| 4597 | |
| 4598 | /* Wait for up to 100ms for the link to come up */ |
| 4599 | do { |
| 4600 | usleep_range(LINK_UP_TIMEOUT_US_MIN, LINK_UP_TIMEOUT_US_MAX); |
| 4601 | val = readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS); |
| 4602 | } while ((!(val & XMLH_LINK_UP) || |
| 4603 | !msm_pcie_confirm_linkup(dev, false, false, NULL)) |
| 4604 | && (link_check_count++ < LINK_UP_CHECK_MAX_COUNT)); |
| 4605 | |
| 4606 | if ((val & XMLH_LINK_UP) && |
| 4607 | msm_pcie_confirm_linkup(dev, false, false, NULL)) { |
| 4608 | PCIE_DBG(dev, "Link is up after %d checkings\n", |
| 4609 | link_check_count); |
| 4610 | PCIE_INFO(dev, "PCIe RC%d link initialized\n", dev->rc_idx); |
| 4611 | } else { |
| 4612 | PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n", |
| 4613 | dev->rc_idx); |
| 4614 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, |
| 4615 | dev->gpio[MSM_PCIE_GPIO_PERST].on); |
| 4616 | PCIE_ERR(dev, "PCIe RC%d link initialization failed\n", |
| 4617 | dev->rc_idx); |
| 4618 | ret = -1; |
| 4619 | goto link_fail; |
| 4620 | } |
| 4621 | |
| 4622 | msm_pcie_config_controller(dev); |
| 4623 | |
| 4624 | if (!dev->msi_gicm_addr) |
| 4625 | msm_pcie_config_msi_controller(dev); |
| 4626 | |
| 4627 | msm_pcie_config_link_state(dev); |
| 4628 | |
| 4629 | dev->link_status = MSM_PCIE_LINK_ENABLED; |
| 4630 | dev->power_on = true; |
| 4631 | dev->suspending = false; |
| 4632 | dev->link_turned_on_counter++; |
| 4633 | |
| 4634 | goto out; |
| 4635 | |
| 4636 | link_fail: |
| 4637 | if (dev->gpio[MSM_PCIE_GPIO_EP].num) |
| 4638 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_EP].num, |
| 4639 | 1 - dev->gpio[MSM_PCIE_GPIO_EP].on); |
| 4640 | msm_pcie_write_reg(dev->phy, |
| 4641 | PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1); |
| 4642 | msm_pcie_write_reg(dev->phy, |
| 4643 | PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0); |
| 4644 | |
| 4645 | mutex_lock(&com_phy_lock); |
| 4646 | num_rc_on--; |
| 4647 | if (!num_rc_on && dev->common_phy) { |
| 4648 | PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n", |
| 4649 | dev->rc_idx); |
| 4650 | msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1); |
| 4651 | msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0); |
| 4652 | } |
| 4653 | mutex_unlock(&com_phy_lock); |
| 4654 | |
| 4655 | msm_pcie_pipe_clk_deinit(dev); |
| 4656 | msm_pcie_clk_deinit(dev); |
| 4657 | clk_fail: |
| 4658 | msm_pcie_vreg_deinit(dev); |
| 4659 | out: |
| 4660 | mutex_unlock(&dev->setup_lock); |
| 4661 | |
| 4662 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 4663 | |
| 4664 | return ret; |
| 4665 | } |
| 4666 | |
| 4667 | void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options) |
| 4668 | { |
| 4669 | PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx); |
| 4670 | |
| 4671 | mutex_lock(&dev->setup_lock); |
| 4672 | |
| 4673 | if (!dev->power_on) { |
| 4674 | PCIE_DBG(dev, |
| 4675 | "PCIe: the link of RC%d is already power down.\n", |
| 4676 | dev->rc_idx); |
| 4677 | mutex_unlock(&dev->setup_lock); |
| 4678 | return; |
| 4679 | } |
| 4680 | |
| 4681 | dev->link_status = MSM_PCIE_LINK_DISABLED; |
| 4682 | dev->power_on = false; |
| 4683 | dev->link_turned_off_counter++; |
| 4684 | |
| 4685 | PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n", |
| 4686 | dev->rc_idx); |
| 4687 | |
| 4688 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, |
| 4689 | dev->gpio[MSM_PCIE_GPIO_PERST].on); |
| 4690 | |
| 4691 | msm_pcie_write_reg(dev->phy, |
| 4692 | PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1); |
| 4693 | msm_pcie_write_reg(dev->phy, |
| 4694 | PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0); |
| 4695 | |
| 4696 | mutex_lock(&com_phy_lock); |
| 4697 | num_rc_on--; |
| 4698 | if (!num_rc_on && dev->common_phy) { |
| 4699 | PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n", |
| 4700 | dev->rc_idx); |
| 4701 | msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1); |
| 4702 | msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0); |
| 4703 | } |
| 4704 | mutex_unlock(&com_phy_lock); |
| 4705 | |
| 4706 | if (options & PM_CLK) { |
| 4707 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, 0, |
| 4708 | BIT(0)); |
| 4709 | msm_pcie_clk_deinit(dev); |
| 4710 | } |
| 4711 | |
| 4712 | if (options & PM_VREG) |
| 4713 | msm_pcie_vreg_deinit(dev); |
| 4714 | |
| 4715 | if (options & PM_PIPE_CLK) |
| 4716 | msm_pcie_pipe_clk_deinit(dev); |
| 4717 | |
| 4718 | if (dev->gpio[MSM_PCIE_GPIO_EP].num) |
| 4719 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_EP].num, |
| 4720 | 1 - dev->gpio[MSM_PCIE_GPIO_EP].on); |
| 4721 | |
| 4722 | mutex_unlock(&dev->setup_lock); |
| 4723 | |
| 4724 | PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx); |
| 4725 | } |
| 4726 | |
| 4727 | static void msm_pcie_config_ep_aer(struct msm_pcie_dev_t *dev, |
| 4728 | struct msm_pcie_device_info *ep_dev_info) |
| 4729 | { |
| 4730 | u32 val; |
| 4731 | void __iomem *ep_base = ep_dev_info->conf_base; |
| 4732 | u32 current_offset = readl_relaxed(ep_base + PCIE_CAP_PTR_OFFSET) & |
| 4733 | 0xff; |
| 4734 | |
| 4735 | while (current_offset) { |
| 4736 | if (msm_pcie_check_align(dev, current_offset)) |
| 4737 | return; |
| 4738 | |
| 4739 | val = readl_relaxed(ep_base + current_offset); |
| 4740 | if ((val & 0xff) == PCIE20_CAP_ID) { |
| 4741 | ep_dev_info->dev_ctrlstts_offset = |
| 4742 | current_offset + 0x8; |
| 4743 | break; |
| 4744 | } |
| 4745 | current_offset = (val >> 8) & 0xff; |
| 4746 | } |
| 4747 | |
| 4748 | if (!ep_dev_info->dev_ctrlstts_offset) { |
| 4749 | PCIE_DBG(dev, |
| 4750 | "RC%d endpoint does not support PCIe cap registers\n", |
| 4751 | dev->rc_idx); |
| 4752 | return; |
| 4753 | } |
| 4754 | |
| 4755 | PCIE_DBG2(dev, "RC%d: EP dev_ctrlstts_offset: 0x%x\n", |
| 4756 | dev->rc_idx, ep_dev_info->dev_ctrlstts_offset); |
| 4757 | |
| 4758 | /* Enable AER on EP */ |
| 4759 | msm_pcie_write_mask(ep_base + ep_dev_info->dev_ctrlstts_offset, 0, |
| 4760 | BIT(3)|BIT(2)|BIT(1)|BIT(0)); |
| 4761 | |
| 4762 | PCIE_DBG(dev, "EP's PCIE20_CAP_DEVCTRLSTATUS:0x%x\n", |
| 4763 | readl_relaxed(ep_base + ep_dev_info->dev_ctrlstts_offset)); |
| 4764 | } |
| 4765 | |
| 4766 | static int msm_pcie_config_device_table(struct device *dev, void *pdev) |
| 4767 | { |
| 4768 | struct pci_dev *pcidev = to_pci_dev(dev); |
| 4769 | struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *) pdev; |
| 4770 | struct msm_pcie_device_info *dev_table_t = pcie_dev->pcidev_table; |
| 4771 | struct resource *axi_conf = pcie_dev->res[MSM_PCIE_RES_CONF].resource; |
| 4772 | int ret = 0; |
| 4773 | u32 rc_idx = pcie_dev->rc_idx; |
| 4774 | u32 i, index; |
| 4775 | u32 bdf = 0; |
| 4776 | u8 type; |
| 4777 | u32 h_type; |
| 4778 | u32 bme; |
| 4779 | |
| 4780 | if (!pcidev) { |
| 4781 | PCIE_ERR(pcie_dev, |
| 4782 | "PCIe: Did not find PCI device in list for RC%d.\n", |
| 4783 | pcie_dev->rc_idx); |
| 4784 | return -ENODEV; |
| 4785 | } |
| 4786 | |
| 4787 | PCIE_DBG(pcie_dev, |
| 4788 | "PCI device found: vendor-id:0x%x device-id:0x%x\n", |
| 4789 | pcidev->vendor, pcidev->device); |
| 4790 | |
| 4791 | if (!pcidev->bus->number) |
| 4792 | return ret; |
| 4793 | |
| 4794 | bdf = BDF_OFFSET(pcidev->bus->number, pcidev->devfn); |
| 4795 | type = pcidev->bus->number == 1 ? |
| 4796 | PCIE20_CTRL1_TYPE_CFG0 : PCIE20_CTRL1_TYPE_CFG1; |
| 4797 | |
| 4798 | for (i = 0; i < (MAX_RC_NUM * MAX_DEVICE_NUM); i++) { |
| 4799 | if (msm_pcie_dev_tbl[i].bdf == bdf && |
| 4800 | !msm_pcie_dev_tbl[i].dev) { |
| 4801 | for (index = 0; index < MAX_DEVICE_NUM; index++) { |
| 4802 | if (dev_table_t[index].bdf == bdf) { |
| 4803 | msm_pcie_dev_tbl[i].dev = pcidev; |
| 4804 | msm_pcie_dev_tbl[i].domain = rc_idx; |
| 4805 | msm_pcie_dev_tbl[i].conf_base = |
| 4806 | pcie_dev->conf + index * SZ_4K; |
| 4807 | msm_pcie_dev_tbl[i].phy_address = |
| 4808 | axi_conf->start + index * SZ_4K; |
| 4809 | |
| 4810 | dev_table_t[index].dev = pcidev; |
| 4811 | dev_table_t[index].domain = rc_idx; |
| 4812 | dev_table_t[index].conf_base = |
| 4813 | pcie_dev->conf + index * SZ_4K; |
| 4814 | dev_table_t[index].phy_address = |
| 4815 | axi_conf->start + index * SZ_4K; |
| 4816 | |
| 4817 | msm_pcie_iatu_config(pcie_dev, index, |
| 4818 | type, |
| 4819 | dev_table_t[index].phy_address, |
| 4820 | dev_table_t[index].phy_address |
| 4821 | + SZ_4K - 1, |
| 4822 | bdf); |
| 4823 | |
| 4824 | h_type = readl_relaxed( |
| 4825 | dev_table_t[index].conf_base + |
| 4826 | PCIE20_HEADER_TYPE); |
| 4827 | |
| 4828 | bme = readl_relaxed( |
| 4829 | dev_table_t[index].conf_base + |
| 4830 | PCIE20_COMMAND_STATUS); |
| 4831 | |
| 4832 | if (h_type & (1 << 16)) { |
| 4833 | pci_write_config_dword(pcidev, |
| 4834 | PCIE20_COMMAND_STATUS, |
| 4835 | bme | 0x06); |
| 4836 | } else { |
| 4837 | pcie_dev->num_ep++; |
| 4838 | dev_table_t[index].registered = |
| 4839 | false; |
| 4840 | } |
| 4841 | |
| 4842 | if (pcie_dev->num_ep > 1) |
| 4843 | pcie_dev->pending_ep_reg = true; |
| 4844 | |
| 4845 | msm_pcie_config_ep_aer(pcie_dev, |
| 4846 | &dev_table_t[index]); |
| 4847 | |
| 4848 | break; |
| 4849 | } |
| 4850 | } |
| 4851 | if (index == MAX_DEVICE_NUM) { |
| 4852 | PCIE_ERR(pcie_dev, |
| 4853 | "RC%d PCI device table is full.\n", |
| 4854 | rc_idx); |
| 4855 | ret = index; |
| 4856 | } else { |
| 4857 | break; |
| 4858 | } |
| 4859 | } else if (msm_pcie_dev_tbl[i].bdf == bdf && |
| 4860 | pcidev == msm_pcie_dev_tbl[i].dev) { |
| 4861 | break; |
| 4862 | } |
| 4863 | } |
| 4864 | if (i == MAX_RC_NUM * MAX_DEVICE_NUM) { |
| 4865 | PCIE_ERR(pcie_dev, |
| 4866 | "Global PCI device table is full: %d elements.\n", |
| 4867 | i); |
| 4868 | PCIE_ERR(pcie_dev, |
| 4869 | "Bus number is 0x%x\nDevice number is 0x%x\n", |
| 4870 | pcidev->bus->number, pcidev->devfn); |
| 4871 | ret = i; |
| 4872 | } |
| 4873 | return ret; |
| 4874 | } |
| 4875 | |
| 4876 | int msm_pcie_configure_sid(struct device *dev, u32 *sid, int *domain) |
| 4877 | { |
| 4878 | struct pci_dev *pcidev; |
| 4879 | struct msm_pcie_dev_t *pcie_dev; |
| 4880 | struct pci_bus *bus; |
| 4881 | int i; |
| 4882 | u32 bdf; |
| 4883 | |
| 4884 | if (!dev) { |
| 4885 | pr_err("%s: PCIe: endpoint device passed in is NULL\n", |
| 4886 | __func__); |
| 4887 | return MSM_PCIE_ERROR; |
| 4888 | } |
| 4889 | |
| 4890 | pcidev = to_pci_dev(dev); |
| 4891 | if (!pcidev) { |
| 4892 | pr_err("%s: PCIe: PCI device of endpoint is NULL\n", |
| 4893 | __func__); |
| 4894 | return MSM_PCIE_ERROR; |
| 4895 | } |
| 4896 | |
| 4897 | bus = pcidev->bus; |
| 4898 | if (!bus) { |
| 4899 | pr_err("%s: PCIe: Bus of PCI device is NULL\n", |
| 4900 | __func__); |
| 4901 | return MSM_PCIE_ERROR; |
| 4902 | } |
| 4903 | |
| 4904 | while (!pci_is_root_bus(bus)) |
| 4905 | bus = bus->parent; |
| 4906 | |
| 4907 | pcie_dev = (struct msm_pcie_dev_t *)(bus->sysdata); |
| 4908 | if (!pcie_dev) { |
| 4909 | pr_err("%s: PCIe: Could not get PCIe structure\n", |
| 4910 | __func__); |
| 4911 | return MSM_PCIE_ERROR; |
| 4912 | } |
| 4913 | |
| 4914 | if (!pcie_dev->smmu_exist) { |
| 4915 | PCIE_DBG(pcie_dev, |
| 4916 | "PCIe: RC:%d: smmu does not exist\n", |
| 4917 | pcie_dev->rc_idx); |
| 4918 | return MSM_PCIE_ERROR; |
| 4919 | } |
| 4920 | |
| 4921 | PCIE_DBG(pcie_dev, "PCIe: RC%d: device address is: %p\n", |
| 4922 | pcie_dev->rc_idx, dev); |
| 4923 | PCIE_DBG(pcie_dev, "PCIe: RC%d: PCI device address is: %p\n", |
| 4924 | pcie_dev->rc_idx, pcidev); |
| 4925 | |
| 4926 | *domain = pcie_dev->rc_idx; |
| 4927 | |
| 4928 | if (pcie_dev->current_short_bdf < (MAX_SHORT_BDF_NUM - 1)) { |
| 4929 | pcie_dev->current_short_bdf++; |
| 4930 | } else { |
| 4931 | PCIE_ERR(pcie_dev, |
| 4932 | "PCIe: RC%d: No more short BDF left\n", |
| 4933 | pcie_dev->rc_idx); |
| 4934 | return MSM_PCIE_ERROR; |
| 4935 | } |
| 4936 | |
| 4937 | bdf = BDF_OFFSET(pcidev->bus->number, pcidev->devfn); |
| 4938 | |
| 4939 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 4940 | if (pcie_dev->pcidev_table[i].bdf == bdf) { |
| 4941 | *sid = pcie_dev->smmu_sid_base + |
| 4942 | ((pcie_dev->rc_idx << 4) | |
| 4943 | pcie_dev->current_short_bdf); |
| 4944 | |
| 4945 | msm_pcie_write_reg(pcie_dev->parf, |
| 4946 | PCIE20_PARF_BDF_TRANSLATE_N + |
| 4947 | pcie_dev->current_short_bdf * 4, |
| 4948 | bdf >> 16); |
| 4949 | |
| 4950 | pcie_dev->pcidev_table[i].sid = *sid; |
| 4951 | pcie_dev->pcidev_table[i].short_bdf = |
| 4952 | pcie_dev->current_short_bdf; |
| 4953 | break; |
| 4954 | } |
| 4955 | } |
| 4956 | |
| 4957 | if (i == MAX_DEVICE_NUM) { |
| 4958 | pcie_dev->current_short_bdf--; |
| 4959 | PCIE_ERR(pcie_dev, |
| 4960 | "PCIe: RC%d could not find BDF:%d\n", |
| 4961 | pcie_dev->rc_idx, bdf); |
| 4962 | return MSM_PCIE_ERROR; |
| 4963 | } |
| 4964 | |
| 4965 | PCIE_DBG(pcie_dev, |
| 4966 | "PCIe: RC%d: Device: %02x:%02x.%01x received SID %d\n", |
| 4967 | pcie_dev->rc_idx, |
| 4968 | bdf >> 24, |
| 4969 | bdf >> 19 & 0x1f, |
| 4970 | bdf >> 16 & 0x07, |
| 4971 | *sid); |
| 4972 | |
| 4973 | return 0; |
| 4974 | } |
| 4975 | EXPORT_SYMBOL(msm_pcie_configure_sid); |
| 4976 | |
| 4977 | int msm_pcie_enumerate(u32 rc_idx) |
| 4978 | { |
| 4979 | int ret = 0, bus_ret = 0, scan_ret = 0; |
| 4980 | struct msm_pcie_dev_t *dev = &msm_pcie_dev[rc_idx]; |
| 4981 | |
| 4982 | mutex_lock(&dev->enumerate_lock); |
| 4983 | |
| 4984 | PCIE_DBG(dev, "Enumerate RC%d\n", rc_idx); |
| 4985 | |
| 4986 | if (!dev->drv_ready) { |
| 4987 | PCIE_DBG(dev, "RC%d has not been successfully probed yet\n", |
| 4988 | rc_idx); |
| 4989 | ret = -EPROBE_DEFER; |
| 4990 | goto out; |
| 4991 | } |
| 4992 | |
| 4993 | if (!dev->enumerated) { |
| 4994 | ret = msm_pcie_enable(dev, PM_ALL); |
| 4995 | |
| 4996 | /* kick start ARM PCI configuration framework */ |
| 4997 | if (!ret) { |
| 4998 | struct pci_dev *pcidev = NULL; |
| 4999 | bool found = false; |
| 5000 | struct pci_bus *bus; |
| 5001 | resource_size_t iobase = 0; |
| 5002 | u32 ids = readl_relaxed(msm_pcie_dev[rc_idx].dm_core); |
| 5003 | u32 vendor_id = ids & 0xffff; |
| 5004 | u32 device_id = (ids & 0xffff0000) >> 16; |
| 5005 | LIST_HEAD(res); |
| 5006 | |
| 5007 | PCIE_DBG(dev, "vendor-id:0x%x device_id:0x%x\n", |
| 5008 | vendor_id, device_id); |
| 5009 | |
| 5010 | ret = of_pci_get_host_bridge_resources( |
| 5011 | dev->pdev->dev.of_node, |
| 5012 | 0, 0xff, &res, &iobase); |
| 5013 | if (ret) { |
| 5014 | PCIE_ERR(dev, |
| 5015 | "PCIe: failed to get host bridge resources for RC%d: %d\n", |
| 5016 | dev->rc_idx, ret); |
| 5017 | goto out; |
| 5018 | } |
| 5019 | |
| 5020 | bus = pci_create_root_bus(&dev->pdev->dev, 0, |
| 5021 | &msm_pcie_ops, |
| 5022 | msm_pcie_setup_sys_data(dev), |
| 5023 | &res); |
| 5024 | if (!bus) { |
| 5025 | PCIE_ERR(dev, |
| 5026 | "PCIe: failed to create root bus for RC%d\n", |
| 5027 | dev->rc_idx); |
| 5028 | ret = -ENOMEM; |
| 5029 | goto out; |
| 5030 | } |
| 5031 | |
| 5032 | scan_ret = pci_scan_child_bus(bus); |
| 5033 | PCIE_DBG(dev, |
| 5034 | "PCIe: RC%d: The max subordinate bus number discovered is %d\n", |
| 5035 | dev->rc_idx, ret); |
| 5036 | |
| 5037 | msm_pcie_fixup_irqs(dev); |
| 5038 | pci_assign_unassigned_bus_resources(bus); |
| 5039 | pci_bus_add_devices(bus); |
| 5040 | |
| 5041 | dev->enumerated = true; |
| 5042 | |
| 5043 | msm_pcie_write_mask(dev->dm_core + |
| 5044 | PCIE20_COMMAND_STATUS, 0, BIT(2)|BIT(1)); |
| 5045 | |
| 5046 | if (dev->cpl_timeout && dev->bridge_found) |
| 5047 | msm_pcie_write_reg_field(dev->dm_core, |
| 5048 | PCIE20_DEVICE_CONTROL2_STATUS2, |
| 5049 | 0xf, dev->cpl_timeout); |
| 5050 | |
| 5051 | if (dev->shadow_en) { |
| 5052 | u32 val = readl_relaxed(dev->dm_core + |
| 5053 | PCIE20_COMMAND_STATUS); |
| 5054 | PCIE_DBG(dev, "PCIE20_COMMAND_STATUS:0x%x\n", |
| 5055 | val); |
| 5056 | dev->rc_shadow[PCIE20_COMMAND_STATUS / 4] = val; |
| 5057 | } |
| 5058 | |
| 5059 | do { |
| 5060 | pcidev = pci_get_device(vendor_id, |
| 5061 | device_id, pcidev); |
| 5062 | if (pcidev && (&msm_pcie_dev[rc_idx] == |
| 5063 | (struct msm_pcie_dev_t *) |
| 5064 | PCIE_BUS_PRIV_DATA(pcidev->bus))) { |
| 5065 | msm_pcie_dev[rc_idx].dev = pcidev; |
| 5066 | found = true; |
| 5067 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 5068 | "PCI device is found for RC%d\n", |
| 5069 | rc_idx); |
| 5070 | } |
| 5071 | } while (!found && pcidev); |
| 5072 | |
| 5073 | if (!pcidev) { |
| 5074 | PCIE_ERR(dev, |
| 5075 | "PCIe: Did not find PCI device for RC%d.\n", |
| 5076 | dev->rc_idx); |
| 5077 | ret = -ENODEV; |
| 5078 | goto out; |
| 5079 | } |
| 5080 | |
| 5081 | bus_ret = bus_for_each_dev(&pci_bus_type, NULL, dev, |
| 5082 | &msm_pcie_config_device_table); |
| 5083 | |
| 5084 | if (bus_ret) { |
| 5085 | PCIE_ERR(dev, |
| 5086 | "PCIe: Failed to set up device table for RC%d\n", |
| 5087 | dev->rc_idx); |
| 5088 | ret = -ENODEV; |
| 5089 | goto out; |
| 5090 | } |
| 5091 | } else { |
| 5092 | PCIE_ERR(dev, "PCIe: failed to enable RC%d.\n", |
| 5093 | dev->rc_idx); |
| 5094 | } |
| 5095 | } else { |
| 5096 | PCIE_ERR(dev, "PCIe: RC%d has already been enumerated.\n", |
| 5097 | dev->rc_idx); |
| 5098 | } |
| 5099 | |
| 5100 | out: |
| 5101 | mutex_unlock(&dev->enumerate_lock); |
| 5102 | |
| 5103 | return ret; |
| 5104 | } |
| 5105 | EXPORT_SYMBOL(msm_pcie_enumerate); |
| 5106 | |
| 5107 | static void msm_pcie_notify_client(struct msm_pcie_dev_t *dev, |
| 5108 | enum msm_pcie_event event) |
| 5109 | { |
| 5110 | if (dev->event_reg && dev->event_reg->callback && |
| 5111 | (dev->event_reg->events & event)) { |
| 5112 | struct msm_pcie_notify *notify = &dev->event_reg->notify; |
| 5113 | |
| 5114 | notify->event = event; |
| 5115 | notify->user = dev->event_reg->user; |
| 5116 | PCIE_DBG(dev, "PCIe: callback RC%d for event %d\n", |
| 5117 | dev->rc_idx, event); |
| 5118 | dev->event_reg->callback(notify); |
| 5119 | |
| 5120 | if ((dev->event_reg->options & MSM_PCIE_CONFIG_NO_RECOVERY) && |
| 5121 | (event == MSM_PCIE_EVENT_LINKDOWN)) { |
| 5122 | dev->user_suspend = true; |
| 5123 | PCIE_DBG(dev, |
| 5124 | "PCIe: Client of RC%d will recover the link later.\n", |
| 5125 | dev->rc_idx); |
| 5126 | return; |
| 5127 | } |
| 5128 | } else { |
| 5129 | PCIE_DBG2(dev, |
| 5130 | "PCIe: Client of RC%d does not have registration for event %d\n", |
| 5131 | dev->rc_idx, event); |
| 5132 | } |
| 5133 | } |
| 5134 | |
| 5135 | static void handle_wake_func(struct work_struct *work) |
| 5136 | { |
| 5137 | int i, ret; |
| 5138 | struct msm_pcie_dev_t *dev = container_of(work, struct msm_pcie_dev_t, |
| 5139 | handle_wake_work); |
| 5140 | |
| 5141 | PCIE_DBG(dev, "PCIe: Wake work for RC%d\n", dev->rc_idx); |
| 5142 | |
| 5143 | mutex_lock(&dev->recovery_lock); |
| 5144 | |
| 5145 | if (!dev->enumerated) { |
| 5146 | PCIE_DBG(dev, |
| 5147 | "PCIe: Start enumeration for RC%d upon the wake from endpoint.\n", |
| 5148 | dev->rc_idx); |
| 5149 | |
| 5150 | ret = msm_pcie_enumerate(dev->rc_idx); |
| 5151 | if (ret) { |
| 5152 | PCIE_ERR(dev, |
| 5153 | "PCIe: failed to enable RC%d upon wake request from the device.\n", |
| 5154 | dev->rc_idx); |
| 5155 | goto out; |
| 5156 | } |
| 5157 | |
| 5158 | if (dev->num_ep > 1) { |
| 5159 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 5160 | dev->event_reg = dev->pcidev_table[i].event_reg; |
| 5161 | |
| 5162 | if ((dev->link_status == MSM_PCIE_LINK_ENABLED) |
| 5163 | && dev->event_reg && |
| 5164 | dev->event_reg->callback && |
| 5165 | (dev->event_reg->events & |
| 5166 | MSM_PCIE_EVENT_LINKUP)) { |
| 5167 | struct msm_pcie_notify *notify = |
| 5168 | &dev->event_reg->notify; |
| 5169 | notify->event = MSM_PCIE_EVENT_LINKUP; |
| 5170 | notify->user = dev->event_reg->user; |
| 5171 | PCIE_DBG(dev, |
| 5172 | "PCIe: Linkup callback for RC%d after enumeration is successful in wake IRQ handling\n", |
| 5173 | dev->rc_idx); |
| 5174 | dev->event_reg->callback(notify); |
| 5175 | } |
| 5176 | } |
| 5177 | } else { |
| 5178 | if ((dev->link_status == MSM_PCIE_LINK_ENABLED) && |
| 5179 | dev->event_reg && dev->event_reg->callback && |
| 5180 | (dev->event_reg->events & |
| 5181 | MSM_PCIE_EVENT_LINKUP)) { |
| 5182 | struct msm_pcie_notify *notify = |
| 5183 | &dev->event_reg->notify; |
| 5184 | notify->event = MSM_PCIE_EVENT_LINKUP; |
| 5185 | notify->user = dev->event_reg->user; |
| 5186 | PCIE_DBG(dev, |
| 5187 | "PCIe: Linkup callback for RC%d after enumeration is successful in wake IRQ handling\n", |
| 5188 | dev->rc_idx); |
| 5189 | dev->event_reg->callback(notify); |
| 5190 | } else { |
| 5191 | PCIE_DBG(dev, |
| 5192 | "PCIe: Client of RC%d does not have registration for linkup event.\n", |
| 5193 | dev->rc_idx); |
| 5194 | } |
| 5195 | } |
| 5196 | goto out; |
| 5197 | } else { |
| 5198 | PCIE_ERR(dev, |
| 5199 | "PCIe: The enumeration for RC%d has already been done.\n", |
| 5200 | dev->rc_idx); |
| 5201 | goto out; |
| 5202 | } |
| 5203 | |
| 5204 | out: |
| 5205 | mutex_unlock(&dev->recovery_lock); |
| 5206 | } |
| 5207 | |
| 5208 | static irqreturn_t handle_aer_irq(int irq, void *data) |
| 5209 | { |
| 5210 | struct msm_pcie_dev_t *dev = data; |
| 5211 | |
| 5212 | int corr_val = 0, uncorr_val = 0, rc_err_status = 0; |
| 5213 | int ep_corr_val = 0, ep_uncorr_val = 0; |
| 5214 | int rc_dev_ctrlstts = 0, ep_dev_ctrlstts = 0; |
| 5215 | u32 ep_dev_ctrlstts_offset = 0; |
| 5216 | int i, j, ep_src_bdf = 0; |
| 5217 | void __iomem *ep_base = NULL; |
| 5218 | unsigned long irqsave_flags; |
| 5219 | |
| 5220 | PCIE_DBG2(dev, |
| 5221 | "AER Interrupt handler fired for RC%d irq %d\nrc_corr_counter: %lu\nrc_non_fatal_counter: %lu\nrc_fatal_counter: %lu\nep_corr_counter: %lu\nep_non_fatal_counter: %lu\nep_fatal_counter: %lu\n", |
| 5222 | dev->rc_idx, irq, dev->rc_corr_counter, |
| 5223 | dev->rc_non_fatal_counter, dev->rc_fatal_counter, |
| 5224 | dev->ep_corr_counter, dev->ep_non_fatal_counter, |
| 5225 | dev->ep_fatal_counter); |
| 5226 | |
| 5227 | spin_lock_irqsave(&dev->aer_lock, irqsave_flags); |
| 5228 | |
| 5229 | if (dev->suspending) { |
| 5230 | PCIE_DBG2(dev, |
| 5231 | "PCIe: RC%d is currently suspending.\n", |
| 5232 | dev->rc_idx); |
| 5233 | spin_unlock_irqrestore(&dev->aer_lock, irqsave_flags); |
| 5234 | return IRQ_HANDLED; |
| 5235 | } |
| 5236 | |
| 5237 | uncorr_val = readl_relaxed(dev->dm_core + |
| 5238 | PCIE20_AER_UNCORR_ERR_STATUS_REG); |
| 5239 | corr_val = readl_relaxed(dev->dm_core + |
| 5240 | PCIE20_AER_CORR_ERR_STATUS_REG); |
| 5241 | rc_err_status = readl_relaxed(dev->dm_core + |
| 5242 | PCIE20_AER_ROOT_ERR_STATUS_REG); |
| 5243 | rc_dev_ctrlstts = readl_relaxed(dev->dm_core + |
| 5244 | PCIE20_CAP_DEVCTRLSTATUS); |
| 5245 | |
| 5246 | if (uncorr_val) |
| 5247 | PCIE_DBG(dev, "RC's PCIE20_AER_UNCORR_ERR_STATUS_REG:0x%x\n", |
| 5248 | uncorr_val); |
| 5249 | if (corr_val && (dev->rc_corr_counter < corr_counter_limit)) |
| 5250 | PCIE_DBG(dev, "RC's PCIE20_AER_CORR_ERR_STATUS_REG:0x%x\n", |
| 5251 | corr_val); |
| 5252 | |
| 5253 | if ((rc_dev_ctrlstts >> 18) & 0x1) |
| 5254 | dev->rc_fatal_counter++; |
| 5255 | if ((rc_dev_ctrlstts >> 17) & 0x1) |
| 5256 | dev->rc_non_fatal_counter++; |
| 5257 | if ((rc_dev_ctrlstts >> 16) & 0x1) |
| 5258 | dev->rc_corr_counter++; |
| 5259 | |
| 5260 | msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_DEVCTRLSTATUS, 0, |
| 5261 | BIT(18)|BIT(17)|BIT(16)); |
| 5262 | |
| 5263 | if (dev->link_status == MSM_PCIE_LINK_DISABLED) { |
| 5264 | PCIE_DBG2(dev, "RC%d link is down\n", dev->rc_idx); |
| 5265 | goto out; |
| 5266 | } |
| 5267 | |
| 5268 | for (i = 0; i < 2; i++) { |
| 5269 | if (i) |
| 5270 | ep_src_bdf = readl_relaxed(dev->dm_core + |
| 5271 | PCIE20_AER_ERR_SRC_ID_REG) & ~0xffff; |
| 5272 | else |
| 5273 | ep_src_bdf = (readl_relaxed(dev->dm_core + |
| 5274 | PCIE20_AER_ERR_SRC_ID_REG) & 0xffff) << 16; |
| 5275 | |
| 5276 | if (!ep_src_bdf) |
| 5277 | continue; |
| 5278 | |
| 5279 | for (j = 0; j < MAX_DEVICE_NUM; j++) { |
| 5280 | if (ep_src_bdf == dev->pcidev_table[j].bdf) { |
| 5281 | PCIE_DBG2(dev, |
| 5282 | "PCIe: %s Error from Endpoint: %02x:%02x.%01x\n", |
| 5283 | i ? "Uncorrectable" : "Correctable", |
| 5284 | dev->pcidev_table[j].bdf >> 24, |
| 5285 | dev->pcidev_table[j].bdf >> 19 & 0x1f, |
| 5286 | dev->pcidev_table[j].bdf >> 16 & 0x07); |
| 5287 | ep_base = dev->pcidev_table[j].conf_base; |
| 5288 | ep_dev_ctrlstts_offset = dev-> |
| 5289 | pcidev_table[j].dev_ctrlstts_offset; |
| 5290 | break; |
| 5291 | } |
| 5292 | } |
| 5293 | |
| 5294 | if (!ep_base) { |
| 5295 | PCIE_ERR(dev, |
| 5296 | "PCIe: RC%d no endpoint found for reported error\n", |
| 5297 | dev->rc_idx); |
| 5298 | goto out; |
| 5299 | } |
| 5300 | |
| 5301 | ep_uncorr_val = readl_relaxed(ep_base + |
| 5302 | PCIE20_AER_UNCORR_ERR_STATUS_REG); |
| 5303 | ep_corr_val = readl_relaxed(ep_base + |
| 5304 | PCIE20_AER_CORR_ERR_STATUS_REG); |
| 5305 | ep_dev_ctrlstts = readl_relaxed(ep_base + |
| 5306 | ep_dev_ctrlstts_offset); |
| 5307 | |
| 5308 | if (ep_uncorr_val) |
| 5309 | PCIE_DBG(dev, |
| 5310 | "EP's PCIE20_AER_UNCORR_ERR_STATUS_REG:0x%x\n", |
| 5311 | ep_uncorr_val); |
| 5312 | if (ep_corr_val && (dev->ep_corr_counter < corr_counter_limit)) |
| 5313 | PCIE_DBG(dev, |
| 5314 | "EP's PCIE20_AER_CORR_ERR_STATUS_REG:0x%x\n", |
| 5315 | ep_corr_val); |
| 5316 | |
| 5317 | if ((ep_dev_ctrlstts >> 18) & 0x1) |
| 5318 | dev->ep_fatal_counter++; |
| 5319 | if ((ep_dev_ctrlstts >> 17) & 0x1) |
| 5320 | dev->ep_non_fatal_counter++; |
| 5321 | if ((ep_dev_ctrlstts >> 16) & 0x1) |
| 5322 | dev->ep_corr_counter++; |
| 5323 | |
| 5324 | msm_pcie_write_mask(ep_base + ep_dev_ctrlstts_offset, 0, |
| 5325 | BIT(18)|BIT(17)|BIT(16)); |
| 5326 | |
| 5327 | msm_pcie_write_reg_field(ep_base, |
| 5328 | PCIE20_AER_UNCORR_ERR_STATUS_REG, |
| 5329 | 0x3fff031, 0x3fff031); |
| 5330 | msm_pcie_write_reg_field(ep_base, |
| 5331 | PCIE20_AER_CORR_ERR_STATUS_REG, |
| 5332 | 0xf1c1, 0xf1c1); |
| 5333 | } |
| 5334 | out: |
| 5335 | if (((dev->rc_corr_counter < corr_counter_limit) && |
| 5336 | (dev->ep_corr_counter < corr_counter_limit)) || |
| 5337 | uncorr_val || ep_uncorr_val) |
| 5338 | PCIE_DBG(dev, "RC's PCIE20_AER_ROOT_ERR_STATUS_REG:0x%x\n", |
| 5339 | rc_err_status); |
| 5340 | msm_pcie_write_reg_field(dev->dm_core, |
| 5341 | PCIE20_AER_UNCORR_ERR_STATUS_REG, |
| 5342 | 0x3fff031, 0x3fff031); |
| 5343 | msm_pcie_write_reg_field(dev->dm_core, |
| 5344 | PCIE20_AER_CORR_ERR_STATUS_REG, |
| 5345 | 0xf1c1, 0xf1c1); |
| 5346 | msm_pcie_write_reg_field(dev->dm_core, |
| 5347 | PCIE20_AER_ROOT_ERR_STATUS_REG, |
| 5348 | 0x7f, 0x7f); |
| 5349 | |
| 5350 | spin_unlock_irqrestore(&dev->aer_lock, irqsave_flags); |
| 5351 | return IRQ_HANDLED; |
| 5352 | } |
| 5353 | |
| 5354 | static irqreturn_t handle_wake_irq(int irq, void *data) |
| 5355 | { |
| 5356 | struct msm_pcie_dev_t *dev = data; |
| 5357 | unsigned long irqsave_flags; |
| 5358 | int i; |
| 5359 | |
| 5360 | spin_lock_irqsave(&dev->wakeup_lock, irqsave_flags); |
| 5361 | |
| 5362 | dev->wake_counter++; |
| 5363 | PCIE_DBG(dev, "PCIe: No. %ld wake IRQ for RC%d\n", |
| 5364 | dev->wake_counter, dev->rc_idx); |
| 5365 | |
| 5366 | PCIE_DBG2(dev, "PCIe WAKE is asserted by Endpoint of RC%d\n", |
| 5367 | dev->rc_idx); |
| 5368 | |
| 5369 | if (!dev->enumerated) { |
| 5370 | PCIE_DBG(dev, "Start enumeating RC%d\n", dev->rc_idx); |
| 5371 | if (dev->ep_wakeirq) |
| 5372 | schedule_work(&dev->handle_wake_work); |
| 5373 | else |
| 5374 | PCIE_DBG(dev, |
| 5375 | "wake irq is received but ep_wakeirq is not supported for RC%d.\n", |
| 5376 | dev->rc_idx); |
| 5377 | } else { |
| 5378 | PCIE_DBG2(dev, "Wake up RC%d\n", dev->rc_idx); |
| 5379 | __pm_stay_awake(&dev->ws); |
| 5380 | __pm_relax(&dev->ws); |
| 5381 | |
| 5382 | if (dev->num_ep > 1) { |
| 5383 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 5384 | dev->event_reg = |
| 5385 | dev->pcidev_table[i].event_reg; |
| 5386 | msm_pcie_notify_client(dev, |
| 5387 | MSM_PCIE_EVENT_WAKEUP); |
| 5388 | } |
| 5389 | } else { |
| 5390 | msm_pcie_notify_client(dev, MSM_PCIE_EVENT_WAKEUP); |
| 5391 | } |
| 5392 | } |
| 5393 | |
| 5394 | spin_unlock_irqrestore(&dev->wakeup_lock, irqsave_flags); |
| 5395 | |
| 5396 | return IRQ_HANDLED; |
| 5397 | } |
| 5398 | |
| 5399 | static irqreturn_t handle_linkdown_irq(int irq, void *data) |
| 5400 | { |
| 5401 | struct msm_pcie_dev_t *dev = data; |
| 5402 | unsigned long irqsave_flags; |
| 5403 | int i; |
| 5404 | |
| 5405 | spin_lock_irqsave(&dev->linkdown_lock, irqsave_flags); |
| 5406 | |
| 5407 | dev->linkdown_counter++; |
| 5408 | |
| 5409 | PCIE_DBG(dev, |
| 5410 | "PCIe: No. %ld linkdown IRQ for RC%d.\n", |
| 5411 | dev->linkdown_counter, dev->rc_idx); |
| 5412 | |
| 5413 | if (!dev->enumerated || dev->link_status != MSM_PCIE_LINK_ENABLED) { |
| 5414 | PCIE_DBG(dev, |
| 5415 | "PCIe:Linkdown IRQ for RC%d when the link is not enabled\n", |
| 5416 | dev->rc_idx); |
| 5417 | } else if (dev->suspending) { |
| 5418 | PCIE_DBG(dev, |
| 5419 | "PCIe:the link of RC%d is suspending.\n", |
| 5420 | dev->rc_idx); |
| 5421 | } else { |
| 5422 | dev->link_status = MSM_PCIE_LINK_DISABLED; |
| 5423 | dev->shadow_en = false; |
| 5424 | |
| 5425 | if (dev->linkdown_panic) |
| 5426 | panic("User has chosen to panic on linkdown\n"); |
| 5427 | |
| 5428 | /* assert PERST */ |
| 5429 | gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, |
| 5430 | dev->gpio[MSM_PCIE_GPIO_PERST].on); |
| 5431 | PCIE_ERR(dev, "PCIe link is down for RC%d\n", dev->rc_idx); |
| 5432 | |
| 5433 | if (dev->num_ep > 1) { |
| 5434 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 5435 | dev->event_reg = |
| 5436 | dev->pcidev_table[i].event_reg; |
| 5437 | msm_pcie_notify_client(dev, |
| 5438 | MSM_PCIE_EVENT_LINKDOWN); |
| 5439 | } |
| 5440 | } else { |
| 5441 | msm_pcie_notify_client(dev, MSM_PCIE_EVENT_LINKDOWN); |
| 5442 | } |
| 5443 | } |
| 5444 | |
| 5445 | spin_unlock_irqrestore(&dev->linkdown_lock, irqsave_flags); |
| 5446 | |
| 5447 | return IRQ_HANDLED; |
| 5448 | } |
| 5449 | |
| 5450 | static irqreturn_t handle_msi_irq(int irq, void *data) |
| 5451 | { |
| 5452 | int i, j; |
| 5453 | unsigned long val; |
| 5454 | struct msm_pcie_dev_t *dev = data; |
| 5455 | void __iomem *ctrl_status; |
| 5456 | |
| 5457 | PCIE_DUMP(dev, "irq: %d\n", irq); |
| 5458 | |
| 5459 | /* |
| 5460 | * check for set bits, clear it by setting that bit |
| 5461 | * and trigger corresponding irq |
| 5462 | */ |
| 5463 | for (i = 0; i < PCIE20_MSI_CTRL_MAX; i++) { |
| 5464 | ctrl_status = dev->dm_core + |
| 5465 | PCIE20_MSI_CTRL_INTR_STATUS + (i * 12); |
| 5466 | |
| 5467 | val = readl_relaxed(ctrl_status); |
| 5468 | while (val) { |
| 5469 | j = find_first_bit(&val, 32); |
| 5470 | writel_relaxed(BIT(j), ctrl_status); |
| 5471 | /* ensure that interrupt is cleared (acked) */ |
| 5472 | wmb(); |
| 5473 | generic_handle_irq( |
| 5474 | irq_find_mapping(dev->irq_domain, (j + (32*i))) |
| 5475 | ); |
| 5476 | val = readl_relaxed(ctrl_status); |
| 5477 | } |
| 5478 | } |
| 5479 | |
| 5480 | return IRQ_HANDLED; |
| 5481 | } |
| 5482 | |
| 5483 | static irqreturn_t handle_global_irq(int irq, void *data) |
| 5484 | { |
| 5485 | int i; |
| 5486 | struct msm_pcie_dev_t *dev = data; |
| 5487 | unsigned long irqsave_flags; |
| 5488 | u32 status = 0; |
| 5489 | |
| 5490 | spin_lock_irqsave(&dev->global_irq_lock, irqsave_flags); |
| 5491 | |
| 5492 | status = readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_STATUS) & |
| 5493 | readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK); |
| 5494 | |
| 5495 | msm_pcie_write_mask(dev->parf + PCIE20_PARF_INT_ALL_CLEAR, 0, status); |
| 5496 | |
| 5497 | PCIE_DBG2(dev, "RC%d: Global IRQ %d received: 0x%x\n", |
| 5498 | dev->rc_idx, irq, status); |
| 5499 | |
| 5500 | for (i = 0; i <= MSM_PCIE_INT_EVT_MAX; i++) { |
| 5501 | if (status & BIT(i)) { |
| 5502 | switch (i) { |
| 5503 | case MSM_PCIE_INT_EVT_LINK_DOWN: |
| 5504 | PCIE_DBG(dev, |
| 5505 | "PCIe: RC%d: handle linkdown event.\n", |
| 5506 | dev->rc_idx); |
| 5507 | handle_linkdown_irq(irq, data); |
| 5508 | break; |
| 5509 | case MSM_PCIE_INT_EVT_AER_LEGACY: |
| 5510 | PCIE_DBG(dev, |
| 5511 | "PCIe: RC%d: AER legacy event.\n", |
| 5512 | dev->rc_idx); |
| 5513 | handle_aer_irq(irq, data); |
| 5514 | break; |
| 5515 | case MSM_PCIE_INT_EVT_AER_ERR: |
| 5516 | PCIE_DBG(dev, |
| 5517 | "PCIe: RC%d: AER event.\n", |
| 5518 | dev->rc_idx); |
| 5519 | handle_aer_irq(irq, data); |
| 5520 | break; |
| 5521 | default: |
| 5522 | PCIE_ERR(dev, |
| 5523 | "PCIe: RC%d: Unexpected event %d is caught!\n", |
| 5524 | dev->rc_idx, i); |
| 5525 | } |
| 5526 | } |
| 5527 | } |
| 5528 | |
| 5529 | spin_unlock_irqrestore(&dev->global_irq_lock, irqsave_flags); |
| 5530 | |
| 5531 | return IRQ_HANDLED; |
| 5532 | } |
| 5533 | |
| 5534 | void msm_pcie_destroy_irq(unsigned int irq, struct msm_pcie_dev_t *pcie_dev) |
| 5535 | { |
| 5536 | int pos, i; |
| 5537 | struct msm_pcie_dev_t *dev; |
| 5538 | |
| 5539 | if (pcie_dev) |
| 5540 | dev = pcie_dev; |
| 5541 | else |
| 5542 | dev = irq_get_chip_data(irq); |
| 5543 | |
| 5544 | if (!dev) { |
| 5545 | pr_err("PCIe: device is null. IRQ:%d\n", irq); |
| 5546 | return; |
| 5547 | } |
| 5548 | |
| 5549 | if (dev->msi_gicm_addr) { |
| 5550 | PCIE_DBG(dev, "destroy QGIC based irq %d\n", irq); |
| 5551 | |
| 5552 | for (i = 0; i < MSM_PCIE_MAX_MSI; i++) |
| 5553 | if (irq == dev->msi[i].num) |
| 5554 | break; |
| 5555 | if (i == MSM_PCIE_MAX_MSI) { |
| 5556 | PCIE_ERR(dev, |
| 5557 | "Could not find irq: %d in RC%d MSI table\n", |
| 5558 | irq, dev->rc_idx); |
| 5559 | return; |
| 5560 | } |
| 5561 | |
| 5562 | pos = i; |
| 5563 | } else { |
| 5564 | PCIE_DBG(dev, "destroy default MSI irq %d\n", irq); |
| 5565 | pos = irq - irq_find_mapping(dev->irq_domain, 0); |
| 5566 | } |
| 5567 | |
| 5568 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5569 | |
| 5570 | PCIE_DBG(dev, "Before clear_bit pos:%d msi_irq_in_use:%ld\n", |
| 5571 | pos, *dev->msi_irq_in_use); |
| 5572 | clear_bit(pos, dev->msi_irq_in_use); |
| 5573 | PCIE_DBG(dev, "After clear_bit pos:%d msi_irq_in_use:%ld\n", |
| 5574 | pos, *dev->msi_irq_in_use); |
| 5575 | } |
| 5576 | |
| 5577 | /* hookup to linux pci msi framework */ |
| 5578 | void arch_teardown_msi_irq(unsigned int irq) |
| 5579 | { |
| 5580 | PCIE_GEN_DBG("irq %d deallocated\n", irq); |
| 5581 | msm_pcie_destroy_irq(irq, NULL); |
| 5582 | } |
| 5583 | |
| 5584 | void arch_teardown_msi_irqs(struct pci_dev *dev) |
| 5585 | { |
| 5586 | struct msi_desc *entry; |
| 5587 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 5588 | |
| 5589 | PCIE_DBG(pcie_dev, "RC:%d EP: vendor_id:0x%x device_id:0x%x\n", |
| 5590 | pcie_dev->rc_idx, dev->vendor, dev->device); |
| 5591 | |
| 5592 | pcie_dev->use_msi = false; |
| 5593 | |
| 5594 | list_for_each_entry(entry, &dev->dev.msi_list, list) { |
| 5595 | int i, nvec; |
| 5596 | |
| 5597 | if (entry->irq == 0) |
| 5598 | continue; |
| 5599 | nvec = 1 << entry->msi_attrib.multiple; |
| 5600 | for (i = 0; i < nvec; i++) |
| 5601 | msm_pcie_destroy_irq(entry->irq + i, pcie_dev); |
| 5602 | } |
| 5603 | } |
| 5604 | |
| 5605 | static void msm_pcie_msi_nop(struct irq_data *d) |
| 5606 | { |
| 5607 | } |
| 5608 | |
| 5609 | static struct irq_chip pcie_msi_chip = { |
| 5610 | .name = "msm-pcie-msi", |
| 5611 | .irq_ack = msm_pcie_msi_nop, |
| 5612 | .irq_enable = unmask_msi_irq, |
| 5613 | .irq_disable = mask_msi_irq, |
| 5614 | .irq_mask = mask_msi_irq, |
| 5615 | .irq_unmask = unmask_msi_irq, |
| 5616 | }; |
| 5617 | |
| 5618 | static int msm_pcie_create_irq(struct msm_pcie_dev_t *dev) |
| 5619 | { |
| 5620 | int irq, pos; |
| 5621 | |
| 5622 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5623 | |
| 5624 | again: |
| 5625 | pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS); |
| 5626 | |
| 5627 | if (pos >= PCIE_MSI_NR_IRQS) |
| 5628 | return -ENOSPC; |
| 5629 | |
| 5630 | PCIE_DBG(dev, "pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use); |
| 5631 | |
| 5632 | if (test_and_set_bit(pos, dev->msi_irq_in_use)) |
| 5633 | goto again; |
| 5634 | else |
| 5635 | PCIE_DBG(dev, "test_and_set_bit is successful pos=%d\n", pos); |
| 5636 | |
| 5637 | irq = irq_create_mapping(dev->irq_domain, pos); |
| 5638 | if (!irq) |
| 5639 | return -EINVAL; |
| 5640 | |
| 5641 | return irq; |
| 5642 | } |
| 5643 | |
| 5644 | static int arch_setup_msi_irq_default(struct pci_dev *pdev, |
| 5645 | struct msi_desc *desc, int nvec) |
| 5646 | { |
| 5647 | int irq; |
| 5648 | struct msi_msg msg; |
| 5649 | struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev->bus); |
| 5650 | |
| 5651 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5652 | |
| 5653 | irq = msm_pcie_create_irq(dev); |
| 5654 | |
| 5655 | PCIE_DBG(dev, "IRQ %d is allocated.\n", irq); |
| 5656 | |
| 5657 | if (irq < 0) |
| 5658 | return irq; |
| 5659 | |
| 5660 | PCIE_DBG(dev, "irq %d allocated\n", irq); |
| 5661 | |
| 5662 | irq_set_msi_desc(irq, desc); |
| 5663 | |
| 5664 | /* write msi vector and data */ |
| 5665 | msg.address_hi = 0; |
| 5666 | msg.address_lo = MSM_PCIE_MSI_PHY; |
| 5667 | msg.data = irq - irq_find_mapping(dev->irq_domain, 0); |
| 5668 | write_msi_msg(irq, &msg); |
| 5669 | |
| 5670 | return 0; |
| 5671 | } |
| 5672 | |
| 5673 | static int msm_pcie_create_irq_qgic(struct msm_pcie_dev_t *dev) |
| 5674 | { |
| 5675 | int irq, pos; |
| 5676 | |
| 5677 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5678 | |
| 5679 | again: |
| 5680 | pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS); |
| 5681 | |
| 5682 | if (pos >= PCIE_MSI_NR_IRQS) |
| 5683 | return -ENOSPC; |
| 5684 | |
| 5685 | PCIE_DBG(dev, "pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use); |
| 5686 | |
| 5687 | if (test_and_set_bit(pos, dev->msi_irq_in_use)) |
| 5688 | goto again; |
| 5689 | else |
| 5690 | PCIE_DBG(dev, "test_and_set_bit is successful pos=%d\n", pos); |
| 5691 | |
| 5692 | if (pos >= MSM_PCIE_MAX_MSI) { |
| 5693 | PCIE_ERR(dev, |
| 5694 | "PCIe: RC%d: pos %d is not less than %d\n", |
| 5695 | dev->rc_idx, pos, MSM_PCIE_MAX_MSI); |
| 5696 | return MSM_PCIE_ERROR; |
| 5697 | } |
| 5698 | |
| 5699 | irq = dev->msi[pos].num; |
| 5700 | if (!irq) { |
| 5701 | PCIE_ERR(dev, "PCIe: RC%d failed to create QGIC MSI IRQ.\n", |
| 5702 | dev->rc_idx); |
| 5703 | return -EINVAL; |
| 5704 | } |
| 5705 | |
| 5706 | return irq; |
| 5707 | } |
| 5708 | |
| 5709 | static int arch_setup_msi_irq_qgic(struct pci_dev *pdev, |
| 5710 | struct msi_desc *desc, int nvec) |
| 5711 | { |
| 5712 | int irq, index, firstirq = 0; |
| 5713 | struct msi_msg msg; |
| 5714 | struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev->bus); |
| 5715 | |
| 5716 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5717 | |
| 5718 | for (index = 0; index < nvec; index++) { |
| 5719 | irq = msm_pcie_create_irq_qgic(dev); |
| 5720 | PCIE_DBG(dev, "irq %d is allocated\n", irq); |
| 5721 | |
| 5722 | if (irq < 0) |
| 5723 | return irq; |
| 5724 | |
| 5725 | if (index == 0) |
| 5726 | firstirq = irq; |
| 5727 | |
| 5728 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
| 5729 | } |
| 5730 | |
| 5731 | /* write msi vector and data */ |
| 5732 | irq_set_msi_desc(firstirq, desc); |
| 5733 | msg.address_hi = 0; |
| 5734 | msg.address_lo = dev->msi_gicm_addr; |
| 5735 | msg.data = dev->msi_gicm_base + (firstirq - dev->msi[0].num); |
| 5736 | write_msi_msg(firstirq, &msg); |
| 5737 | |
| 5738 | return 0; |
| 5739 | } |
| 5740 | |
| 5741 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
| 5742 | { |
| 5743 | struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev->bus); |
| 5744 | |
| 5745 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5746 | |
| 5747 | if (dev->msi_gicm_addr) |
| 5748 | return arch_setup_msi_irq_qgic(pdev, desc, 1); |
| 5749 | else |
| 5750 | return arch_setup_msi_irq_default(pdev, desc, 1); |
| 5751 | } |
| 5752 | |
| 5753 | static int msm_pcie_get_msi_multiple(int nvec) |
| 5754 | { |
| 5755 | int msi_multiple = 0; |
| 5756 | |
| 5757 | while (nvec) { |
| 5758 | nvec = nvec >> 1; |
| 5759 | msi_multiple++; |
| 5760 | } |
| 5761 | PCIE_GEN_DBG("log2 number of MSI multiple:%d\n", |
| 5762 | msi_multiple - 1); |
| 5763 | |
| 5764 | return msi_multiple - 1; |
| 5765 | } |
| 5766 | |
| 5767 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
| 5768 | { |
| 5769 | struct msi_desc *entry; |
| 5770 | int ret; |
| 5771 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 5772 | |
| 5773 | PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx); |
| 5774 | |
| 5775 | if (type != PCI_CAP_ID_MSI || nvec > 32) |
| 5776 | return -ENOSPC; |
| 5777 | |
| 5778 | PCIE_DBG(pcie_dev, "nvec = %d\n", nvec); |
| 5779 | |
| 5780 | list_for_each_entry(entry, &dev->dev.msi_list, list) { |
| 5781 | entry->msi_attrib.multiple = |
| 5782 | msm_pcie_get_msi_multiple(nvec); |
| 5783 | |
| 5784 | if (pcie_dev->msi_gicm_addr) |
| 5785 | ret = arch_setup_msi_irq_qgic(dev, entry, nvec); |
| 5786 | else |
| 5787 | ret = arch_setup_msi_irq_default(dev, entry, nvec); |
| 5788 | |
| 5789 | PCIE_DBG(pcie_dev, "ret from msi_irq: %d\n", ret); |
| 5790 | |
| 5791 | if (ret < 0) |
| 5792 | return ret; |
| 5793 | if (ret > 0) |
| 5794 | return -ENOSPC; |
| 5795 | } |
| 5796 | |
| 5797 | pcie_dev->use_msi = true; |
| 5798 | |
| 5799 | return 0; |
| 5800 | } |
| 5801 | |
| 5802 | static int msm_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
| 5803 | irq_hw_number_t hwirq) |
| 5804 | { |
| 5805 | irq_set_chip_and_handler (irq, &pcie_msi_chip, handle_simple_irq); |
| 5806 | irq_set_chip_data(irq, domain->host_data); |
| 5807 | return 0; |
| 5808 | } |
| 5809 | |
| 5810 | static const struct irq_domain_ops msm_pcie_msi_ops = { |
| 5811 | .map = msm_pcie_msi_map, |
| 5812 | }; |
| 5813 | |
| 5814 | int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) |
| 5815 | { |
| 5816 | int rc; |
| 5817 | int msi_start = 0; |
| 5818 | struct device *pdev = &dev->pdev->dev; |
| 5819 | |
| 5820 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5821 | |
| 5822 | if (dev->rc_idx) |
| 5823 | wakeup_source_init(&dev->ws, "RC1 pcie_wakeup_source"); |
| 5824 | else |
| 5825 | wakeup_source_init(&dev->ws, "RC0 pcie_wakeup_source"); |
| 5826 | |
| 5827 | /* register handler for linkdown interrupt */ |
| 5828 | if (dev->irq[MSM_PCIE_INT_LINK_DOWN].num) { |
| 5829 | rc = devm_request_irq(pdev, |
| 5830 | dev->irq[MSM_PCIE_INT_LINK_DOWN].num, |
| 5831 | handle_linkdown_irq, |
| 5832 | IRQF_TRIGGER_RISING, |
| 5833 | dev->irq[MSM_PCIE_INT_LINK_DOWN].name, |
| 5834 | dev); |
| 5835 | if (rc) { |
| 5836 | PCIE_ERR(dev, |
| 5837 | "PCIe: Unable to request linkdown interrupt:%d\n", |
| 5838 | dev->irq[MSM_PCIE_INT_LINK_DOWN].num); |
| 5839 | return rc; |
| 5840 | } |
| 5841 | } |
| 5842 | |
| 5843 | /* register handler for physical MSI interrupt line */ |
| 5844 | if (dev->irq[MSM_PCIE_INT_MSI].num) { |
| 5845 | rc = devm_request_irq(pdev, |
| 5846 | dev->irq[MSM_PCIE_INT_MSI].num, |
| 5847 | handle_msi_irq, |
| 5848 | IRQF_TRIGGER_RISING, |
| 5849 | dev->irq[MSM_PCIE_INT_MSI].name, |
| 5850 | dev); |
| 5851 | if (rc) { |
| 5852 | PCIE_ERR(dev, |
| 5853 | "PCIe: RC%d: Unable to request MSI interrupt\n", |
| 5854 | dev->rc_idx); |
| 5855 | return rc; |
| 5856 | } |
| 5857 | } |
| 5858 | |
| 5859 | /* register handler for AER interrupt */ |
| 5860 | if (dev->irq[MSM_PCIE_INT_PLS_ERR].num) { |
| 5861 | rc = devm_request_irq(pdev, |
| 5862 | dev->irq[MSM_PCIE_INT_PLS_ERR].num, |
| 5863 | handle_aer_irq, |
| 5864 | IRQF_TRIGGER_RISING, |
| 5865 | dev->irq[MSM_PCIE_INT_PLS_ERR].name, |
| 5866 | dev); |
| 5867 | if (rc) { |
| 5868 | PCIE_ERR(dev, |
| 5869 | "PCIe: RC%d: Unable to request aer pls_err interrupt: %d\n", |
| 5870 | dev->rc_idx, |
| 5871 | dev->irq[MSM_PCIE_INT_PLS_ERR].num); |
| 5872 | return rc; |
| 5873 | } |
| 5874 | } |
| 5875 | |
| 5876 | /* register handler for AER legacy interrupt */ |
| 5877 | if (dev->irq[MSM_PCIE_INT_AER_LEGACY].num) { |
| 5878 | rc = devm_request_irq(pdev, |
| 5879 | dev->irq[MSM_PCIE_INT_AER_LEGACY].num, |
| 5880 | handle_aer_irq, |
| 5881 | IRQF_TRIGGER_RISING, |
| 5882 | dev->irq[MSM_PCIE_INT_AER_LEGACY].name, |
| 5883 | dev); |
| 5884 | if (rc) { |
| 5885 | PCIE_ERR(dev, |
| 5886 | "PCIe: RC%d: Unable to request aer aer_legacy interrupt: %d\n", |
| 5887 | dev->rc_idx, |
| 5888 | dev->irq[MSM_PCIE_INT_AER_LEGACY].num); |
| 5889 | return rc; |
| 5890 | } |
| 5891 | } |
| 5892 | |
| 5893 | if (dev->irq[MSM_PCIE_INT_GLOBAL_INT].num) { |
| 5894 | rc = devm_request_irq(pdev, |
| 5895 | dev->irq[MSM_PCIE_INT_GLOBAL_INT].num, |
| 5896 | handle_global_irq, |
| 5897 | IRQF_TRIGGER_RISING, |
| 5898 | dev->irq[MSM_PCIE_INT_GLOBAL_INT].name, |
| 5899 | dev); |
| 5900 | if (rc) { |
| 5901 | PCIE_ERR(dev, |
| 5902 | "PCIe: RC%d: Unable to request global_int interrupt: %d\n", |
| 5903 | dev->rc_idx, |
| 5904 | dev->irq[MSM_PCIE_INT_GLOBAL_INT].num); |
| 5905 | return rc; |
| 5906 | } |
| 5907 | } |
| 5908 | |
| 5909 | /* register handler for PCIE_WAKE_N interrupt line */ |
| 5910 | if (dev->wake_n) { |
| 5911 | rc = devm_request_irq(pdev, |
| 5912 | dev->wake_n, handle_wake_irq, |
| 5913 | IRQF_TRIGGER_FALLING, "msm_pcie_wake", dev); |
| 5914 | if (rc) { |
| 5915 | PCIE_ERR(dev, |
| 5916 | "PCIe: RC%d: Unable to request wake interrupt\n", |
| 5917 | dev->rc_idx); |
| 5918 | return rc; |
| 5919 | } |
| 5920 | |
| 5921 | INIT_WORK(&dev->handle_wake_work, handle_wake_func); |
| 5922 | |
| 5923 | rc = enable_irq_wake(dev->wake_n); |
| 5924 | if (rc) { |
| 5925 | PCIE_ERR(dev, |
| 5926 | "PCIe: RC%d: Unable to enable wake interrupt\n", |
| 5927 | dev->rc_idx); |
| 5928 | return rc; |
| 5929 | } |
| 5930 | } |
| 5931 | |
| 5932 | /* Create a virtual domain of interrupts */ |
| 5933 | if (!dev->msi_gicm_addr) { |
| 5934 | dev->irq_domain = irq_domain_add_linear(dev->pdev->dev.of_node, |
| 5935 | PCIE_MSI_NR_IRQS, &msm_pcie_msi_ops, dev); |
| 5936 | |
| 5937 | if (!dev->irq_domain) { |
| 5938 | PCIE_ERR(dev, |
| 5939 | "PCIe: RC%d: Unable to initialize irq domain\n", |
| 5940 | dev->rc_idx); |
| 5941 | |
| 5942 | if (dev->wake_n) |
| 5943 | disable_irq(dev->wake_n); |
| 5944 | |
| 5945 | return PTR_ERR(dev->irq_domain); |
| 5946 | } |
| 5947 | |
| 5948 | msi_start = irq_create_mapping(dev->irq_domain, 0); |
| 5949 | } |
| 5950 | |
| 5951 | return 0; |
| 5952 | } |
| 5953 | |
| 5954 | void msm_pcie_irq_deinit(struct msm_pcie_dev_t *dev) |
| 5955 | { |
| 5956 | PCIE_DBG(dev, "RC%d\n", dev->rc_idx); |
| 5957 | |
| 5958 | wakeup_source_trash(&dev->ws); |
| 5959 | |
| 5960 | if (dev->wake_n) |
| 5961 | disable_irq(dev->wake_n); |
| 5962 | } |
| 5963 | |
| 5964 | |
| 5965 | static int msm_pcie_probe(struct platform_device *pdev) |
| 5966 | { |
| 5967 | int ret = 0; |
| 5968 | int rc_idx = -1; |
| 5969 | int i, j; |
| 5970 | |
| 5971 | PCIE_GEN_DBG("%s\n", __func__); |
| 5972 | |
| 5973 | mutex_lock(&pcie_drv.drv_lock); |
| 5974 | |
| 5975 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 5976 | "cell-index", &rc_idx); |
| 5977 | if (ret) { |
| 5978 | PCIE_GEN_DBG("Did not find RC index.\n"); |
| 5979 | goto out; |
| 5980 | } else { |
| 5981 | if (rc_idx >= MAX_RC_NUM) { |
| 5982 | pr_err( |
| 5983 | "PCIe: Invalid RC Index %d (max supported = %d)\n", |
| 5984 | rc_idx, MAX_RC_NUM); |
| 5985 | goto out; |
| 5986 | } |
| 5987 | pcie_drv.rc_num++; |
| 5988 | PCIE_DBG(&msm_pcie_dev[rc_idx], "PCIe: RC index is %d.\n", |
| 5989 | rc_idx); |
| 5990 | } |
| 5991 | |
| 5992 | msm_pcie_dev[rc_idx].l0s_supported = |
| 5993 | of_property_read_bool((&pdev->dev)->of_node, |
| 5994 | "qcom,l0s-supported"); |
| 5995 | PCIE_DBG(&msm_pcie_dev[rc_idx], "L0s is %s supported.\n", |
| 5996 | msm_pcie_dev[rc_idx].l0s_supported ? "" : "not"); |
| 5997 | msm_pcie_dev[rc_idx].l1_supported = |
| 5998 | of_property_read_bool((&pdev->dev)->of_node, |
| 5999 | "qcom,l1-supported"); |
| 6000 | PCIE_DBG(&msm_pcie_dev[rc_idx], "L1 is %s supported.\n", |
| 6001 | msm_pcie_dev[rc_idx].l1_supported ? "" : "not"); |
| 6002 | msm_pcie_dev[rc_idx].l1ss_supported = |
| 6003 | of_property_read_bool((&pdev->dev)->of_node, |
| 6004 | "qcom,l1ss-supported"); |
| 6005 | PCIE_DBG(&msm_pcie_dev[rc_idx], "L1ss is %s supported.\n", |
| 6006 | msm_pcie_dev[rc_idx].l1ss_supported ? "" : "not"); |
| 6007 | msm_pcie_dev[rc_idx].common_clk_en = |
| 6008 | of_property_read_bool((&pdev->dev)->of_node, |
| 6009 | "qcom,common-clk-en"); |
| 6010 | PCIE_DBG(&msm_pcie_dev[rc_idx], "Common clock is %s enabled.\n", |
| 6011 | msm_pcie_dev[rc_idx].common_clk_en ? "" : "not"); |
| 6012 | msm_pcie_dev[rc_idx].clk_power_manage_en = |
| 6013 | of_property_read_bool((&pdev->dev)->of_node, |
| 6014 | "qcom,clk-power-manage-en"); |
| 6015 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6016 | "Clock power management is %s enabled.\n", |
| 6017 | msm_pcie_dev[rc_idx].clk_power_manage_en ? "" : "not"); |
| 6018 | msm_pcie_dev[rc_idx].aux_clk_sync = |
| 6019 | of_property_read_bool((&pdev->dev)->of_node, |
| 6020 | "qcom,aux-clk-sync"); |
| 6021 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6022 | "AUX clock is %s synchronous to Core clock.\n", |
| 6023 | msm_pcie_dev[rc_idx].aux_clk_sync ? "" : "not"); |
| 6024 | |
| 6025 | msm_pcie_dev[rc_idx].use_19p2mhz_aux_clk = |
| 6026 | of_property_read_bool((&pdev->dev)->of_node, |
| 6027 | "qcom,use-19p2mhz-aux-clk"); |
| 6028 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6029 | "AUX clock frequency is %s 19.2MHz.\n", |
| 6030 | msm_pcie_dev[rc_idx].use_19p2mhz_aux_clk ? "" : "not"); |
| 6031 | |
| 6032 | msm_pcie_dev[rc_idx].smmu_exist = |
| 6033 | of_property_read_bool((&pdev->dev)->of_node, |
| 6034 | "qcom,smmu-exist"); |
| 6035 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6036 | "SMMU does %s exist.\n", |
| 6037 | msm_pcie_dev[rc_idx].smmu_exist ? "" : "not"); |
| 6038 | |
| 6039 | msm_pcie_dev[rc_idx].smmu_sid_base = 0; |
| 6040 | ret = of_property_read_u32((&pdev->dev)->of_node, "qcom,smmu-sid-base", |
| 6041 | &msm_pcie_dev[rc_idx].smmu_sid_base); |
| 6042 | if (ret) |
| 6043 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6044 | "RC%d SMMU sid base not found\n", |
| 6045 | msm_pcie_dev[rc_idx].rc_idx); |
| 6046 | else |
| 6047 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6048 | "RC%d: qcom,smmu-sid-base: 0x%x.\n", |
| 6049 | msm_pcie_dev[rc_idx].rc_idx, |
| 6050 | msm_pcie_dev[rc_idx].smmu_sid_base); |
| 6051 | |
| 6052 | msm_pcie_dev[rc_idx].ep_wakeirq = |
| 6053 | of_property_read_bool((&pdev->dev)->of_node, |
| 6054 | "qcom,ep-wakeirq"); |
| 6055 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6056 | "PCIe: EP of RC%d does %s assert wake when it is up.\n", |
| 6057 | rc_idx, msm_pcie_dev[rc_idx].ep_wakeirq ? "" : "not"); |
| 6058 | |
| 6059 | msm_pcie_dev[rc_idx].phy_ver = 1; |
| 6060 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6061 | "qcom,pcie-phy-ver", |
| 6062 | &msm_pcie_dev[rc_idx].phy_ver); |
| 6063 | if (ret) |
| 6064 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6065 | "RC%d: pcie-phy-ver does not exist.\n", |
| 6066 | msm_pcie_dev[rc_idx].rc_idx); |
| 6067 | else |
| 6068 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6069 | "RC%d: pcie-phy-ver: %d.\n", |
| 6070 | msm_pcie_dev[rc_idx].rc_idx, |
| 6071 | msm_pcie_dev[rc_idx].phy_ver); |
| 6072 | |
| 6073 | msm_pcie_dev[rc_idx].n_fts = 0; |
| 6074 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6075 | "qcom,n-fts", |
| 6076 | &msm_pcie_dev[rc_idx].n_fts); |
| 6077 | |
| 6078 | if (ret) |
| 6079 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6080 | "n-fts does not exist. ret=%d\n", ret); |
| 6081 | else |
| 6082 | PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n", |
| 6083 | msm_pcie_dev[rc_idx].n_fts); |
| 6084 | |
| 6085 | msm_pcie_dev[rc_idx].common_phy = |
| 6086 | of_property_read_bool((&pdev->dev)->of_node, |
| 6087 | "qcom,common-phy"); |
| 6088 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6089 | "PCIe: RC%d: Common PHY does %s exist.\n", |
| 6090 | rc_idx, msm_pcie_dev[rc_idx].common_phy ? "" : "not"); |
| 6091 | |
| 6092 | msm_pcie_dev[rc_idx].ext_ref_clk = |
| 6093 | of_property_read_bool((&pdev->dev)->of_node, |
| 6094 | "qcom,ext-ref-clk"); |
| 6095 | PCIE_DBG(&msm_pcie_dev[rc_idx], "ref clk is %s.\n", |
| 6096 | msm_pcie_dev[rc_idx].ext_ref_clk ? "external" : "internal"); |
| 6097 | |
| 6098 | msm_pcie_dev[rc_idx].ep_latency = 0; |
| 6099 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6100 | "qcom,ep-latency", |
| 6101 | &msm_pcie_dev[rc_idx].ep_latency); |
| 6102 | if (ret) |
| 6103 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6104 | "RC%d: ep-latency does not exist.\n", |
| 6105 | rc_idx); |
| 6106 | else |
| 6107 | PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n", |
| 6108 | rc_idx, msm_pcie_dev[rc_idx].ep_latency); |
| 6109 | |
| 6110 | msm_pcie_dev[rc_idx].wr_halt_size = 0; |
| 6111 | ret = of_property_read_u32(pdev->dev.of_node, |
| 6112 | "qcom,wr-halt-size", |
| 6113 | &msm_pcie_dev[rc_idx].wr_halt_size); |
| 6114 | if (ret) |
| 6115 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6116 | "RC%d: wr-halt-size not specified in dt. Use default value.\n", |
| 6117 | rc_idx); |
| 6118 | else |
| 6119 | PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: wr-halt-size: 0x%x.\n", |
| 6120 | rc_idx, msm_pcie_dev[rc_idx].wr_halt_size); |
| 6121 | |
| 6122 | msm_pcie_dev[rc_idx].cpl_timeout = 0; |
| 6123 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6124 | "qcom,cpl-timeout", |
| 6125 | &msm_pcie_dev[rc_idx].cpl_timeout); |
| 6126 | if (ret) |
| 6127 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6128 | "RC%d: Using default cpl-timeout.\n", |
| 6129 | rc_idx); |
| 6130 | else |
| 6131 | PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: cpl-timeout: 0x%x.\n", |
| 6132 | rc_idx, msm_pcie_dev[rc_idx].cpl_timeout); |
| 6133 | |
| 6134 | msm_pcie_dev[rc_idx].perst_delay_us_min = |
| 6135 | PERST_PROPAGATION_DELAY_US_MIN; |
| 6136 | ret = of_property_read_u32(pdev->dev.of_node, |
| 6137 | "qcom,perst-delay-us-min", |
| 6138 | &msm_pcie_dev[rc_idx].perst_delay_us_min); |
| 6139 | if (ret) |
| 6140 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6141 | "RC%d: perst-delay-us-min does not exist. Use default value %dus.\n", |
| 6142 | rc_idx, msm_pcie_dev[rc_idx].perst_delay_us_min); |
| 6143 | else |
| 6144 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6145 | "RC%d: perst-delay-us-min: %dus.\n", |
| 6146 | rc_idx, msm_pcie_dev[rc_idx].perst_delay_us_min); |
| 6147 | |
| 6148 | msm_pcie_dev[rc_idx].perst_delay_us_max = |
| 6149 | PERST_PROPAGATION_DELAY_US_MAX; |
| 6150 | ret = of_property_read_u32(pdev->dev.of_node, |
| 6151 | "qcom,perst-delay-us-max", |
| 6152 | &msm_pcie_dev[rc_idx].perst_delay_us_max); |
| 6153 | if (ret) |
| 6154 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6155 | "RC%d: perst-delay-us-max does not exist. Use default value %dus.\n", |
| 6156 | rc_idx, msm_pcie_dev[rc_idx].perst_delay_us_max); |
| 6157 | else |
| 6158 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6159 | "RC%d: perst-delay-us-max: %dus.\n", |
| 6160 | rc_idx, msm_pcie_dev[rc_idx].perst_delay_us_max); |
| 6161 | |
| 6162 | msm_pcie_dev[rc_idx].tlp_rd_size = PCIE_TLP_RD_SIZE; |
| 6163 | ret = of_property_read_u32(pdev->dev.of_node, |
| 6164 | "qcom,tlp-rd-size", |
| 6165 | &msm_pcie_dev[rc_idx].tlp_rd_size); |
| 6166 | if (ret) |
| 6167 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6168 | "RC%d: tlp-rd-size does not exist. tlp-rd-size: 0x%x.\n", |
| 6169 | rc_idx, msm_pcie_dev[rc_idx].tlp_rd_size); |
| 6170 | else |
| 6171 | PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: tlp-rd-size: 0x%x.\n", |
| 6172 | rc_idx, msm_pcie_dev[rc_idx].tlp_rd_size); |
| 6173 | |
| 6174 | msm_pcie_dev[rc_idx].msi_gicm_addr = 0; |
| 6175 | msm_pcie_dev[rc_idx].msi_gicm_base = 0; |
| 6176 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6177 | "qcom,msi-gicm-addr", |
| 6178 | &msm_pcie_dev[rc_idx].msi_gicm_addr); |
| 6179 | |
| 6180 | if (ret) { |
| 6181 | PCIE_DBG(&msm_pcie_dev[rc_idx], "%s", |
| 6182 | "msi-gicm-addr does not exist.\n"); |
| 6183 | } else { |
| 6184 | PCIE_DBG(&msm_pcie_dev[rc_idx], "msi-gicm-addr: 0x%x.\n", |
| 6185 | msm_pcie_dev[rc_idx].msi_gicm_addr); |
| 6186 | |
| 6187 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6188 | "qcom,msi-gicm-base", |
| 6189 | &msm_pcie_dev[rc_idx].msi_gicm_base); |
| 6190 | |
| 6191 | if (ret) { |
| 6192 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6193 | "PCIe: RC%d: msi-gicm-base does not exist.\n", |
| 6194 | rc_idx); |
| 6195 | goto decrease_rc_num; |
| 6196 | } else { |
| 6197 | PCIE_DBG(&msm_pcie_dev[rc_idx], "msi-gicm-base: 0x%x\n", |
| 6198 | msm_pcie_dev[rc_idx].msi_gicm_base); |
| 6199 | } |
| 6200 | } |
| 6201 | |
| 6202 | msm_pcie_dev[rc_idx].scm_dev_id = 0; |
| 6203 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6204 | "qcom,scm-dev-id", |
| 6205 | &msm_pcie_dev[rc_idx].scm_dev_id); |
| 6206 | |
| 6207 | msm_pcie_dev[rc_idx].rc_idx = rc_idx; |
| 6208 | msm_pcie_dev[rc_idx].pdev = pdev; |
| 6209 | msm_pcie_dev[rc_idx].vreg_n = 0; |
| 6210 | msm_pcie_dev[rc_idx].gpio_n = 0; |
| 6211 | msm_pcie_dev[rc_idx].parf_deemph = 0; |
| 6212 | msm_pcie_dev[rc_idx].parf_swing = 0; |
| 6213 | msm_pcie_dev[rc_idx].link_status = MSM_PCIE_LINK_DEINIT; |
| 6214 | msm_pcie_dev[rc_idx].user_suspend = false; |
| 6215 | msm_pcie_dev[rc_idx].disable_pc = false; |
| 6216 | msm_pcie_dev[rc_idx].saved_state = NULL; |
| 6217 | msm_pcie_dev[rc_idx].enumerated = false; |
| 6218 | msm_pcie_dev[rc_idx].num_active_ep = 0; |
| 6219 | msm_pcie_dev[rc_idx].num_ep = 0; |
| 6220 | msm_pcie_dev[rc_idx].pending_ep_reg = false; |
| 6221 | msm_pcie_dev[rc_idx].phy_len = 0; |
| 6222 | msm_pcie_dev[rc_idx].port_phy_len = 0; |
| 6223 | msm_pcie_dev[rc_idx].phy_sequence = NULL; |
| 6224 | msm_pcie_dev[rc_idx].port_phy_sequence = NULL; |
| 6225 | msm_pcie_dev[rc_idx].event_reg = NULL; |
| 6226 | msm_pcie_dev[rc_idx].linkdown_counter = 0; |
| 6227 | msm_pcie_dev[rc_idx].link_turned_on_counter = 0; |
| 6228 | msm_pcie_dev[rc_idx].link_turned_off_counter = 0; |
| 6229 | msm_pcie_dev[rc_idx].rc_corr_counter = 0; |
| 6230 | msm_pcie_dev[rc_idx].rc_non_fatal_counter = 0; |
| 6231 | msm_pcie_dev[rc_idx].rc_fatal_counter = 0; |
| 6232 | msm_pcie_dev[rc_idx].ep_corr_counter = 0; |
| 6233 | msm_pcie_dev[rc_idx].ep_non_fatal_counter = 0; |
| 6234 | msm_pcie_dev[rc_idx].ep_fatal_counter = 0; |
| 6235 | msm_pcie_dev[rc_idx].suspending = false; |
| 6236 | msm_pcie_dev[rc_idx].wake_counter = 0; |
| 6237 | msm_pcie_dev[rc_idx].aer_enable = true; |
| 6238 | msm_pcie_dev[rc_idx].power_on = false; |
| 6239 | msm_pcie_dev[rc_idx].current_short_bdf = 0; |
| 6240 | msm_pcie_dev[rc_idx].use_msi = false; |
| 6241 | msm_pcie_dev[rc_idx].use_pinctrl = false; |
| 6242 | msm_pcie_dev[rc_idx].linkdown_panic = false; |
| 6243 | msm_pcie_dev[rc_idx].bridge_found = false; |
| 6244 | memcpy(msm_pcie_dev[rc_idx].vreg, msm_pcie_vreg_info, |
| 6245 | sizeof(msm_pcie_vreg_info)); |
| 6246 | memcpy(msm_pcie_dev[rc_idx].gpio, msm_pcie_gpio_info, |
| 6247 | sizeof(msm_pcie_gpio_info)); |
| 6248 | memcpy(msm_pcie_dev[rc_idx].clk, msm_pcie_clk_info[rc_idx], |
| 6249 | sizeof(msm_pcie_clk_info[rc_idx])); |
| 6250 | memcpy(msm_pcie_dev[rc_idx].pipeclk, msm_pcie_pipe_clk_info[rc_idx], |
| 6251 | sizeof(msm_pcie_pipe_clk_info[rc_idx])); |
| 6252 | memcpy(msm_pcie_dev[rc_idx].res, msm_pcie_res_info, |
| 6253 | sizeof(msm_pcie_res_info)); |
| 6254 | memcpy(msm_pcie_dev[rc_idx].irq, msm_pcie_irq_info, |
| 6255 | sizeof(msm_pcie_irq_info)); |
| 6256 | memcpy(msm_pcie_dev[rc_idx].msi, msm_pcie_msi_info, |
| 6257 | sizeof(msm_pcie_msi_info)); |
| 6258 | memcpy(msm_pcie_dev[rc_idx].reset, msm_pcie_reset_info[rc_idx], |
| 6259 | sizeof(msm_pcie_reset_info[rc_idx])); |
| 6260 | memcpy(msm_pcie_dev[rc_idx].pipe_reset, |
| 6261 | msm_pcie_pipe_reset_info[rc_idx], |
| 6262 | sizeof(msm_pcie_pipe_reset_info[rc_idx])); |
| 6263 | msm_pcie_dev[rc_idx].shadow_en = true; |
| 6264 | for (i = 0; i < PCIE_CONF_SPACE_DW; i++) |
| 6265 | msm_pcie_dev[rc_idx].rc_shadow[i] = PCIE_CLEAR; |
| 6266 | for (i = 0; i < MAX_DEVICE_NUM; i++) |
| 6267 | for (j = 0; j < PCIE_CONF_SPACE_DW; j++) |
| 6268 | msm_pcie_dev[rc_idx].ep_shadow[i][j] = PCIE_CLEAR; |
| 6269 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 6270 | msm_pcie_dev[rc_idx].pcidev_table[i].bdf = 0; |
| 6271 | msm_pcie_dev[rc_idx].pcidev_table[i].dev = NULL; |
| 6272 | msm_pcie_dev[rc_idx].pcidev_table[i].short_bdf = 0; |
| 6273 | msm_pcie_dev[rc_idx].pcidev_table[i].sid = 0; |
| 6274 | msm_pcie_dev[rc_idx].pcidev_table[i].domain = rc_idx; |
| 6275 | msm_pcie_dev[rc_idx].pcidev_table[i].conf_base = 0; |
| 6276 | msm_pcie_dev[rc_idx].pcidev_table[i].phy_address = 0; |
| 6277 | msm_pcie_dev[rc_idx].pcidev_table[i].dev_ctrlstts_offset = 0; |
| 6278 | msm_pcie_dev[rc_idx].pcidev_table[i].event_reg = NULL; |
| 6279 | msm_pcie_dev[rc_idx].pcidev_table[i].registered = true; |
| 6280 | } |
| 6281 | |
| 6282 | ret = msm_pcie_get_resources(&msm_pcie_dev[rc_idx], |
| 6283 | msm_pcie_dev[rc_idx].pdev); |
| 6284 | |
| 6285 | if (ret) |
| 6286 | goto decrease_rc_num; |
| 6287 | |
| 6288 | msm_pcie_dev[rc_idx].pinctrl = devm_pinctrl_get(&pdev->dev); |
| 6289 | if (IS_ERR_OR_NULL(msm_pcie_dev[rc_idx].pinctrl)) |
| 6290 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6291 | "PCIe: RC%d failed to get pinctrl\n", |
| 6292 | rc_idx); |
| 6293 | else |
| 6294 | msm_pcie_dev[rc_idx].use_pinctrl = true; |
| 6295 | |
| 6296 | if (msm_pcie_dev[rc_idx].use_pinctrl) { |
| 6297 | msm_pcie_dev[rc_idx].pins_default = |
| 6298 | pinctrl_lookup_state(msm_pcie_dev[rc_idx].pinctrl, |
| 6299 | "default"); |
| 6300 | if (IS_ERR(msm_pcie_dev[rc_idx].pins_default)) { |
| 6301 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6302 | "PCIe: RC%d could not get pinctrl default state\n", |
| 6303 | rc_idx); |
| 6304 | msm_pcie_dev[rc_idx].pins_default = NULL; |
| 6305 | } |
| 6306 | |
| 6307 | msm_pcie_dev[rc_idx].pins_sleep = |
| 6308 | pinctrl_lookup_state(msm_pcie_dev[rc_idx].pinctrl, |
| 6309 | "sleep"); |
| 6310 | if (IS_ERR(msm_pcie_dev[rc_idx].pins_sleep)) { |
| 6311 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6312 | "PCIe: RC%d could not get pinctrl sleep state\n", |
| 6313 | rc_idx); |
| 6314 | msm_pcie_dev[rc_idx].pins_sleep = NULL; |
| 6315 | } |
| 6316 | } |
| 6317 | |
| 6318 | ret = msm_pcie_gpio_init(&msm_pcie_dev[rc_idx]); |
| 6319 | if (ret) { |
| 6320 | msm_pcie_release_resources(&msm_pcie_dev[rc_idx]); |
| 6321 | goto decrease_rc_num; |
| 6322 | } |
| 6323 | |
| 6324 | ret = msm_pcie_irq_init(&msm_pcie_dev[rc_idx]); |
| 6325 | if (ret) { |
| 6326 | msm_pcie_release_resources(&msm_pcie_dev[rc_idx]); |
| 6327 | msm_pcie_gpio_deinit(&msm_pcie_dev[rc_idx]); |
| 6328 | goto decrease_rc_num; |
| 6329 | } |
| 6330 | |
| 6331 | msm_pcie_dev[rc_idx].drv_ready = true; |
| 6332 | |
| 6333 | if (msm_pcie_dev[rc_idx].ep_wakeirq) { |
| 6334 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6335 | "PCIe: RC%d will be enumerated upon WAKE signal from Endpoint.\n", |
| 6336 | rc_idx); |
| 6337 | mutex_unlock(&pcie_drv.drv_lock); |
| 6338 | return 0; |
| 6339 | } |
| 6340 | |
| 6341 | ret = msm_pcie_enumerate(rc_idx); |
| 6342 | |
| 6343 | if (ret) |
| 6344 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6345 | "PCIe: RC%d is not enabled during bootup; it will be enumerated upon client request.\n", |
| 6346 | rc_idx); |
| 6347 | else |
| 6348 | PCIE_ERR(&msm_pcie_dev[rc_idx], "RC%d is enabled in bootup\n", |
| 6349 | rc_idx); |
| 6350 | |
| 6351 | PCIE_DBG(&msm_pcie_dev[rc_idx], "PCIE probed %s\n", |
| 6352 | dev_name(&(pdev->dev))); |
| 6353 | |
| 6354 | mutex_unlock(&pcie_drv.drv_lock); |
| 6355 | return 0; |
| 6356 | |
| 6357 | decrease_rc_num: |
| 6358 | pcie_drv.rc_num--; |
| 6359 | out: |
| 6360 | if (rc_idx < 0 || rc_idx >= MAX_RC_NUM) |
| 6361 | pr_err("PCIe: Invalid RC index %d. Driver probe failed\n", |
| 6362 | rc_idx); |
| 6363 | else |
| 6364 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6365 | "PCIe: Driver probe failed for RC%d:%d\n", |
| 6366 | rc_idx, ret); |
| 6367 | |
| 6368 | mutex_unlock(&pcie_drv.drv_lock); |
| 6369 | |
| 6370 | return ret; |
| 6371 | } |
| 6372 | |
| 6373 | static int msm_pcie_remove(struct platform_device *pdev) |
| 6374 | { |
| 6375 | int ret = 0; |
| 6376 | int rc_idx; |
| 6377 | |
| 6378 | PCIE_GEN_DBG("PCIe:%s.\n", __func__); |
| 6379 | |
| 6380 | mutex_lock(&pcie_drv.drv_lock); |
| 6381 | |
| 6382 | ret = of_property_read_u32((&pdev->dev)->of_node, |
| 6383 | "cell-index", &rc_idx); |
| 6384 | if (ret) { |
| 6385 | pr_err("%s: Did not find RC index.\n", __func__); |
| 6386 | goto out; |
| 6387 | } else { |
| 6388 | pcie_drv.rc_num--; |
| 6389 | PCIE_GEN_DBG("%s: RC index is 0x%x.", __func__, rc_idx); |
| 6390 | } |
| 6391 | |
| 6392 | msm_pcie_irq_deinit(&msm_pcie_dev[rc_idx]); |
| 6393 | msm_pcie_vreg_deinit(&msm_pcie_dev[rc_idx]); |
| 6394 | msm_pcie_clk_deinit(&msm_pcie_dev[rc_idx]); |
| 6395 | msm_pcie_gpio_deinit(&msm_pcie_dev[rc_idx]); |
| 6396 | msm_pcie_release_resources(&msm_pcie_dev[rc_idx]); |
| 6397 | |
| 6398 | out: |
| 6399 | mutex_unlock(&pcie_drv.drv_lock); |
| 6400 | |
| 6401 | return ret; |
| 6402 | } |
| 6403 | |
| 6404 | static const struct of_device_id msm_pcie_match[] = { |
| 6405 | { .compatible = "qcom,pci-msm", |
| 6406 | }, |
| 6407 | {} |
| 6408 | }; |
| 6409 | |
| 6410 | static struct platform_driver msm_pcie_driver = { |
| 6411 | .probe = msm_pcie_probe, |
| 6412 | .remove = msm_pcie_remove, |
| 6413 | .driver = { |
| 6414 | .name = "pci-msm", |
| 6415 | .owner = THIS_MODULE, |
| 6416 | .of_match_table = msm_pcie_match, |
| 6417 | }, |
| 6418 | }; |
| 6419 | |
| 6420 | int __init pcie_init(void) |
| 6421 | { |
| 6422 | int ret = 0, i; |
| 6423 | char rc_name[MAX_RC_NAME_LEN]; |
| 6424 | |
| 6425 | pr_alert("pcie:%s.\n", __func__); |
| 6426 | |
| 6427 | pcie_drv.rc_num = 0; |
| 6428 | mutex_init(&pcie_drv.drv_lock); |
| 6429 | mutex_init(&com_phy_lock); |
| 6430 | |
| 6431 | for (i = 0; i < MAX_RC_NUM; i++) { |
| 6432 | snprintf(rc_name, MAX_RC_NAME_LEN, "pcie%d-short", i); |
| 6433 | msm_pcie_dev[i].ipc_log = |
| 6434 | ipc_log_context_create(PCIE_LOG_PAGES, rc_name, 0); |
| 6435 | if (msm_pcie_dev[i].ipc_log == NULL) |
| 6436 | pr_err("%s: unable to create IPC log context for %s\n", |
| 6437 | __func__, rc_name); |
| 6438 | else |
| 6439 | PCIE_DBG(&msm_pcie_dev[i], |
| 6440 | "PCIe IPC logging is enable for RC%d\n", |
| 6441 | i); |
| 6442 | snprintf(rc_name, MAX_RC_NAME_LEN, "pcie%d-long", i); |
| 6443 | msm_pcie_dev[i].ipc_log_long = |
| 6444 | ipc_log_context_create(PCIE_LOG_PAGES, rc_name, 0); |
| 6445 | if (msm_pcie_dev[i].ipc_log_long == NULL) |
| 6446 | pr_err("%s: unable to create IPC log context for %s\n", |
| 6447 | __func__, rc_name); |
| 6448 | else |
| 6449 | PCIE_DBG(&msm_pcie_dev[i], |
| 6450 | "PCIe IPC logging %s is enable for RC%d\n", |
| 6451 | rc_name, i); |
| 6452 | snprintf(rc_name, MAX_RC_NAME_LEN, "pcie%d-dump", i); |
| 6453 | msm_pcie_dev[i].ipc_log_dump = |
| 6454 | ipc_log_context_create(PCIE_LOG_PAGES, rc_name, 0); |
| 6455 | if (msm_pcie_dev[i].ipc_log_dump == NULL) |
| 6456 | pr_err("%s: unable to create IPC log context for %s\n", |
| 6457 | __func__, rc_name); |
| 6458 | else |
| 6459 | PCIE_DBG(&msm_pcie_dev[i], |
| 6460 | "PCIe IPC logging %s is enable for RC%d\n", |
| 6461 | rc_name, i); |
| 6462 | spin_lock_init(&msm_pcie_dev[i].cfg_lock); |
| 6463 | msm_pcie_dev[i].cfg_access = true; |
| 6464 | mutex_init(&msm_pcie_dev[i].enumerate_lock); |
| 6465 | mutex_init(&msm_pcie_dev[i].setup_lock); |
| 6466 | mutex_init(&msm_pcie_dev[i].recovery_lock); |
| 6467 | spin_lock_init(&msm_pcie_dev[i].linkdown_lock); |
| 6468 | spin_lock_init(&msm_pcie_dev[i].wakeup_lock); |
| 6469 | spin_lock_init(&msm_pcie_dev[i].global_irq_lock); |
| 6470 | spin_lock_init(&msm_pcie_dev[i].aer_lock); |
| 6471 | msm_pcie_dev[i].drv_ready = false; |
| 6472 | } |
| 6473 | for (i = 0; i < MAX_RC_NUM * MAX_DEVICE_NUM; i++) { |
| 6474 | msm_pcie_dev_tbl[i].bdf = 0; |
| 6475 | msm_pcie_dev_tbl[i].dev = NULL; |
| 6476 | msm_pcie_dev_tbl[i].short_bdf = 0; |
| 6477 | msm_pcie_dev_tbl[i].sid = 0; |
| 6478 | msm_pcie_dev_tbl[i].domain = -1; |
| 6479 | msm_pcie_dev_tbl[i].conf_base = 0; |
| 6480 | msm_pcie_dev_tbl[i].phy_address = 0; |
| 6481 | msm_pcie_dev_tbl[i].dev_ctrlstts_offset = 0; |
| 6482 | msm_pcie_dev_tbl[i].event_reg = NULL; |
| 6483 | msm_pcie_dev_tbl[i].registered = true; |
| 6484 | } |
| 6485 | |
| 6486 | msm_pcie_debugfs_init(); |
| 6487 | |
| 6488 | ret = platform_driver_register(&msm_pcie_driver); |
| 6489 | |
| 6490 | return ret; |
| 6491 | } |
| 6492 | |
| 6493 | static void __exit pcie_exit(void) |
| 6494 | { |
| 6495 | PCIE_GEN_DBG("pcie:%s.\n", __func__); |
| 6496 | |
| 6497 | platform_driver_unregister(&msm_pcie_driver); |
| 6498 | |
| 6499 | msm_pcie_debugfs_exit(); |
| 6500 | } |
| 6501 | |
| 6502 | subsys_initcall_sync(pcie_init); |
| 6503 | module_exit(pcie_exit); |
| 6504 | |
| 6505 | |
| 6506 | /* RC do not represent the right class; set it to PCI_CLASS_BRIDGE_PCI */ |
| 6507 | static void msm_pcie_fixup_early(struct pci_dev *dev) |
| 6508 | { |
| 6509 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6510 | |
| 6511 | PCIE_DBG(pcie_dev, "hdr_type %d\n", dev->hdr_type); |
| 6512 | if (dev->hdr_type == 1) |
| 6513 | dev->class = (dev->class & 0xff) | (PCI_CLASS_BRIDGE_PCI << 8); |
| 6514 | } |
| 6515 | DECLARE_PCI_FIXUP_EARLY(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP, |
| 6516 | msm_pcie_fixup_early); |
| 6517 | |
| 6518 | /* Suspend the PCIe link */ |
| 6519 | static int msm_pcie_pm_suspend(struct pci_dev *dev, |
| 6520 | void *user, void *data, u32 options) |
| 6521 | { |
| 6522 | int ret = 0; |
| 6523 | u32 val = 0; |
| 6524 | int ret_l23; |
| 6525 | unsigned long irqsave_flags; |
| 6526 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6527 | |
| 6528 | PCIE_DBG(pcie_dev, "RC%d: entry\n", pcie_dev->rc_idx); |
| 6529 | |
| 6530 | spin_lock_irqsave(&pcie_dev->aer_lock, irqsave_flags); |
| 6531 | pcie_dev->suspending = true; |
| 6532 | spin_unlock_irqrestore(&pcie_dev->aer_lock, irqsave_flags); |
| 6533 | |
| 6534 | if (!pcie_dev->power_on) { |
| 6535 | PCIE_DBG(pcie_dev, |
| 6536 | "PCIe: power of RC%d has been turned off.\n", |
| 6537 | pcie_dev->rc_idx); |
| 6538 | return ret; |
| 6539 | } |
| 6540 | |
| 6541 | if (dev && !(options & MSM_PCIE_CONFIG_NO_CFG_RESTORE) |
| 6542 | && msm_pcie_confirm_linkup(pcie_dev, true, true, |
| 6543 | pcie_dev->conf)) { |
| 6544 | ret = pci_save_state(dev); |
| 6545 | pcie_dev->saved_state = pci_store_saved_state(dev); |
| 6546 | } |
| 6547 | if (ret) { |
| 6548 | PCIE_ERR(pcie_dev, "PCIe: fail to save state of RC%d:%d.\n", |
| 6549 | pcie_dev->rc_idx, ret); |
| 6550 | pcie_dev->suspending = false; |
| 6551 | return ret; |
| 6552 | } |
| 6553 | |
| 6554 | spin_lock_irqsave(&pcie_dev->cfg_lock, |
| 6555 | pcie_dev->irqsave_flags); |
| 6556 | pcie_dev->cfg_access = false; |
| 6557 | spin_unlock_irqrestore(&pcie_dev->cfg_lock, |
| 6558 | pcie_dev->irqsave_flags); |
| 6559 | |
| 6560 | msm_pcie_write_mask(pcie_dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, |
| 6561 | BIT(4)); |
| 6562 | |
| 6563 | PCIE_DBG(pcie_dev, "RC%d: PME_TURNOFF_MSG is sent out\n", |
| 6564 | pcie_dev->rc_idx); |
| 6565 | |
| 6566 | ret_l23 = readl_poll_timeout((pcie_dev->parf |
| 6567 | + PCIE20_PARF_PM_STTS), val, (val & BIT(5)), 10000, 100000); |
| 6568 | |
| 6569 | /* check L23_Ready */ |
| 6570 | PCIE_DBG(pcie_dev, "RC%d: PCIE20_PARF_PM_STTS is 0x%x.\n", |
| 6571 | pcie_dev->rc_idx, |
| 6572 | readl_relaxed(pcie_dev->parf + PCIE20_PARF_PM_STTS)); |
| 6573 | if (!ret_l23) |
| 6574 | PCIE_DBG(pcie_dev, "RC%d: PM_Enter_L23 is received\n", |
| 6575 | pcie_dev->rc_idx); |
| 6576 | else |
| 6577 | PCIE_DBG(pcie_dev, "RC%d: PM_Enter_L23 is NOT received\n", |
| 6578 | pcie_dev->rc_idx); |
| 6579 | |
| 6580 | msm_pcie_disable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG); |
| 6581 | |
| 6582 | if (pcie_dev->use_pinctrl && pcie_dev->pins_sleep) |
| 6583 | pinctrl_select_state(pcie_dev->pinctrl, |
| 6584 | pcie_dev->pins_sleep); |
| 6585 | |
| 6586 | PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx); |
| 6587 | |
| 6588 | return ret; |
| 6589 | } |
| 6590 | |
| 6591 | static void msm_pcie_fixup_suspend(struct pci_dev *dev) |
| 6592 | { |
| 6593 | int ret; |
| 6594 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6595 | |
| 6596 | PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx); |
| 6597 | |
| 6598 | if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED) |
| 6599 | return; |
| 6600 | |
| 6601 | spin_lock_irqsave(&pcie_dev->cfg_lock, |
| 6602 | pcie_dev->irqsave_flags); |
| 6603 | if (pcie_dev->disable_pc) { |
| 6604 | PCIE_DBG(pcie_dev, |
| 6605 | "RC%d: Skip suspend because of user request\n", |
| 6606 | pcie_dev->rc_idx); |
| 6607 | spin_unlock_irqrestore(&pcie_dev->cfg_lock, |
| 6608 | pcie_dev->irqsave_flags); |
| 6609 | return; |
| 6610 | } |
| 6611 | spin_unlock_irqrestore(&pcie_dev->cfg_lock, |
| 6612 | pcie_dev->irqsave_flags); |
| 6613 | |
| 6614 | mutex_lock(&pcie_dev->recovery_lock); |
| 6615 | |
| 6616 | ret = msm_pcie_pm_suspend(dev, NULL, NULL, 0); |
| 6617 | if (ret) |
| 6618 | PCIE_ERR(pcie_dev, "PCIe: RC%d got failure in suspend:%d.\n", |
| 6619 | pcie_dev->rc_idx, ret); |
| 6620 | |
| 6621 | mutex_unlock(&pcie_dev->recovery_lock); |
| 6622 | } |
| 6623 | DECLARE_PCI_FIXUP_SUSPEND(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP, |
| 6624 | msm_pcie_fixup_suspend); |
| 6625 | |
| 6626 | /* Resume the PCIe link */ |
| 6627 | static int msm_pcie_pm_resume(struct pci_dev *dev, |
| 6628 | void *user, void *data, u32 options) |
| 6629 | { |
| 6630 | int ret; |
| 6631 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6632 | |
| 6633 | PCIE_DBG(pcie_dev, "RC%d: entry\n", pcie_dev->rc_idx); |
| 6634 | |
| 6635 | if (pcie_dev->use_pinctrl && pcie_dev->pins_default) |
| 6636 | pinctrl_select_state(pcie_dev->pinctrl, |
| 6637 | pcie_dev->pins_default); |
| 6638 | |
| 6639 | spin_lock_irqsave(&pcie_dev->cfg_lock, |
| 6640 | pcie_dev->irqsave_flags); |
| 6641 | pcie_dev->cfg_access = true; |
| 6642 | spin_unlock_irqrestore(&pcie_dev->cfg_lock, |
| 6643 | pcie_dev->irqsave_flags); |
| 6644 | |
| 6645 | ret = msm_pcie_enable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG); |
| 6646 | if (ret) { |
| 6647 | PCIE_ERR(pcie_dev, |
| 6648 | "PCIe: RC%d fail to enable PCIe link in resume.\n", |
| 6649 | pcie_dev->rc_idx); |
| 6650 | return ret; |
| 6651 | } |
| 6652 | |
| 6653 | pcie_dev->suspending = false; |
| 6654 | PCIE_DBG(pcie_dev, |
| 6655 | "dev->bus->number = %d dev->bus->primary = %d\n", |
| 6656 | dev->bus->number, dev->bus->primary); |
| 6657 | |
| 6658 | if (!(options & MSM_PCIE_CONFIG_NO_CFG_RESTORE)) { |
| 6659 | PCIE_DBG(pcie_dev, |
| 6660 | "RC%d: entry of PCI framework restore state\n", |
| 6661 | pcie_dev->rc_idx); |
| 6662 | |
| 6663 | pci_load_and_free_saved_state(dev, |
| 6664 | &pcie_dev->saved_state); |
| 6665 | pci_restore_state(dev); |
| 6666 | |
| 6667 | PCIE_DBG(pcie_dev, |
| 6668 | "RC%d: exit of PCI framework restore state\n", |
| 6669 | pcie_dev->rc_idx); |
| 6670 | } |
| 6671 | |
| 6672 | if (pcie_dev->bridge_found) { |
| 6673 | PCIE_DBG(pcie_dev, |
| 6674 | "RC%d: entry of PCIe recover config\n", |
| 6675 | pcie_dev->rc_idx); |
| 6676 | |
| 6677 | msm_pcie_recover_config(dev); |
| 6678 | |
| 6679 | PCIE_DBG(pcie_dev, |
| 6680 | "RC%d: exit of PCIe recover config\n", |
| 6681 | pcie_dev->rc_idx); |
| 6682 | } |
| 6683 | |
| 6684 | PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx); |
| 6685 | |
| 6686 | return ret; |
| 6687 | } |
| 6688 | |
| 6689 | void msm_pcie_fixup_resume(struct pci_dev *dev) |
| 6690 | { |
| 6691 | int ret; |
| 6692 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6693 | |
| 6694 | PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx); |
| 6695 | |
| 6696 | if ((pcie_dev->link_status != MSM_PCIE_LINK_DISABLED) || |
| 6697 | pcie_dev->user_suspend) |
| 6698 | return; |
| 6699 | |
| 6700 | mutex_lock(&pcie_dev->recovery_lock); |
| 6701 | ret = msm_pcie_pm_resume(dev, NULL, NULL, 0); |
| 6702 | if (ret) |
| 6703 | PCIE_ERR(pcie_dev, |
| 6704 | "PCIe: RC%d got failure in fixup resume:%d.\n", |
| 6705 | pcie_dev->rc_idx, ret); |
| 6706 | |
| 6707 | mutex_unlock(&pcie_dev->recovery_lock); |
| 6708 | } |
| 6709 | DECLARE_PCI_FIXUP_RESUME(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP, |
| 6710 | msm_pcie_fixup_resume); |
| 6711 | |
| 6712 | void msm_pcie_fixup_resume_early(struct pci_dev *dev) |
| 6713 | { |
| 6714 | int ret; |
| 6715 | struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 6716 | |
| 6717 | PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx); |
| 6718 | |
| 6719 | if ((pcie_dev->link_status != MSM_PCIE_LINK_DISABLED) || |
| 6720 | pcie_dev->user_suspend) |
| 6721 | return; |
| 6722 | |
| 6723 | mutex_lock(&pcie_dev->recovery_lock); |
| 6724 | ret = msm_pcie_pm_resume(dev, NULL, NULL, 0); |
| 6725 | if (ret) |
| 6726 | PCIE_ERR(pcie_dev, "PCIe: RC%d got failure in resume:%d.\n", |
| 6727 | pcie_dev->rc_idx, ret); |
| 6728 | |
| 6729 | mutex_unlock(&pcie_dev->recovery_lock); |
| 6730 | } |
| 6731 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP, |
| 6732 | msm_pcie_fixup_resume_early); |
| 6733 | |
| 6734 | int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr, void *user, |
| 6735 | void *data, u32 options) |
| 6736 | { |
| 6737 | int i, ret = 0; |
| 6738 | struct pci_dev *dev; |
| 6739 | u32 rc_idx = 0; |
| 6740 | struct msm_pcie_dev_t *pcie_dev; |
| 6741 | |
| 6742 | PCIE_GEN_DBG("PCIe: pm_opt:%d;busnr:%d;options:%d\n", |
| 6743 | pm_opt, busnr, options); |
| 6744 | |
| 6745 | |
| 6746 | if (!user) { |
| 6747 | pr_err("PCIe: endpoint device is NULL\n"); |
| 6748 | ret = -ENODEV; |
| 6749 | goto out; |
| 6750 | } |
| 6751 | |
| 6752 | pcie_dev = PCIE_BUS_PRIV_DATA(((struct pci_dev *)user)->bus); |
| 6753 | |
| 6754 | if (pcie_dev) { |
| 6755 | rc_idx = pcie_dev->rc_idx; |
| 6756 | PCIE_DBG(pcie_dev, |
| 6757 | "PCIe: RC%d: pm_opt:%d;busnr:%d;options:%d\n", |
| 6758 | rc_idx, pm_opt, busnr, options); |
| 6759 | } else { |
| 6760 | pr_err( |
| 6761 | "PCIe: did not find RC for pci endpoint device.\n" |
| 6762 | ); |
| 6763 | ret = -ENODEV; |
| 6764 | goto out; |
| 6765 | } |
| 6766 | |
| 6767 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 6768 | if (!busnr) |
| 6769 | break; |
| 6770 | if (user == pcie_dev->pcidev_table[i].dev) { |
| 6771 | if (busnr == pcie_dev->pcidev_table[i].bdf >> 24) |
| 6772 | break; |
| 6773 | |
| 6774 | PCIE_ERR(pcie_dev, |
| 6775 | "PCIe: RC%d: bus number %d does not match with the expected value %d\n", |
| 6776 | pcie_dev->rc_idx, busnr, |
| 6777 | pcie_dev->pcidev_table[i].bdf >> 24); |
| 6778 | ret = MSM_PCIE_ERROR; |
| 6779 | goto out; |
| 6780 | } |
| 6781 | } |
| 6782 | |
| 6783 | if (i == MAX_DEVICE_NUM) { |
| 6784 | PCIE_ERR(pcie_dev, |
| 6785 | "PCIe: RC%d: endpoint device was not found in device table", |
| 6786 | pcie_dev->rc_idx); |
| 6787 | ret = MSM_PCIE_ERROR; |
| 6788 | goto out; |
| 6789 | } |
| 6790 | |
| 6791 | dev = msm_pcie_dev[rc_idx].dev; |
| 6792 | |
| 6793 | if (!msm_pcie_dev[rc_idx].drv_ready) { |
| 6794 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6795 | "RC%d has not been successfully probed yet\n", |
| 6796 | rc_idx); |
| 6797 | return -EPROBE_DEFER; |
| 6798 | } |
| 6799 | |
| 6800 | switch (pm_opt) { |
| 6801 | case MSM_PCIE_SUSPEND: |
| 6802 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6803 | "User of RC%d requests to suspend the link\n", rc_idx); |
| 6804 | if (msm_pcie_dev[rc_idx].link_status != MSM_PCIE_LINK_ENABLED) |
| 6805 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6806 | "PCIe: RC%d: requested to suspend when link is not enabled:%d.\n", |
| 6807 | rc_idx, msm_pcie_dev[rc_idx].link_status); |
| 6808 | |
| 6809 | if (!msm_pcie_dev[rc_idx].power_on) { |
| 6810 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6811 | "PCIe: RC%d: requested to suspend when link is powered down:%d.\n", |
| 6812 | rc_idx, msm_pcie_dev[rc_idx].link_status); |
| 6813 | break; |
| 6814 | } |
| 6815 | |
| 6816 | if (msm_pcie_dev[rc_idx].pending_ep_reg) { |
| 6817 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6818 | "PCIe: RC%d: request to suspend the link is rejected\n", |
| 6819 | rc_idx); |
| 6820 | break; |
| 6821 | } |
| 6822 | |
| 6823 | if (pcie_dev->num_active_ep) { |
| 6824 | PCIE_DBG(pcie_dev, |
| 6825 | "RC%d: an EP requested to suspend the link, but other EPs are still active: %d\n", |
| 6826 | pcie_dev->rc_idx, pcie_dev->num_active_ep); |
| 6827 | return ret; |
| 6828 | } |
| 6829 | |
| 6830 | msm_pcie_dev[rc_idx].user_suspend = true; |
| 6831 | |
| 6832 | mutex_lock(&msm_pcie_dev[rc_idx].recovery_lock); |
| 6833 | |
| 6834 | ret = msm_pcie_pm_suspend(dev, user, data, options); |
| 6835 | if (ret) { |
| 6836 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6837 | "PCIe: RC%d: user failed to suspend the link.\n", |
| 6838 | rc_idx); |
| 6839 | msm_pcie_dev[rc_idx].user_suspend = false; |
| 6840 | } |
| 6841 | |
| 6842 | mutex_unlock(&msm_pcie_dev[rc_idx].recovery_lock); |
| 6843 | break; |
| 6844 | case MSM_PCIE_RESUME: |
| 6845 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6846 | "User of RC%d requests to resume the link\n", rc_idx); |
| 6847 | if (msm_pcie_dev[rc_idx].link_status != |
| 6848 | MSM_PCIE_LINK_DISABLED) { |
| 6849 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6850 | "PCIe: RC%d: requested to resume when link is not disabled:%d. Number of active EP(s): %d\n", |
| 6851 | rc_idx, msm_pcie_dev[rc_idx].link_status, |
| 6852 | msm_pcie_dev[rc_idx].num_active_ep); |
| 6853 | break; |
| 6854 | } |
| 6855 | |
| 6856 | mutex_lock(&msm_pcie_dev[rc_idx].recovery_lock); |
| 6857 | ret = msm_pcie_pm_resume(dev, user, data, options); |
| 6858 | if (ret) { |
| 6859 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6860 | "PCIe: RC%d: user failed to resume the link.\n", |
| 6861 | rc_idx); |
| 6862 | } else { |
| 6863 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6864 | "PCIe: RC%d: user succeeded to resume the link.\n", |
| 6865 | rc_idx); |
| 6866 | |
| 6867 | msm_pcie_dev[rc_idx].user_suspend = false; |
| 6868 | } |
| 6869 | |
| 6870 | mutex_unlock(&msm_pcie_dev[rc_idx].recovery_lock); |
| 6871 | |
| 6872 | break; |
| 6873 | case MSM_PCIE_DISABLE_PC: |
| 6874 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6875 | "User of RC%d requests to keep the link always alive.\n", |
| 6876 | rc_idx); |
| 6877 | spin_lock_irqsave(&msm_pcie_dev[rc_idx].cfg_lock, |
| 6878 | msm_pcie_dev[rc_idx].irqsave_flags); |
| 6879 | if (msm_pcie_dev[rc_idx].suspending) { |
| 6880 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6881 | "PCIe: RC%d Link has been suspended before request\n", |
| 6882 | rc_idx); |
| 6883 | ret = MSM_PCIE_ERROR; |
| 6884 | } else { |
| 6885 | msm_pcie_dev[rc_idx].disable_pc = true; |
| 6886 | } |
| 6887 | spin_unlock_irqrestore(&msm_pcie_dev[rc_idx].cfg_lock, |
| 6888 | msm_pcie_dev[rc_idx].irqsave_flags); |
| 6889 | break; |
| 6890 | case MSM_PCIE_ENABLE_PC: |
| 6891 | PCIE_DBG(&msm_pcie_dev[rc_idx], |
| 6892 | "User of RC%d cancels the request of alive link.\n", |
| 6893 | rc_idx); |
| 6894 | spin_lock_irqsave(&msm_pcie_dev[rc_idx].cfg_lock, |
| 6895 | msm_pcie_dev[rc_idx].irqsave_flags); |
| 6896 | msm_pcie_dev[rc_idx].disable_pc = false; |
| 6897 | spin_unlock_irqrestore(&msm_pcie_dev[rc_idx].cfg_lock, |
| 6898 | msm_pcie_dev[rc_idx].irqsave_flags); |
| 6899 | break; |
| 6900 | default: |
| 6901 | PCIE_ERR(&msm_pcie_dev[rc_idx], |
| 6902 | "PCIe: RC%d: unsupported pm operation:%d.\n", |
| 6903 | rc_idx, pm_opt); |
| 6904 | ret = -ENODEV; |
| 6905 | goto out; |
| 6906 | } |
| 6907 | |
| 6908 | out: |
| 6909 | return ret; |
| 6910 | } |
| 6911 | EXPORT_SYMBOL(msm_pcie_pm_control); |
| 6912 | |
| 6913 | int msm_pcie_register_event(struct msm_pcie_register_event *reg) |
| 6914 | { |
| 6915 | int i, ret = 0; |
| 6916 | struct msm_pcie_dev_t *pcie_dev; |
| 6917 | |
| 6918 | if (!reg) { |
| 6919 | pr_err("PCIe: Event registration is NULL\n"); |
| 6920 | return -ENODEV; |
| 6921 | } |
| 6922 | |
| 6923 | if (!reg->user) { |
| 6924 | pr_err("PCIe: User of event registration is NULL\n"); |
| 6925 | return -ENODEV; |
| 6926 | } |
| 6927 | |
| 6928 | pcie_dev = PCIE_BUS_PRIV_DATA(((struct pci_dev *)reg->user)->bus); |
| 6929 | |
| 6930 | if (!pcie_dev) { |
| 6931 | PCIE_ERR(pcie_dev, "%s", |
| 6932 | "PCIe: did not find RC for pci endpoint device.\n"); |
| 6933 | return -ENODEV; |
| 6934 | } |
| 6935 | |
| 6936 | if (pcie_dev->num_ep > 1) { |
| 6937 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 6938 | if (reg->user == |
| 6939 | pcie_dev->pcidev_table[i].dev) { |
| 6940 | pcie_dev->event_reg = |
| 6941 | pcie_dev->pcidev_table[i].event_reg; |
| 6942 | |
| 6943 | if (!pcie_dev->event_reg) { |
| 6944 | pcie_dev->pcidev_table[i].registered = |
| 6945 | true; |
| 6946 | |
| 6947 | pcie_dev->num_active_ep++; |
| 6948 | PCIE_DBG(pcie_dev, |
| 6949 | "PCIe: RC%d: number of active EP(s): %d.\n", |
| 6950 | pcie_dev->rc_idx, |
| 6951 | pcie_dev->num_active_ep); |
| 6952 | } |
| 6953 | |
| 6954 | pcie_dev->event_reg = reg; |
| 6955 | pcie_dev->pcidev_table[i].event_reg = reg; |
| 6956 | PCIE_DBG(pcie_dev, |
| 6957 | "Event 0x%x is registered for RC %d\n", |
| 6958 | reg->events, |
| 6959 | pcie_dev->rc_idx); |
| 6960 | |
| 6961 | break; |
| 6962 | } |
| 6963 | } |
| 6964 | |
| 6965 | if (pcie_dev->pending_ep_reg) { |
| 6966 | for (i = 0; i < MAX_DEVICE_NUM; i++) |
| 6967 | if (!pcie_dev->pcidev_table[i].registered) |
| 6968 | break; |
| 6969 | |
| 6970 | if (i == MAX_DEVICE_NUM) |
| 6971 | pcie_dev->pending_ep_reg = false; |
| 6972 | } |
| 6973 | } else { |
| 6974 | pcie_dev->event_reg = reg; |
| 6975 | PCIE_DBG(pcie_dev, |
| 6976 | "Event 0x%x is registered for RC %d\n", reg->events, |
| 6977 | pcie_dev->rc_idx); |
| 6978 | } |
| 6979 | |
| 6980 | return ret; |
| 6981 | } |
| 6982 | EXPORT_SYMBOL(msm_pcie_register_event); |
| 6983 | |
| 6984 | int msm_pcie_deregister_event(struct msm_pcie_register_event *reg) |
| 6985 | { |
| 6986 | int i, ret = 0; |
| 6987 | struct msm_pcie_dev_t *pcie_dev; |
| 6988 | |
| 6989 | if (!reg) { |
| 6990 | pr_err("PCIe: Event deregistration is NULL\n"); |
| 6991 | return -ENODEV; |
| 6992 | } |
| 6993 | |
| 6994 | if (!reg->user) { |
| 6995 | pr_err("PCIe: User of event deregistration is NULL\n"); |
| 6996 | return -ENODEV; |
| 6997 | } |
| 6998 | |
| 6999 | pcie_dev = PCIE_BUS_PRIV_DATA(((struct pci_dev *)reg->user)->bus); |
| 7000 | |
| 7001 | if (!pcie_dev) { |
| 7002 | PCIE_ERR(pcie_dev, "%s", |
| 7003 | "PCIe: did not find RC for pci endpoint device.\n"); |
| 7004 | return -ENODEV; |
| 7005 | } |
| 7006 | |
| 7007 | if (pcie_dev->num_ep > 1) { |
| 7008 | for (i = 0; i < MAX_DEVICE_NUM; i++) { |
| 7009 | if (reg->user == pcie_dev->pcidev_table[i].dev) { |
| 7010 | if (pcie_dev->pcidev_table[i].event_reg) { |
| 7011 | pcie_dev->num_active_ep--; |
| 7012 | PCIE_DBG(pcie_dev, |
| 7013 | "PCIe: RC%d: number of active EP(s) left: %d.\n", |
| 7014 | pcie_dev->rc_idx, |
| 7015 | pcie_dev->num_active_ep); |
| 7016 | } |
| 7017 | |
| 7018 | pcie_dev->event_reg = NULL; |
| 7019 | pcie_dev->pcidev_table[i].event_reg = NULL; |
| 7020 | PCIE_DBG(pcie_dev, |
| 7021 | "Event is deregistered for RC %d\n", |
| 7022 | pcie_dev->rc_idx); |
| 7023 | |
| 7024 | break; |
| 7025 | } |
| 7026 | } |
| 7027 | } else { |
| 7028 | pcie_dev->event_reg = NULL; |
| 7029 | PCIE_DBG(pcie_dev, "Event is deregistered for RC %d\n", |
| 7030 | pcie_dev->rc_idx); |
| 7031 | } |
| 7032 | |
| 7033 | return ret; |
| 7034 | } |
| 7035 | EXPORT_SYMBOL(msm_pcie_deregister_event); |
| 7036 | |
| 7037 | int msm_pcie_recover_config(struct pci_dev *dev) |
| 7038 | { |
| 7039 | int ret = 0; |
| 7040 | struct msm_pcie_dev_t *pcie_dev; |
| 7041 | |
| 7042 | if (dev) { |
| 7043 | pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 7044 | PCIE_DBG(pcie_dev, |
| 7045 | "Recovery for the link of RC%d\n", pcie_dev->rc_idx); |
| 7046 | } else { |
| 7047 | pr_err("PCIe: the input pci dev is NULL.\n"); |
| 7048 | return -ENODEV; |
| 7049 | } |
| 7050 | |
| 7051 | if (msm_pcie_confirm_linkup(pcie_dev, true, true, pcie_dev->conf)) { |
| 7052 | PCIE_DBG(pcie_dev, |
| 7053 | "Recover config space of RC%d and its EP\n", |
| 7054 | pcie_dev->rc_idx); |
| 7055 | pcie_dev->shadow_en = false; |
| 7056 | PCIE_DBG(pcie_dev, "Recover RC%d\n", pcie_dev->rc_idx); |
| 7057 | msm_pcie_cfg_recover(pcie_dev, true); |
| 7058 | PCIE_DBG(pcie_dev, "Recover EP of RC%d\n", pcie_dev->rc_idx); |
| 7059 | msm_pcie_cfg_recover(pcie_dev, false); |
| 7060 | PCIE_DBG(pcie_dev, |
| 7061 | "Refreshing the saved config space in PCI framework for RC%d and its EP\n", |
| 7062 | pcie_dev->rc_idx); |
| 7063 | pci_save_state(pcie_dev->dev); |
| 7064 | pci_save_state(dev); |
| 7065 | pcie_dev->shadow_en = true; |
| 7066 | PCIE_DBG(pcie_dev, "Turn on shadow for RC%d\n", |
| 7067 | pcie_dev->rc_idx); |
| 7068 | } else { |
| 7069 | PCIE_ERR(pcie_dev, |
| 7070 | "PCIe: the link of RC%d is not up yet; can't recover config space.\n", |
| 7071 | pcie_dev->rc_idx); |
| 7072 | ret = -ENODEV; |
| 7073 | } |
| 7074 | |
| 7075 | return ret; |
| 7076 | } |
| 7077 | EXPORT_SYMBOL(msm_pcie_recover_config); |
| 7078 | |
| 7079 | int msm_pcie_shadow_control(struct pci_dev *dev, bool enable) |
| 7080 | { |
| 7081 | int ret = 0; |
| 7082 | struct msm_pcie_dev_t *pcie_dev; |
| 7083 | |
| 7084 | if (dev) { |
| 7085 | pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); |
| 7086 | PCIE_DBG(pcie_dev, |
| 7087 | "User requests to %s shadow\n", |
| 7088 | enable ? "enable" : "disable"); |
| 7089 | } else { |
| 7090 | pr_err("PCIe: the input pci dev is NULL.\n"); |
| 7091 | return -ENODEV; |
| 7092 | } |
| 7093 | |
| 7094 | PCIE_DBG(pcie_dev, |
| 7095 | "The shadowing of RC%d is %s enabled currently.\n", |
| 7096 | pcie_dev->rc_idx, pcie_dev->shadow_en ? "" : "not"); |
| 7097 | |
| 7098 | pcie_dev->shadow_en = enable; |
| 7099 | |
| 7100 | PCIE_DBG(pcie_dev, |
| 7101 | "Shadowing of RC%d is turned %s upon user's request.\n", |
| 7102 | pcie_dev->rc_idx, enable ? "on" : "off"); |
| 7103 | |
| 7104 | return ret; |
| 7105 | } |
| 7106 | EXPORT_SYMBOL(msm_pcie_shadow_control); |