blob: 93ec158d06c109af63d695b6ac921e0df5a3a67c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090019#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21
22/**
23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
24 * @bus: pointer to PCI bus structure to search
25 *
26 * Given a PCI bus, returns the highest PCI bus number present in the set
27 * including the given PCI bus and its list of child PCI buses.
28 */
29unsigned char __devinit
30pci_bus_max_busnr(struct pci_bus* bus)
31{
32 struct list_head *tmp;
33 unsigned char max, n;
34
35 max = bus->number;
36 list_for_each(tmp, &bus->children) {
37 n = pci_bus_max_busnr(pci_bus_b(tmp));
38 if(n > max)
39 max = n;
40 }
41 return max;
42}
43
44/**
45 * pci_max_busnr - returns maximum PCI bus number
46 *
47 * Returns the highest PCI bus number present in the system global list of
48 * PCI buses.
49 */
50unsigned char __devinit
51pci_max_busnr(void)
52{
53 struct pci_bus *bus = NULL;
54 unsigned char max, n;
55
56 max = 0;
57 while ((bus = pci_find_next_bus(bus)) != NULL) {
58 n = pci_bus_max_busnr(bus);
59 if(n > max)
60 max = n;
61 }
62 return max;
63}
64
65static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
66{
67 u16 status;
68 u8 pos, id;
69 int ttl = 48;
70
71 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
72 if (!(status & PCI_STATUS_CAP_LIST))
73 return 0;
74
75 switch (hdr_type) {
76 case PCI_HEADER_TYPE_NORMAL:
77 case PCI_HEADER_TYPE_BRIDGE:
78 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
79 break;
80 case PCI_HEADER_TYPE_CARDBUS:
81 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
82 break;
83 default:
84 return 0;
85 }
86 while (ttl-- && pos >= 0x40) {
87 pos &= ~3;
88 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
89 if (id == 0xff)
90 break;
91 if (id == cap)
92 return pos;
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
94 }
95 return 0;
96}
97
98/**
99 * pci_find_capability - query for devices' capabilities
100 * @dev: PCI device to query
101 * @cap: capability code
102 *
103 * Tell if a device supports a given PCI capability.
104 * Returns the address of the requested capability structure within the
105 * device's PCI configuration space or 0 in case the device does not
106 * support it. Possible values for @cap:
107 *
108 * %PCI_CAP_ID_PM Power Management
109 * %PCI_CAP_ID_AGP Accelerated Graphics Port
110 * %PCI_CAP_ID_VPD Vital Product Data
111 * %PCI_CAP_ID_SLOTID Slot Identification
112 * %PCI_CAP_ID_MSI Message Signalled Interrupts
113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
114 * %PCI_CAP_ID_PCIX PCI-X
115 * %PCI_CAP_ID_EXP PCI Express
116 */
117int pci_find_capability(struct pci_dev *dev, int cap)
118{
119 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
120}
121
122/**
123 * pci_bus_find_capability - query for devices' capabilities
124 * @bus: the PCI bus to query
125 * @devfn: PCI device to query
126 * @cap: capability code
127 *
128 * Like pci_find_capability() but works for pci devices that do not have a
129 * pci_dev structure set up yet.
130 *
131 * Returns the address of the requested capability structure within the
132 * device's PCI configuration space or 0 in case the device does not
133 * support it.
134 */
135int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
136{
137 u8 hdr_type;
138
139 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
140
141 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
142}
143
144/**
145 * pci_find_ext_capability - Find an extended capability
146 * @dev: PCI device to query
147 * @cap: capability code
148 *
149 * Returns the address of the requested extended capability structure
150 * within the device's PCI configuration space or 0 if the device does
151 * not support it. Possible values for @cap:
152 *
153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
154 * %PCI_EXT_CAP_ID_VC Virtual Channel
155 * %PCI_EXT_CAP_ID_DSN Device Serial Number
156 * %PCI_EXT_CAP_ID_PWR Power Budgeting
157 */
158int pci_find_ext_capability(struct pci_dev *dev, int cap)
159{
160 u32 header;
161 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
162 int pos = 0x100;
163
164 if (dev->cfg_size <= 256)
165 return 0;
166
167 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
168 return 0;
169
170 /*
171 * If we have no capabilities, this is indicated by cap ID,
172 * cap version and next pointer all being 0.
173 */
174 if (header == 0)
175 return 0;
176
177 while (ttl-- > 0) {
178 if (PCI_EXT_CAP_ID(header) == cap)
179 return pos;
180
181 pos = PCI_EXT_CAP_NEXT(header);
182 if (pos < 0x100)
183 break;
184
185 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
186 break;
187 }
188
189 return 0;
190}
191
192/**
193 * pci_find_parent_resource - return resource region of parent bus of given region
194 * @dev: PCI device structure contains resources to be searched
195 * @res: child resource record for which parent is sought
196 *
197 * For given resource region of given device, return the resource
198 * region of parent bus the given region is contained in or where
199 * it should be allocated from.
200 */
201struct resource *
202pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
203{
204 const struct pci_bus *bus = dev->bus;
205 int i;
206 struct resource *best = NULL;
207
208 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
209 struct resource *r = bus->resource[i];
210 if (!r)
211 continue;
212 if (res->start && !(res->start >= r->start && res->end <= r->end))
213 continue; /* Not contained */
214 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
215 continue; /* Wrong type */
216 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
217 return r; /* Exact match */
218 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
219 best = r; /* Approximating prefetchable by non-prefetchable */
220 }
221 return best;
222}
223
224/**
John W. Linville064b53db2005-07-27 10:19:44 -0400225 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
226 * @dev: PCI device to have its BARs restored
227 *
228 * Restore the BAR values for a given device, so as to make it
229 * accessible by its driver.
230 */
231void
232pci_restore_bars(struct pci_dev *dev)
233{
234 int i, numres;
235
236 switch (dev->hdr_type) {
237 case PCI_HEADER_TYPE_NORMAL:
238 numres = 6;
239 break;
240 case PCI_HEADER_TYPE_BRIDGE:
241 numres = 2;
242 break;
243 case PCI_HEADER_TYPE_CARDBUS:
244 numres = 1;
245 break;
246 default:
247 /* Should never get here, but just in case... */
248 return;
249 }
250
251 for (i = 0; i < numres; i ++)
252 pci_update_resource(dev, &dev->resource[i], i);
253}
254
255/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 * pci_set_power_state - Set the power state of a PCI device
257 * @dev: PCI device to be suspended
258 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
259 *
260 * Transition a device to a new power state, using the Power Management
261 * Capabilities in the device's config space.
262 *
263 * RETURN VALUE:
264 * -EINVAL if trying to enter a lower state than we're already in.
265 * 0 if we're already in the requested state.
266 * -EIO if device does not support PCI PM.
267 * 0 if we can successfully change the power state.
268 */
Greg Kroah-Hartmanf165b102005-03-30 21:23:19 -0500269int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270int
271pci_set_power_state(struct pci_dev *dev, pci_power_t state)
272{
John W. Linville064b53db2005-07-27 10:19:44 -0400273 int pm, need_restore = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 u16 pmcsr, pmc;
275
276 /* bound the state we're entering */
277 if (state > PCI_D3hot)
278 state = PCI_D3hot;
279
280 /* Validate current state:
281 * Can enter D0 from any state, but if we can only go deeper
282 * to sleep if we're already in a low power state
283 */
284 if (state != PCI_D0 && dev->current_state > state)
285 return -EINVAL;
286 else if (dev->current_state == state)
287 return 0; /* we're already there */
288
289 /* find PCI PM capability in list */
290 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
291
292 /* abort if the device doesn't support PM capabilities */
293 if (!pm)
294 return -EIO;
295
296 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
297 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
298 printk(KERN_DEBUG
299 "PCI: %s has unsupported PM cap regs version (%u)\n",
300 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
301 return -EIO;
302 }
303
304 /* check if this device supports the desired state */
305 if (state == PCI_D1 || state == PCI_D2) {
306 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
307 return -EIO;
308 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
309 return -EIO;
310 }
311
John W. Linville064b53db2005-07-27 10:19:44 -0400312 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
313
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 /* If we're in D3, force entire word to 0.
315 * This doesn't affect PME_Status, disables PME_En, and
316 * sets PowerState to 0.
317 */
John W. Linville064b53db2005-07-27 10:19:44 -0400318 if (dev->current_state >= PCI_D3hot) {
319 if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
320 need_restore = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 pmcsr = 0;
John W. Linville064b53db2005-07-27 10:19:44 -0400322 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
324 pmcsr |= state;
325 }
326
327 /* enter specified state */
328 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
329
330 /* Mandatory power management transition delays */
331 /* see PCI PM 1.1 5.6.1 table 18 */
332 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
333 msleep(10);
334 else if (state == PCI_D2 || dev->current_state == PCI_D2)
335 udelay(200);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
David Shaohua Lib9131002005-03-19 00:16:18 -0500337 /*
338 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
339 * Firmware method after natice method ?
340 */
341 if (platform_pci_set_power_state)
342 platform_pci_set_power_state(dev, state);
343
344 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400345
346 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
347 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
348 * from D3hot to D0 _may_ perform an internal reset, thereby
349 * going to "D0 Uninitialized" rather than "D0 Initialized".
350 * For example, at least some versions of the 3c905B and the
351 * 3c556B exhibit this behaviour.
352 *
353 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
354 * devices in a D3hot state at boot. Consequently, we need to
355 * restore at least the BARs so that the device will be
356 * accessible to its driver.
357 */
358 if (need_restore)
359 pci_restore_bars(dev);
360
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 return 0;
362}
363
Greg Kroah-Hartmanf165b102005-03-30 21:23:19 -0500364int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
David Shaohua Li0f644742005-03-19 00:15:48 -0500365
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366/**
367 * pci_choose_state - Choose the power state of a PCI device
368 * @dev: PCI device to be suspended
369 * @state: target sleep state for the whole system. This is the value
370 * that is passed to suspend() function.
371 *
372 * Returns PCI power state suitable for given device and given system
373 * message.
374 */
375
376pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
377{
David Shaohua Li0f644742005-03-19 00:15:48 -0500378 int ret;
379
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
381 return PCI_D0;
382
David Shaohua Li0f644742005-03-19 00:15:48 -0500383 if (platform_pci_choose_state) {
384 ret = platform_pci_choose_state(dev, state);
385 if (ret >= 0)
Pavel Machekca078ba2005-09-03 15:56:57 -0700386 state.event = ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500387 }
Pavel Machekca078ba2005-09-03 15:56:57 -0700388
389 switch (state.event) {
390 case PM_EVENT_ON:
391 return PCI_D0;
392 case PM_EVENT_FREEZE:
393 case PM_EVENT_SUSPEND:
394 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 default:
Pavel Machekca078ba2005-09-03 15:56:57 -0700396 printk("They asked me for state %d\n", state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 BUG();
398 }
399 return PCI_D0;
400}
401
402EXPORT_SYMBOL(pci_choose_state);
403
404/**
405 * pci_save_state - save the PCI configuration space of a device before suspending
406 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 */
408int
409pci_save_state(struct pci_dev *dev)
410{
411 int i;
412 /* XXX: 100% dword access ok here? */
413 for (i = 0; i < 16; i++)
414 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
415 return 0;
416}
417
418/**
419 * pci_restore_state - Restore the saved state of a PCI device
420 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 */
422int
423pci_restore_state(struct pci_dev *dev)
424{
425 int i;
426
427 for (i = 0; i < 16; i++)
428 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
429 return 0;
430}
431
432/**
433 * pci_enable_device_bars - Initialize some of a device for use
434 * @dev: PCI device to be initialized
435 * @bars: bitmask of BAR's that must be configured
436 *
437 * Initialize device before it's used by a driver. Ask low-level code
438 * to enable selected I/O and memory resources. Wake up the device if it
439 * was suspended. Beware, this function can fail.
440 */
441
442int
443pci_enable_device_bars(struct pci_dev *dev, int bars)
444{
445 int err;
446
447 pci_set_power_state(dev, PCI_D0);
448 if ((err = pcibios_enable_device(dev, bars)) < 0)
449 return err;
450 return 0;
451}
452
453/**
454 * pci_enable_device - Initialize device before it's used by a driver.
455 * @dev: PCI device to be initialized
456 *
457 * Initialize device before it's used by a driver. Ask low-level code
458 * to enable I/O and memory. Wake up the device if it was suspended.
459 * Beware, this function can fail.
460 */
461int
462pci_enable_device(struct pci_dev *dev)
463{
464 int err;
465
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1)))
467 return err;
468 pci_fixup_device(pci_fixup_enable, dev);
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900469 dev->is_enabled = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 return 0;
471}
472
473/**
474 * pcibios_disable_device - disable arch specific PCI resources for device dev
475 * @dev: the PCI device to disable
476 *
477 * Disables architecture specific PCI resources for the device. This
478 * is the default implementation. Architecture implementations can
479 * override this.
480 */
481void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
482
483/**
484 * pci_disable_device - Disable PCI device after use
485 * @dev: PCI device to be disabled
486 *
487 * Signal to the system that the PCI device is not in use by the system
488 * anymore. This only involves disabling PCI bus-mastering, if active.
489 */
490void
491pci_disable_device(struct pci_dev *dev)
492{
493 u16 pci_command;
494
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
496 if (pci_command & PCI_COMMAND_MASTER) {
497 pci_command &= ~PCI_COMMAND_MASTER;
498 pci_write_config_word(dev, PCI_COMMAND, pci_command);
499 }
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900500 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501
502 pcibios_disable_device(dev);
Kenji Kaneshigeceb43742005-04-08 14:53:31 +0900503 dev->is_enabled = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504}
505
506/**
507 * pci_enable_wake - enable device to generate PME# when suspended
508 * @dev: - PCI device to operate on
509 * @state: - Current state of device.
510 * @enable: - Flag to enable or disable generation
511 *
512 * Set the bits in the device's PM Capabilities to generate PME# when
513 * the system is suspended.
514 *
515 * -EIO is returned if device doesn't have PM Capabilities.
516 * -EINVAL is returned if device supports it, but can't generate wake events.
517 * 0 if operation is successful.
518 *
519 */
520int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
521{
522 int pm;
523 u16 value;
524
525 /* find PCI PM capability in list */
526 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
527
528 /* If device doesn't support PM Capabilities, but request is to disable
529 * wake events, it's a nop; otherwise fail */
530 if (!pm)
531 return enable ? -EIO : 0;
532
533 /* Check device's ability to generate PME# */
534 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
535
536 value &= PCI_PM_CAP_PME_MASK;
537 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
538
539 /* Check if it can generate PME# from requested state. */
540 if (!value || !(value & (1 << state)))
541 return enable ? -EINVAL : 0;
542
543 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
544
545 /* Clear PME_Status by writing 1 to it and enable PME# */
546 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
547
548 if (!enable)
549 value &= ~PCI_PM_CTRL_PME_ENABLE;
550
551 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
552
553 return 0;
554}
555
556int
557pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
558{
559 u8 pin;
560
561 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
562 if (!pin)
563 return -1;
564 pin--;
565 while (dev->bus->self) {
566 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
567 dev = dev->bus->self;
568 }
569 *bridge = dev;
570 return pin;
571}
572
573/**
574 * pci_release_region - Release a PCI bar
575 * @pdev: PCI device whose resources were previously reserved by pci_request_region
576 * @bar: BAR to release
577 *
578 * Releases the PCI I/O and memory resources previously reserved by a
579 * successful call to pci_request_region. Call this function only
580 * after all use of the PCI regions has ceased.
581 */
582void pci_release_region(struct pci_dev *pdev, int bar)
583{
584 if (pci_resource_len(pdev, bar) == 0)
585 return;
586 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
587 release_region(pci_resource_start(pdev, bar),
588 pci_resource_len(pdev, bar));
589 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
590 release_mem_region(pci_resource_start(pdev, bar),
591 pci_resource_len(pdev, bar));
592}
593
594/**
595 * pci_request_region - Reserved PCI I/O and memory resource
596 * @pdev: PCI device whose resources are to be reserved
597 * @bar: BAR to be reserved
598 * @res_name: Name to be associated with resource.
599 *
600 * Mark the PCI region associated with PCI device @pdev BR @bar as
601 * being reserved by owner @res_name. Do not access any
602 * address inside the PCI regions unless this call returns
603 * successfully.
604 *
605 * Returns 0 on success, or %EBUSY on error. A warning
606 * message is also printed on failure.
607 */
608int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
609{
610 if (pci_resource_len(pdev, bar) == 0)
611 return 0;
612
613 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
614 if (!request_region(pci_resource_start(pdev, bar),
615 pci_resource_len(pdev, bar), res_name))
616 goto err_out;
617 }
618 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
619 if (!request_mem_region(pci_resource_start(pdev, bar),
620 pci_resource_len(pdev, bar), res_name))
621 goto err_out;
622 }
623
624 return 0;
625
626err_out:
627 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
628 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
629 bar + 1, /* PCI BAR # */
630 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
631 pci_name(pdev));
632 return -EBUSY;
633}
634
635
636/**
637 * pci_release_regions - Release reserved PCI I/O and memory resources
638 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
639 *
640 * Releases all PCI I/O and memory resources previously reserved by a
641 * successful call to pci_request_regions. Call this function only
642 * after all use of the PCI regions has ceased.
643 */
644
645void pci_release_regions(struct pci_dev *pdev)
646{
647 int i;
648
649 for (i = 0; i < 6; i++)
650 pci_release_region(pdev, i);
651}
652
653/**
654 * pci_request_regions - Reserved PCI I/O and memory resources
655 * @pdev: PCI device whose resources are to be reserved
656 * @res_name: Name to be associated with resource.
657 *
658 * Mark all PCI regions associated with PCI device @pdev as
659 * being reserved by owner @res_name. Do not access any
660 * address inside the PCI regions unless this call returns
661 * successfully.
662 *
663 * Returns 0 on success, or %EBUSY on error. A warning
664 * message is also printed on failure.
665 */
666int pci_request_regions(struct pci_dev *pdev, char *res_name)
667{
668 int i;
669
670 for (i = 0; i < 6; i++)
671 if(pci_request_region(pdev, i, res_name))
672 goto err_out;
673 return 0;
674
675err_out:
676 while(--i >= 0)
677 pci_release_region(pdev, i);
678
679 return -EBUSY;
680}
681
682/**
683 * pci_set_master - enables bus-mastering for device dev
684 * @dev: the PCI device to enable
685 *
686 * Enables bus-mastering on the device and calls pcibios_set_master()
687 * to do the needed arch specific settings.
688 */
689void
690pci_set_master(struct pci_dev *dev)
691{
692 u16 cmd;
693
694 pci_read_config_word(dev, PCI_COMMAND, &cmd);
695 if (! (cmd & PCI_COMMAND_MASTER)) {
696 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
697 cmd |= PCI_COMMAND_MASTER;
698 pci_write_config_word(dev, PCI_COMMAND, cmd);
699 }
700 dev->is_busmaster = 1;
701 pcibios_set_master(dev);
702}
703
704#ifndef HAVE_ARCH_PCI_MWI
705/* This can be overridden by arch code. */
706u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
707
708/**
709 * pci_generic_prep_mwi - helper function for pci_set_mwi
710 * @dev: the PCI device for which MWI is enabled
711 *
712 * Helper function for generic implementation of pcibios_prep_mwi
713 * function. Originally copied from drivers/net/acenic.c.
714 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
715 *
716 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
717 */
718static int
719pci_generic_prep_mwi(struct pci_dev *dev)
720{
721 u8 cacheline_size;
722
723 if (!pci_cache_line_size)
724 return -EINVAL; /* The system doesn't support MWI. */
725
726 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
727 equal to or multiple of the right value. */
728 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
729 if (cacheline_size >= pci_cache_line_size &&
730 (cacheline_size % pci_cache_line_size) == 0)
731 return 0;
732
733 /* Write the correct value. */
734 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
735 /* Read it back. */
736 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
737 if (cacheline_size == pci_cache_line_size)
738 return 0;
739
740 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
741 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
742
743 return -EINVAL;
744}
745#endif /* !HAVE_ARCH_PCI_MWI */
746
747/**
748 * pci_set_mwi - enables memory-write-invalidate PCI transaction
749 * @dev: the PCI device for which MWI is enabled
750 *
751 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
752 * and then calls @pcibios_set_mwi to do the needed arch specific
753 * operations or a generic mwi-prep function.
754 *
755 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
756 */
757int
758pci_set_mwi(struct pci_dev *dev)
759{
760 int rc;
761 u16 cmd;
762
763#ifdef HAVE_ARCH_PCI_MWI
764 rc = pcibios_prep_mwi(dev);
765#else
766 rc = pci_generic_prep_mwi(dev);
767#endif
768
769 if (rc)
770 return rc;
771
772 pci_read_config_word(dev, PCI_COMMAND, &cmd);
773 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
774 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
775 cmd |= PCI_COMMAND_INVALIDATE;
776 pci_write_config_word(dev, PCI_COMMAND, cmd);
777 }
778
779 return 0;
780}
781
782/**
783 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
784 * @dev: the PCI device to disable
785 *
786 * Disables PCI Memory-Write-Invalidate transaction on the device
787 */
788void
789pci_clear_mwi(struct pci_dev *dev)
790{
791 u16 cmd;
792
793 pci_read_config_word(dev, PCI_COMMAND, &cmd);
794 if (cmd & PCI_COMMAND_INVALIDATE) {
795 cmd &= ~PCI_COMMAND_INVALIDATE;
796 pci_write_config_word(dev, PCI_COMMAND, cmd);
797 }
798}
799
800#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
801/*
802 * These can be overridden by arch-specific implementations
803 */
804int
805pci_set_dma_mask(struct pci_dev *dev, u64 mask)
806{
807 if (!pci_dma_supported(dev, mask))
808 return -EIO;
809
810 dev->dma_mask = mask;
811
812 return 0;
813}
814
815int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
817{
818 if (!pci_dma_supported(dev, mask))
819 return -EIO;
820
821 dev->dev.coherent_dma_mask = mask;
822
823 return 0;
824}
825#endif
826
827static int __devinit pci_init(void)
828{
829 struct pci_dev *dev = NULL;
830
831 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
832 pci_fixup_device(pci_fixup_final, dev);
833 }
834 return 0;
835}
836
837static int __devinit pci_setup(char *str)
838{
839 while (str) {
840 char *k = strchr(str, ',');
841 if (k)
842 *k++ = 0;
843 if (*str && (str = pcibios_setup(str)) && *str) {
844 /* PCI layer options should be handled here */
845 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
846 }
847 str = k;
848 }
849 return 1;
850}
851
852device_initcall(pci_init);
853
854__setup("pci=", pci_setup);
855
856#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
857/* FIXME: Some boxes have multiple ISA bridges! */
858struct pci_dev *isa_bridge;
859EXPORT_SYMBOL(isa_bridge);
860#endif
861
John W. Linville064b53db2005-07-27 10:19:44 -0400862EXPORT_SYMBOL_GPL(pci_restore_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863EXPORT_SYMBOL(pci_enable_device_bars);
864EXPORT_SYMBOL(pci_enable_device);
865EXPORT_SYMBOL(pci_disable_device);
866EXPORT_SYMBOL(pci_max_busnr);
867EXPORT_SYMBOL(pci_bus_max_busnr);
868EXPORT_SYMBOL(pci_find_capability);
869EXPORT_SYMBOL(pci_bus_find_capability);
870EXPORT_SYMBOL(pci_release_regions);
871EXPORT_SYMBOL(pci_request_regions);
872EXPORT_SYMBOL(pci_release_region);
873EXPORT_SYMBOL(pci_request_region);
874EXPORT_SYMBOL(pci_set_master);
875EXPORT_SYMBOL(pci_set_mwi);
876EXPORT_SYMBOL(pci_clear_mwi);
877EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878EXPORT_SYMBOL(pci_set_consistent_dma_mask);
879EXPORT_SYMBOL(pci_assign_resource);
880EXPORT_SYMBOL(pci_find_parent_resource);
881
882EXPORT_SYMBOL(pci_set_power_state);
883EXPORT_SYMBOL(pci_save_state);
884EXPORT_SYMBOL(pci_restore_state);
885EXPORT_SYMBOL(pci_enable_wake);
886
887/* Quirk info */
888
889EXPORT_SYMBOL(isa_dma_bridge_buggy);
890EXPORT_SYMBOL(pci_pci_problems);