| Adrian Bunk | b00dc83 | 2008-05-19 16:52:27 -0700 | [diff] [blame] | 1 | /* |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * VISsave.S: Code for saving FPU register state for |
| 3 | * VIS routines. One should not call this directly, |
| 4 | * but use macros provided in <asm/visasm.h>. |
| 5 | * |
| 6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) |
| 7 | */ |
| 8 | |
| Sam Ravnborg | 73958c6 | 2015-08-07 20:34:12 +0200 | [diff] [blame] | 9 | #include <linux/linkage.h> |
| 10 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <asm/asi.h> |
| 12 | #include <asm/page.h> |
| 13 | #include <asm/ptrace.h> |
| 14 | #include <asm/visasm.h> |
| 15 | #include <asm/thread_info.h> |
| 16 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | /* On entry: %o5=current FPRS value, %g7 is callers address */ |
| 18 | /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */ |
| 19 | |
| 20 | /* Nothing special need be done here to handle pre-emption, this |
| 21 | * FPU save/restore mechanism is already preemption safe. |
| 22 | */ |
| Sam Ravnborg | 73958c6 | 2015-08-07 20:34:12 +0200 | [diff] [blame] | 23 | .text |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | .align 32 |
| Sam Ravnborg | 73958c6 | 2015-08-07 20:34:12 +0200 | [diff] [blame] | 25 | ENTRY(VISenter) |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | ldub [%g6 + TI_FPDEPTH], %g1 |
| 27 | brnz,a,pn %g1, 1f |
| 28 | cmp %g1, 1 |
| 29 | stb %g0, [%g6 + TI_FPSAVED] |
| 30 | stx %fsr, [%g6 + TI_XFSR] |
| 31 | 9: jmpl %g7 + %g0, %g0 |
| 32 | nop |
| 33 | 1: bne,pn %icc, 2f |
| 34 | |
| 35 | srl %g1, 1, %g1 |
| 36 | vis1: ldub [%g6 + TI_FPSAVED], %g3 |
| 37 | stx %fsr, [%g6 + TI_XFSR] |
| 38 | or %g3, %o5, %g3 |
| 39 | stb %g3, [%g6 + TI_FPSAVED] |
| 40 | rd %gsr, %g3 |
| 41 | clr %g1 |
| 42 | ba,pt %xcc, 3f |
| 43 | |
| 44 | stx %g3, [%g6 + TI_GSR] |
| 45 | 2: add %g6, %g1, %g3 |
| David S. Miller | 4492215 | 2015-08-06 19:13:25 -0700 | [diff] [blame] | 46 | mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5 |
| 47 | sll %g1, 3, %g1 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | stb %o5, [%g3 + TI_FPSAVED] |
| 49 | rd %gsr, %g2 |
| 50 | add %g6, %g1, %g3 |
| 51 | stx %g2, [%g3 + TI_GSR] |
| 52 | |
| 53 | add %g6, %g1, %g2 |
| 54 | stx %fsr, [%g2 + TI_XFSR] |
| 55 | sll %g1, 5, %g1 |
| 56 | 3: andcc %o5, FPRS_DL|FPRS_DU, %g0 |
| 57 | be,pn %icc, 9b |
| 58 | add %g6, TI_FPREGS, %g2 |
| 59 | andcc %o5, FPRS_DL, %g0 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | |
| 61 | be,pn %icc, 4f |
| 62 | add %g6, TI_FPREGS+0x40, %g3 |
| David S. Miller | ba639933 | 2005-10-07 13:30:49 -0700 | [diff] [blame] | 63 | membar #Sync |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | stda %f0, [%g2 + %g1] ASI_BLK_P |
| 65 | stda %f16, [%g3 + %g1] ASI_BLK_P |
| David S. Miller | ba639933 | 2005-10-07 13:30:49 -0700 | [diff] [blame] | 66 | membar #Sync |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | andcc %o5, FPRS_DU, %g0 |
| 68 | be,pn %icc, 5f |
| 69 | 4: add %g1, 128, %g1 |
| David S. Miller | ba639933 | 2005-10-07 13:30:49 -0700 | [diff] [blame] | 70 | membar #Sync |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | stda %f32, [%g2 + %g1] ASI_BLK_P |
| 72 | |
| 73 | stda %f48, [%g3 + %g1] ASI_BLK_P |
| 74 | 5: membar #Sync |
| David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 75 | ba,pt %xcc, 80f |
| 76 | nop |
| 77 | |
| 78 | .align 32 |
| 79 | 80: jmpl %g7 + %g0, %g0 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | nop |
| Sam Ravnborg | 73958c6 | 2015-08-07 20:34:12 +0200 | [diff] [blame] | 81 | ENDPROC(VISenter) |