Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * OMAP DMAengine support |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 8 | #include <linux/delay.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 9 | #include <linux/dmaengine.h> |
| 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/err.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/list.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/omap-dma.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/spinlock.h> |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 20 | #include <linux/of_dma.h> |
| 21 | #include <linux/of_device.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 22 | |
| 23 | #include "virt-dma.h" |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 24 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 25 | struct omap_dmadev { |
| 26 | struct dma_device ddev; |
| 27 | spinlock_t lock; |
| 28 | struct tasklet_struct task; |
| 29 | struct list_head pending; |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 30 | struct omap_system_dma_plat_info *plat; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | struct omap_chan { |
| 34 | struct virt_dma_chan vc; |
| 35 | struct list_head node; |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 36 | struct omap_system_dma_plat_info *plat; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 37 | |
| 38 | struct dma_slave_config cfg; |
| 39 | unsigned dma_sig; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 40 | bool cyclic; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 41 | bool paused; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 42 | |
| 43 | int dma_ch; |
| 44 | struct omap_desc *desc; |
| 45 | unsigned sgidx; |
| 46 | }; |
| 47 | |
| 48 | struct omap_sg { |
| 49 | dma_addr_t addr; |
| 50 | uint32_t en; /* number of elements (24-bit) */ |
| 51 | uint32_t fn; /* number of frames (16-bit) */ |
| 52 | }; |
| 53 | |
| 54 | struct omap_desc { |
| 55 | struct virt_dma_desc vd; |
| 56 | enum dma_transfer_direction dir; |
| 57 | dma_addr_t dev_addr; |
| 58 | |
Russell King | 7c836bc | 2012-06-18 16:45:19 +0100 | [diff] [blame] | 59 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 60 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 61 | uint32_t ccr; /* CCR value */ |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame^] | 62 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 63 | uint16_t cicr; /* CICR value */ |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 64 | uint32_t csdp; /* CSDP value */ |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 65 | |
| 66 | unsigned sglen; |
| 67 | struct omap_sg sg[0]; |
| 68 | }; |
| 69 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 70 | enum { |
| 71 | CCR_FS = BIT(5), |
| 72 | CCR_READ_PRIORITY = BIT(6), |
| 73 | CCR_ENABLE = BIT(7), |
| 74 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ |
| 75 | CCR_REPEAT = BIT(9), /* OMAP1 only */ |
| 76 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ |
| 77 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ |
| 78 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ |
| 79 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ |
| 80 | CCR_SRC_AMODE_CONSTANT = 0 << 12, |
| 81 | CCR_SRC_AMODE_POSTINC = 1 << 12, |
| 82 | CCR_SRC_AMODE_SGLIDX = 2 << 12, |
| 83 | CCR_SRC_AMODE_DBLIDX = 3 << 12, |
| 84 | CCR_DST_AMODE_CONSTANT = 0 << 14, |
| 85 | CCR_DST_AMODE_POSTINC = 1 << 14, |
| 86 | CCR_DST_AMODE_SGLIDX = 2 << 14, |
| 87 | CCR_DST_AMODE_DBLIDX = 3 << 14, |
| 88 | CCR_CONSTANT_FILL = BIT(16), |
| 89 | CCR_TRANSPARENT_COPY = BIT(17), |
| 90 | CCR_BS = BIT(18), |
| 91 | CCR_SUPERVISOR = BIT(22), |
| 92 | CCR_PREFETCH = BIT(23), |
| 93 | CCR_TRIGGER_SRC = BIT(24), |
| 94 | CCR_BUFFERING_DISABLE = BIT(25), |
| 95 | CCR_WRITE_PRIORITY = BIT(26), |
| 96 | CCR_SYNC_ELEMENT = 0, |
| 97 | CCR_SYNC_FRAME = CCR_FS, |
| 98 | CCR_SYNC_BLOCK = CCR_BS, |
| 99 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, |
| 100 | |
| 101 | CSDP_DATA_TYPE_8 = 0, |
| 102 | CSDP_DATA_TYPE_16 = 1, |
| 103 | CSDP_DATA_TYPE_32 = 2, |
| 104 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ |
| 105 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ |
| 106 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ |
| 107 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ |
| 108 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ |
| 109 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ |
| 110 | CSDP_SRC_PACKED = BIT(6), |
| 111 | CSDP_SRC_BURST_1 = 0 << 7, |
| 112 | CSDP_SRC_BURST_16 = 1 << 7, |
| 113 | CSDP_SRC_BURST_32 = 2 << 7, |
| 114 | CSDP_SRC_BURST_64 = 3 << 7, |
| 115 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ |
| 116 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ |
| 117 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ |
| 118 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ |
| 119 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ |
| 120 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ |
| 121 | CSDP_DST_PACKED = BIT(13), |
| 122 | CSDP_DST_BURST_1 = 0 << 14, |
| 123 | CSDP_DST_BURST_16 = 1 << 14, |
| 124 | CSDP_DST_BURST_32 = 2 << 14, |
| 125 | CSDP_DST_BURST_64 = 3 << 14, |
| 126 | |
| 127 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ |
| 128 | CICR_DROP_IE = BIT(1), |
| 129 | CICR_HALF_IE = BIT(2), |
| 130 | CICR_FRAME_IE = BIT(3), |
| 131 | CICR_LAST_IE = BIT(4), |
| 132 | CICR_BLOCK_IE = BIT(5), |
| 133 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ |
| 134 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ |
| 135 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ |
| 136 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ |
| 137 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ |
| 138 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ |
| 139 | |
| 140 | CLNK_CTRL_ENABLE_LNK = BIT(15), |
| 141 | }; |
| 142 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 143 | static const unsigned es_bytes[] = { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 144 | [CSDP_DATA_TYPE_8] = 1, |
| 145 | [CSDP_DATA_TYPE_16] = 2, |
| 146 | [CSDP_DATA_TYPE_32] = 4, |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 147 | }; |
| 148 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 149 | static struct of_dma_filter_info omap_dma_info = { |
| 150 | .filter_fn = omap_dma_filter_fn, |
| 151 | }; |
| 152 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 153 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
| 154 | { |
| 155 | return container_of(d, struct omap_dmadev, ddev); |
| 156 | } |
| 157 | |
| 158 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) |
| 159 | { |
| 160 | return container_of(c, struct omap_chan, vc.chan); |
| 161 | } |
| 162 | |
| 163 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) |
| 164 | { |
| 165 | return container_of(t, struct omap_desc, vd.tx); |
| 166 | } |
| 167 | |
| 168 | static void omap_dma_desc_free(struct virt_dma_desc *vd) |
| 169 | { |
| 170 | kfree(container_of(vd, struct omap_desc, vd)); |
| 171 | } |
| 172 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 173 | static void omap_dma_clear_csr(struct omap_chan *c) |
| 174 | { |
| 175 | if (dma_omap1()) |
| 176 | c->plat->dma_read(CSR, c->dma_ch); |
| 177 | else |
| 178 | c->plat->dma_write(~0, CSR, c->dma_ch); |
| 179 | } |
| 180 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 181 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
| 182 | { |
| 183 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 184 | uint32_t val; |
| 185 | |
| 186 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 187 | c->plat->dma_write(0, CPC, c->dma_ch); |
| 188 | else |
| 189 | c->plat->dma_write(0, CDAC, c->dma_ch); |
| 190 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 191 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 192 | |
| 193 | /* Enable interrupts */ |
| 194 | c->plat->dma_write(d->cicr, CICR, c->dma_ch); |
| 195 | |
| 196 | val = c->plat->dma_read(CCR, c->dma_ch); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 197 | val |= CCR_ENABLE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 198 | mb(); |
| 199 | c->plat->dma_write(val, CCR, c->dma_ch); |
| 200 | } |
| 201 | |
| 202 | static void omap_dma_stop(struct omap_chan *c) |
| 203 | { |
| 204 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 205 | uint32_t val; |
| 206 | |
| 207 | /* disable irq */ |
| 208 | c->plat->dma_write(0, CICR, c->dma_ch); |
| 209 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 210 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 211 | |
| 212 | val = c->plat->dma_read(CCR, c->dma_ch); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 213 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 214 | uint32_t sysconfig; |
| 215 | unsigned i; |
| 216 | |
| 217 | sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch); |
| 218 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
| 219 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); |
| 220 | c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch); |
| 221 | |
| 222 | val = c->plat->dma_read(CCR, c->dma_ch); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 223 | val &= ~CCR_ENABLE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 224 | c->plat->dma_write(val, CCR, c->dma_ch); |
| 225 | |
| 226 | /* Wait for sDMA FIFO to drain */ |
| 227 | for (i = 0; ; i++) { |
| 228 | val = c->plat->dma_read(CCR, c->dma_ch); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 229 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 230 | break; |
| 231 | |
| 232 | if (i > 100) |
| 233 | break; |
| 234 | |
| 235 | udelay(5); |
| 236 | } |
| 237 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 238 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 239 | dev_err(c->vc.chan.device->dev, |
| 240 | "DMA drain did not complete on lch %d\n", |
| 241 | c->dma_ch); |
| 242 | |
| 243 | c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch); |
| 244 | } else { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 245 | val &= ~CCR_ENABLE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 246 | c->plat->dma_write(val, CCR, c->dma_ch); |
| 247 | } |
| 248 | |
| 249 | mb(); |
| 250 | |
| 251 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { |
| 252 | val = c->plat->dma_read(CLNK_CTRL, c->dma_ch); |
| 253 | |
| 254 | if (dma_omap1()) |
| 255 | val |= 1 << 14; /* set the STOP_LNK bit */ |
| 256 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 257 | val &= ~CLNK_CTRL_ENABLE_LNK; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 258 | |
| 259 | c->plat->dma_write(val, CLNK_CTRL, c->dma_ch); |
| 260 | } |
| 261 | } |
| 262 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 263 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
| 264 | unsigned idx) |
| 265 | { |
| 266 | struct omap_sg *sg = d->sg + idx; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 267 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 268 | |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 269 | if (d->dir == DMA_DEV_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 270 | cxsa = CDSA; |
| 271 | cxei = CDEI; |
| 272 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 273 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 274 | cxsa = CSSA; |
| 275 | cxei = CSEI; |
| 276 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 277 | } |
| 278 | |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 279 | c->plat->dma_write(sg->addr, cxsa, c->dma_ch); |
| 280 | c->plat->dma_write(0, cxei, c->dma_ch); |
| 281 | c->plat->dma_write(0, cxfi, c->dma_ch); |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 282 | c->plat->dma_write(sg->en, CEN, c->dma_ch); |
| 283 | c->plat->dma_write(sg->fn, CFN, c->dma_ch); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 284 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 285 | omap_dma_start(c, d); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | static void omap_dma_start_desc(struct omap_chan *c) |
| 289 | { |
| 290 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); |
| 291 | struct omap_desc *d; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 292 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 293 | |
| 294 | if (!vd) { |
| 295 | c->desc = NULL; |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | list_del(&vd->node); |
| 300 | |
| 301 | c->desc = d = to_omap_dma_desc(&vd->tx); |
| 302 | c->sgidx = 0; |
| 303 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 304 | c->plat->dma_write(d->ccr, CCR, c->dma_ch); |
| 305 | if (dma_omap1()) |
| 306 | c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 307 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 308 | if (d->dir == DMA_DEV_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 309 | cxsa = CSSA; |
| 310 | cxei = CSEI; |
| 311 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 312 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 313 | cxsa = CDSA; |
| 314 | cxei = CDEI; |
| 315 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 316 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 317 | |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 318 | c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch); |
| 319 | c->plat->dma_write(0, cxei, c->dma_ch); |
| 320 | c->plat->dma_write(d->fi, cxfi, c->dma_ch); |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 321 | c->plat->dma_write(d->csdp, CSDP, c->dma_ch); |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame^] | 322 | c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch); |
Russell King | 913a2d0 | 2013-11-02 14:41:42 +0000 | [diff] [blame] | 323 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 324 | omap_dma_start_sg(c, d, 0); |
| 325 | } |
| 326 | |
| 327 | static void omap_dma_callback(int ch, u16 status, void *data) |
| 328 | { |
| 329 | struct omap_chan *c = data; |
| 330 | struct omap_desc *d; |
| 331 | unsigned long flags; |
| 332 | |
| 333 | spin_lock_irqsave(&c->vc.lock, flags); |
| 334 | d = c->desc; |
| 335 | if (d) { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 336 | if (!c->cyclic) { |
| 337 | if (++c->sgidx < d->sglen) { |
| 338 | omap_dma_start_sg(c, d, c->sgidx); |
| 339 | } else { |
| 340 | omap_dma_start_desc(c); |
| 341 | vchan_cookie_complete(&d->vd); |
| 342 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 343 | } else { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 344 | vchan_cyclic_callback(&d->vd); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 345 | } |
| 346 | } |
| 347 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 348 | } |
| 349 | |
| 350 | /* |
| 351 | * This callback schedules all pending channels. We could be more |
| 352 | * clever here by postponing allocation of the real DMA channels to |
| 353 | * this point, and freeing them when our virtual channel becomes idle. |
| 354 | * |
| 355 | * We would then need to deal with 'all channels in-use' |
| 356 | */ |
| 357 | static void omap_dma_sched(unsigned long data) |
| 358 | { |
| 359 | struct omap_dmadev *d = (struct omap_dmadev *)data; |
| 360 | LIST_HEAD(head); |
| 361 | |
| 362 | spin_lock_irq(&d->lock); |
| 363 | list_splice_tail_init(&d->pending, &head); |
| 364 | spin_unlock_irq(&d->lock); |
| 365 | |
| 366 | while (!list_empty(&head)) { |
| 367 | struct omap_chan *c = list_first_entry(&head, |
| 368 | struct omap_chan, node); |
| 369 | |
| 370 | spin_lock_irq(&c->vc.lock); |
| 371 | list_del_init(&c->node); |
| 372 | omap_dma_start_desc(c); |
| 373 | spin_unlock_irq(&c->vc.lock); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
| 378 | { |
| 379 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 380 | |
Ezequiel Garcia | 9e2f7d8 | 2013-12-19 22:22:29 -0300 | [diff] [blame] | 381 | dev_dbg(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 382 | |
| 383 | return omap_request_dma(c->dma_sig, "DMA engine", |
| 384 | omap_dma_callback, c, &c->dma_ch); |
| 385 | } |
| 386 | |
| 387 | static void omap_dma_free_chan_resources(struct dma_chan *chan) |
| 388 | { |
| 389 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 390 | |
| 391 | vchan_free_chan_resources(&c->vc); |
| 392 | omap_free_dma(c->dma_ch); |
| 393 | |
Ezequiel Garcia | 9e2f7d8 | 2013-12-19 22:22:29 -0300 | [diff] [blame] | 394 | dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 395 | } |
| 396 | |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 397 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
| 398 | { |
| 399 | return sg->en * sg->fn; |
| 400 | } |
| 401 | |
| 402 | static size_t omap_dma_desc_size(struct omap_desc *d) |
| 403 | { |
| 404 | unsigned i; |
| 405 | size_t size; |
| 406 | |
| 407 | for (size = i = 0; i < d->sglen; i++) |
| 408 | size += omap_dma_sg_size(&d->sg[i]); |
| 409 | |
| 410 | return size * es_bytes[d->es]; |
| 411 | } |
| 412 | |
| 413 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) |
| 414 | { |
| 415 | unsigned i; |
| 416 | size_t size, es_size = es_bytes[d->es]; |
| 417 | |
| 418 | for (size = i = 0; i < d->sglen; i++) { |
| 419 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; |
| 420 | |
| 421 | if (size) |
| 422 | size += this_size; |
| 423 | else if (addr >= d->sg[i].addr && |
| 424 | addr < d->sg[i].addr + this_size) |
| 425 | size += d->sg[i].addr + this_size - addr; |
| 426 | } |
| 427 | return size; |
| 428 | } |
| 429 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 430 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
| 431 | { |
| 432 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 433 | dma_addr_t addr; |
| 434 | |
| 435 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 436 | addr = c->plat->dma_read(CPC, c->dma_ch); |
| 437 | else |
| 438 | addr = c->plat->dma_read(CSAC, c->dma_ch); |
| 439 | |
| 440 | if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0) |
| 441 | addr = c->plat->dma_read(CSAC, c->dma_ch); |
| 442 | |
| 443 | if (!__dma_omap15xx(od->plat->dma_attr)) { |
| 444 | /* |
| 445 | * CDAC == 0 indicates that the DMA transfer on the channel has |
| 446 | * not been started (no data has been transferred so far). |
| 447 | * Return the programmed source start address in this case. |
| 448 | */ |
| 449 | if (c->plat->dma_read(CDAC, c->dma_ch)) |
| 450 | addr = c->plat->dma_read(CSAC, c->dma_ch); |
| 451 | else |
| 452 | addr = c->plat->dma_read(CSSA, c->dma_ch); |
| 453 | } |
| 454 | |
| 455 | if (dma_omap1()) |
| 456 | addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000; |
| 457 | |
| 458 | return addr; |
| 459 | } |
| 460 | |
| 461 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) |
| 462 | { |
| 463 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 464 | dma_addr_t addr; |
| 465 | |
| 466 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 467 | addr = c->plat->dma_read(CPC, c->dma_ch); |
| 468 | else |
| 469 | addr = c->plat->dma_read(CDAC, c->dma_ch); |
| 470 | |
| 471 | /* |
| 472 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is |
| 473 | * read before the DMA controller finished disabling the channel. |
| 474 | */ |
| 475 | if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) { |
| 476 | addr = c->plat->dma_read(CDAC, c->dma_ch); |
| 477 | /* |
| 478 | * CDAC == 0 indicates that the DMA transfer on the channel has |
| 479 | * not been started (no data has been transferred so far). |
| 480 | * Return the programmed destination start address in this case. |
| 481 | */ |
| 482 | if (addr == 0) |
| 483 | addr = c->plat->dma_read(CDSA, c->dma_ch); |
| 484 | } |
| 485 | |
| 486 | if (dma_omap1()) |
| 487 | addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000; |
| 488 | |
| 489 | return addr; |
| 490 | } |
| 491 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 492 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
| 493 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 494 | { |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 495 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 496 | struct virt_dma_desc *vd; |
| 497 | enum dma_status ret; |
| 498 | unsigned long flags; |
| 499 | |
| 500 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 7cce508 | 2013-10-16 20:51:54 +0530 | [diff] [blame] | 501 | if (ret == DMA_COMPLETE || !txstate) |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 502 | return ret; |
| 503 | |
| 504 | spin_lock_irqsave(&c->vc.lock, flags); |
| 505 | vd = vchan_find_desc(&c->vc, cookie); |
| 506 | if (vd) { |
| 507 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); |
| 508 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { |
| 509 | struct omap_desc *d = c->desc; |
| 510 | dma_addr_t pos; |
| 511 | |
| 512 | if (d->dir == DMA_MEM_TO_DEV) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 513 | pos = omap_dma_get_src_pos(c); |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 514 | else if (d->dir == DMA_DEV_TO_MEM) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 515 | pos = omap_dma_get_dst_pos(c); |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 516 | else |
| 517 | pos = 0; |
| 518 | |
| 519 | txstate->residue = omap_dma_desc_size_pos(d, pos); |
| 520 | } else { |
| 521 | txstate->residue = 0; |
| 522 | } |
| 523 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 524 | |
| 525 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | static void omap_dma_issue_pending(struct dma_chan *chan) |
| 529 | { |
| 530 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 531 | unsigned long flags; |
| 532 | |
| 533 | spin_lock_irqsave(&c->vc.lock, flags); |
| 534 | if (vchan_issue_pending(&c->vc) && !c->desc) { |
Peter Ujfalusi | 7650246 | 2013-04-09 16:33:06 +0200 | [diff] [blame] | 535 | /* |
| 536 | * c->cyclic is used only by audio and in this case the DMA need |
| 537 | * to be started without delay. |
| 538 | */ |
| 539 | if (!c->cyclic) { |
| 540 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); |
| 541 | spin_lock(&d->lock); |
| 542 | if (list_empty(&c->node)) |
| 543 | list_add_tail(&c->node, &d->pending); |
| 544 | spin_unlock(&d->lock); |
| 545 | tasklet_schedule(&d->task); |
| 546 | } else { |
| 547 | omap_dma_start_desc(c); |
| 548 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 549 | } |
| 550 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 551 | } |
| 552 | |
| 553 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( |
| 554 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, |
| 555 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) |
| 556 | { |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 557 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 558 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 559 | enum dma_slave_buswidth dev_width; |
| 560 | struct scatterlist *sgent; |
| 561 | struct omap_desc *d; |
| 562 | dma_addr_t dev_addr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 563 | unsigned i, j = 0, es, en, frame_bytes; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 564 | u32 burst; |
| 565 | |
| 566 | if (dir == DMA_DEV_TO_MEM) { |
| 567 | dev_addr = c->cfg.src_addr; |
| 568 | dev_width = c->cfg.src_addr_width; |
| 569 | burst = c->cfg.src_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 570 | } else if (dir == DMA_MEM_TO_DEV) { |
| 571 | dev_addr = c->cfg.dst_addr; |
| 572 | dev_width = c->cfg.dst_addr_width; |
| 573 | burst = c->cfg.dst_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 574 | } else { |
| 575 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 576 | return NULL; |
| 577 | } |
| 578 | |
| 579 | /* Bus width translates to the element size (ES) */ |
| 580 | switch (dev_width) { |
| 581 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 582 | es = CSDP_DATA_TYPE_8; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 583 | break; |
| 584 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 585 | es = CSDP_DATA_TYPE_16; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 586 | break; |
| 587 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 588 | es = CSDP_DATA_TYPE_32; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 589 | break; |
| 590 | default: /* not reached */ |
| 591 | return NULL; |
| 592 | } |
| 593 | |
| 594 | /* Now allocate and setup the descriptor. */ |
| 595 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); |
| 596 | if (!d) |
| 597 | return NULL; |
| 598 | |
| 599 | d->dir = dir; |
| 600 | d->dev_addr = dev_addr; |
| 601 | d->es = es; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 602 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 603 | d->ccr = CCR_SYNC_FRAME; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 604 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 605 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 606 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 607 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 608 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 609 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 610 | d->csdp = es; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 611 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 612 | if (dma_omap1()) { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 613 | if (__dma_omap16xx(od->plat->dma_attr)) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 614 | d->ccr |= CCR_OMAP31_DISABLE; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 615 | /* Duplicate what plat-omap/dma.c does */ |
| 616 | d->ccr |= c->dma_ch + 1; |
| 617 | } else { |
| 618 | d->ccr |= c->dma_sig & 0x1f; |
| 619 | } |
| 620 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 621 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 622 | |
| 623 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 624 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 625 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 626 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 627 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 628 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
| 629 | d->ccr |= c->dma_sig & 0x1f; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 630 | |
| 631 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 632 | d->ccr |= CCR_TRIGGER_SRC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 633 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 634 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 635 | } |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 636 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
| 637 | d->ccr |= CCR_BUFFERING_DISABLE; |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame^] | 638 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
| 639 | d->clnk_ctrl = c->dma_ch; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 640 | |
| 641 | /* |
| 642 | * Build our scatterlist entries: each contains the address, |
| 643 | * the number of elements (EN) in each frame, and the number of |
| 644 | * frames (FN). Number of bytes for this entry = ES * EN * FN. |
| 645 | * |
| 646 | * Burst size translates to number of elements with frame sync. |
| 647 | * Note: DMA engine defines burst to be the number of dev-width |
| 648 | * transfers. |
| 649 | */ |
| 650 | en = burst; |
| 651 | frame_bytes = es_bytes[es] * en; |
| 652 | for_each_sg(sgl, sgent, sglen, i) { |
| 653 | d->sg[j].addr = sg_dma_address(sgent); |
| 654 | d->sg[j].en = en; |
| 655 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; |
| 656 | j++; |
| 657 | } |
| 658 | |
| 659 | d->sglen = j; |
| 660 | |
| 661 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); |
| 662 | } |
| 663 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 664 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
| 665 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 666 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
| 667 | void *context) |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 668 | { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 669 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 670 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 671 | enum dma_slave_buswidth dev_width; |
| 672 | struct omap_desc *d; |
| 673 | dma_addr_t dev_addr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 674 | unsigned es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 675 | u32 burst; |
| 676 | |
| 677 | if (dir == DMA_DEV_TO_MEM) { |
| 678 | dev_addr = c->cfg.src_addr; |
| 679 | dev_width = c->cfg.src_addr_width; |
| 680 | burst = c->cfg.src_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 681 | } else if (dir == DMA_MEM_TO_DEV) { |
| 682 | dev_addr = c->cfg.dst_addr; |
| 683 | dev_width = c->cfg.dst_addr_width; |
| 684 | burst = c->cfg.dst_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 685 | } else { |
| 686 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 687 | return NULL; |
| 688 | } |
| 689 | |
| 690 | /* Bus width translates to the element size (ES) */ |
| 691 | switch (dev_width) { |
| 692 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 693 | es = CSDP_DATA_TYPE_8; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 694 | break; |
| 695 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 696 | es = CSDP_DATA_TYPE_16; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 697 | break; |
| 698 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 699 | es = CSDP_DATA_TYPE_32; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 700 | break; |
| 701 | default: /* not reached */ |
| 702 | return NULL; |
| 703 | } |
| 704 | |
| 705 | /* Now allocate and setup the descriptor. */ |
| 706 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 707 | if (!d) |
| 708 | return NULL; |
| 709 | |
| 710 | d->dir = dir; |
| 711 | d->dev_addr = dev_addr; |
| 712 | d->fi = burst; |
| 713 | d->es = es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 714 | d->sg[0].addr = buf_addr; |
| 715 | d->sg[0].en = period_len / es_bytes[es]; |
| 716 | d->sg[0].fn = buf_len / period_len; |
| 717 | d->sglen = 1; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 718 | |
| 719 | d->ccr = 0; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 720 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 721 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 722 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 723 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 724 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 725 | d->cicr = CICR_DROP_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 726 | if (flags & DMA_PREP_INTERRUPT) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 727 | d->cicr |= CICR_FRAME_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 728 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 729 | d->csdp = es; |
| 730 | |
| 731 | if (dma_omap1()) { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 732 | if (__dma_omap16xx(od->plat->dma_attr)) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 733 | d->ccr |= CCR_OMAP31_DISABLE; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 734 | /* Duplicate what plat-omap/dma.c does */ |
| 735 | d->ccr |= c->dma_ch + 1; |
| 736 | } else { |
| 737 | d->ccr |= c->dma_sig & 0x1f; |
| 738 | } |
| 739 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 740 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 741 | |
| 742 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 743 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 744 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 745 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 746 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 747 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
| 748 | d->ccr |= c->dma_sig & 0x1f; |
| 749 | |
| 750 | if (burst) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 751 | d->ccr |= CCR_SYNC_PACKET; |
| 752 | else |
| 753 | d->ccr |= CCR_SYNC_ELEMENT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 754 | |
| 755 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 756 | d->ccr |= CCR_TRIGGER_SRC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 757 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 758 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 759 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 760 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 761 | } |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 762 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
| 763 | d->ccr |= CCR_BUFFERING_DISABLE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 764 | |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame^] | 765 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 766 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; |
| 767 | else |
| 768 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; |
| 769 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 770 | c->cyclic = true; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 771 | |
Peter Ujfalusi | 2dde5b9 | 2012-09-14 15:05:48 +0300 | [diff] [blame] | 772 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 773 | } |
| 774 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 775 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
| 776 | { |
| 777 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 778 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
| 779 | return -EINVAL; |
| 780 | |
| 781 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); |
| 782 | |
| 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static int omap_dma_terminate_all(struct omap_chan *c) |
| 787 | { |
| 788 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); |
| 789 | unsigned long flags; |
| 790 | LIST_HEAD(head); |
| 791 | |
| 792 | spin_lock_irqsave(&c->vc.lock, flags); |
| 793 | |
| 794 | /* Prevent this channel being scheduled */ |
| 795 | spin_lock(&d->lock); |
| 796 | list_del_init(&c->node); |
| 797 | spin_unlock(&d->lock); |
| 798 | |
| 799 | /* |
| 800 | * Stop DMA activity: we assume the callback will not be called |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 801 | * after omap_dma_stop() returns (even if it does, it will see |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 802 | * c->desc is NULL and exit.) |
| 803 | */ |
| 804 | if (c->desc) { |
| 805 | c->desc = NULL; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 806 | /* Avoid stopping the dma twice */ |
| 807 | if (!c->paused) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 808 | omap_dma_stop(c); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 809 | } |
| 810 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 811 | if (c->cyclic) { |
| 812 | c->cyclic = false; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 813 | c->paused = false; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 814 | } |
| 815 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 816 | vchan_get_all_descriptors(&c->vc, &head); |
| 817 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 818 | vchan_dma_desc_free_list(&c->vc, &head); |
| 819 | |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | static int omap_dma_pause(struct omap_chan *c) |
| 824 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 825 | /* Pause/Resume only allowed with cyclic mode */ |
| 826 | if (!c->cyclic) |
| 827 | return -EINVAL; |
| 828 | |
| 829 | if (!c->paused) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 830 | omap_dma_stop(c); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 831 | c->paused = true; |
| 832 | } |
| 833 | |
| 834 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | static int omap_dma_resume(struct omap_chan *c) |
| 838 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 839 | /* Pause/Resume only allowed with cyclic mode */ |
| 840 | if (!c->cyclic) |
| 841 | return -EINVAL; |
| 842 | |
| 843 | if (c->paused) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 844 | omap_dma_start(c, c->desc); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 845 | c->paused = false; |
| 846 | } |
| 847 | |
| 848 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 849 | } |
| 850 | |
| 851 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 852 | unsigned long arg) |
| 853 | { |
| 854 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 855 | int ret; |
| 856 | |
| 857 | switch (cmd) { |
| 858 | case DMA_SLAVE_CONFIG: |
| 859 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); |
| 860 | break; |
| 861 | |
| 862 | case DMA_TERMINATE_ALL: |
| 863 | ret = omap_dma_terminate_all(c); |
| 864 | break; |
| 865 | |
| 866 | case DMA_PAUSE: |
| 867 | ret = omap_dma_pause(c); |
| 868 | break; |
| 869 | |
| 870 | case DMA_RESUME: |
| 871 | ret = omap_dma_resume(c); |
| 872 | break; |
| 873 | |
| 874 | default: |
| 875 | ret = -ENXIO; |
| 876 | break; |
| 877 | } |
| 878 | |
| 879 | return ret; |
| 880 | } |
| 881 | |
| 882 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) |
| 883 | { |
| 884 | struct omap_chan *c; |
| 885 | |
| 886 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
| 887 | if (!c) |
| 888 | return -ENOMEM; |
| 889 | |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 890 | c->plat = od->plat; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 891 | c->dma_sig = dma_sig; |
| 892 | c->vc.desc_free = omap_dma_desc_free; |
| 893 | vchan_init(&c->vc, &od->ddev); |
| 894 | INIT_LIST_HEAD(&c->node); |
| 895 | |
| 896 | od->ddev.chancnt++; |
| 897 | |
| 898 | return 0; |
| 899 | } |
| 900 | |
| 901 | static void omap_dma_free(struct omap_dmadev *od) |
| 902 | { |
| 903 | tasklet_kill(&od->task); |
| 904 | while (!list_empty(&od->ddev.channels)) { |
| 905 | struct omap_chan *c = list_first_entry(&od->ddev.channels, |
| 906 | struct omap_chan, vc.chan.device_node); |
| 907 | |
| 908 | list_del(&c->vc.chan.device_node); |
| 909 | tasklet_kill(&c->vc.task); |
| 910 | kfree(c); |
| 911 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | static int omap_dma_probe(struct platform_device *pdev) |
| 915 | { |
| 916 | struct omap_dmadev *od; |
| 917 | int rc, i; |
| 918 | |
Russell King | 104fce7 | 2013-11-02 12:58:29 +0000 | [diff] [blame] | 919 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 920 | if (!od) |
| 921 | return -ENOMEM; |
| 922 | |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 923 | od->plat = omap_get_plat_info(); |
| 924 | if (!od->plat) |
| 925 | return -EPROBE_DEFER; |
| 926 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 927 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 928 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 929 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
| 930 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; |
| 931 | od->ddev.device_tx_status = omap_dma_tx_status; |
| 932 | od->ddev.device_issue_pending = omap_dma_issue_pending; |
| 933 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 934 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 935 | od->ddev.device_control = omap_dma_control; |
| 936 | od->ddev.dev = &pdev->dev; |
| 937 | INIT_LIST_HEAD(&od->ddev.channels); |
| 938 | INIT_LIST_HEAD(&od->pending); |
| 939 | spin_lock_init(&od->lock); |
| 940 | |
| 941 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); |
| 942 | |
| 943 | for (i = 0; i < 127; i++) { |
| 944 | rc = omap_dma_chan_init(od, i); |
| 945 | if (rc) { |
| 946 | omap_dma_free(od); |
| 947 | return rc; |
| 948 | } |
| 949 | } |
| 950 | |
| 951 | rc = dma_async_device_register(&od->ddev); |
| 952 | if (rc) { |
| 953 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", |
| 954 | rc); |
| 955 | omap_dma_free(od); |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 956 | return rc; |
| 957 | } |
| 958 | |
| 959 | platform_set_drvdata(pdev, od); |
| 960 | |
| 961 | if (pdev->dev.of_node) { |
| 962 | omap_dma_info.dma_cap = od->ddev.cap_mask; |
| 963 | |
| 964 | /* Device-tree DMA controller registration */ |
| 965 | rc = of_dma_controller_register(pdev->dev.of_node, |
| 966 | of_dma_simple_xlate, &omap_dma_info); |
| 967 | if (rc) { |
| 968 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); |
| 969 | dma_async_device_unregister(&od->ddev); |
| 970 | omap_dma_free(od); |
| 971 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 972 | } |
| 973 | |
| 974 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); |
| 975 | |
| 976 | return rc; |
| 977 | } |
| 978 | |
| 979 | static int omap_dma_remove(struct platform_device *pdev) |
| 980 | { |
| 981 | struct omap_dmadev *od = platform_get_drvdata(pdev); |
| 982 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 983 | if (pdev->dev.of_node) |
| 984 | of_dma_controller_free(pdev->dev.of_node); |
| 985 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 986 | dma_async_device_unregister(&od->ddev); |
| 987 | omap_dma_free(od); |
| 988 | |
| 989 | return 0; |
| 990 | } |
| 991 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 992 | static const struct of_device_id omap_dma_match[] = { |
| 993 | { .compatible = "ti,omap2420-sdma", }, |
| 994 | { .compatible = "ti,omap2430-sdma", }, |
| 995 | { .compatible = "ti,omap3430-sdma", }, |
| 996 | { .compatible = "ti,omap3630-sdma", }, |
| 997 | { .compatible = "ti,omap4430-sdma", }, |
| 998 | {}, |
| 999 | }; |
| 1000 | MODULE_DEVICE_TABLE(of, omap_dma_match); |
| 1001 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1002 | static struct platform_driver omap_dma_driver = { |
| 1003 | .probe = omap_dma_probe, |
| 1004 | .remove = omap_dma_remove, |
| 1005 | .driver = { |
| 1006 | .name = "omap-dma-engine", |
| 1007 | .owner = THIS_MODULE, |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1008 | .of_match_table = of_match_ptr(omap_dma_match), |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1009 | }, |
| 1010 | }; |
| 1011 | |
| 1012 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) |
| 1013 | { |
| 1014 | if (chan->device->dev->driver == &omap_dma_driver.driver) { |
| 1015 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1016 | unsigned req = *(unsigned *)param; |
| 1017 | |
| 1018 | return req == c->dma_sig; |
| 1019 | } |
| 1020 | return false; |
| 1021 | } |
| 1022 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); |
| 1023 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1024 | static int omap_dma_init(void) |
| 1025 | { |
Tony Lindgren | be1f948 | 2013-01-11 11:24:19 -0800 | [diff] [blame] | 1026 | return platform_driver_register(&omap_dma_driver); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1027 | } |
| 1028 | subsys_initcall(omap_dma_init); |
| 1029 | |
| 1030 | static void __exit omap_dma_exit(void) |
| 1031 | { |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1032 | platform_driver_unregister(&omap_dma_driver); |
| 1033 | } |
| 1034 | module_exit(omap_dma_exit); |
| 1035 | |
| 1036 | MODULE_AUTHOR("Russell King"); |
| 1037 | MODULE_LICENSE("GPL"); |