Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 27 | #include <linux/module.h> |
| 28 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 30 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 31 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 32 | #include "drmP.h" |
| 33 | #include "intel_drv.h" |
| 34 | #include "i915_drm.h" |
| 35 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 36 | #include "i915_trace.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 37 | #include "drm_dp_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | |
| 39 | #include "drm_crtc_helper.h" |
| 40 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 41 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 42 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 44 | static void intel_update_watermarks(struct drm_device *dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 46 | |
| 47 | typedef struct { |
| 48 | /* given values */ |
| 49 | int n; |
| 50 | int m1, m2; |
| 51 | int p1, p2; |
| 52 | /* derived values */ |
| 53 | int dot; |
| 54 | int vco; |
| 55 | int m; |
| 56 | int p; |
| 57 | } intel_clock_t; |
| 58 | |
| 59 | typedef struct { |
| 60 | int min, max; |
| 61 | } intel_range_t; |
| 62 | |
| 63 | typedef struct { |
| 64 | int dot_limit; |
| 65 | int p2_slow, p2_fast; |
| 66 | } intel_p2_t; |
| 67 | |
| 68 | #define INTEL_P2_NUM 2 |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 69 | typedef struct intel_limit intel_limit_t; |
| 70 | struct intel_limit { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 71 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 72 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 73 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
| 74 | int, int, intel_clock_t *); |
| 75 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | |
| 77 | #define I8XX_DOT_MIN 25000 |
| 78 | #define I8XX_DOT_MAX 350000 |
| 79 | #define I8XX_VCO_MIN 930000 |
| 80 | #define I8XX_VCO_MAX 1400000 |
| 81 | #define I8XX_N_MIN 3 |
| 82 | #define I8XX_N_MAX 16 |
| 83 | #define I8XX_M_MIN 96 |
| 84 | #define I8XX_M_MAX 140 |
| 85 | #define I8XX_M1_MIN 18 |
| 86 | #define I8XX_M1_MAX 26 |
| 87 | #define I8XX_M2_MIN 6 |
| 88 | #define I8XX_M2_MAX 16 |
| 89 | #define I8XX_P_MIN 4 |
| 90 | #define I8XX_P_MAX 128 |
| 91 | #define I8XX_P1_MIN 2 |
| 92 | #define I8XX_P1_MAX 33 |
| 93 | #define I8XX_P1_LVDS_MIN 1 |
| 94 | #define I8XX_P1_LVDS_MAX 6 |
| 95 | #define I8XX_P2_SLOW 4 |
| 96 | #define I8XX_P2_FAST 2 |
| 97 | #define I8XX_P2_LVDS_SLOW 14 |
ling.ma@intel.com | 0c2e395 | 2009-07-17 11:44:30 +0800 | [diff] [blame] | 98 | #define I8XX_P2_LVDS_FAST 7 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 99 | #define I8XX_P2_SLOW_LIMIT 165000 |
| 100 | |
| 101 | #define I9XX_DOT_MIN 20000 |
| 102 | #define I9XX_DOT_MAX 400000 |
| 103 | #define I9XX_VCO_MIN 1400000 |
| 104 | #define I9XX_VCO_MAX 2800000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 105 | #define PINEVIEW_VCO_MIN 1700000 |
| 106 | #define PINEVIEW_VCO_MAX 3500000 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 107 | #define I9XX_N_MIN 1 |
| 108 | #define I9XX_N_MAX 6 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 109 | /* Pineview's Ncounter is a ring counter */ |
| 110 | #define PINEVIEW_N_MIN 3 |
| 111 | #define PINEVIEW_N_MAX 6 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 112 | #define I9XX_M_MIN 70 |
| 113 | #define I9XX_M_MAX 120 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 114 | #define PINEVIEW_M_MIN 2 |
| 115 | #define PINEVIEW_M_MAX 256 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 116 | #define I9XX_M1_MIN 10 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 117 | #define I9XX_M1_MAX 22 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 118 | #define I9XX_M2_MIN 5 |
| 119 | #define I9XX_M2_MAX 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 120 | /* Pineview M1 is reserved, and must be 0 */ |
| 121 | #define PINEVIEW_M1_MIN 0 |
| 122 | #define PINEVIEW_M1_MAX 0 |
| 123 | #define PINEVIEW_M2_MIN 0 |
| 124 | #define PINEVIEW_M2_MAX 254 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 125 | #define I9XX_P_SDVO_DAC_MIN 5 |
| 126 | #define I9XX_P_SDVO_DAC_MAX 80 |
| 127 | #define I9XX_P_LVDS_MIN 7 |
| 128 | #define I9XX_P_LVDS_MAX 98 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 129 | #define PINEVIEW_P_LVDS_MIN 7 |
| 130 | #define PINEVIEW_P_LVDS_MAX 112 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 131 | #define I9XX_P1_MIN 1 |
| 132 | #define I9XX_P1_MAX 8 |
| 133 | #define I9XX_P2_SDVO_DAC_SLOW 10 |
| 134 | #define I9XX_P2_SDVO_DAC_FAST 5 |
| 135 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 |
| 136 | #define I9XX_P2_LVDS_SLOW 14 |
| 137 | #define I9XX_P2_LVDS_FAST 7 |
| 138 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 |
| 139 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 140 | /*The parameter is for SDVO on G4x platform*/ |
| 141 | #define G4X_DOT_SDVO_MIN 25000 |
| 142 | #define G4X_DOT_SDVO_MAX 270000 |
| 143 | #define G4X_VCO_MIN 1750000 |
| 144 | #define G4X_VCO_MAX 3500000 |
| 145 | #define G4X_N_SDVO_MIN 1 |
| 146 | #define G4X_N_SDVO_MAX 4 |
| 147 | #define G4X_M_SDVO_MIN 104 |
| 148 | #define G4X_M_SDVO_MAX 138 |
| 149 | #define G4X_M1_SDVO_MIN 17 |
| 150 | #define G4X_M1_SDVO_MAX 23 |
| 151 | #define G4X_M2_SDVO_MIN 5 |
| 152 | #define G4X_M2_SDVO_MAX 11 |
| 153 | #define G4X_P_SDVO_MIN 10 |
| 154 | #define G4X_P_SDVO_MAX 30 |
| 155 | #define G4X_P1_SDVO_MIN 1 |
| 156 | #define G4X_P1_SDVO_MAX 3 |
| 157 | #define G4X_P2_SDVO_SLOW 10 |
| 158 | #define G4X_P2_SDVO_FAST 10 |
| 159 | #define G4X_P2_SDVO_LIMIT 270000 |
| 160 | |
| 161 | /*The parameter is for HDMI_DAC on G4x platform*/ |
| 162 | #define G4X_DOT_HDMI_DAC_MIN 22000 |
| 163 | #define G4X_DOT_HDMI_DAC_MAX 400000 |
| 164 | #define G4X_N_HDMI_DAC_MIN 1 |
| 165 | #define G4X_N_HDMI_DAC_MAX 4 |
| 166 | #define G4X_M_HDMI_DAC_MIN 104 |
| 167 | #define G4X_M_HDMI_DAC_MAX 138 |
| 168 | #define G4X_M1_HDMI_DAC_MIN 16 |
| 169 | #define G4X_M1_HDMI_DAC_MAX 23 |
| 170 | #define G4X_M2_HDMI_DAC_MIN 5 |
| 171 | #define G4X_M2_HDMI_DAC_MAX 11 |
| 172 | #define G4X_P_HDMI_DAC_MIN 5 |
| 173 | #define G4X_P_HDMI_DAC_MAX 80 |
| 174 | #define G4X_P1_HDMI_DAC_MIN 1 |
| 175 | #define G4X_P1_HDMI_DAC_MAX 8 |
| 176 | #define G4X_P2_HDMI_DAC_SLOW 10 |
| 177 | #define G4X_P2_HDMI_DAC_FAST 5 |
| 178 | #define G4X_P2_HDMI_DAC_LIMIT 165000 |
| 179 | |
| 180 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ |
| 181 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 |
| 182 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 |
| 183 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 |
| 184 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 |
| 185 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 |
| 186 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 |
| 187 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 |
| 188 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 |
| 189 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 |
| 190 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 |
| 191 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 |
| 192 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 |
| 193 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 |
| 194 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 |
| 195 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 |
| 196 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 |
| 197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 |
| 198 | |
| 199 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ |
| 200 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 |
| 201 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 |
| 202 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 |
| 203 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 |
| 204 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 |
| 205 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 |
| 206 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 |
| 207 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 |
| 208 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 |
| 209 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 |
| 210 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 |
| 211 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 |
| 212 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 |
| 213 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 |
| 214 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 |
| 215 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 |
| 216 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 |
| 217 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 218 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
| 219 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 |
| 220 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 |
| 221 | #define G4X_N_DISPLAY_PORT_MIN 1 |
| 222 | #define G4X_N_DISPLAY_PORT_MAX 2 |
| 223 | #define G4X_M_DISPLAY_PORT_MIN 97 |
| 224 | #define G4X_M_DISPLAY_PORT_MAX 108 |
| 225 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 |
| 226 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 |
| 227 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 |
| 228 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 |
| 229 | #define G4X_P_DISPLAY_PORT_MIN 10 |
| 230 | #define G4X_P_DISPLAY_PORT_MAX 20 |
| 231 | #define G4X_P1_DISPLAY_PORT_MIN 1 |
| 232 | #define G4X_P1_DISPLAY_PORT_MAX 2 |
| 233 | #define G4X_P2_DISPLAY_PORT_SLOW 10 |
| 234 | #define G4X_P2_DISPLAY_PORT_FAST 10 |
| 235 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 |
| 236 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 237 | /* Ironlake / Sandybridge */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 238 | /* as we calculate clock using (register_value + 2) for |
| 239 | N/M1/M2, so here the range value for them is (actual_value-2). |
| 240 | */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 241 | #define IRONLAKE_DOT_MIN 25000 |
| 242 | #define IRONLAKE_DOT_MAX 350000 |
| 243 | #define IRONLAKE_VCO_MIN 1760000 |
| 244 | #define IRONLAKE_VCO_MAX 3510000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 245 | #define IRONLAKE_M1_MIN 12 |
Zhao Yakui | a59e385 | 2010-01-06 22:05:57 +0800 | [diff] [blame] | 246 | #define IRONLAKE_M1_MAX 22 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 247 | #define IRONLAKE_M2_MIN 5 |
| 248 | #define IRONLAKE_M2_MAX 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 249 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 250 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 251 | /* We have parameter ranges for different type of outputs. */ |
| 252 | |
| 253 | /* DAC & HDMI Refclk 120Mhz */ |
| 254 | #define IRONLAKE_DAC_N_MIN 1 |
| 255 | #define IRONLAKE_DAC_N_MAX 5 |
| 256 | #define IRONLAKE_DAC_M_MIN 79 |
| 257 | #define IRONLAKE_DAC_M_MAX 127 |
| 258 | #define IRONLAKE_DAC_P_MIN 5 |
| 259 | #define IRONLAKE_DAC_P_MAX 80 |
| 260 | #define IRONLAKE_DAC_P1_MIN 1 |
| 261 | #define IRONLAKE_DAC_P1_MAX 8 |
| 262 | #define IRONLAKE_DAC_P2_SLOW 10 |
| 263 | #define IRONLAKE_DAC_P2_FAST 5 |
| 264 | |
| 265 | /* LVDS single-channel 120Mhz refclk */ |
| 266 | #define IRONLAKE_LVDS_S_N_MIN 1 |
| 267 | #define IRONLAKE_LVDS_S_N_MAX 3 |
| 268 | #define IRONLAKE_LVDS_S_M_MIN 79 |
| 269 | #define IRONLAKE_LVDS_S_M_MAX 118 |
| 270 | #define IRONLAKE_LVDS_S_P_MIN 28 |
| 271 | #define IRONLAKE_LVDS_S_P_MAX 112 |
| 272 | #define IRONLAKE_LVDS_S_P1_MIN 2 |
| 273 | #define IRONLAKE_LVDS_S_P1_MAX 8 |
| 274 | #define IRONLAKE_LVDS_S_P2_SLOW 14 |
| 275 | #define IRONLAKE_LVDS_S_P2_FAST 14 |
| 276 | |
| 277 | /* LVDS dual-channel 120Mhz refclk */ |
| 278 | #define IRONLAKE_LVDS_D_N_MIN 1 |
| 279 | #define IRONLAKE_LVDS_D_N_MAX 3 |
| 280 | #define IRONLAKE_LVDS_D_M_MIN 79 |
| 281 | #define IRONLAKE_LVDS_D_M_MAX 127 |
| 282 | #define IRONLAKE_LVDS_D_P_MIN 14 |
| 283 | #define IRONLAKE_LVDS_D_P_MAX 56 |
| 284 | #define IRONLAKE_LVDS_D_P1_MIN 2 |
| 285 | #define IRONLAKE_LVDS_D_P1_MAX 8 |
| 286 | #define IRONLAKE_LVDS_D_P2_SLOW 7 |
| 287 | #define IRONLAKE_LVDS_D_P2_FAST 7 |
| 288 | |
| 289 | /* LVDS single-channel 100Mhz refclk */ |
| 290 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 |
| 291 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 |
| 292 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 |
| 293 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 |
| 294 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 |
| 295 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 |
| 296 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 |
| 297 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 |
| 298 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 |
| 299 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 |
| 300 | |
| 301 | /* LVDS dual-channel 100Mhz refclk */ |
| 302 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 |
| 303 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 |
| 304 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 |
| 305 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 |
| 306 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 |
| 307 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 |
| 308 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 |
| 309 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 |
| 310 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 |
| 311 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 |
| 312 | |
| 313 | /* DisplayPort */ |
| 314 | #define IRONLAKE_DP_N_MIN 1 |
| 315 | #define IRONLAKE_DP_N_MAX 2 |
| 316 | #define IRONLAKE_DP_M_MIN 81 |
| 317 | #define IRONLAKE_DP_M_MAX 90 |
| 318 | #define IRONLAKE_DP_P_MIN 10 |
| 319 | #define IRONLAKE_DP_P_MAX 20 |
| 320 | #define IRONLAKE_DP_P2_FAST 10 |
| 321 | #define IRONLAKE_DP_P2_SLOW 10 |
| 322 | #define IRONLAKE_DP_P2_LIMIT 0 |
| 323 | #define IRONLAKE_DP_P1_MIN 1 |
| 324 | #define IRONLAKE_DP_P1_MAX 2 |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 325 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 326 | static bool |
| 327 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 328 | int target, int refclk, intel_clock_t *best_clock); |
| 329 | static bool |
| 330 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 331 | int target, int refclk, intel_clock_t *best_clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 332 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 333 | static bool |
| 334 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 335 | int target, int refclk, intel_clock_t *best_clock); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 336 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 337 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 338 | int target, int refclk, intel_clock_t *best_clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 339 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 340 | static const intel_limit_t intel_limits_i8xx_dvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 341 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 342 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 343 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 344 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 345 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 346 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 347 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 348 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, |
| 349 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 350 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 351 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 355 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 356 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 357 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 358 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 359 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 360 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 361 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 362 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, |
| 363 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 364 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 365 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 366 | }; |
| 367 | |
| 368 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 369 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 370 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 371 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 372 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 373 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 374 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 375 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 376 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 377 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 378 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 379 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 380 | }; |
| 381 | |
| 382 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 383 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 384 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 385 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 386 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 387 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 388 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 389 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, |
| 390 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 391 | /* The single-channel range is 25-112Mhz, and dual-channel |
| 392 | * is 80-224Mhz. Prefer single channel as much as possible. |
| 393 | */ |
| 394 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 395 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 396 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 397 | }; |
| 398 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 399 | /* below parameter and function is for G4X Chipset Family*/ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 400 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 401 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
| 402 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 403 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, |
| 404 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, |
| 405 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, |
| 406 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, |
| 407 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, |
| 408 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, |
| 409 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, |
| 410 | .p2_slow = G4X_P2_SDVO_SLOW, |
| 411 | .p2_fast = G4X_P2_SDVO_FAST |
| 412 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 413 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 414 | }; |
| 415 | |
| 416 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 417 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
| 418 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 419 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, |
| 420 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, |
| 421 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, |
| 422 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, |
| 423 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, |
| 424 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, |
| 425 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, |
| 426 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, |
| 427 | .p2_fast = G4X_P2_HDMI_DAC_FAST |
| 428 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 429 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 430 | }; |
| 431 | |
| 432 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 433 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
| 434 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, |
| 435 | .vco = { .min = G4X_VCO_MIN, |
| 436 | .max = G4X_VCO_MAX }, |
| 437 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, |
| 438 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, |
| 439 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, |
| 440 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, |
| 441 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, |
| 442 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, |
| 443 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, |
| 444 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, |
| 445 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, |
| 446 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, |
| 447 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, |
| 448 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, |
| 449 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, |
| 450 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, |
| 451 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST |
| 452 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 453 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 454 | }; |
| 455 | |
| 456 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 457 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
| 458 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, |
| 459 | .vco = { .min = G4X_VCO_MIN, |
| 460 | .max = G4X_VCO_MAX }, |
| 461 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, |
| 462 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, |
| 463 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, |
| 464 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, |
| 465 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, |
| 466 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, |
| 467 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, |
| 468 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, |
| 469 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, |
| 470 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, |
| 471 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, |
| 472 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, |
| 473 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, |
| 474 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, |
| 475 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST |
| 476 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 477 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 478 | }; |
| 479 | |
| 480 | static const intel_limit_t intel_limits_g4x_display_port = { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 481 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
| 482 | .max = G4X_DOT_DISPLAY_PORT_MAX }, |
| 483 | .vco = { .min = G4X_VCO_MIN, |
| 484 | .max = G4X_VCO_MAX}, |
| 485 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, |
| 486 | .max = G4X_N_DISPLAY_PORT_MAX }, |
| 487 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, |
| 488 | .max = G4X_M_DISPLAY_PORT_MAX }, |
| 489 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, |
| 490 | .max = G4X_M1_DISPLAY_PORT_MAX }, |
| 491 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, |
| 492 | .max = G4X_M2_DISPLAY_PORT_MAX }, |
| 493 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, |
| 494 | .max = G4X_P_DISPLAY_PORT_MAX }, |
| 495 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, |
| 496 | .max = G4X_P1_DISPLAY_PORT_MAX}, |
| 497 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, |
| 498 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, |
| 499 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, |
| 500 | .find_pll = intel_find_pll_g4x_dp, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 501 | }; |
| 502 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 503 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 504 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 505 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
| 506 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, |
| 507 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, |
| 508 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, |
| 509 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 510 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 511 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 512 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 513 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 514 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 515 | }; |
| 516 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 517 | static const intel_limit_t intel_limits_pineview_lvds = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 518 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 519 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
| 520 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, |
| 521 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, |
| 522 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, |
| 523 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, |
| 524 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 525 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 526 | /* Pineview only supports single-channel mode. */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 527 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 528 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 529 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 530 | }; |
| 531 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 532 | static const intel_limit_t intel_limits_ironlake_dac = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 533 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 534 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 535 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
| 536 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 537 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 538 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 539 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
| 540 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 541 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 542 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
| 543 | .p2_fast = IRONLAKE_DAC_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 544 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 545 | }; |
| 546 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 547 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 548 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 549 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 550 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
| 551 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 552 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 553 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 554 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
| 555 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 556 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 557 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
| 558 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, |
| 559 | .find_pll = intel_g4x_find_best_PLL, |
| 560 | }; |
| 561 | |
| 562 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
| 563 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 564 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 565 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, |
| 566 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, |
| 567 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 568 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 569 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, |
| 570 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, |
| 571 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 572 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, |
| 573 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, |
| 574 | .find_pll = intel_g4x_find_best_PLL, |
| 575 | }; |
| 576 | |
| 577 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
| 578 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 579 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 580 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, |
| 581 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, |
| 582 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 583 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 584 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, |
| 585 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, |
| 586 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 587 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, |
| 588 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, |
| 589 | .find_pll = intel_g4x_find_best_PLL, |
| 590 | }; |
| 591 | |
| 592 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
| 593 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
| 594 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, |
| 595 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, |
| 596 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, |
| 597 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
| 598 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, |
| 599 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, |
| 600 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, |
| 601 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
| 602 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, |
| 603 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 604 | .find_pll = intel_g4x_find_best_PLL, |
| 605 | }; |
| 606 | |
| 607 | static const intel_limit_t intel_limits_ironlake_display_port = { |
| 608 | .dot = { .min = IRONLAKE_DOT_MIN, |
| 609 | .max = IRONLAKE_DOT_MAX }, |
| 610 | .vco = { .min = IRONLAKE_VCO_MIN, |
| 611 | .max = IRONLAKE_VCO_MAX}, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 612 | .n = { .min = IRONLAKE_DP_N_MIN, |
| 613 | .max = IRONLAKE_DP_N_MAX }, |
| 614 | .m = { .min = IRONLAKE_DP_M_MIN, |
| 615 | .max = IRONLAKE_DP_M_MAX }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 616 | .m1 = { .min = IRONLAKE_M1_MIN, |
| 617 | .max = IRONLAKE_M1_MAX }, |
| 618 | .m2 = { .min = IRONLAKE_M2_MIN, |
| 619 | .max = IRONLAKE_M2_MAX }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 620 | .p = { .min = IRONLAKE_DP_P_MIN, |
| 621 | .max = IRONLAKE_DP_P_MAX }, |
| 622 | .p1 = { .min = IRONLAKE_DP_P1_MIN, |
| 623 | .max = IRONLAKE_DP_P1_MAX}, |
| 624 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, |
| 625 | .p2_slow = IRONLAKE_DP_P2_SLOW, |
| 626 | .p2_fast = IRONLAKE_DP_P2_FAST }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 627 | .find_pll = intel_find_pll_ironlake_dp, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 628 | }; |
| 629 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 630 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 631 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 632 | struct drm_device *dev = crtc->dev; |
| 633 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 634 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 635 | int refclk = 120; |
| 636 | |
| 637 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 638 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) |
| 639 | refclk = 100; |
| 640 | |
| 641 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
| 642 | LVDS_CLKB_POWER_UP) { |
| 643 | /* LVDS dual channel */ |
| 644 | if (refclk == 100) |
| 645 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 646 | else |
| 647 | limit = &intel_limits_ironlake_dual_lvds; |
| 648 | } else { |
| 649 | if (refclk == 100) |
| 650 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 651 | else |
| 652 | limit = &intel_limits_ironlake_single_lvds; |
| 653 | } |
| 654 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 655 | HAS_eDP) |
| 656 | limit = &intel_limits_ironlake_display_port; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 657 | else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 658 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 659 | |
| 660 | return limit; |
| 661 | } |
| 662 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 663 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 664 | { |
| 665 | struct drm_device *dev = crtc->dev; |
| 666 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 667 | const intel_limit_t *limit; |
| 668 | |
| 669 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 670 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 671 | LVDS_CLKB_POWER_UP) |
| 672 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 673 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 674 | else |
| 675 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 676 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 677 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 678 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 679 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 680 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 681 | limit = &intel_limits_g4x_sdvo; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 682 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 683 | limit = &intel_limits_g4x_display_port; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 684 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 685 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 686 | |
| 687 | return limit; |
| 688 | } |
| 689 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 690 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
| 691 | { |
| 692 | struct drm_device *dev = crtc->dev; |
| 693 | const intel_limit_t *limit; |
| 694 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 695 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 696 | limit = intel_ironlake_limit(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 697 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 698 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 699 | } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 700 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 701 | limit = &intel_limits_i9xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 702 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 703 | limit = &intel_limits_i9xx_sdvo; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 704 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 705 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 706 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 707 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 708 | limit = &intel_limits_pineview_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 709 | } else { |
| 710 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 711 | limit = &intel_limits_i8xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 712 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 713 | limit = &intel_limits_i8xx_dvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 714 | } |
| 715 | return limit; |
| 716 | } |
| 717 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 718 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 719 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 720 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 721 | clock->m = clock->m2 + 2; |
| 722 | clock->p = clock->p1 * clock->p2; |
| 723 | clock->vco = refclk * clock->m / clock->n; |
| 724 | clock->dot = clock->vco / clock->p; |
| 725 | } |
| 726 | |
| 727 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
| 728 | { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 729 | if (IS_PINEVIEW(dev)) { |
| 730 | pineview_clock(refclk, clock); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 731 | return; |
| 732 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 733 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 734 | clock->p = clock->p1 * clock->p2; |
| 735 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 736 | clock->dot = clock->vco / clock->p; |
| 737 | } |
| 738 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 739 | /** |
| 740 | * Returns whether any output on the specified pipe is of the specified type |
| 741 | */ |
| 742 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) |
| 743 | { |
| 744 | struct drm_device *dev = crtc->dev; |
| 745 | struct drm_mode_config *mode_config = &dev->mode_config; |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 746 | struct drm_encoder *l_entry; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 747 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 748 | list_for_each_entry(l_entry, &mode_config->encoder_list, head) { |
| 749 | if (l_entry && l_entry->crtc == crtc) { |
| 750 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 751 | if (intel_encoder->type == type) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 752 | return true; |
| 753 | } |
| 754 | } |
| 755 | return false; |
| 756 | } |
| 757 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 758 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 759 | /** |
| 760 | * Returns whether the given set of divisors are valid for a given refclk with |
| 761 | * the given connectors. |
| 762 | */ |
| 763 | |
| 764 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) |
| 765 | { |
| 766 | const intel_limit_t *limit = intel_limit (crtc); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 767 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 768 | |
| 769 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 770 | INTELPllInvalid ("p1 out of range\n"); |
| 771 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 772 | INTELPllInvalid ("p out of range\n"); |
| 773 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 774 | INTELPllInvalid ("m2 out of range\n"); |
| 775 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 776 | INTELPllInvalid ("m1 out of range\n"); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 777 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 778 | INTELPllInvalid ("m1 <= m2\n"); |
| 779 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 780 | INTELPllInvalid ("m out of range\n"); |
| 781 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 782 | INTELPllInvalid ("n out of range\n"); |
| 783 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 784 | INTELPllInvalid ("vco out of range\n"); |
| 785 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 786 | * connector, etc., rather than just a single range. |
| 787 | */ |
| 788 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 789 | INTELPllInvalid ("dot out of range\n"); |
| 790 | |
| 791 | return true; |
| 792 | } |
| 793 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 794 | static bool |
| 795 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 796 | int target, int refclk, intel_clock_t *best_clock) |
| 797 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 798 | { |
| 799 | struct drm_device *dev = crtc->dev; |
| 800 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 801 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 802 | int err = target; |
| 803 | |
Bruno Prémont | bc5e571 | 2009-08-08 13:01:17 +0200 | [diff] [blame] | 804 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Florian Mickler | 832cc28 | 2009-07-13 18:40:32 +0800 | [diff] [blame] | 805 | (I915_READ(LVDS)) != 0) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 806 | /* |
| 807 | * For LVDS, if the panel is on, just rely on its current |
| 808 | * settings for dual-channel. We haven't figured out how to |
| 809 | * reliably set up different single/dual channel state, if we |
| 810 | * even can. |
| 811 | */ |
| 812 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 813 | LVDS_CLKB_POWER_UP) |
| 814 | clock.p2 = limit->p2.p2_fast; |
| 815 | else |
| 816 | clock.p2 = limit->p2.p2_slow; |
| 817 | } else { |
| 818 | if (target < limit->p2.dot_limit) |
| 819 | clock.p2 = limit->p2.p2_slow; |
| 820 | else |
| 821 | clock.p2 = limit->p2.p2_fast; |
| 822 | } |
| 823 | |
| 824 | memset (best_clock, 0, sizeof (*best_clock)); |
| 825 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 826 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 827 | clock.m1++) { |
| 828 | for (clock.m2 = limit->m2.min; |
| 829 | clock.m2 <= limit->m2.max; clock.m2++) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 830 | /* m1 is always 0 in Pineview */ |
| 831 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 832 | break; |
| 833 | for (clock.n = limit->n.min; |
| 834 | clock.n <= limit->n.max; clock.n++) { |
| 835 | for (clock.p1 = limit->p1.min; |
| 836 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 837 | int this_err; |
| 838 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 839 | intel_clock(dev, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 840 | |
| 841 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 842 | continue; |
| 843 | |
| 844 | this_err = abs(clock.dot - target); |
| 845 | if (this_err < err) { |
| 846 | *best_clock = clock; |
| 847 | err = this_err; |
| 848 | } |
| 849 | } |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | |
| 854 | return (err != target); |
| 855 | } |
| 856 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 857 | static bool |
| 858 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 859 | int target, int refclk, intel_clock_t *best_clock) |
| 860 | { |
| 861 | struct drm_device *dev = crtc->dev; |
| 862 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 863 | intel_clock_t clock; |
| 864 | int max_n; |
| 865 | bool found; |
| 866 | /* approximately equals target * 0.00488 */ |
| 867 | int err_most = (target >> 8) + (target >> 10); |
| 868 | found = false; |
| 869 | |
| 870 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 871 | int lvds_reg; |
| 872 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 873 | if (HAS_PCH_SPLIT(dev)) |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 874 | lvds_reg = PCH_LVDS; |
| 875 | else |
| 876 | lvds_reg = LVDS; |
| 877 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 878 | LVDS_CLKB_POWER_UP) |
| 879 | clock.p2 = limit->p2.p2_fast; |
| 880 | else |
| 881 | clock.p2 = limit->p2.p2_slow; |
| 882 | } else { |
| 883 | if (target < limit->p2.dot_limit) |
| 884 | clock.p2 = limit->p2.p2_slow; |
| 885 | else |
| 886 | clock.p2 = limit->p2.p2_fast; |
| 887 | } |
| 888 | |
| 889 | memset(best_clock, 0, sizeof(*best_clock)); |
| 890 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 891 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 892 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 893 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 894 | for (clock.m1 = limit->m1.max; |
| 895 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 896 | for (clock.m2 = limit->m2.max; |
| 897 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 898 | for (clock.p1 = limit->p1.max; |
| 899 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 900 | int this_err; |
| 901 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 902 | intel_clock(dev, refclk, &clock); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 903 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 904 | continue; |
| 905 | this_err = abs(clock.dot - target) ; |
| 906 | if (this_err < err_most) { |
| 907 | *best_clock = clock; |
| 908 | err_most = this_err; |
| 909 | max_n = clock.n; |
| 910 | found = true; |
| 911 | } |
| 912 | } |
| 913 | } |
| 914 | } |
| 915 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 916 | return found; |
| 917 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 918 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 919 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 920 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 921 | int target, int refclk, intel_clock_t *best_clock) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 922 | { |
| 923 | struct drm_device *dev = crtc->dev; |
| 924 | intel_clock_t clock; |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 925 | |
| 926 | /* return directly when it is eDP */ |
| 927 | if (HAS_eDP) |
| 928 | return true; |
| 929 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 930 | if (target < 200000) { |
| 931 | clock.n = 1; |
| 932 | clock.p1 = 2; |
| 933 | clock.p2 = 10; |
| 934 | clock.m1 = 12; |
| 935 | clock.m2 = 9; |
| 936 | } else { |
| 937 | clock.n = 2; |
| 938 | clock.p1 = 1; |
| 939 | clock.p2 = 10; |
| 940 | clock.m1 = 14; |
| 941 | clock.m2 = 8; |
| 942 | } |
| 943 | intel_clock(dev, refclk, &clock); |
| 944 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 945 | return true; |
| 946 | } |
| 947 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 948 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
| 949 | static bool |
| 950 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 951 | int target, int refclk, intel_clock_t *best_clock) |
| 952 | { |
| 953 | intel_clock_t clock; |
| 954 | if (target < 200000) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 955 | clock.p1 = 2; |
| 956 | clock.p2 = 10; |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 957 | clock.n = 2; |
| 958 | clock.m1 = 23; |
| 959 | clock.m2 = 8; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 960 | } else { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 961 | clock.p1 = 1; |
| 962 | clock.p2 = 10; |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 963 | clock.n = 1; |
| 964 | clock.m1 = 14; |
| 965 | clock.m2 = 2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 966 | } |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 967 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
| 968 | clock.p = (clock.p1 * clock.p2); |
| 969 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
Jesse Barnes | fe798b9 | 2009-10-20 07:55:28 +0900 | [diff] [blame] | 970 | clock.vco = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 971 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 972 | return true; |
| 973 | } |
| 974 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 975 | void |
| 976 | intel_wait_for_vblank(struct drm_device *dev) |
| 977 | { |
| 978 | /* Wait for 20ms, i.e. one cycle at 50hz. */ |
Shaohua Li | 311089d | 2009-11-26 14:22:41 +0800 | [diff] [blame] | 979 | msleep(20); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 980 | } |
| 981 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 982 | /* Parameters have changed, update FBC info */ |
| 983 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 984 | { |
| 985 | struct drm_device *dev = crtc->dev; |
| 986 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 987 | struct drm_framebuffer *fb = crtc->fb; |
| 988 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 989 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 991 | int plane, i; |
| 992 | u32 fbc_ctl, fbc_ctl2; |
| 993 | |
| 994 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
| 995 | |
| 996 | if (fb->pitch < dev_priv->cfb_pitch) |
| 997 | dev_priv->cfb_pitch = fb->pitch; |
| 998 | |
| 999 | /* FBC_CTL wants 64B units */ |
| 1000 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1001 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1002 | dev_priv->cfb_plane = intel_crtc->plane; |
| 1003 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
| 1004 | |
| 1005 | /* Clear old tags */ |
| 1006 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 1007 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 1008 | |
| 1009 | /* Set it up... */ |
| 1010 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; |
| 1011 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1012 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
| 1013 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 1014 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 1015 | |
| 1016 | /* enable it... */ |
| 1017 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
Jesse Barnes | ee25df2 | 2010-02-06 10:41:53 -0800 | [diff] [blame] | 1018 | if (IS_I945GM(dev)) |
Priit Laes | 4967790 | 2010-03-02 11:37:00 +0200 | [diff] [blame] | 1019 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1020 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 1021 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
| 1022 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1023 | fbc_ctl |= dev_priv->cfb_fence; |
| 1024 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1025 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1026 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1027 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
| 1028 | } |
| 1029 | |
| 1030 | void i8xx_disable_fbc(struct drm_device *dev) |
| 1031 | { |
| 1032 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9517a92 | 2010-05-21 09:40:45 -0700 | [diff] [blame] | 1033 | unsigned long timeout = jiffies + msecs_to_jiffies(1); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1034 | u32 fbc_ctl; |
| 1035 | |
Jesse Barnes | c1a1cdc | 2009-09-16 15:05:00 -0700 | [diff] [blame] | 1036 | if (!I915_HAS_FBC(dev)) |
| 1037 | return; |
| 1038 | |
Jesse Barnes | 9517a92 | 2010-05-21 09:40:45 -0700 | [diff] [blame] | 1039 | if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN)) |
| 1040 | return; /* Already off, just return */ |
| 1041 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1042 | /* Disable compression */ |
| 1043 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 1044 | fbc_ctl &= ~FBC_CTL_EN; |
| 1045 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1046 | |
| 1047 | /* Wait for compressing bit to clear */ |
Jesse Barnes | 9517a92 | 2010-05-21 09:40:45 -0700 | [diff] [blame] | 1048 | while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) { |
| 1049 | if (time_after(jiffies, timeout)) { |
| 1050 | DRM_DEBUG_DRIVER("FBC idle timed out\n"); |
| 1051 | break; |
| 1052 | } |
| 1053 | ; /* do nothing */ |
| 1054 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1055 | |
| 1056 | intel_wait_for_vblank(dev); |
| 1057 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1058 | DRM_DEBUG_KMS("disabled FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1059 | } |
| 1060 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1061 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1062 | { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1063 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1064 | |
| 1065 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 1066 | } |
| 1067 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1068 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1069 | { |
| 1070 | struct drm_device *dev = crtc->dev; |
| 1071 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1072 | struct drm_framebuffer *fb = crtc->fb; |
| 1073 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1074 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1076 | int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : |
| 1077 | DPFC_CTL_PLANEB); |
| 1078 | unsigned long stall_watermark = 200; |
| 1079 | u32 dpfc_ctl; |
| 1080 | |
| 1081 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1082 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1083 | dev_priv->cfb_plane = intel_crtc->plane; |
| 1084 | |
| 1085 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
| 1086 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1087 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
| 1088 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 1089 | } else { |
| 1090 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); |
| 1091 | } |
| 1092 | |
| 1093 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 1094 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1095 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1096 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1097 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 1098 | |
| 1099 | /* enable it... */ |
| 1100 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 1101 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1102 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | void g4x_disable_fbc(struct drm_device *dev) |
| 1106 | { |
| 1107 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1108 | u32 dpfc_ctl; |
| 1109 | |
| 1110 | /* Disable compression */ |
| 1111 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 1112 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1113 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 1114 | intel_wait_for_vblank(dev); |
| 1115 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1116 | DRM_DEBUG_KMS("disabled FBC\n"); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1117 | } |
| 1118 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1119 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1120 | { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1121 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1122 | |
| 1123 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 1124 | } |
| 1125 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1126 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1127 | { |
| 1128 | struct drm_device *dev = crtc->dev; |
| 1129 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1130 | struct drm_framebuffer *fb = crtc->fb; |
| 1131 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 1132 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
| 1133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1134 | int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA : |
| 1135 | DPFC_CTL_PLANEB; |
| 1136 | unsigned long stall_watermark = 200; |
| 1137 | u32 dpfc_ctl; |
| 1138 | |
| 1139 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1140 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1141 | dev_priv->cfb_plane = intel_crtc->plane; |
| 1142 | |
| 1143 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 1144 | dpfc_ctl &= DPFC_RESERVED; |
| 1145 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
| 1146 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1147 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
| 1148 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 1149 | } else { |
| 1150 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); |
| 1151 | } |
| 1152 | |
| 1153 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 1154 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1155 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1156 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1157 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
| 1158 | I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID); |
| 1159 | /* enable it... */ |
| 1160 | I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) | |
| 1161 | DPFC_CTL_EN); |
| 1162 | |
| 1163 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 1164 | } |
| 1165 | |
| 1166 | void ironlake_disable_fbc(struct drm_device *dev) |
| 1167 | { |
| 1168 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1169 | u32 dpfc_ctl; |
| 1170 | |
| 1171 | /* Disable compression */ |
| 1172 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 1173 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1174 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 1175 | intel_wait_for_vblank(dev); |
| 1176 | |
| 1177 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 1178 | } |
| 1179 | |
| 1180 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
| 1181 | { |
| 1182 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1183 | |
| 1184 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 1185 | } |
| 1186 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1187 | bool intel_fbc_enabled(struct drm_device *dev) |
| 1188 | { |
| 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1190 | |
| 1191 | if (!dev_priv->display.fbc_enabled) |
| 1192 | return false; |
| 1193 | |
| 1194 | return dev_priv->display.fbc_enabled(dev); |
| 1195 | } |
| 1196 | |
| 1197 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1198 | { |
| 1199 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1200 | |
| 1201 | if (!dev_priv->display.enable_fbc) |
| 1202 | return; |
| 1203 | |
| 1204 | dev_priv->display.enable_fbc(crtc, interval); |
| 1205 | } |
| 1206 | |
| 1207 | void intel_disable_fbc(struct drm_device *dev) |
| 1208 | { |
| 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1210 | |
| 1211 | if (!dev_priv->display.disable_fbc) |
| 1212 | return; |
| 1213 | |
| 1214 | dev_priv->display.disable_fbc(dev); |
| 1215 | } |
| 1216 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1217 | /** |
| 1218 | * intel_update_fbc - enable/disable FBC as needed |
| 1219 | * @crtc: CRTC to point the compressor at |
| 1220 | * @mode: mode in use |
| 1221 | * |
| 1222 | * Set up the framebuffer compression hardware at mode set time. We |
| 1223 | * enable it if possible: |
| 1224 | * - plane A only (on pre-965) |
| 1225 | * - no pixel mulitply/line duplication |
| 1226 | * - no alpha buffer discard |
| 1227 | * - no dual wide |
| 1228 | * - framebuffer <= 2048 in width, 1536 in height |
| 1229 | * |
| 1230 | * We can't assume that any compression will take place (worst case), |
| 1231 | * so the compressed buffer has to be the same size as the uncompressed |
| 1232 | * one. It also must reside (along with the line length buffer) in |
| 1233 | * stolen memory. |
| 1234 | * |
| 1235 | * We need to enable/disable FBC on a global basis. |
| 1236 | */ |
| 1237 | static void intel_update_fbc(struct drm_crtc *crtc, |
| 1238 | struct drm_display_mode *mode) |
| 1239 | { |
| 1240 | struct drm_device *dev = crtc->dev; |
| 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1242 | struct drm_framebuffer *fb = crtc->fb; |
| 1243 | struct intel_framebuffer *intel_fb; |
| 1244 | struct drm_i915_gem_object *obj_priv; |
| 1245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1246 | int plane = intel_crtc->plane; |
| 1247 | |
| 1248 | if (!i915_powersave) |
| 1249 | return; |
| 1250 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1251 | if (!I915_HAS_FBC(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1252 | return; |
| 1253 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1254 | if (!crtc->fb) |
| 1255 | return; |
| 1256 | |
| 1257 | intel_fb = to_intel_framebuffer(fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1258 | obj_priv = to_intel_bo(intel_fb->obj); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1259 | |
| 1260 | /* |
| 1261 | * If FBC is already on, we just have to verify that we can |
| 1262 | * keep it that way... |
| 1263 | * Need to disable if: |
| 1264 | * - changing FBC params (stride, fence, mode) |
| 1265 | * - new fb is too large to fit in compressed buffer |
| 1266 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 1267 | */ |
| 1268 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1269 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
| 1270 | "compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1271 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1272 | goto out_disable; |
| 1273 | } |
| 1274 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 1275 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1276 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 1277 | "disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1278 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1279 | goto out_disable; |
| 1280 | } |
| 1281 | if ((mode->hdisplay > 2048) || |
| 1282 | (mode->vdisplay > 1536)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1283 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1284 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1285 | goto out_disable; |
| 1286 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1287 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1288 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1289 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1290 | goto out_disable; |
| 1291 | } |
| 1292 | if (obj_priv->tiling_mode != I915_TILING_X) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1293 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1294 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1295 | goto out_disable; |
| 1296 | } |
| 1297 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1298 | if (intel_fbc_enabled(dev)) { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1299 | /* We can re-enable it in this case, but need to update pitch */ |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1300 | if ((fb->pitch > dev_priv->cfb_pitch) || |
| 1301 | (obj_priv->fence_reg != dev_priv->cfb_fence) || |
| 1302 | (plane != dev_priv->cfb_plane)) |
| 1303 | intel_disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1304 | } |
| 1305 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1306 | /* Now try to turn it back on if possible */ |
| 1307 | if (!intel_fbc_enabled(dev)) |
| 1308 | intel_enable_fbc(crtc, 500); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1309 | |
| 1310 | return; |
| 1311 | |
| 1312 | out_disable: |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1313 | /* Multiple disables should be harmless */ |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 1314 | if (intel_fbc_enabled(dev)) { |
| 1315 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1316 | intel_disable_fbc(dev); |
Chris Wilson | a939406 | 2010-05-27 13:18:16 +0100 | [diff] [blame] | 1317 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1318 | } |
| 1319 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1320 | static int |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1321 | intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) |
| 1322 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1323 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1324 | u32 alignment; |
| 1325 | int ret; |
| 1326 | |
| 1327 | switch (obj_priv->tiling_mode) { |
| 1328 | case I915_TILING_NONE: |
| 1329 | alignment = 64 * 1024; |
| 1330 | break; |
| 1331 | case I915_TILING_X: |
| 1332 | /* pin() will align the object as required by fence */ |
| 1333 | alignment = 0; |
| 1334 | break; |
| 1335 | case I915_TILING_Y: |
| 1336 | /* FIXME: Is this true? */ |
| 1337 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
| 1338 | return -EINVAL; |
| 1339 | default: |
| 1340 | BUG(); |
| 1341 | } |
| 1342 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1343 | ret = i915_gem_object_pin(obj, alignment); |
| 1344 | if (ret != 0) |
| 1345 | return ret; |
| 1346 | |
| 1347 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 1348 | * fence, whereas 965+ only requires a fence if using |
| 1349 | * framebuffer compression. For simplicity, we always install |
| 1350 | * a fence as the cost is not that onerous. |
| 1351 | */ |
| 1352 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && |
| 1353 | obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1354 | ret = i915_gem_object_get_fence_reg(obj); |
| 1355 | if (ret != 0) { |
| 1356 | i915_gem_object_unpin(obj); |
| 1357 | return ret; |
| 1358 | } |
| 1359 | } |
| 1360 | |
| 1361 | return 0; |
| 1362 | } |
| 1363 | |
| 1364 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1365 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
| 1366 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1367 | { |
| 1368 | struct drm_device *dev = crtc->dev; |
| 1369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1370 | struct drm_i915_master_private *master_priv; |
| 1371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1372 | struct intel_framebuffer *intel_fb; |
| 1373 | struct drm_i915_gem_object *obj_priv; |
| 1374 | struct drm_gem_object *obj; |
| 1375 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1376 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1377 | unsigned long Start, Offset; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1378 | int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR); |
| 1379 | int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF); |
| 1380 | int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; |
| 1381 | int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); |
| 1382 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1383 | u32 dspcntr; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1384 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1385 | |
| 1386 | /* no fb bound */ |
| 1387 | if (!crtc->fb) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1388 | DRM_DEBUG_KMS("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1389 | return 0; |
| 1390 | } |
| 1391 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1392 | switch (plane) { |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1393 | case 0: |
| 1394 | case 1: |
| 1395 | break; |
| 1396 | default: |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1397 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1398 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1399 | } |
| 1400 | |
| 1401 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1402 | obj = intel_fb->obj; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1403 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1404 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1405 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1406 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1407 | if (ret != 0) { |
| 1408 | mutex_unlock(&dev->struct_mutex); |
| 1409 | return ret; |
| 1410 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1411 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 1412 | ret = i915_gem_object_set_to_display_plane(obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1413 | if (ret != 0) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1414 | i915_gem_object_unpin(obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1415 | mutex_unlock(&dev->struct_mutex); |
| 1416 | return ret; |
| 1417 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1418 | |
| 1419 | dspcntr = I915_READ(dspcntr_reg); |
Jesse Barnes | 712531b | 2009-01-09 13:56:14 -0800 | [diff] [blame] | 1420 | /* Mask out pixel format bits in case we change it */ |
| 1421 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1422 | switch (crtc->fb->bits_per_pixel) { |
| 1423 | case 8: |
| 1424 | dspcntr |= DISPPLANE_8BPP; |
| 1425 | break; |
| 1426 | case 16: |
| 1427 | if (crtc->fb->depth == 15) |
| 1428 | dspcntr |= DISPPLANE_15_16BPP; |
| 1429 | else |
| 1430 | dspcntr |= DISPPLANE_16BPP; |
| 1431 | break; |
| 1432 | case 24: |
| 1433 | case 32: |
Kristian Høgsberg | a4f45cf | 2009-10-19 14:35:30 -0400 | [diff] [blame] | 1434 | if (crtc->fb->depth == 30) |
| 1435 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
| 1436 | else |
| 1437 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1438 | break; |
| 1439 | default: |
| 1440 | DRM_ERROR("Unknown color depth\n"); |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1441 | i915_gem_object_unpin(obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1442 | mutex_unlock(&dev->struct_mutex); |
| 1443 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1444 | } |
Jesse Barnes | f544847 | 2009-04-14 14:17:47 -0700 | [diff] [blame] | 1445 | if (IS_I965G(dev)) { |
| 1446 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1447 | dspcntr |= DISPPLANE_TILED; |
| 1448 | else |
| 1449 | dspcntr &= ~DISPPLANE_TILED; |
| 1450 | } |
| 1451 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1452 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 1453 | /* must disable */ |
| 1454 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 1455 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1456 | I915_WRITE(dspcntr_reg, dspcntr); |
| 1457 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1458 | Start = obj_priv->gtt_offset; |
| 1459 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); |
| 1460 | |
Chris Wilson | a7faf32 | 2010-05-27 13:18:17 +0100 | [diff] [blame] | 1461 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 1462 | Start, Offset, x, y, crtc->fb->pitch); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1463 | I915_WRITE(dspstride, crtc->fb->pitch); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1464 | if (IS_I965G(dev)) { |
| 1465 | I915_WRITE(dspbase, Offset); |
| 1466 | I915_READ(dspbase); |
| 1467 | I915_WRITE(dspsurf, Start); |
| 1468 | I915_READ(dspsurf); |
Jesse Barnes | f544847 | 2009-04-14 14:17:47 -0700 | [diff] [blame] | 1469 | I915_WRITE(dsptileoff, (y << 16) | x); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1470 | } else { |
| 1471 | I915_WRITE(dspbase, Start + Offset); |
| 1472 | I915_READ(dspbase); |
| 1473 | } |
| 1474 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1475 | if ((IS_I965G(dev) || plane == 0)) |
Jesse Barnes | edb8195 | 2009-09-17 17:06:47 -0700 | [diff] [blame] | 1476 | intel_update_fbc(crtc, &crtc->mode); |
| 1477 | |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1478 | intel_wait_for_vblank(dev); |
| 1479 | |
| 1480 | if (old_fb) { |
| 1481 | intel_fb = to_intel_framebuffer(old_fb); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1482 | obj_priv = to_intel_bo(intel_fb->obj); |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1483 | i915_gem_object_unpin(intel_fb->obj); |
| 1484 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1485 | intel_increase_pllclock(crtc, true); |
| 1486 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1487 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1488 | |
| 1489 | if (!dev->primary->master) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1490 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1491 | |
| 1492 | master_priv = dev->primary->master->driver_priv; |
| 1493 | if (!master_priv->sarea_priv) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1494 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1495 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1496 | if (pipe) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1497 | master_priv->sarea_priv->pipeB_x = x; |
| 1498 | master_priv->sarea_priv->pipeB_y = y; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1499 | } else { |
| 1500 | master_priv->sarea_priv->pipeA_x = x; |
| 1501 | master_priv->sarea_priv->pipeA_y = y; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1502 | } |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1503 | |
| 1504 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1505 | } |
| 1506 | |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 1507 | /* Disable the VGA plane that we never use */ |
| 1508 | static void i915_disable_vga (struct drm_device *dev) |
| 1509 | { |
| 1510 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1511 | u8 sr1; |
| 1512 | u32 vga_reg; |
| 1513 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1514 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 1515 | vga_reg = CPU_VGACNTRL; |
| 1516 | else |
| 1517 | vga_reg = VGACNTRL; |
| 1518 | |
| 1519 | if (I915_READ(vga_reg) & VGA_DISP_DISABLE) |
| 1520 | return; |
| 1521 | |
| 1522 | I915_WRITE8(VGA_SR_INDEX, 1); |
| 1523 | sr1 = I915_READ8(VGA_SR_DATA); |
| 1524 | I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5)); |
| 1525 | udelay(100); |
| 1526 | |
| 1527 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 1528 | } |
| 1529 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1530 | static void ironlake_disable_pll_edp (struct drm_crtc *crtc) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1531 | { |
| 1532 | struct drm_device *dev = crtc->dev; |
| 1533 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1534 | u32 dpa_ctl; |
| 1535 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1536 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1537 | dpa_ctl = I915_READ(DP_A); |
| 1538 | dpa_ctl &= ~DP_PLL_ENABLE; |
| 1539 | I915_WRITE(DP_A, dpa_ctl); |
| 1540 | } |
| 1541 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1542 | static void ironlake_enable_pll_edp (struct drm_crtc *crtc) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1543 | { |
| 1544 | struct drm_device *dev = crtc->dev; |
| 1545 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1546 | u32 dpa_ctl; |
| 1547 | |
| 1548 | dpa_ctl = I915_READ(DP_A); |
| 1549 | dpa_ctl |= DP_PLL_ENABLE; |
| 1550 | I915_WRITE(DP_A, dpa_ctl); |
| 1551 | udelay(200); |
| 1552 | } |
| 1553 | |
| 1554 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1555 | static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1556 | { |
| 1557 | struct drm_device *dev = crtc->dev; |
| 1558 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1559 | u32 dpa_ctl; |
| 1560 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1561 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1562 | dpa_ctl = I915_READ(DP_A); |
| 1563 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 1564 | |
| 1565 | if (clock < 200000) { |
| 1566 | u32 temp; |
| 1567 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 1568 | /* workaround for 160Mhz: |
| 1569 | 1) program 0x4600c bits 15:0 = 0x8124 |
| 1570 | 2) program 0x46010 bit 0 = 1 |
| 1571 | 3) program 0x46034 bit 24 = 1 |
| 1572 | 4) program 0x64000 bit 14 = 1 |
| 1573 | */ |
| 1574 | temp = I915_READ(0x4600c); |
| 1575 | temp &= 0xffff0000; |
| 1576 | I915_WRITE(0x4600c, temp | 0x8124); |
| 1577 | |
| 1578 | temp = I915_READ(0x46010); |
| 1579 | I915_WRITE(0x46010, temp | 1); |
| 1580 | |
| 1581 | temp = I915_READ(0x46034); |
| 1582 | I915_WRITE(0x46034, temp | (1 << 24)); |
| 1583 | } else { |
| 1584 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 1585 | } |
| 1586 | I915_WRITE(DP_A, dpa_ctl); |
| 1587 | |
| 1588 | udelay(500); |
| 1589 | } |
| 1590 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1591 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 1592 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 1593 | { |
| 1594 | struct drm_device *dev = crtc->dev; |
| 1595 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1597 | int pipe = intel_crtc->pipe; |
| 1598 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
| 1599 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
| 1600 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; |
| 1601 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; |
| 1602 | u32 temp, tries = 0; |
| 1603 | |
| 1604 | /* enable CPU FDI TX and PCH FDI RX */ |
| 1605 | temp = I915_READ(fdi_tx_reg); |
| 1606 | temp |= FDI_TX_ENABLE; |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 1607 | temp &= ~(7 << 19); |
| 1608 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1609 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1610 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1611 | I915_WRITE(fdi_tx_reg, temp); |
| 1612 | I915_READ(fdi_tx_reg); |
| 1613 | |
| 1614 | temp = I915_READ(fdi_rx_reg); |
| 1615 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1616 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1617 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); |
| 1618 | I915_READ(fdi_rx_reg); |
| 1619 | udelay(150); |
| 1620 | |
| 1621 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 1622 | for train result */ |
| 1623 | temp = I915_READ(fdi_rx_imr_reg); |
| 1624 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 1625 | temp &= ~FDI_RX_BIT_LOCK; |
| 1626 | I915_WRITE(fdi_rx_imr_reg, temp); |
| 1627 | I915_READ(fdi_rx_imr_reg); |
| 1628 | udelay(150); |
| 1629 | |
| 1630 | for (;;) { |
| 1631 | temp = I915_READ(fdi_rx_iir_reg); |
| 1632 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1633 | |
| 1634 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 1635 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 1636 | I915_WRITE(fdi_rx_iir_reg, |
| 1637 | temp | FDI_RX_BIT_LOCK); |
| 1638 | break; |
| 1639 | } |
| 1640 | |
| 1641 | tries++; |
| 1642 | |
| 1643 | if (tries > 5) { |
| 1644 | DRM_DEBUG_KMS("FDI train 1 fail!\n"); |
| 1645 | break; |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | /* Train 2 */ |
| 1650 | temp = I915_READ(fdi_tx_reg); |
| 1651 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1652 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1653 | I915_WRITE(fdi_tx_reg, temp); |
| 1654 | |
| 1655 | temp = I915_READ(fdi_rx_reg); |
| 1656 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1657 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1658 | I915_WRITE(fdi_rx_reg, temp); |
| 1659 | udelay(150); |
| 1660 | |
| 1661 | tries = 0; |
| 1662 | |
| 1663 | for (;;) { |
| 1664 | temp = I915_READ(fdi_rx_iir_reg); |
| 1665 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1666 | |
| 1667 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 1668 | I915_WRITE(fdi_rx_iir_reg, |
| 1669 | temp | FDI_RX_SYMBOL_LOCK); |
| 1670 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 1671 | break; |
| 1672 | } |
| 1673 | |
| 1674 | tries++; |
| 1675 | |
| 1676 | if (tries > 5) { |
| 1677 | DRM_DEBUG_KMS("FDI train 2 fail!\n"); |
| 1678 | break; |
| 1679 | } |
| 1680 | } |
| 1681 | |
| 1682 | DRM_DEBUG_KMS("FDI train done\n"); |
| 1683 | } |
| 1684 | |
| 1685 | static int snb_b_fdi_train_param [] = { |
| 1686 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 1687 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 1688 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 1689 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 1690 | }; |
| 1691 | |
| 1692 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 1693 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 1694 | { |
| 1695 | struct drm_device *dev = crtc->dev; |
| 1696 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1698 | int pipe = intel_crtc->pipe; |
| 1699 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
| 1700 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
| 1701 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; |
| 1702 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; |
| 1703 | u32 temp, i; |
| 1704 | |
| 1705 | /* enable CPU FDI TX and PCH FDI RX */ |
| 1706 | temp = I915_READ(fdi_tx_reg); |
| 1707 | temp |= FDI_TX_ENABLE; |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 1708 | temp &= ~(7 << 19); |
| 1709 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1710 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1711 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1712 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1713 | /* SNB-B */ |
| 1714 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 1715 | I915_WRITE(fdi_tx_reg, temp); |
| 1716 | I915_READ(fdi_tx_reg); |
| 1717 | |
| 1718 | temp = I915_READ(fdi_rx_reg); |
| 1719 | if (HAS_PCH_CPT(dev)) { |
| 1720 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 1721 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 1722 | } else { |
| 1723 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1724 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1725 | } |
| 1726 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); |
| 1727 | I915_READ(fdi_rx_reg); |
| 1728 | udelay(150); |
| 1729 | |
| 1730 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 1731 | for train result */ |
| 1732 | temp = I915_READ(fdi_rx_imr_reg); |
| 1733 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 1734 | temp &= ~FDI_RX_BIT_LOCK; |
| 1735 | I915_WRITE(fdi_rx_imr_reg, temp); |
| 1736 | I915_READ(fdi_rx_imr_reg); |
| 1737 | udelay(150); |
| 1738 | |
| 1739 | for (i = 0; i < 4; i++ ) { |
| 1740 | temp = I915_READ(fdi_tx_reg); |
| 1741 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1742 | temp |= snb_b_fdi_train_param[i]; |
| 1743 | I915_WRITE(fdi_tx_reg, temp); |
| 1744 | udelay(500); |
| 1745 | |
| 1746 | temp = I915_READ(fdi_rx_iir_reg); |
| 1747 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1748 | |
| 1749 | if (temp & FDI_RX_BIT_LOCK) { |
| 1750 | I915_WRITE(fdi_rx_iir_reg, |
| 1751 | temp | FDI_RX_BIT_LOCK); |
| 1752 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 1753 | break; |
| 1754 | } |
| 1755 | } |
| 1756 | if (i == 4) |
| 1757 | DRM_DEBUG_KMS("FDI train 1 fail!\n"); |
| 1758 | |
| 1759 | /* Train 2 */ |
| 1760 | temp = I915_READ(fdi_tx_reg); |
| 1761 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1762 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1763 | if (IS_GEN6(dev)) { |
| 1764 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1765 | /* SNB-B */ |
| 1766 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 1767 | } |
| 1768 | I915_WRITE(fdi_tx_reg, temp); |
| 1769 | |
| 1770 | temp = I915_READ(fdi_rx_reg); |
| 1771 | if (HAS_PCH_CPT(dev)) { |
| 1772 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 1773 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 1774 | } else { |
| 1775 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1776 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1777 | } |
| 1778 | I915_WRITE(fdi_rx_reg, temp); |
| 1779 | udelay(150); |
| 1780 | |
| 1781 | for (i = 0; i < 4; i++ ) { |
| 1782 | temp = I915_READ(fdi_tx_reg); |
| 1783 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 1784 | temp |= snb_b_fdi_train_param[i]; |
| 1785 | I915_WRITE(fdi_tx_reg, temp); |
| 1786 | udelay(500); |
| 1787 | |
| 1788 | temp = I915_READ(fdi_rx_iir_reg); |
| 1789 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 1790 | |
| 1791 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 1792 | I915_WRITE(fdi_rx_iir_reg, |
| 1793 | temp | FDI_RX_SYMBOL_LOCK); |
| 1794 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 1795 | break; |
| 1796 | } |
| 1797 | } |
| 1798 | if (i == 4) |
| 1799 | DRM_DEBUG_KMS("FDI train 2 fail!\n"); |
| 1800 | |
| 1801 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 1802 | } |
| 1803 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1804 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1805 | { |
| 1806 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1807 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1809 | int pipe = intel_crtc->pipe; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1810 | int plane = intel_crtc->plane; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1811 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
| 1812 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 1813 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
| 1814 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; |
| 1815 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
| 1816 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1817 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; |
| 1818 | int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1819 | int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1820 | int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1821 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
| 1822 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; |
| 1823 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; |
| 1824 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; |
| 1825 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; |
| 1826 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; |
| 1827 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; |
| 1828 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; |
| 1829 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; |
| 1830 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; |
| 1831 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; |
| 1832 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1833 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1834 | u32 temp; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1835 | int n; |
Zhao Yakui | 8faf3b3 | 2010-01-04 16:29:31 +0800 | [diff] [blame] | 1836 | u32 pipe_bpc; |
| 1837 | |
| 1838 | temp = I915_READ(pipeconf_reg); |
| 1839 | pipe_bpc = temp & PIPE_BPC_MASK; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1840 | |
| 1841 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 1842 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 1843 | */ |
| 1844 | switch (mode) { |
| 1845 | case DRM_MODE_DPMS_ON: |
| 1846 | case DRM_MODE_DPMS_STANDBY: |
| 1847 | case DRM_MODE_DPMS_SUSPEND: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1848 | DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 1849 | |
| 1850 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 1851 | temp = I915_READ(PCH_LVDS); |
| 1852 | if ((temp & LVDS_PORT_EN) == 0) { |
| 1853 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
| 1854 | POSTING_READ(PCH_LVDS); |
| 1855 | } |
| 1856 | } |
| 1857 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1858 | if (HAS_eDP) { |
| 1859 | /* enable eDP PLL */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1860 | ironlake_enable_pll_edp(crtc); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1861 | } else { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1862 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1863 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
| 1864 | temp = I915_READ(fdi_rx_reg); |
Zhao Yakui | 8faf3b3 | 2010-01-04 16:29:31 +0800 | [diff] [blame] | 1865 | /* |
| 1866 | * make the BPC in FDI Rx be consistent with that in |
| 1867 | * pipeconf reg. |
| 1868 | */ |
| 1869 | temp &= ~(0x7 << 16); |
| 1870 | temp |= (pipe_bpc << 11); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 1871 | temp &= ~(7 << 19); |
| 1872 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
| 1873 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1874 | I915_READ(fdi_rx_reg); |
| 1875 | udelay(200); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1876 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1877 | /* Switch from Rawclk to PCDclk */ |
| 1878 | temp = I915_READ(fdi_rx_reg); |
| 1879 | I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1880 | I915_READ(fdi_rx_reg); |
| 1881 | udelay(200); |
| 1882 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1883 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1884 | temp = I915_READ(fdi_tx_reg); |
| 1885 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 1886 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); |
| 1887 | I915_READ(fdi_tx_reg); |
| 1888 | udelay(100); |
| 1889 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1890 | } |
| 1891 | |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1892 | /* Enable panel fitting for LVDS */ |
| 1893 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 1894 | temp = I915_READ(pf_ctl_reg); |
Zhenyu Wang | b1f60b7 | 2009-10-19 15:43:49 +0800 | [diff] [blame] | 1895 | I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1896 | |
| 1897 | /* currently full aspect */ |
| 1898 | I915_WRITE(pf_win_pos, 0); |
| 1899 | |
| 1900 | I915_WRITE(pf_win_size, |
| 1901 | (dev_priv->panel_fixed_mode->hdisplay << 16) | |
| 1902 | (dev_priv->panel_fixed_mode->vdisplay)); |
| 1903 | } |
| 1904 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1905 | /* Enable CPU pipe */ |
| 1906 | temp = I915_READ(pipeconf_reg); |
| 1907 | if ((temp & PIPEACONF_ENABLE) == 0) { |
| 1908 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); |
| 1909 | I915_READ(pipeconf_reg); |
| 1910 | udelay(100); |
| 1911 | } |
| 1912 | |
| 1913 | /* configure and enable CPU plane */ |
| 1914 | temp = I915_READ(dspcntr_reg); |
| 1915 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
| 1916 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); |
| 1917 | /* Flush the plane changes */ |
| 1918 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 1919 | } |
| 1920 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1921 | if (!HAS_eDP) { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1922 | /* For PCH output, training FDI link */ |
| 1923 | if (IS_GEN6(dev)) |
| 1924 | gen6_fdi_link_train(crtc); |
| 1925 | else |
| 1926 | ironlake_fdi_link_train(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1927 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1928 | /* enable PCH DPLL */ |
| 1929 | temp = I915_READ(pch_dpll_reg); |
| 1930 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
| 1931 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); |
| 1932 | I915_READ(pch_dpll_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1933 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1934 | udelay(200); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1935 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1936 | if (HAS_PCH_CPT(dev)) { |
| 1937 | /* Be sure PCH DPLL SEL is set */ |
| 1938 | temp = I915_READ(PCH_DPLL_SEL); |
| 1939 | if (trans_dpll_sel == 0 && |
| 1940 | (temp & TRANSA_DPLL_ENABLE) == 0) |
| 1941 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
| 1942 | else if (trans_dpll_sel == 1 && |
| 1943 | (temp & TRANSB_DPLL_ENABLE) == 0) |
| 1944 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
| 1945 | I915_WRITE(PCH_DPLL_SEL, temp); |
| 1946 | I915_READ(PCH_DPLL_SEL); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1947 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1948 | |
| 1949 | /* set transcoder timing */ |
| 1950 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); |
| 1951 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); |
| 1952 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); |
| 1953 | |
| 1954 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); |
| 1955 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); |
| 1956 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); |
| 1957 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1958 | /* enable normal train */ |
| 1959 | temp = I915_READ(fdi_tx_reg); |
| 1960 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1961 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | |
| 1962 | FDI_TX_ENHANCE_FRAME_ENABLE); |
| 1963 | I915_READ(fdi_tx_reg); |
| 1964 | |
| 1965 | temp = I915_READ(fdi_rx_reg); |
| 1966 | if (HAS_PCH_CPT(dev)) { |
| 1967 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 1968 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 1969 | } else { |
| 1970 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1971 | temp |= FDI_LINK_TRAIN_NONE; |
| 1972 | } |
| 1973 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 1974 | I915_READ(fdi_rx_reg); |
| 1975 | |
| 1976 | /* wait one idle pattern time */ |
| 1977 | udelay(100); |
| 1978 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1979 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 1980 | if (HAS_PCH_CPT(dev) && |
| 1981 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 1982 | int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; |
| 1983 | int reg; |
| 1984 | |
| 1985 | reg = I915_READ(trans_dp_ctl); |
| 1986 | reg &= ~TRANS_DP_PORT_SEL_MASK; |
| 1987 | reg = TRANS_DP_OUTPUT_ENABLE | |
| 1988 | TRANS_DP_ENH_FRAMING | |
| 1989 | TRANS_DP_VSYNC_ACTIVE_HIGH | |
| 1990 | TRANS_DP_HSYNC_ACTIVE_HIGH; |
| 1991 | |
| 1992 | switch (intel_trans_dp_port_sel(crtc)) { |
| 1993 | case PCH_DP_B: |
| 1994 | reg |= TRANS_DP_PORT_SEL_B; |
| 1995 | break; |
| 1996 | case PCH_DP_C: |
| 1997 | reg |= TRANS_DP_PORT_SEL_C; |
| 1998 | break; |
| 1999 | case PCH_DP_D: |
| 2000 | reg |= TRANS_DP_PORT_SEL_D; |
| 2001 | break; |
| 2002 | default: |
| 2003 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
| 2004 | reg |= TRANS_DP_PORT_SEL_B; |
| 2005 | break; |
| 2006 | } |
| 2007 | |
| 2008 | I915_WRITE(trans_dp_ctl, reg); |
| 2009 | POSTING_READ(trans_dp_ctl); |
| 2010 | } |
| 2011 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2012 | /* enable PCH transcoder */ |
| 2013 | temp = I915_READ(transconf_reg); |
Zhao Yakui | 8faf3b3 | 2010-01-04 16:29:31 +0800 | [diff] [blame] | 2014 | /* |
| 2015 | * make the BPC in transcoder be consistent with |
| 2016 | * that in pipeconf reg. |
| 2017 | */ |
| 2018 | temp &= ~PIPE_BPC_MASK; |
| 2019 | temp |= pipe_bpc; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2020 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); |
| 2021 | I915_READ(transconf_reg); |
| 2022 | |
| 2023 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) |
| 2024 | ; |
| 2025 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2026 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2027 | |
| 2028 | intel_crtc_load_lut(crtc); |
| 2029 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 2030 | intel_update_fbc(crtc, &crtc->mode); |
| 2031 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2032 | break; |
| 2033 | case DRM_MODE_DPMS_OFF: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2034 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2035 | |
Li Peng | c062df6 | 2010-01-23 00:12:58 +0800 | [diff] [blame] | 2036 | drm_vblank_off(dev, pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2037 | /* Disable display plane */ |
| 2038 | temp = I915_READ(dspcntr_reg); |
| 2039 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
| 2040 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); |
| 2041 | /* Flush the plane changes */ |
| 2042 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 2043 | I915_READ(dspbase_reg); |
| 2044 | } |
| 2045 | |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 2046 | if (dev_priv->cfb_plane == plane && |
| 2047 | dev_priv->display.disable_fbc) |
| 2048 | dev_priv->display.disable_fbc(dev); |
| 2049 | |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2050 | i915_disable_vga(dev); |
| 2051 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2052 | /* disable cpu pipe, disable after all planes disabled */ |
| 2053 | temp = I915_READ(pipeconf_reg); |
| 2054 | if ((temp & PIPEACONF_ENABLE) != 0) { |
| 2055 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); |
| 2056 | I915_READ(pipeconf_reg); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2057 | n = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2058 | /* wait for cpu pipe off, pipe state */ |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2059 | while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { |
| 2060 | n++; |
| 2061 | if (n < 60) { |
| 2062 | udelay(500); |
| 2063 | continue; |
| 2064 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2065 | DRM_DEBUG_KMS("pipe %d off delay\n", |
| 2066 | pipe); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2067 | break; |
| 2068 | } |
| 2069 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2070 | } else |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2071 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2072 | |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2073 | udelay(100); |
| 2074 | |
| 2075 | /* Disable PF */ |
| 2076 | temp = I915_READ(pf_ctl_reg); |
| 2077 | if ((temp & PF_ENABLE) != 0) { |
| 2078 | I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); |
| 2079 | I915_READ(pf_ctl_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2080 | } |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2081 | I915_WRITE(pf_win_size, 0); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2082 | POSTING_READ(pf_win_size); |
| 2083 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2084 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2085 | /* disable CPU FDI tx and PCH FDI rx */ |
| 2086 | temp = I915_READ(fdi_tx_reg); |
| 2087 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); |
| 2088 | I915_READ(fdi_tx_reg); |
| 2089 | |
| 2090 | temp = I915_READ(fdi_rx_reg); |
Zhao Yakui | 8faf3b3 | 2010-01-04 16:29:31 +0800 | [diff] [blame] | 2091 | /* BPC in FDI rx is consistent with that in pipeconf */ |
| 2092 | temp &= ~(0x07 << 16); |
| 2093 | temp |= (pipe_bpc << 11); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2094 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); |
| 2095 | I915_READ(fdi_rx_reg); |
| 2096 | |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2097 | udelay(100); |
| 2098 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2099 | /* still set train pattern 1 */ |
| 2100 | temp = I915_READ(fdi_tx_reg); |
| 2101 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2102 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2103 | I915_WRITE(fdi_tx_reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2104 | POSTING_READ(fdi_tx_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2105 | |
| 2106 | temp = I915_READ(fdi_rx_reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2107 | if (HAS_PCH_CPT(dev)) { |
| 2108 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2109 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2110 | } else { |
| 2111 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2112 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2113 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2114 | I915_WRITE(fdi_rx_reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2115 | POSTING_READ(fdi_rx_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2116 | |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2117 | udelay(100); |
| 2118 | |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2119 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 2120 | temp = I915_READ(PCH_LVDS); |
| 2121 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); |
| 2122 | I915_READ(PCH_LVDS); |
| 2123 | udelay(100); |
| 2124 | } |
| 2125 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2126 | /* disable PCH transcoder */ |
| 2127 | temp = I915_READ(transconf_reg); |
| 2128 | if ((temp & TRANS_ENABLE) != 0) { |
| 2129 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); |
| 2130 | I915_READ(transconf_reg); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2131 | n = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2132 | /* wait for PCH transcoder off, transcoder state */ |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2133 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { |
| 2134 | n++; |
| 2135 | if (n < 60) { |
| 2136 | udelay(500); |
| 2137 | continue; |
| 2138 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2139 | DRM_DEBUG_KMS("transcoder %d off " |
| 2140 | "delay\n", pipe); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2141 | break; |
| 2142 | } |
| 2143 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2144 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2145 | |
Zhao Yakui | 8faf3b3 | 2010-01-04 16:29:31 +0800 | [diff] [blame] | 2146 | temp = I915_READ(transconf_reg); |
| 2147 | /* BPC in transcoder is consistent with that in pipeconf */ |
| 2148 | temp &= ~PIPE_BPC_MASK; |
| 2149 | temp |= pipe_bpc; |
| 2150 | I915_WRITE(transconf_reg, temp); |
| 2151 | I915_READ(transconf_reg); |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2152 | udelay(100); |
| 2153 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2154 | if (HAS_PCH_CPT(dev)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2155 | /* disable TRANS_DP_CTL */ |
| 2156 | int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; |
| 2157 | int reg; |
| 2158 | |
| 2159 | reg = I915_READ(trans_dp_ctl); |
| 2160 | reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
| 2161 | I915_WRITE(trans_dp_ctl, reg); |
| 2162 | POSTING_READ(trans_dp_ctl); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2163 | |
| 2164 | /* disable DPLL_SEL */ |
| 2165 | temp = I915_READ(PCH_DPLL_SEL); |
| 2166 | if (trans_dpll_sel == 0) |
| 2167 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
| 2168 | else |
| 2169 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
| 2170 | I915_WRITE(PCH_DPLL_SEL, temp); |
| 2171 | I915_READ(PCH_DPLL_SEL); |
| 2172 | |
| 2173 | } |
| 2174 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2175 | /* disable PCH DPLL */ |
| 2176 | temp = I915_READ(pch_dpll_reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2177 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); |
| 2178 | I915_READ(pch_dpll_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2179 | |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2180 | if (HAS_eDP) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2181 | ironlake_disable_pll_edp(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2182 | } |
| 2183 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2184 | /* Switch from PCDclk to Rawclk */ |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2185 | temp = I915_READ(fdi_rx_reg); |
| 2186 | temp &= ~FDI_SEL_PCDCLK; |
| 2187 | I915_WRITE(fdi_rx_reg, temp); |
| 2188 | I915_READ(fdi_rx_reg); |
| 2189 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2190 | /* Disable CPU FDI TX PLL */ |
| 2191 | temp = I915_READ(fdi_tx_reg); |
| 2192 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE); |
| 2193 | I915_READ(fdi_tx_reg); |
| 2194 | udelay(100); |
| 2195 | |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2196 | temp = I915_READ(fdi_rx_reg); |
| 2197 | temp &= ~FDI_RX_PLL_ENABLE; |
| 2198 | I915_WRITE(fdi_rx_reg, temp); |
| 2199 | I915_READ(fdi_rx_reg); |
| 2200 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2201 | /* Wait for the clocks to turn off. */ |
Zhenyu Wang | 1b3c7a4 | 2009-11-25 13:09:38 +0800 | [diff] [blame] | 2202 | udelay(100); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2203 | break; |
| 2204 | } |
| 2205 | } |
| 2206 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2207 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 2208 | { |
| 2209 | struct intel_overlay *overlay; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 2210 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2211 | |
| 2212 | if (!enable && intel_crtc->overlay) { |
| 2213 | overlay = intel_crtc->overlay; |
| 2214 | mutex_lock(&overlay->dev->struct_mutex); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 2215 | for (;;) { |
| 2216 | ret = intel_overlay_switch_off(overlay); |
| 2217 | if (ret == 0) |
| 2218 | break; |
| 2219 | |
| 2220 | ret = intel_overlay_recover_from_interrupt(overlay, 0); |
| 2221 | if (ret != 0) { |
| 2222 | /* overlay doesn't react anymore. Usually |
| 2223 | * results in a black screen and an unkillable |
| 2224 | * X server. */ |
| 2225 | BUG(); |
| 2226 | overlay->hw_wedged = HW_WEDGED; |
| 2227 | break; |
| 2228 | } |
| 2229 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2230 | mutex_unlock(&overlay->dev->struct_mutex); |
| 2231 | } |
| 2232 | /* Let userspace switch the overlay on again. In most cases userspace |
| 2233 | * has to recompute where to put it anyway. */ |
| 2234 | |
| 2235 | return; |
| 2236 | } |
| 2237 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2238 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2239 | { |
| 2240 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2243 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2244 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2245 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2246 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
| 2247 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2248 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 2249 | u32 temp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2250 | |
| 2251 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 2252 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 2253 | */ |
| 2254 | switch (mode) { |
| 2255 | case DRM_MODE_DPMS_ON: |
| 2256 | case DRM_MODE_DPMS_STANDBY: |
| 2257 | case DRM_MODE_DPMS_SUSPEND: |
Jesse Barnes | 629598d | 2009-10-20 07:37:32 +0900 | [diff] [blame] | 2258 | intel_update_watermarks(dev); |
| 2259 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2260 | /* Enable the DPLL */ |
| 2261 | temp = I915_READ(dpll_reg); |
| 2262 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
| 2263 | I915_WRITE(dpll_reg, temp); |
| 2264 | I915_READ(dpll_reg); |
| 2265 | /* Wait for the clocks to stabilize. */ |
| 2266 | udelay(150); |
| 2267 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 2268 | I915_READ(dpll_reg); |
| 2269 | /* Wait for the clocks to stabilize. */ |
| 2270 | udelay(150); |
| 2271 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 2272 | I915_READ(dpll_reg); |
| 2273 | /* Wait for the clocks to stabilize. */ |
| 2274 | udelay(150); |
| 2275 | } |
| 2276 | |
| 2277 | /* Enable the pipe */ |
| 2278 | temp = I915_READ(pipeconf_reg); |
| 2279 | if ((temp & PIPEACONF_ENABLE) == 0) |
| 2280 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); |
| 2281 | |
| 2282 | /* Enable the plane */ |
| 2283 | temp = I915_READ(dspcntr_reg); |
| 2284 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
| 2285 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); |
| 2286 | /* Flush the plane changes */ |
| 2287 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 2288 | } |
| 2289 | |
| 2290 | intel_crtc_load_lut(crtc); |
| 2291 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 2292 | if ((IS_I965G(dev) || plane == 0)) |
| 2293 | intel_update_fbc(crtc, &crtc->mode); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2294 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2295 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2296 | intel_crtc_dpms_overlay(intel_crtc, true); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2297 | break; |
| 2298 | case DRM_MODE_DPMS_OFF: |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2299 | intel_update_watermarks(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2300 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2301 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2302 | intel_crtc_dpms_overlay(intel_crtc, false); |
Li Peng | 778c902 | 2009-11-09 12:51:22 +0800 | [diff] [blame] | 2303 | drm_vblank_off(dev, pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2304 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2305 | if (dev_priv->cfb_plane == plane && |
| 2306 | dev_priv->display.disable_fbc) |
| 2307 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2308 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2309 | /* Disable the VGA plane that we never use */ |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 2310 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2311 | |
| 2312 | /* Disable display plane */ |
| 2313 | temp = I915_READ(dspcntr_reg); |
| 2314 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
| 2315 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); |
| 2316 | /* Flush the plane changes */ |
| 2317 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 2318 | I915_READ(dspbase_reg); |
| 2319 | } |
| 2320 | |
| 2321 | if (!IS_I9XX(dev)) { |
| 2322 | /* Wait for vblank for the disable to take effect */ |
| 2323 | intel_wait_for_vblank(dev); |
| 2324 | } |
| 2325 | |
| 2326 | /* Next, disable display pipes */ |
| 2327 | temp = I915_READ(pipeconf_reg); |
| 2328 | if ((temp & PIPEACONF_ENABLE) != 0) { |
| 2329 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); |
| 2330 | I915_READ(pipeconf_reg); |
| 2331 | } |
| 2332 | |
| 2333 | /* Wait for vblank for the disable to take effect. */ |
| 2334 | intel_wait_for_vblank(dev); |
| 2335 | |
| 2336 | temp = I915_READ(dpll_reg); |
| 2337 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
| 2338 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); |
| 2339 | I915_READ(dpll_reg); |
| 2340 | } |
| 2341 | |
| 2342 | /* Wait for the clocks to turn off. */ |
| 2343 | udelay(150); |
| 2344 | break; |
| 2345 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2346 | } |
| 2347 | |
| 2348 | /** |
| 2349 | * Sets the power management mode of the pipe and plane. |
| 2350 | * |
| 2351 | * This code should probably grow support for turning the cursor off and back |
| 2352 | * on appropriately at the same time as we're turning the pipe off/on. |
| 2353 | */ |
| 2354 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2355 | { |
| 2356 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2357 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2358 | struct drm_i915_master_private *master_priv; |
| 2359 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2360 | int pipe = intel_crtc->pipe; |
| 2361 | bool enabled; |
| 2362 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2363 | dev_priv->display.dpms(crtc, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2364 | |
Daniel Vetter | 65655d4 | 2009-08-11 16:05:31 +0200 | [diff] [blame] | 2365 | intel_crtc->dpms_mode = mode; |
| 2366 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2367 | if (!dev->primary->master) |
| 2368 | return; |
| 2369 | |
| 2370 | master_priv = dev->primary->master->driver_priv; |
| 2371 | if (!master_priv->sarea_priv) |
| 2372 | return; |
| 2373 | |
| 2374 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 2375 | |
| 2376 | switch (pipe) { |
| 2377 | case 0: |
| 2378 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 2379 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 2380 | break; |
| 2381 | case 1: |
| 2382 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 2383 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 2384 | break; |
| 2385 | default: |
| 2386 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); |
| 2387 | break; |
| 2388 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2389 | } |
| 2390 | |
| 2391 | static void intel_crtc_prepare (struct drm_crtc *crtc) |
| 2392 | { |
| 2393 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 2394 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 2395 | } |
| 2396 | |
| 2397 | static void intel_crtc_commit (struct drm_crtc *crtc) |
| 2398 | { |
| 2399 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 2400 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 2401 | } |
| 2402 | |
| 2403 | void intel_encoder_prepare (struct drm_encoder *encoder) |
| 2404 | { |
| 2405 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 2406 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
| 2407 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 2408 | } |
| 2409 | |
| 2410 | void intel_encoder_commit (struct drm_encoder *encoder) |
| 2411 | { |
| 2412 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 2413 | /* lvds has its own version of commit see intel_lvds_commit */ |
| 2414 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 2415 | } |
| 2416 | |
| 2417 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 2418 | struct drm_display_mode *mode, |
| 2419 | struct drm_display_mode *adjusted_mode) |
| 2420 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2421 | struct drm_device *dev = crtc->dev; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2422 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2423 | /* FDI link clock is fixed at 2.7G */ |
| 2424 | if (mode->clock * 3 > 27000 * 4) |
| 2425 | return MODE_CLOCK_HIGH; |
| 2426 | } |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 2427 | |
| 2428 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2429 | return true; |
| 2430 | } |
| 2431 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2432 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2433 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2434 | return 400000; |
| 2435 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2436 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2437 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 2438 | { |
| 2439 | return 333000; |
| 2440 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2441 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2442 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 2443 | { |
| 2444 | return 200000; |
| 2445 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2446 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2447 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 2448 | { |
| 2449 | u16 gcfgc = 0; |
| 2450 | |
| 2451 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 2452 | |
| 2453 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2454 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2455 | else { |
| 2456 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 2457 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 2458 | return 333000; |
| 2459 | default: |
| 2460 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 2461 | return 190000; |
| 2462 | } |
| 2463 | } |
| 2464 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2465 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2466 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 2467 | { |
| 2468 | return 266000; |
| 2469 | } |
| 2470 | |
| 2471 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 2472 | { |
| 2473 | u16 hpllcc = 0; |
| 2474 | /* Assume that the hardware is in the high speed state. This |
| 2475 | * should be the default. |
| 2476 | */ |
| 2477 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 2478 | case GC_CLOCK_133_200: |
| 2479 | case GC_CLOCK_100_200: |
| 2480 | return 200000; |
| 2481 | case GC_CLOCK_166_250: |
| 2482 | return 250000; |
| 2483 | case GC_CLOCK_100_133: |
| 2484 | return 133000; |
| 2485 | } |
| 2486 | |
| 2487 | /* Shouldn't happen */ |
| 2488 | return 0; |
| 2489 | } |
| 2490 | |
| 2491 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 2492 | { |
| 2493 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2494 | } |
| 2495 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2496 | /** |
| 2497 | * Return the pipe currently connected to the panel fitter, |
| 2498 | * or -1 if the panel fitter is not present or not in use |
| 2499 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2500 | int intel_panel_fitter_pipe (struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2501 | { |
| 2502 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2503 | u32 pfit_control; |
| 2504 | |
| 2505 | /* i830 doesn't have a panel fitter */ |
| 2506 | if (IS_I830(dev)) |
| 2507 | return -1; |
| 2508 | |
| 2509 | pfit_control = I915_READ(PFIT_CONTROL); |
| 2510 | |
| 2511 | /* See if the panel fitter is in use */ |
| 2512 | if ((pfit_control & PFIT_ENABLE) == 0) |
| 2513 | return -1; |
| 2514 | |
| 2515 | /* 965 can place panel fitter on either pipe */ |
| 2516 | if (IS_I965G(dev)) |
| 2517 | return (pfit_control >> 29) & 0x3; |
| 2518 | |
| 2519 | /* older chips can only use pipe 1 */ |
| 2520 | return 1; |
| 2521 | } |
| 2522 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2523 | struct fdi_m_n { |
| 2524 | u32 tu; |
| 2525 | u32 gmch_m; |
| 2526 | u32 gmch_n; |
| 2527 | u32 link_m; |
| 2528 | u32 link_n; |
| 2529 | }; |
| 2530 | |
| 2531 | static void |
| 2532 | fdi_reduce_ratio(u32 *num, u32 *den) |
| 2533 | { |
| 2534 | while (*num > 0xffffff || *den > 0xffffff) { |
| 2535 | *num >>= 1; |
| 2536 | *den >>= 1; |
| 2537 | } |
| 2538 | } |
| 2539 | |
| 2540 | #define DATA_N 0x800000 |
| 2541 | #define LINK_N 0x80000 |
| 2542 | |
| 2543 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2544 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
| 2545 | int link_clock, struct fdi_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2546 | { |
| 2547 | u64 temp; |
| 2548 | |
| 2549 | m_n->tu = 64; /* default size */ |
| 2550 | |
| 2551 | temp = (u64) DATA_N * pixel_clock; |
| 2552 | temp = div_u64(temp, link_clock); |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2553 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
| 2554 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2555 | m_n->gmch_n = DATA_N; |
| 2556 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 2557 | |
| 2558 | temp = (u64) LINK_N * pixel_clock; |
| 2559 | m_n->link_m = div_u64(temp, link_clock); |
| 2560 | m_n->link_n = LINK_N; |
| 2561 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 2562 | } |
| 2563 | |
| 2564 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2565 | struct intel_watermark_params { |
| 2566 | unsigned long fifo_size; |
| 2567 | unsigned long max_wm; |
| 2568 | unsigned long default_wm; |
| 2569 | unsigned long guard_size; |
| 2570 | unsigned long cacheline_size; |
| 2571 | }; |
| 2572 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2573 | /* Pineview has different values for various configs */ |
| 2574 | static struct intel_watermark_params pineview_display_wm = { |
| 2575 | PINEVIEW_DISPLAY_FIFO, |
| 2576 | PINEVIEW_MAX_WM, |
| 2577 | PINEVIEW_DFT_WM, |
| 2578 | PINEVIEW_GUARD_WM, |
| 2579 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2580 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2581 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
| 2582 | PINEVIEW_DISPLAY_FIFO, |
| 2583 | PINEVIEW_MAX_WM, |
| 2584 | PINEVIEW_DFT_HPLLOFF_WM, |
| 2585 | PINEVIEW_GUARD_WM, |
| 2586 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2587 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2588 | static struct intel_watermark_params pineview_cursor_wm = { |
| 2589 | PINEVIEW_CURSOR_FIFO, |
| 2590 | PINEVIEW_CURSOR_MAX_WM, |
| 2591 | PINEVIEW_CURSOR_DFT_WM, |
| 2592 | PINEVIEW_CURSOR_GUARD_WM, |
| 2593 | PINEVIEW_FIFO_LINE_SIZE, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2594 | }; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2595 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
| 2596 | PINEVIEW_CURSOR_FIFO, |
| 2597 | PINEVIEW_CURSOR_MAX_WM, |
| 2598 | PINEVIEW_CURSOR_DFT_WM, |
| 2599 | PINEVIEW_CURSOR_GUARD_WM, |
| 2600 | PINEVIEW_FIFO_LINE_SIZE |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2601 | }; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2602 | static struct intel_watermark_params g4x_wm_info = { |
| 2603 | G4X_FIFO_SIZE, |
| 2604 | G4X_MAX_WM, |
| 2605 | G4X_MAX_WM, |
| 2606 | 2, |
| 2607 | G4X_FIFO_LINE_SIZE, |
| 2608 | }; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 2609 | static struct intel_watermark_params g4x_cursor_wm_info = { |
| 2610 | I965_CURSOR_FIFO, |
| 2611 | I965_CURSOR_MAX_WM, |
| 2612 | I965_CURSOR_DFT_WM, |
| 2613 | 2, |
| 2614 | G4X_FIFO_LINE_SIZE, |
| 2615 | }; |
| 2616 | static struct intel_watermark_params i965_cursor_wm_info = { |
| 2617 | I965_CURSOR_FIFO, |
| 2618 | I965_CURSOR_MAX_WM, |
| 2619 | I965_CURSOR_DFT_WM, |
| 2620 | 2, |
| 2621 | I915_FIFO_LINE_SIZE, |
| 2622 | }; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2623 | static struct intel_watermark_params i945_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2624 | I945_FIFO_SIZE, |
| 2625 | I915_MAX_WM, |
| 2626 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2627 | 2, |
| 2628 | I915_FIFO_LINE_SIZE |
| 2629 | }; |
| 2630 | static struct intel_watermark_params i915_wm_info = { |
| 2631 | I915_FIFO_SIZE, |
| 2632 | I915_MAX_WM, |
| 2633 | 1, |
| 2634 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2635 | I915_FIFO_LINE_SIZE |
| 2636 | }; |
| 2637 | static struct intel_watermark_params i855_wm_info = { |
| 2638 | I855GM_FIFO_SIZE, |
| 2639 | I915_MAX_WM, |
| 2640 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2641 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2642 | I830_FIFO_LINE_SIZE |
| 2643 | }; |
| 2644 | static struct intel_watermark_params i830_wm_info = { |
| 2645 | I830_FIFO_SIZE, |
| 2646 | I915_MAX_WM, |
| 2647 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2648 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2649 | I830_FIFO_LINE_SIZE |
| 2650 | }; |
| 2651 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2652 | static struct intel_watermark_params ironlake_display_wm_info = { |
| 2653 | ILK_DISPLAY_FIFO, |
| 2654 | ILK_DISPLAY_MAXWM, |
| 2655 | ILK_DISPLAY_DFTWM, |
| 2656 | 2, |
| 2657 | ILK_FIFO_LINE_SIZE |
| 2658 | }; |
| 2659 | |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 2660 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
| 2661 | ILK_CURSOR_FIFO, |
| 2662 | ILK_CURSOR_MAXWM, |
| 2663 | ILK_CURSOR_DFTWM, |
| 2664 | 2, |
| 2665 | ILK_FIFO_LINE_SIZE |
| 2666 | }; |
| 2667 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2668 | static struct intel_watermark_params ironlake_display_srwm_info = { |
| 2669 | ILK_DISPLAY_SR_FIFO, |
| 2670 | ILK_DISPLAY_MAX_SRWM, |
| 2671 | ILK_DISPLAY_DFT_SRWM, |
| 2672 | 2, |
| 2673 | ILK_FIFO_LINE_SIZE |
| 2674 | }; |
| 2675 | |
| 2676 | static struct intel_watermark_params ironlake_cursor_srwm_info = { |
| 2677 | ILK_CURSOR_SR_FIFO, |
| 2678 | ILK_CURSOR_MAX_SRWM, |
| 2679 | ILK_CURSOR_DFT_SRWM, |
| 2680 | 2, |
| 2681 | ILK_FIFO_LINE_SIZE |
| 2682 | }; |
| 2683 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2684 | /** |
| 2685 | * intel_calculate_wm - calculate watermark level |
| 2686 | * @clock_in_khz: pixel clock |
| 2687 | * @wm: chip FIFO params |
| 2688 | * @pixel_size: display pixel size |
| 2689 | * @latency_ns: memory latency for the platform |
| 2690 | * |
| 2691 | * Calculate the watermark level (the level at which the display plane will |
| 2692 | * start fetching from memory again). Each chip has a different display |
| 2693 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 2694 | * in the correct intel_watermark_params structure. |
| 2695 | * |
| 2696 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 2697 | * on the pixel size. When it reaches the watermark level, it'll start |
| 2698 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 2699 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 2700 | * will occur, and a display engine hang could result. |
| 2701 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2702 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 2703 | struct intel_watermark_params *wm, |
| 2704 | int pixel_size, |
| 2705 | unsigned long latency_ns) |
| 2706 | { |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2707 | long entries_required, wm_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2708 | |
Jesse Barnes | d660467 | 2009-09-11 12:25:56 -0700 | [diff] [blame] | 2709 | /* |
| 2710 | * Note: we need to make sure we don't overflow for various clock & |
| 2711 | * latency values. |
| 2712 | * clocks go from a few thousand to several hundred thousand. |
| 2713 | * latency is usually a few thousand |
| 2714 | */ |
| 2715 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 2716 | 1000; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2717 | entries_required /= wm->cacheline_size; |
| 2718 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2719 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2720 | |
| 2721 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); |
| 2722 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2723 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2724 | |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2725 | /* Don't promote wm_size to unsigned... */ |
| 2726 | if (wm_size > (long)wm->max_wm) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2727 | wm_size = wm->max_wm; |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2728 | if (wm_size <= 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2729 | wm_size = wm->default_wm; |
| 2730 | return wm_size; |
| 2731 | } |
| 2732 | |
| 2733 | struct cxsr_latency { |
| 2734 | int is_desktop; |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2735 | int is_ddr3; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2736 | unsigned long fsb_freq; |
| 2737 | unsigned long mem_freq; |
| 2738 | unsigned long display_sr; |
| 2739 | unsigned long display_hpll_disable; |
| 2740 | unsigned long cursor_sr; |
| 2741 | unsigned long cursor_hpll_disable; |
| 2742 | }; |
| 2743 | |
| 2744 | static struct cxsr_latency cxsr_latency_table[] = { |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2745 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 2746 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 2747 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 2748 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 2749 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2750 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2751 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 2752 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 2753 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 2754 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 2755 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2756 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2757 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 2758 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 2759 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 2760 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 2761 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2762 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2763 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 2764 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 2765 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 2766 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 2767 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2768 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2769 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 2770 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 2771 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 2772 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 2773 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2774 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2775 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 2776 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 2777 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 2778 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 2779 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2780 | }; |
| 2781 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2782 | static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, |
| 2783 | int fsb, int mem) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2784 | { |
| 2785 | int i; |
| 2786 | struct cxsr_latency *latency; |
| 2787 | |
| 2788 | if (fsb == 0 || mem == 0) |
| 2789 | return NULL; |
| 2790 | |
| 2791 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 2792 | latency = &cxsr_latency_table[i]; |
| 2793 | if (is_desktop == latency->is_desktop && |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2794 | is_ddr3 == latency->is_ddr3 && |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2795 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 2796 | return latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2797 | } |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2798 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2799 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2800 | |
| 2801 | return NULL; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2802 | } |
| 2803 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2804 | static void pineview_disable_cxsr(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2805 | { |
| 2806 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2807 | u32 reg; |
| 2808 | |
| 2809 | /* deactivate cxsr */ |
| 2810 | reg = I915_READ(DSPFW3); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2811 | reg &= ~(PINEVIEW_SELF_REFRESH_EN); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2812 | I915_WRITE(DSPFW3, reg); |
| 2813 | DRM_INFO("Big FIFO is disabled\n"); |
| 2814 | } |
| 2815 | |
Jesse Barnes | bcc24fb | 2009-08-31 10:24:31 -0700 | [diff] [blame] | 2816 | /* |
| 2817 | * Latency for FIFO fetches is dependent on several factors: |
| 2818 | * - memory configuration (speed, channels) |
| 2819 | * - chipset |
| 2820 | * - current MCH state |
| 2821 | * It can be fairly high in some situations, so here we assume a fairly |
| 2822 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 2823 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 2824 | * and power consumption (set it too low to save power and we might see |
| 2825 | * FIFO underruns and display "flicker"). |
| 2826 | * |
| 2827 | * A value of 5us seems to be a good balance; safe for very low end |
| 2828 | * platforms but not overly aggressive on lower latency configs. |
| 2829 | */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 2830 | static const int latency_ns = 5000; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2831 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2832 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2833 | { |
| 2834 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2835 | uint32_t dsparb = I915_READ(DSPARB); |
| 2836 | int size; |
| 2837 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2838 | if (plane == 0) |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 2839 | size = dsparb & 0x7f; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2840 | else |
| 2841 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - |
| 2842 | (dsparb & 0x7f); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2843 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2844 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2845 | plane ? "B" : "A", size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2846 | |
| 2847 | return size; |
| 2848 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2849 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2850 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
| 2851 | { |
| 2852 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2853 | uint32_t dsparb = I915_READ(DSPARB); |
| 2854 | int size; |
| 2855 | |
| 2856 | if (plane == 0) |
| 2857 | size = dsparb & 0x1ff; |
| 2858 | else |
| 2859 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - |
| 2860 | (dsparb & 0x1ff); |
| 2861 | size >>= 1; /* Convert to cachelines */ |
| 2862 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2863 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2864 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2865 | |
| 2866 | return size; |
| 2867 | } |
| 2868 | |
| 2869 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
| 2870 | { |
| 2871 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2872 | uint32_t dsparb = I915_READ(DSPARB); |
| 2873 | int size; |
| 2874 | |
| 2875 | size = dsparb & 0x7f; |
| 2876 | size >>= 2; /* Convert to cachelines */ |
| 2877 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2878 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2879 | plane ? "B" : "A", |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2880 | size); |
| 2881 | |
| 2882 | return size; |
| 2883 | } |
| 2884 | |
| 2885 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
| 2886 | { |
| 2887 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2888 | uint32_t dsparb = I915_READ(DSPARB); |
| 2889 | int size; |
| 2890 | |
| 2891 | size = dsparb & 0x7f; |
| 2892 | size >>= 1; /* Convert to cachelines */ |
| 2893 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2894 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2895 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2896 | |
| 2897 | return size; |
| 2898 | } |
| 2899 | |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2900 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 2901 | int planeb_clock, int sr_hdisplay, int unused, |
| 2902 | int pixel_size) |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2903 | { |
| 2904 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2905 | u32 reg; |
| 2906 | unsigned long wm; |
| 2907 | struct cxsr_latency *latency; |
| 2908 | int sr_clock; |
| 2909 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 2910 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 2911 | dev_priv->fsb_freq, dev_priv->mem_freq); |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2912 | if (!latency) { |
| 2913 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 2914 | pineview_disable_cxsr(dev); |
| 2915 | return; |
| 2916 | } |
| 2917 | |
| 2918 | if (!planea_clock || !planeb_clock) { |
| 2919 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
| 2920 | |
| 2921 | /* Display SR */ |
| 2922 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, |
| 2923 | pixel_size, latency->display_sr); |
| 2924 | reg = I915_READ(DSPFW1); |
| 2925 | reg &= ~DSPFW_SR_MASK; |
| 2926 | reg |= wm << DSPFW_SR_SHIFT; |
| 2927 | I915_WRITE(DSPFW1, reg); |
| 2928 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 2929 | |
| 2930 | /* cursor SR */ |
| 2931 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, |
| 2932 | pixel_size, latency->cursor_sr); |
| 2933 | reg = I915_READ(DSPFW3); |
| 2934 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 2935 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 2936 | I915_WRITE(DSPFW3, reg); |
| 2937 | |
| 2938 | /* Display HPLL off SR */ |
| 2939 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, |
| 2940 | pixel_size, latency->display_hpll_disable); |
| 2941 | reg = I915_READ(DSPFW3); |
| 2942 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 2943 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 2944 | I915_WRITE(DSPFW3, reg); |
| 2945 | |
| 2946 | /* cursor HPLL off SR */ |
| 2947 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, |
| 2948 | pixel_size, latency->cursor_hpll_disable); |
| 2949 | reg = I915_READ(DSPFW3); |
| 2950 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 2951 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 2952 | I915_WRITE(DSPFW3, reg); |
| 2953 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 2954 | |
| 2955 | /* activate cxsr */ |
| 2956 | reg = I915_READ(DSPFW3); |
| 2957 | reg |= PINEVIEW_SELF_REFRESH_EN; |
| 2958 | I915_WRITE(DSPFW3, reg); |
| 2959 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 2960 | } else { |
| 2961 | pineview_disable_cxsr(dev); |
| 2962 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 2963 | } |
| 2964 | } |
| 2965 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2966 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 2967 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 2968 | int pixel_size) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2969 | { |
| 2970 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2971 | int total_size, cacheline_size; |
| 2972 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; |
| 2973 | struct intel_watermark_params planea_params, planeb_params; |
| 2974 | unsigned long line_time_us; |
| 2975 | int sr_clock, sr_entries = 0, entries_required; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2976 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2977 | /* Create copies of the base settings for each pipe */ |
| 2978 | planea_params = planeb_params = g4x_wm_info; |
| 2979 | |
| 2980 | /* Grab a couple of global values before we overwrite them */ |
| 2981 | total_size = planea_params.fifo_size; |
| 2982 | cacheline_size = planea_params.cacheline_size; |
| 2983 | |
| 2984 | /* |
| 2985 | * Note: we need to make sure we don't overflow for various clock & |
| 2986 | * latency values. |
| 2987 | * clocks go from a few thousand to several hundred thousand. |
| 2988 | * latency is usually a few thousand |
| 2989 | */ |
| 2990 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / |
| 2991 | 1000; |
| 2992 | entries_required /= G4X_FIFO_LINE_SIZE; |
| 2993 | planea_wm = entries_required + planea_params.guard_size; |
| 2994 | |
| 2995 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / |
| 2996 | 1000; |
| 2997 | entries_required /= G4X_FIFO_LINE_SIZE; |
| 2998 | planeb_wm = entries_required + planeb_params.guard_size; |
| 2999 | |
| 3000 | cursora_wm = cursorb_wm = 16; |
| 3001 | cursor_sr = 32; |
| 3002 | |
| 3003 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 3004 | |
| 3005 | /* Calc sr entries for one plane configs */ |
| 3006 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 3007 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3008 | static const int sr_latency_ns = 12000; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3009 | |
| 3010 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3011 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3012 | |
| 3013 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3014 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 3015 | pixel_size * sr_hdisplay; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3016 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3017 | |
| 3018 | entries_required = (((sr_latency_ns / line_time_us) + |
| 3019 | 1000) / 1000) * pixel_size * 64; |
| 3020 | entries_required = roundup(entries_required / |
| 3021 | g4x_cursor_wm_info.cacheline_size, 1); |
| 3022 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
| 3023 | |
| 3024 | if (cursor_sr > g4x_cursor_wm_info.max_wm) |
| 3025 | cursor_sr = g4x_cursor_wm_info.max_wm; |
| 3026 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 3027 | "cursor %d\n", sr_entries, cursor_sr); |
| 3028 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3029 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3030 | } else { |
| 3031 | /* Turn off self refresh if both pipes are enabled */ |
| 3032 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 3033 | & ~FW_BLC_SELF_EN); |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 3034 | } |
| 3035 | |
| 3036 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", |
| 3037 | planea_wm, planeb_wm, sr_entries); |
| 3038 | |
| 3039 | planea_wm &= 0x3f; |
| 3040 | planeb_wm &= 0x3f; |
| 3041 | |
| 3042 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | |
| 3043 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 3044 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); |
| 3045 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
| 3046 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 3047 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 3048 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
| 3049 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3050 | } |
| 3051 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3052 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3053 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3054 | int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3055 | { |
| 3056 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3057 | unsigned long line_time_us; |
| 3058 | int sr_clock, sr_entries, srwm = 1; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3059 | int cursor_sr = 16; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3060 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3061 | /* Calc sr entries for one plane configs */ |
| 3062 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 3063 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3064 | static const int sr_latency_ns = 12000; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3065 | |
| 3066 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3067 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3068 | |
| 3069 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3070 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 3071 | pixel_size * sr_hdisplay; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3072 | sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1); |
| 3073 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 3074 | srwm = I965_FIFO_SIZE - sr_entries; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3075 | if (srwm < 0) |
| 3076 | srwm = 1; |
Zhao Yakui | 1b07e04 | 2010-06-12 14:32:24 +0800 | [diff] [blame] | 3077 | srwm &= 0x1ff; |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3078 | |
| 3079 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 3080 | pixel_size * 64; |
| 3081 | sr_entries = roundup(sr_entries / |
| 3082 | i965_cursor_wm_info.cacheline_size, 1); |
| 3083 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 3084 | (sr_entries + i965_cursor_wm_info.guard_size); |
| 3085 | |
| 3086 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 3087 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 3088 | |
| 3089 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 3090 | "cursor %d\n", srwm, cursor_sr); |
| 3091 | |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 3092 | if (IS_I965GM(dev)) |
| 3093 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3094 | } else { |
| 3095 | /* Turn off self refresh if both pipes are enabled */ |
Jesse Barnes | adcdbc6 | 2010-06-30 13:49:37 -0700 | [diff] [blame] | 3096 | if (IS_I965GM(dev)) |
| 3097 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 3098 | & ~FW_BLC_SELF_EN); |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3099 | } |
| 3100 | |
| 3101 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 3102 | srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3103 | |
| 3104 | /* 965 has limitations... */ |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 3105 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
| 3106 | (8 << 0)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3107 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
Zhao Yakui | 4fe5e61 | 2010-06-12 14:32:25 +0800 | [diff] [blame] | 3108 | /* update cursor SR watermark */ |
| 3109 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3110 | } |
| 3111 | |
| 3112 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3113 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3114 | int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3115 | { |
| 3116 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3117 | uint32_t fwater_lo; |
| 3118 | uint32_t fwater_hi; |
| 3119 | int total_size, cacheline_size, cwm, srwm = 1; |
| 3120 | int planea_wm, planeb_wm; |
| 3121 | struct intel_watermark_params planea_params, planeb_params; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3122 | unsigned long line_time_us; |
| 3123 | int sr_clock, sr_entries = 0; |
| 3124 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3125 | /* Create copies of the base settings for each pipe */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3126 | if (IS_I965GM(dev) || IS_I945GM(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3127 | planea_params = planeb_params = i945_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3128 | else if (IS_I9XX(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3129 | planea_params = planeb_params = i915_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3130 | else |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3131 | planea_params = planeb_params = i855_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3132 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3133 | /* Grab a couple of global values before we overwrite them */ |
| 3134 | total_size = planea_params.fifo_size; |
| 3135 | cacheline_size = planea_params.cacheline_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3136 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3137 | /* Update per-plane FIFO sizes */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3138 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 3139 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3140 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3141 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
| 3142 | pixel_size, latency_ns); |
| 3143 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, |
| 3144 | pixel_size, latency_ns); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3145 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3146 | |
| 3147 | /* |
| 3148 | * Overlay gets an aggressive default since video jitter is bad. |
| 3149 | */ |
| 3150 | cwm = 2; |
| 3151 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3152 | /* Calc sr entries for one plane configs */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3153 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
| 3154 | (!planea_clock || !planeb_clock)) { |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3155 | /* self-refresh has much higher latency */ |
Tobias Klauser | 69e302a | 2009-12-23 14:14:34 +0100 | [diff] [blame] | 3156 | static const int sr_latency_ns = 6000; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3157 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3158 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3159 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3160 | |
| 3161 | /* Use ns/us then divide to preserve precision */ |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3162 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 3163 | pixel_size * sr_hdisplay; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3164 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3165 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3166 | srwm = total_size - sr_entries; |
| 3167 | if (srwm < 0) |
| 3168 | srwm = 1; |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 3169 | |
| 3170 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 3171 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 3172 | else if (IS_I915GM(dev)) { |
| 3173 | /* 915M has a smaller SRWM field */ |
| 3174 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 3175 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
| 3176 | } |
David John | 33c5fd1 | 2010-01-27 15:19:08 +0530 | [diff] [blame] | 3177 | } else { |
| 3178 | /* Turn off self refresh if both pipes are enabled */ |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 3179 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 3180 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 3181 | & ~FW_BLC_SELF_EN); |
| 3182 | } else if (IS_I915GM(dev)) { |
| 3183 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
| 3184 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3185 | } |
| 3186 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3187 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3188 | planea_wm, planeb_wm, cwm, srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3189 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3190 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 3191 | fwater_hi = (cwm & 0x1f); |
| 3192 | |
| 3193 | /* Set request length to 8 cachelines per fetch */ |
| 3194 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 3195 | fwater_hi = fwater_hi | (1 << 8); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3196 | |
| 3197 | I915_WRITE(FW_BLC, fwater_lo); |
| 3198 | I915_WRITE(FW_BLC2, fwater_hi); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3199 | } |
| 3200 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3201 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3202 | int unused2, int unused3, int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3203 | { |
| 3204 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 3205 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3206 | int planea_wm; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3207 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3208 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3209 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 3210 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
| 3211 | pixel_size, latency_ns); |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 3212 | fwater_lo |= (3<<8) | planea_wm; |
| 3213 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3214 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3215 | |
| 3216 | I915_WRITE(FW_BLC, fwater_lo); |
| 3217 | } |
| 3218 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3219 | #define ILK_LP0_PLANE_LATENCY 700 |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3220 | #define ILK_LP0_CURSOR_LATENCY 1300 |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3221 | |
| 3222 | static void ironlake_update_wm(struct drm_device *dev, int planea_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3223 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
| 3224 | int pixel_size) |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3225 | { |
| 3226 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3227 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 3228 | int sr_wm, cursor_wm; |
| 3229 | unsigned long line_time_us; |
| 3230 | int sr_clock, entries_required; |
| 3231 | u32 reg_value; |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3232 | int line_count; |
| 3233 | int planea_htotal = 0, planeb_htotal = 0; |
| 3234 | struct drm_crtc *crtc; |
| 3235 | struct intel_crtc *intel_crtc; |
| 3236 | |
| 3237 | /* Need htotal for all active display plane */ |
| 3238 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 3239 | intel_crtc = to_intel_crtc(crtc); |
| 3240 | if (crtc->enabled) { |
| 3241 | if (intel_crtc->plane == 0) |
| 3242 | planea_htotal = crtc->mode.htotal; |
| 3243 | else |
| 3244 | planeb_htotal = crtc->mode.htotal; |
| 3245 | } |
| 3246 | } |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3247 | |
| 3248 | /* Calculate and update the watermark for plane A */ |
| 3249 | if (planea_clock) { |
| 3250 | entries_required = ((planea_clock / 1000) * pixel_size * |
| 3251 | ILK_LP0_PLANE_LATENCY) / 1000; |
| 3252 | entries_required = DIV_ROUND_UP(entries_required, |
| 3253 | ironlake_display_wm_info.cacheline_size); |
| 3254 | planea_wm = entries_required + |
| 3255 | ironlake_display_wm_info.guard_size; |
| 3256 | |
| 3257 | if (planea_wm > (int)ironlake_display_wm_info.max_wm) |
| 3258 | planea_wm = ironlake_display_wm_info.max_wm; |
| 3259 | |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3260 | /* Use the large buffer method to calculate cursor watermark */ |
| 3261 | line_time_us = (planea_htotal * 1000) / planea_clock; |
| 3262 | |
| 3263 | /* Use ns/us then divide to preserve precision */ |
| 3264 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; |
| 3265 | |
| 3266 | /* calculate the cursor watermark for cursor A */ |
| 3267 | entries_required = line_count * 64 * pixel_size; |
| 3268 | entries_required = DIV_ROUND_UP(entries_required, |
| 3269 | ironlake_cursor_wm_info.cacheline_size); |
| 3270 | cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size; |
| 3271 | if (cursora_wm > ironlake_cursor_wm_info.max_wm) |
| 3272 | cursora_wm = ironlake_cursor_wm_info.max_wm; |
| 3273 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3274 | reg_value = I915_READ(WM0_PIPEA_ILK); |
| 3275 | reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 3276 | reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) | |
| 3277 | (cursora_wm & WM0_PIPE_CURSOR_MASK); |
| 3278 | I915_WRITE(WM0_PIPEA_ILK, reg_value); |
| 3279 | DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, " |
| 3280 | "cursor: %d\n", planea_wm, cursora_wm); |
| 3281 | } |
| 3282 | /* Calculate and update the watermark for plane B */ |
| 3283 | if (planeb_clock) { |
| 3284 | entries_required = ((planeb_clock / 1000) * pixel_size * |
| 3285 | ILK_LP0_PLANE_LATENCY) / 1000; |
| 3286 | entries_required = DIV_ROUND_UP(entries_required, |
| 3287 | ironlake_display_wm_info.cacheline_size); |
| 3288 | planeb_wm = entries_required + |
| 3289 | ironlake_display_wm_info.guard_size; |
| 3290 | |
| 3291 | if (planeb_wm > (int)ironlake_display_wm_info.max_wm) |
| 3292 | planeb_wm = ironlake_display_wm_info.max_wm; |
| 3293 | |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3294 | /* Use the large buffer method to calculate cursor watermark */ |
| 3295 | line_time_us = (planeb_htotal * 1000) / planeb_clock; |
| 3296 | |
| 3297 | /* Use ns/us then divide to preserve precision */ |
| 3298 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; |
| 3299 | |
| 3300 | /* calculate the cursor watermark for cursor B */ |
| 3301 | entries_required = line_count * 64 * pixel_size; |
| 3302 | entries_required = DIV_ROUND_UP(entries_required, |
| 3303 | ironlake_cursor_wm_info.cacheline_size); |
| 3304 | cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size; |
| 3305 | if (cursorb_wm > ironlake_cursor_wm_info.max_wm) |
| 3306 | cursorb_wm = ironlake_cursor_wm_info.max_wm; |
| 3307 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3308 | reg_value = I915_READ(WM0_PIPEB_ILK); |
| 3309 | reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 3310 | reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) | |
| 3311 | (cursorb_wm & WM0_PIPE_CURSOR_MASK); |
| 3312 | I915_WRITE(WM0_PIPEB_ILK, reg_value); |
| 3313 | DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, " |
| 3314 | "cursor: %d\n", planeb_wm, cursorb_wm); |
| 3315 | } |
| 3316 | |
| 3317 | /* |
| 3318 | * Calculate and update the self-refresh watermark only when one |
| 3319 | * display plane is used. |
| 3320 | */ |
| 3321 | if (!planea_clock || !planeb_clock) { |
Zhao Yakui | c936f44 | 2010-06-12 14:32:26 +0800 | [diff] [blame] | 3322 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3323 | /* Read the self-refresh latency. The unit is 0.5us */ |
| 3324 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; |
| 3325 | |
| 3326 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3327 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 3328 | |
| 3329 | /* Use ns/us then divide to preserve precision */ |
| 3330 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) |
| 3331 | / 1000; |
| 3332 | |
| 3333 | /* calculate the self-refresh watermark for display plane */ |
| 3334 | entries_required = line_count * sr_hdisplay * pixel_size; |
| 3335 | entries_required = DIV_ROUND_UP(entries_required, |
| 3336 | ironlake_display_srwm_info.cacheline_size); |
| 3337 | sr_wm = entries_required + |
| 3338 | ironlake_display_srwm_info.guard_size; |
| 3339 | |
| 3340 | /* calculate the self-refresh watermark for display cursor */ |
| 3341 | entries_required = line_count * pixel_size * 64; |
| 3342 | entries_required = DIV_ROUND_UP(entries_required, |
| 3343 | ironlake_cursor_srwm_info.cacheline_size); |
| 3344 | cursor_wm = entries_required + |
| 3345 | ironlake_cursor_srwm_info.guard_size; |
| 3346 | |
| 3347 | /* configure watermark and enable self-refresh */ |
| 3348 | reg_value = I915_READ(WM1_LP_ILK); |
| 3349 | reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | |
| 3350 | WM1_LP_CURSOR_MASK); |
| 3351 | reg_value |= WM1_LP_SR_EN | |
| 3352 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | |
| 3353 | (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; |
| 3354 | |
| 3355 | I915_WRITE(WM1_LP_ILK, reg_value); |
| 3356 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 3357 | "cursor %d\n", sr_wm, cursor_wm); |
| 3358 | |
| 3359 | } else { |
| 3360 | /* Turn off self refresh if both pipes are enabled */ |
| 3361 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
| 3362 | } |
| 3363 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3364 | /** |
| 3365 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 3366 | * |
| 3367 | * Calculate watermark values for the various WM regs based on current mode |
| 3368 | * and plane configuration. |
| 3369 | * |
| 3370 | * There are several cases to deal with here: |
| 3371 | * - normal (i.e. non-self-refresh) |
| 3372 | * - self-refresh (SR) mode |
| 3373 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 3374 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 3375 | * lines), so need to account for TLB latency |
| 3376 | * |
| 3377 | * The normal calculation is: |
| 3378 | * watermark = dotclock * bytes per pixel * latency |
| 3379 | * where latency is platform & configuration dependent (we assume pessimal |
| 3380 | * values here). |
| 3381 | * |
| 3382 | * The SR calculation is: |
| 3383 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 3384 | * bytes per pixel |
| 3385 | * where |
| 3386 | * line time = htotal / dotclock |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3387 | * surface width = hdisplay for normal plane and 64 for cursor |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3388 | * and latency is assumed to be high, as above. |
| 3389 | * |
| 3390 | * The final value programmed to the register should always be rounded up, |
| 3391 | * and include an extra 2 entries to account for clock crossings. |
| 3392 | * |
| 3393 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 3394 | * to set the non-SR watermarks to 8. |
| 3395 | */ |
| 3396 | static void intel_update_watermarks(struct drm_device *dev) |
| 3397 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3398 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3399 | struct drm_crtc *crtc; |
| 3400 | struct intel_crtc *intel_crtc; |
| 3401 | int sr_hdisplay = 0; |
| 3402 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; |
| 3403 | int enabled = 0, pixel_size = 0; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3404 | int sr_htotal = 0; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3405 | |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 3406 | if (!dev_priv->display.update_wm) |
| 3407 | return; |
| 3408 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3409 | /* Get the clock config from both planes */ |
| 3410 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 3411 | intel_crtc = to_intel_crtc(crtc); |
| 3412 | if (crtc->enabled) { |
| 3413 | enabled++; |
| 3414 | if (intel_crtc->plane == 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3415 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3416 | intel_crtc->pipe, crtc->mode.clock); |
| 3417 | planea_clock = crtc->mode.clock; |
| 3418 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3419 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3420 | intel_crtc->pipe, crtc->mode.clock); |
| 3421 | planeb_clock = crtc->mode.clock; |
| 3422 | } |
| 3423 | sr_hdisplay = crtc->mode.hdisplay; |
| 3424 | sr_clock = crtc->mode.clock; |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3425 | sr_htotal = crtc->mode.htotal; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3426 | if (crtc->fb) |
| 3427 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 3428 | else |
| 3429 | pixel_size = 4; /* by default */ |
| 3430 | } |
| 3431 | } |
| 3432 | |
| 3433 | if (enabled <= 0) |
| 3434 | return; |
| 3435 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3436 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
Zhao Yakui | fa14321 | 2010-06-12 14:32:23 +0800 | [diff] [blame] | 3437 | sr_hdisplay, sr_htotal, pixel_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3438 | } |
| 3439 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3440 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
| 3441 | struct drm_display_mode *mode, |
| 3442 | struct drm_display_mode *adjusted_mode, |
| 3443 | int x, int y, |
| 3444 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3445 | { |
| 3446 | struct drm_device *dev = crtc->dev; |
| 3447 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3448 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3449 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3450 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3451 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; |
| 3452 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 3453 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3454 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3455 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 3456 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
| 3457 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; |
| 3458 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; |
| 3459 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; |
| 3460 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; |
| 3461 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3462 | int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; |
| 3463 | int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3464 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3465 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3466 | intel_clock_t clock, reduced_clock; |
| 3467 | u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; |
| 3468 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3469 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3470 | bool is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3471 | struct drm_mode_config *mode_config = &dev->mode_config; |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 3472 | struct drm_encoder *encoder; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 3473 | struct intel_encoder *intel_encoder = NULL; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3474 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3475 | int ret; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3476 | struct fdi_m_n m_n = {0}; |
| 3477 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; |
| 3478 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; |
| 3479 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; |
| 3480 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; |
| 3481 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; |
| 3482 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
| 3483 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3484 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
| 3485 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3486 | int lvds_reg = LVDS; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3487 | u32 temp; |
| 3488 | int sdvo_pixel_multiply; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3489 | int target_clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3490 | |
| 3491 | drm_vblank_pre_modeset(dev, pipe); |
| 3492 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 3493 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3494 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 3495 | if (!encoder || encoder->crtc != crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3496 | continue; |
| 3497 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 3498 | intel_encoder = enc_to_intel_encoder(encoder); |
| 3499 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 3500 | switch (intel_encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3501 | case INTEL_OUTPUT_LVDS: |
| 3502 | is_lvds = true; |
| 3503 | break; |
| 3504 | case INTEL_OUTPUT_SDVO: |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 3505 | case INTEL_OUTPUT_HDMI: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3506 | is_sdvo = true; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 3507 | if (intel_encoder->needs_tv_clock) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 3508 | is_tv = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3509 | break; |
| 3510 | case INTEL_OUTPUT_DVO: |
| 3511 | is_dvo = true; |
| 3512 | break; |
| 3513 | case INTEL_OUTPUT_TVOUT: |
| 3514 | is_tv = true; |
| 3515 | break; |
| 3516 | case INTEL_OUTPUT_ANALOG: |
| 3517 | is_crt = true; |
| 3518 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3519 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3520 | is_dp = true; |
| 3521 | break; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3522 | case INTEL_OUTPUT_EDP: |
| 3523 | is_edp = true; |
| 3524 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3525 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3526 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3527 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3528 | } |
| 3529 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3530 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3531 | refclk = dev_priv->lvds_ssc_freq * 1000; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3532 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 3533 | refclk / 1000); |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3534 | } else if (IS_I9XX(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3535 | refclk = 96000; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3536 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3537 | refclk = 120000; /* 120Mhz refclk */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3538 | } else { |
| 3539 | refclk = 48000; |
| 3540 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3541 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3542 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3543 | /* |
| 3544 | * Returns a set of divisors for the desired target clock with the given |
| 3545 | * refclk, or FALSE. The returned values represent the clock equation: |
| 3546 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 3547 | */ |
| 3548 | limit = intel_limit(crtc); |
| 3549 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3550 | if (!ok) { |
| 3551 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 3552 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3553 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3554 | } |
| 3555 | |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 3556 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 3557 | has_reduced_clock = limit->find_pll(limit, crtc, |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 3558 | dev_priv->lvds_downclock, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3559 | refclk, |
| 3560 | &reduced_clock); |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 3561 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
| 3562 | /* |
| 3563 | * If the different P is found, it means that we can't |
| 3564 | * switch the display clock by using the FP0/FP1. |
| 3565 | * In such case we will disable the LVDS downclock |
| 3566 | * feature. |
| 3567 | */ |
| 3568 | DRM_DEBUG_KMS("Different P is found for " |
| 3569 | "LVDS clock/downclock\n"); |
| 3570 | has_reduced_clock = 0; |
| 3571 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3572 | } |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 3573 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 3574 | this mirrors vbios setting. */ |
| 3575 | if (is_sdvo && is_tv) { |
| 3576 | if (adjusted_mode->clock >= 100000 |
| 3577 | && adjusted_mode->clock < 140500) { |
| 3578 | clock.p1 = 2; |
| 3579 | clock.p2 = 10; |
| 3580 | clock.n = 3; |
| 3581 | clock.m1 = 16; |
| 3582 | clock.m2 = 8; |
| 3583 | } else if (adjusted_mode->clock >= 140500 |
| 3584 | && adjusted_mode->clock <= 200000) { |
| 3585 | clock.p1 = 1; |
| 3586 | clock.p2 = 10; |
| 3587 | clock.n = 6; |
| 3588 | clock.m1 = 12; |
| 3589 | clock.m2 = 8; |
| 3590 | } |
| 3591 | } |
| 3592 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3593 | /* FDI link */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3594 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 3595 | int lane = 0, link_bw, bpp; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3596 | /* eDP doesn't require FDI link, so just set DP M/N |
| 3597 | according to current link config */ |
| 3598 | if (is_edp) { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3599 | target_clock = mode->clock; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 3600 | intel_edp_link_config(intel_encoder, |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3601 | &lane, &link_bw); |
| 3602 | } else { |
| 3603 | /* DP over FDI requires target mode clock |
| 3604 | instead of link clock */ |
| 3605 | if (is_dp) |
| 3606 | target_clock = mode->clock; |
| 3607 | else |
| 3608 | target_clock = adjusted_mode->clock; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3609 | link_bw = 270000; |
| 3610 | } |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 3611 | |
| 3612 | /* determine panel color depth */ |
| 3613 | temp = I915_READ(pipeconf_reg); |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3614 | temp &= ~PIPE_BPC_MASK; |
| 3615 | if (is_lvds) { |
| 3616 | int lvds_reg = I915_READ(PCH_LVDS); |
| 3617 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
| 3618 | if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
| 3619 | temp |= PIPE_8BPC; |
| 3620 | else |
| 3621 | temp |= PIPE_6BPC; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3622 | } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) { |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 3623 | switch (dev_priv->edp_bpp/3) { |
| 3624 | case 8: |
| 3625 | temp |= PIPE_8BPC; |
| 3626 | break; |
| 3627 | case 10: |
| 3628 | temp |= PIPE_10BPC; |
| 3629 | break; |
| 3630 | case 6: |
| 3631 | temp |= PIPE_6BPC; |
| 3632 | break; |
| 3633 | case 12: |
| 3634 | temp |= PIPE_12BPC; |
| 3635 | break; |
| 3636 | } |
Zhao Yakui | e5a95eb | 2010-01-04 16:29:32 +0800 | [diff] [blame] | 3637 | } else |
| 3638 | temp |= PIPE_8BPC; |
| 3639 | I915_WRITE(pipeconf_reg, temp); |
| 3640 | I915_READ(pipeconf_reg); |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 3641 | |
| 3642 | switch (temp & PIPE_BPC_MASK) { |
| 3643 | case PIPE_8BPC: |
| 3644 | bpp = 24; |
| 3645 | break; |
| 3646 | case PIPE_10BPC: |
| 3647 | bpp = 30; |
| 3648 | break; |
| 3649 | case PIPE_6BPC: |
| 3650 | bpp = 18; |
| 3651 | break; |
| 3652 | case PIPE_12BPC: |
| 3653 | bpp = 36; |
| 3654 | break; |
| 3655 | default: |
| 3656 | DRM_ERROR("unknown pipe bpc value\n"); |
| 3657 | bpp = 24; |
| 3658 | } |
| 3659 | |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 3660 | if (!lane) { |
| 3661 | /* |
| 3662 | * Account for spread spectrum to avoid |
| 3663 | * oversubscribing the link. Max center spread |
| 3664 | * is 2.5%; use 5% for safety's sake. |
| 3665 | */ |
| 3666 | u32 bps = target_clock * bpp * 21 / 20; |
| 3667 | lane = bps / (link_bw * 8) + 1; |
| 3668 | } |
| 3669 | |
| 3670 | intel_crtc->fdi_lanes = lane; |
| 3671 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3672 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3673 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3674 | |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3675 | /* Ironlake: try to setup display ref clock before DPLL |
| 3676 | * enabling. This is only under driver's control after |
| 3677 | * PCH B stepping, previous chipset stepping should be |
| 3678 | * ignoring this setting. |
| 3679 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3680 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 3681 | temp = I915_READ(PCH_DREF_CONTROL); |
| 3682 | /* Always enable nonspread source */ |
| 3683 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 3684 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 3685 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3686 | POSTING_READ(PCH_DREF_CONTROL); |
| 3687 | |
| 3688 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 3689 | temp |= DREF_SSC_SOURCE_ENABLE; |
| 3690 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3691 | POSTING_READ(PCH_DREF_CONTROL); |
| 3692 | |
| 3693 | udelay(200); |
| 3694 | |
| 3695 | if (is_edp) { |
| 3696 | if (dev_priv->lvds_use_ssc) { |
| 3697 | temp |= DREF_SSC1_ENABLE; |
| 3698 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3699 | POSTING_READ(PCH_DREF_CONTROL); |
| 3700 | |
| 3701 | udelay(200); |
| 3702 | |
| 3703 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 3704 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 3705 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3706 | POSTING_READ(PCH_DREF_CONTROL); |
| 3707 | } else { |
| 3708 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 3709 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3710 | POSTING_READ(PCH_DREF_CONTROL); |
| 3711 | } |
| 3712 | } |
| 3713 | } |
| 3714 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3715 | if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3716 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3717 | if (has_reduced_clock) |
| 3718 | fp2 = (1 << reduced_clock.n) << 16 | |
| 3719 | reduced_clock.m1 << 8 | reduced_clock.m2; |
| 3720 | } else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3721 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3722 | if (has_reduced_clock) |
| 3723 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
| 3724 | reduced_clock.m2; |
| 3725 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3726 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3727 | if (!HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3728 | dpll = DPLL_VGA_MODE_DIS; |
| 3729 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3730 | if (IS_I9XX(dev)) { |
| 3731 | if (is_lvds) |
| 3732 | dpll |= DPLLB_MODE_LVDS; |
| 3733 | else |
| 3734 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 3735 | if (is_sdvo) { |
| 3736 | dpll |= DPLL_DVO_HIGH_SPEED; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3737 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
Sean Young | 942642a | 2009-08-06 17:35:50 +0800 | [diff] [blame] | 3738 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3739 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3740 | else if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3741 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3742 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3743 | if (is_dp) |
| 3744 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3745 | |
| 3746 | /* compute bitmask from p1 value */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3747 | if (IS_PINEVIEW(dev)) |
| 3748 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3749 | else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3750 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3751 | /* also FPA1 */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3752 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3753 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3754 | if (IS_G4X(dev) && has_reduced_clock) |
| 3755 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3756 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3757 | switch (clock.p2) { |
| 3758 | case 5: |
| 3759 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 3760 | break; |
| 3761 | case 7: |
| 3762 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 3763 | break; |
| 3764 | case 10: |
| 3765 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 3766 | break; |
| 3767 | case 14: |
| 3768 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 3769 | break; |
| 3770 | } |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3771 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3772 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 3773 | } else { |
| 3774 | if (is_lvds) { |
| 3775 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3776 | } else { |
| 3777 | if (clock.p1 == 2) |
| 3778 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 3779 | else |
| 3780 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3781 | if (clock.p2 == 4) |
| 3782 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 3783 | } |
| 3784 | } |
| 3785 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3786 | if (is_sdvo && is_tv) |
| 3787 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 3788 | else if (is_tv) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3789 | /* XXX: just matching BIOS for now */ |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3790 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3791 | dpll |= 3; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3792 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3793 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3794 | else |
| 3795 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 3796 | |
| 3797 | /* setup pipeconf */ |
| 3798 | pipeconf = I915_READ(pipeconf_reg); |
| 3799 | |
| 3800 | /* Set up the display plane register */ |
| 3801 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 3802 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3803 | /* Ironlake's plane is forced to pipe, bit 24 is to |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3804 | enable color space conversion */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3805 | if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3806 | if (pipe == 0) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3807 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3808 | else |
| 3809 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 3810 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3811 | |
| 3812 | if (pipe == 0 && !IS_I965G(dev)) { |
| 3813 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
| 3814 | * core speed. |
| 3815 | * |
| 3816 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
| 3817 | * pipe == 0 check? |
| 3818 | */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3819 | if (mode->clock > |
| 3820 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3821 | pipeconf |= PIPEACONF_DOUBLE_WIDE; |
| 3822 | else |
| 3823 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; |
| 3824 | } |
| 3825 | |
Linus Torvalds | 8d86dc6 | 2010-06-08 20:16:28 -0700 | [diff] [blame] | 3826 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 3827 | pipeconf |= PIPEACONF_ENABLE; |
| 3828 | dpll |= DPLL_VCO_ENABLE; |
| 3829 | |
| 3830 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3831 | /* Disable the panel fitter if it was on our pipe */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3832 | if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3833 | I915_WRITE(PFIT_CONTROL, 0); |
| 3834 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3835 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3836 | drm_mode_debug_printmodeline(mode); |
| 3837 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3838 | /* assign to Ironlake registers */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3839 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3840 | fp_reg = pch_fp_reg; |
| 3841 | dpll_reg = pch_dpll_reg; |
| 3842 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3843 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3844 | if (is_edp) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3845 | ironlake_disable_pll_edp(crtc); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3846 | } else if ((dpll & DPLL_VCO_ENABLE)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3847 | I915_WRITE(fp_reg, fp); |
| 3848 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); |
| 3849 | I915_READ(dpll_reg); |
| 3850 | udelay(150); |
| 3851 | } |
| 3852 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3853 | /* enable transcoder DPLL */ |
| 3854 | if (HAS_PCH_CPT(dev)) { |
| 3855 | temp = I915_READ(PCH_DPLL_SEL); |
| 3856 | if (trans_dpll_sel == 0) |
| 3857 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
| 3858 | else |
| 3859 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
| 3860 | I915_WRITE(PCH_DPLL_SEL, temp); |
| 3861 | I915_READ(PCH_DPLL_SEL); |
| 3862 | udelay(150); |
| 3863 | } |
| 3864 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3865 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 3866 | * This is an exception to the general rule that mode_set doesn't turn |
| 3867 | * things on. |
| 3868 | */ |
| 3869 | if (is_lvds) { |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3870 | u32 lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3871 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3872 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3873 | lvds_reg = PCH_LVDS; |
| 3874 | |
| 3875 | lvds = I915_READ(lvds_reg); |
Adam Jackson | 0f3ee80 | 2010-03-31 11:41:51 -0400 | [diff] [blame] | 3876 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
Zhenyu Wang | b3b095b | 2010-04-07 16:15:56 +0800 | [diff] [blame] | 3877 | if (pipe == 1) { |
| 3878 | if (HAS_PCH_CPT(dev)) |
| 3879 | lvds |= PORT_TRANS_B_SEL_CPT; |
| 3880 | else |
| 3881 | lvds |= LVDS_PIPEB_SELECT; |
| 3882 | } else { |
| 3883 | if (HAS_PCH_CPT(dev)) |
| 3884 | lvds &= ~PORT_TRANS_SEL_MASK; |
| 3885 | else |
| 3886 | lvds &= ~LVDS_PIPEB_SELECT; |
| 3887 | } |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 3888 | /* set the corresponsding LVDS_BORDER bit */ |
| 3889 | lvds |= dev_priv->lvds_border_bits; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3890 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 3891 | * set the DPLLs for dual-channel mode or not. |
| 3892 | */ |
| 3893 | if (clock.p2 == 7) |
| 3894 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 3895 | else |
| 3896 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 3897 | |
| 3898 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 3899 | * appropriately here, but we need to look more thoroughly into how |
| 3900 | * panels behave in the two modes. |
| 3901 | */ |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3902 | /* set the dithering flag */ |
| 3903 | if (IS_I965G(dev)) { |
| 3904 | if (dev_priv->lvds_dither) { |
Adam Jackson | 0a31a44 | 2010-04-19 15:57:25 -0400 | [diff] [blame] | 3905 | if (HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3906 | pipeconf |= PIPE_ENABLE_DITHER; |
Adam Jackson | 0a31a44 | 2010-04-19 15:57:25 -0400 | [diff] [blame] | 3907 | pipeconf |= PIPE_DITHER_TYPE_ST01; |
| 3908 | } else |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3909 | lvds |= LVDS_ENABLE_DITHER; |
| 3910 | } else { |
Adam Jackson | 0a31a44 | 2010-04-19 15:57:25 -0400 | [diff] [blame] | 3911 | if (HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3912 | pipeconf &= ~PIPE_ENABLE_DITHER; |
Adam Jackson | 0a31a44 | 2010-04-19 15:57:25 -0400 | [diff] [blame] | 3913 | pipeconf &= ~PIPE_DITHER_TYPE_MASK; |
| 3914 | } else |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 3915 | lvds &= ~LVDS_ENABLE_DITHER; |
| 3916 | } |
| 3917 | } |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3918 | I915_WRITE(lvds_reg, lvds); |
| 3919 | I915_READ(lvds_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3920 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3921 | if (is_dp) |
| 3922 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 3923 | else if (HAS_PCH_SPLIT(dev)) { |
| 3924 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
| 3925 | if (pipe == 0) { |
| 3926 | I915_WRITE(TRANSA_DATA_M1, 0); |
| 3927 | I915_WRITE(TRANSA_DATA_N1, 0); |
| 3928 | I915_WRITE(TRANSA_DP_LINK_M1, 0); |
| 3929 | I915_WRITE(TRANSA_DP_LINK_N1, 0); |
| 3930 | } else { |
| 3931 | I915_WRITE(TRANSB_DATA_M1, 0); |
| 3932 | I915_WRITE(TRANSB_DATA_N1, 0); |
| 3933 | I915_WRITE(TRANSB_DP_LINK_M1, 0); |
| 3934 | I915_WRITE(TRANSB_DP_LINK_N1, 0); |
| 3935 | } |
| 3936 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3937 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3938 | if (!is_edp) { |
| 3939 | I915_WRITE(fp_reg, fp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3940 | I915_WRITE(dpll_reg, dpll); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3941 | I915_READ(dpll_reg); |
| 3942 | /* Wait for the clocks to stabilize. */ |
| 3943 | udelay(150); |
| 3944 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3945 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { |
Zhao Yakui | bb66c51 | 2009-09-10 15:45:49 +0800 | [diff] [blame] | 3946 | if (is_sdvo) { |
| 3947 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
| 3948 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3949 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); |
Zhao Yakui | bb66c51 | 2009-09-10 15:45:49 +0800 | [diff] [blame] | 3950 | } else |
| 3951 | I915_WRITE(dpll_md_reg, 0); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3952 | } else { |
| 3953 | /* write it again -- the BIOS does, after all */ |
| 3954 | I915_WRITE(dpll_reg, dpll); |
| 3955 | } |
| 3956 | I915_READ(dpll_reg); |
| 3957 | /* Wait for the clocks to stabilize. */ |
| 3958 | udelay(150); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3959 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3960 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3961 | if (is_lvds && has_reduced_clock && i915_powersave) { |
| 3962 | I915_WRITE(fp_reg + 4, fp2); |
| 3963 | intel_crtc->lowfreq_avail = true; |
| 3964 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3965 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3966 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 3967 | } |
| 3968 | } else { |
| 3969 | I915_WRITE(fp_reg + 4, fp); |
| 3970 | intel_crtc->lowfreq_avail = false; |
| 3971 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3972 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3973 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 3974 | } |
| 3975 | } |
| 3976 | |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 3977 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 3978 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 3979 | /* the chip adds 2 halflines automatically */ |
| 3980 | adjusted_mode->crtc_vdisplay -= 1; |
| 3981 | adjusted_mode->crtc_vtotal -= 1; |
| 3982 | adjusted_mode->crtc_vblank_start -= 1; |
| 3983 | adjusted_mode->crtc_vblank_end -= 1; |
| 3984 | adjusted_mode->crtc_vsync_end -= 1; |
| 3985 | adjusted_mode->crtc_vsync_start -= 1; |
| 3986 | } else |
| 3987 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ |
| 3988 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3989 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | |
| 3990 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 3991 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | |
| 3992 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 3993 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | |
| 3994 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 3995 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | |
| 3996 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
| 3997 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | |
| 3998 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
| 3999 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | |
| 4000 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 4001 | /* pipesrc and dspsize control the size that is scaled from, which should |
| 4002 | * always be the user's requested size. |
| 4003 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4004 | if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4005 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | |
| 4006 | (mode->hdisplay - 1)); |
| 4007 | I915_WRITE(dsppos_reg, 0); |
| 4008 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4009 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4010 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4011 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4012 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 4013 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); |
| 4014 | I915_WRITE(link_m1_reg, m_n.link_m); |
| 4015 | I915_WRITE(link_n1_reg, m_n.link_n); |
| 4016 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4017 | if (is_edp) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4018 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4019 | } else { |
| 4020 | /* enable FDI RX PLL too */ |
| 4021 | temp = I915_READ(fdi_rx_reg); |
| 4022 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4023 | I915_READ(fdi_rx_reg); |
| 4024 | udelay(200); |
| 4025 | |
| 4026 | /* enable FDI TX PLL too */ |
| 4027 | temp = I915_READ(fdi_tx_reg); |
| 4028 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); |
| 4029 | I915_READ(fdi_tx_reg); |
| 4030 | |
| 4031 | /* enable FDI RX PCDCLK */ |
| 4032 | temp = I915_READ(fdi_rx_reg); |
| 4033 | I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK); |
| 4034 | I915_READ(fdi_rx_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4035 | udelay(200); |
| 4036 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4037 | } |
| 4038 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4039 | I915_WRITE(pipeconf_reg, pipeconf); |
| 4040 | I915_READ(pipeconf_reg); |
| 4041 | |
| 4042 | intel_wait_for_vblank(dev); |
| 4043 | |
Eric Anholt | c2416fc | 2009-11-05 15:30:35 -0800 | [diff] [blame] | 4044 | if (IS_IRONLAKE(dev)) { |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 4045 | /* enable address swizzle for tiling buffer */ |
| 4046 | temp = I915_READ(DISP_ARB_CTL); |
| 4047 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); |
| 4048 | } |
| 4049 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4050 | I915_WRITE(dspcntr_reg, dspcntr); |
| 4051 | |
| 4052 | /* Flush the plane changes */ |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4053 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4054 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 4055 | if ((IS_I965G(dev) || plane == 0)) |
| 4056 | intel_update_fbc(crtc, &crtc->mode); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4057 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4058 | intel_update_watermarks(dev); |
| 4059 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4060 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4061 | |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 4062 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4063 | } |
| 4064 | |
| 4065 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 4066 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 4067 | { |
| 4068 | struct drm_device *dev = crtc->dev; |
| 4069 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4071 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; |
| 4072 | int i; |
| 4073 | |
| 4074 | /* The clocks have to be on to load the palette. */ |
| 4075 | if (!crtc->enabled) |
| 4076 | return; |
| 4077 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4078 | /* use legacy palette for Ironlake */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4079 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4080 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
| 4081 | LGC_PALETTE_B; |
| 4082 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4083 | for (i = 0; i < 256; i++) { |
| 4084 | I915_WRITE(palreg + 4 * i, |
| 4085 | (intel_crtc->lut_r[i] << 16) | |
| 4086 | (intel_crtc->lut_g[i] << 8) | |
| 4087 | intel_crtc->lut_b[i]); |
| 4088 | } |
| 4089 | } |
| 4090 | |
| 4091 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
| 4092 | struct drm_file *file_priv, |
| 4093 | uint32_t handle, |
| 4094 | uint32_t width, uint32_t height) |
| 4095 | { |
| 4096 | struct drm_device *dev = crtc->dev; |
| 4097 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4099 | struct drm_gem_object *bo; |
| 4100 | struct drm_i915_gem_object *obj_priv; |
| 4101 | int pipe = intel_crtc->pipe; |
| 4102 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; |
| 4103 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 4104 | uint32_t temp = I915_READ(control); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4105 | size_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4106 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4107 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4108 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4109 | |
| 4110 | /* if we want to turn off the cursor ignore width and height */ |
| 4111 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4112 | DRM_DEBUG_KMS("cursor off\n"); |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 4113 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
| 4114 | temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 4115 | temp |= CURSOR_MODE_DISABLE; |
| 4116 | } else { |
| 4117 | temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
| 4118 | } |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4119 | addr = 0; |
| 4120 | bo = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 4121 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4122 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4123 | } |
| 4124 | |
| 4125 | /* Currently we only support 64x64 cursors */ |
| 4126 | if (width != 64 || height != 64) { |
| 4127 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 4128 | return -EINVAL; |
| 4129 | } |
| 4130 | |
| 4131 | bo = drm_gem_object_lookup(dev, file_priv, handle); |
| 4132 | if (!bo) |
| 4133 | return -ENOENT; |
| 4134 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4135 | obj_priv = to_intel_bo(bo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4136 | |
| 4137 | if (bo->size < width * height * 4) { |
| 4138 | DRM_ERROR("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4139 | ret = -ENOMEM; |
| 4140 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4141 | } |
| 4142 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4143 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4144 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4145 | if (!dev_priv->info->cursor_needs_physical) { |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4146 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
| 4147 | if (ret) { |
| 4148 | DRM_ERROR("failed to pin cursor bo\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4149 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4150 | } |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4151 | |
| 4152 | ret = i915_gem_object_set_to_gtt_domain(bo, 0); |
| 4153 | if (ret) { |
| 4154 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
| 4155 | goto fail_unpin; |
| 4156 | } |
| 4157 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4158 | addr = obj_priv->gtt_offset; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4159 | } else { |
| 4160 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); |
| 4161 | if (ret) { |
| 4162 | DRM_ERROR("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4163 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4164 | } |
| 4165 | addr = obj_priv->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4166 | } |
| 4167 | |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 4168 | if (!IS_I9XX(dev)) |
| 4169 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 4170 | |
| 4171 | /* Hooray for CUR*CNTR differences */ |
| 4172 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
| 4173 | temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 4174 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 4175 | temp |= (pipe << 28); /* Connect to correct pipe */ |
| 4176 | } else { |
| 4177 | temp &= ~(CURSOR_FORMAT_MASK); |
| 4178 | temp |= CURSOR_ENABLE; |
| 4179 | temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; |
| 4180 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4181 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4182 | finish: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4183 | I915_WRITE(control, temp); |
| 4184 | I915_WRITE(base, addr); |
| 4185 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4186 | if (intel_crtc->cursor_bo) { |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4187 | if (dev_priv->info->cursor_needs_physical) { |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4188 | if (intel_crtc->cursor_bo != bo) |
| 4189 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 4190 | } else |
| 4191 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4192 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
| 4193 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4194 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4195 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4196 | |
| 4197 | intel_crtc->cursor_addr = addr; |
| 4198 | intel_crtc->cursor_bo = bo; |
| 4199 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4200 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4201 | fail_unpin: |
| 4202 | i915_gem_object_unpin(bo); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4203 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4204 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 4205 | fail: |
| 4206 | drm_gem_object_unreference_unlocked(bo); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4207 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4208 | } |
| 4209 | |
| 4210 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 4211 | { |
| 4212 | struct drm_device *dev = crtc->dev; |
| 4213 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4215 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4216 | int pipe = intel_crtc->pipe; |
| 4217 | uint32_t temp = 0; |
| 4218 | uint32_t adder; |
| 4219 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4220 | if (crtc->fb) { |
| 4221 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 4222 | intel_mark_busy(dev, intel_fb->obj); |
| 4223 | } |
| 4224 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4225 | if (x < 0) { |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 4226 | temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4227 | x = -x; |
| 4228 | } |
| 4229 | if (y < 0) { |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 4230 | temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4231 | y = -y; |
| 4232 | } |
| 4233 | |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 4234 | temp |= x << CURSOR_X_SHIFT; |
| 4235 | temp |= y << CURSOR_Y_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4236 | |
| 4237 | adder = intel_crtc->cursor_addr; |
| 4238 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); |
| 4239 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); |
| 4240 | |
| 4241 | return 0; |
| 4242 | } |
| 4243 | |
| 4244 | /** Sets the color ramps on behalf of RandR */ |
| 4245 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 4246 | u16 blue, int regno) |
| 4247 | { |
| 4248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4249 | |
| 4250 | intel_crtc->lut_r[regno] = red >> 8; |
| 4251 | intel_crtc->lut_g[regno] = green >> 8; |
| 4252 | intel_crtc->lut_b[regno] = blue >> 8; |
| 4253 | } |
| 4254 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 4255 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 4256 | u16 *blue, int regno) |
| 4257 | { |
| 4258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4259 | |
| 4260 | *red = intel_crtc->lut_r[regno] << 8; |
| 4261 | *green = intel_crtc->lut_g[regno] << 8; |
| 4262 | *blue = intel_crtc->lut_b[regno] << 8; |
| 4263 | } |
| 4264 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4265 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 4266 | u16 *blue, uint32_t size) |
| 4267 | { |
| 4268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4269 | int i; |
| 4270 | |
| 4271 | if (size != 256) |
| 4272 | return; |
| 4273 | |
| 4274 | for (i = 0; i < 256; i++) { |
| 4275 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 4276 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 4277 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 4278 | } |
| 4279 | |
| 4280 | intel_crtc_load_lut(crtc); |
| 4281 | } |
| 4282 | |
| 4283 | /** |
| 4284 | * Get a pipe with a simple mode set on it for doing load-based monitor |
| 4285 | * detection. |
| 4286 | * |
| 4287 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4288 | * its requirements. The pipe will be connected to no other encoders. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4289 | * |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4290 | * Currently this code will only succeed if there is a pipe with no encoders |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4291 | * configured for it. In the future, it could choose to temporarily disable |
| 4292 | * some outputs to free up a pipe for its use. |
| 4293 | * |
| 4294 | * \return crtc, or NULL if no pipes are available. |
| 4295 | */ |
| 4296 | |
| 4297 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 4298 | static struct drm_display_mode load_detect_mode = { |
| 4299 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 4300 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 4301 | }; |
| 4302 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4303 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4304 | struct drm_connector *connector, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4305 | struct drm_display_mode *mode, |
| 4306 | int *dpms_mode) |
| 4307 | { |
| 4308 | struct intel_crtc *intel_crtc; |
| 4309 | struct drm_crtc *possible_crtc; |
| 4310 | struct drm_crtc *supported_crtc =NULL; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4311 | struct drm_encoder *encoder = &intel_encoder->enc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4312 | struct drm_crtc *crtc = NULL; |
| 4313 | struct drm_device *dev = encoder->dev; |
| 4314 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 4315 | struct drm_crtc_helper_funcs *crtc_funcs; |
| 4316 | int i = -1; |
| 4317 | |
| 4318 | /* |
| 4319 | * Algorithm gets a little messy: |
| 4320 | * - if the connector already has an assigned crtc, use it (but make |
| 4321 | * sure it's on first) |
| 4322 | * - try to find the first unused crtc that can drive this connector, |
| 4323 | * and use that if we find one |
| 4324 | * - if there are no unused crtcs available, try to use the first |
| 4325 | * one we found that supports the connector |
| 4326 | */ |
| 4327 | |
| 4328 | /* See if we already have a CRTC for this connector */ |
| 4329 | if (encoder->crtc) { |
| 4330 | crtc = encoder->crtc; |
| 4331 | /* Make sure the crtc and connector are running */ |
| 4332 | intel_crtc = to_intel_crtc(crtc); |
| 4333 | *dpms_mode = intel_crtc->dpms_mode; |
| 4334 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 4335 | crtc_funcs = crtc->helper_private; |
| 4336 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 4337 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 4338 | } |
| 4339 | return crtc; |
| 4340 | } |
| 4341 | |
| 4342 | /* Find an unused one (if possible) */ |
| 4343 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 4344 | i++; |
| 4345 | if (!(encoder->possible_crtcs & (1 << i))) |
| 4346 | continue; |
| 4347 | if (!possible_crtc->enabled) { |
| 4348 | crtc = possible_crtc; |
| 4349 | break; |
| 4350 | } |
| 4351 | if (!supported_crtc) |
| 4352 | supported_crtc = possible_crtc; |
| 4353 | } |
| 4354 | |
| 4355 | /* |
| 4356 | * If we didn't find an unused CRTC, don't use any. |
| 4357 | */ |
| 4358 | if (!crtc) { |
| 4359 | return NULL; |
| 4360 | } |
| 4361 | |
| 4362 | encoder->crtc = crtc; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4363 | connector->encoder = encoder; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4364 | intel_encoder->load_detect_temp = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4365 | |
| 4366 | intel_crtc = to_intel_crtc(crtc); |
| 4367 | *dpms_mode = intel_crtc->dpms_mode; |
| 4368 | |
| 4369 | if (!crtc->enabled) { |
| 4370 | if (!mode) |
| 4371 | mode = &load_detect_mode; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 4372 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4373 | } else { |
| 4374 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 4375 | crtc_funcs = crtc->helper_private; |
| 4376 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 4377 | } |
| 4378 | |
| 4379 | /* Add this connector to the crtc */ |
| 4380 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); |
| 4381 | encoder_funcs->commit(encoder); |
| 4382 | } |
| 4383 | /* let the connector get through one full cycle before testing */ |
| 4384 | intel_wait_for_vblank(dev); |
| 4385 | |
| 4386 | return crtc; |
| 4387 | } |
| 4388 | |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4389 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
| 4390 | struct drm_connector *connector, int dpms_mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4391 | { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4392 | struct drm_encoder *encoder = &intel_encoder->enc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4393 | struct drm_device *dev = encoder->dev; |
| 4394 | struct drm_crtc *crtc = encoder->crtc; |
| 4395 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 4396 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 4397 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4398 | if (intel_encoder->load_detect_temp) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4399 | encoder->crtc = NULL; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 4400 | connector->encoder = NULL; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 4401 | intel_encoder->load_detect_temp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4402 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
| 4403 | drm_helper_disable_unused_functions(dev); |
| 4404 | } |
| 4405 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4406 | /* Switch crtc and encoder back off if necessary */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4407 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
| 4408 | if (encoder->crtc == crtc) |
| 4409 | encoder_funcs->dpms(encoder, dpms_mode); |
| 4410 | crtc_funcs->dpms(crtc, dpms_mode); |
| 4411 | } |
| 4412 | } |
| 4413 | |
| 4414 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 4415 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
| 4416 | { |
| 4417 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4418 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4419 | int pipe = intel_crtc->pipe; |
| 4420 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); |
| 4421 | u32 fp; |
| 4422 | intel_clock_t clock; |
| 4423 | |
| 4424 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 4425 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); |
| 4426 | else |
| 4427 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); |
| 4428 | |
| 4429 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4430 | if (IS_PINEVIEW(dev)) { |
| 4431 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 4432 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4433 | } else { |
| 4434 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 4435 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 4436 | } |
| 4437 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4438 | if (IS_I9XX(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4439 | if (IS_PINEVIEW(dev)) |
| 4440 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 4441 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4442 | else |
| 4443 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4444 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 4445 | |
| 4446 | switch (dpll & DPLL_MODE_MASK) { |
| 4447 | case DPLLB_MODE_DAC_SERIAL: |
| 4448 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 4449 | 5 : 10; |
| 4450 | break; |
| 4451 | case DPLLB_MODE_LVDS: |
| 4452 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 4453 | 7 : 14; |
| 4454 | break; |
| 4455 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4456 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4457 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 4458 | return 0; |
| 4459 | } |
| 4460 | |
| 4461 | /* XXX: Handle the 100Mhz refclk */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4462 | intel_clock(dev, 96000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4463 | } else { |
| 4464 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
| 4465 | |
| 4466 | if (is_lvds) { |
| 4467 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 4468 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 4469 | clock.p2 = 14; |
| 4470 | |
| 4471 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 4472 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 4473 | /* XXX: might not be 66MHz */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4474 | intel_clock(dev, 66000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4475 | } else |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4476 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4477 | } else { |
| 4478 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 4479 | clock.p1 = 2; |
| 4480 | else { |
| 4481 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 4482 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 4483 | } |
| 4484 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 4485 | clock.p2 = 4; |
| 4486 | else |
| 4487 | clock.p2 = 2; |
| 4488 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 4489 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4490 | } |
| 4491 | } |
| 4492 | |
| 4493 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 4494 | * i830PllIsValid() because it relies on the xf86_config connector |
| 4495 | * configuration being accurate, which it isn't necessarily. |
| 4496 | */ |
| 4497 | |
| 4498 | return clock.dot; |
| 4499 | } |
| 4500 | |
| 4501 | /** Returns the currently programmed mode of the given pipe. */ |
| 4502 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 4503 | struct drm_crtc *crtc) |
| 4504 | { |
| 4505 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4507 | int pipe = intel_crtc->pipe; |
| 4508 | struct drm_display_mode *mode; |
| 4509 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); |
| 4510 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); |
| 4511 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); |
| 4512 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); |
| 4513 | |
| 4514 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 4515 | if (!mode) |
| 4516 | return NULL; |
| 4517 | |
| 4518 | mode->clock = intel_crtc_clock_get(dev, crtc); |
| 4519 | mode->hdisplay = (htot & 0xffff) + 1; |
| 4520 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 4521 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 4522 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 4523 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 4524 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 4525 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 4526 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 4527 | |
| 4528 | drm_mode_set_name(mode); |
| 4529 | drm_mode_set_crtcinfo(mode, 0); |
| 4530 | |
| 4531 | return mode; |
| 4532 | } |
| 4533 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4534 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
| 4535 | |
| 4536 | /* When this timer fires, we've been idle for awhile */ |
| 4537 | static void intel_gpu_idle_timer(unsigned long arg) |
| 4538 | { |
| 4539 | struct drm_device *dev = (struct drm_device *)arg; |
| 4540 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4541 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4542 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4543 | |
| 4544 | dev_priv->busy = false; |
| 4545 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 4546 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4547 | } |
| 4548 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4549 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
| 4550 | |
| 4551 | static void intel_crtc_idle_timer(unsigned long arg) |
| 4552 | { |
| 4553 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; |
| 4554 | struct drm_crtc *crtc = &intel_crtc->base; |
| 4555 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; |
| 4556 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4557 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4558 | |
| 4559 | intel_crtc->busy = false; |
| 4560 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 4561 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4562 | } |
| 4563 | |
| 4564 | static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) |
| 4565 | { |
| 4566 | struct drm_device *dev = crtc->dev; |
| 4567 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4569 | int pipe = intel_crtc->pipe; |
| 4570 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 4571 | int dpll = I915_READ(dpll_reg); |
| 4572 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4573 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4574 | return; |
| 4575 | |
| 4576 | if (!dev_priv->lvds_downclock_avail) |
| 4577 | return; |
| 4578 | |
| 4579 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4580 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4581 | |
| 4582 | /* Unlock panel regs */ |
| 4583 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); |
| 4584 | |
| 4585 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 4586 | I915_WRITE(dpll_reg, dpll); |
| 4587 | dpll = I915_READ(dpll_reg); |
| 4588 | intel_wait_for_vblank(dev); |
| 4589 | dpll = I915_READ(dpll_reg); |
| 4590 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4591 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4592 | |
| 4593 | /* ...and lock them again */ |
| 4594 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 4595 | } |
| 4596 | |
| 4597 | /* Schedule downclock */ |
| 4598 | if (schedule) |
| 4599 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 4600 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 4601 | } |
| 4602 | |
| 4603 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 4604 | { |
| 4605 | struct drm_device *dev = crtc->dev; |
| 4606 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4608 | int pipe = intel_crtc->pipe; |
| 4609 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 4610 | int dpll = I915_READ(dpll_reg); |
| 4611 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4612 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4613 | return; |
| 4614 | |
| 4615 | if (!dev_priv->lvds_downclock_avail) |
| 4616 | return; |
| 4617 | |
| 4618 | /* |
| 4619 | * Since this is called by a timer, we should never get here in |
| 4620 | * the manual case. |
| 4621 | */ |
| 4622 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4623 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4624 | |
| 4625 | /* Unlock panel regs */ |
| 4626 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); |
| 4627 | |
| 4628 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 4629 | I915_WRITE(dpll_reg, dpll); |
| 4630 | dpll = I915_READ(dpll_reg); |
| 4631 | intel_wait_for_vblank(dev); |
| 4632 | dpll = I915_READ(dpll_reg); |
| 4633 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4634 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4635 | |
| 4636 | /* ...and lock them again */ |
| 4637 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 4638 | } |
| 4639 | |
| 4640 | } |
| 4641 | |
| 4642 | /** |
| 4643 | * intel_idle_update - adjust clocks for idleness |
| 4644 | * @work: work struct |
| 4645 | * |
| 4646 | * Either the GPU or display (or both) went idle. Check the busy status |
| 4647 | * here and adjust the CRTC and GPU clocks as necessary. |
| 4648 | */ |
| 4649 | static void intel_idle_update(struct work_struct *work) |
| 4650 | { |
| 4651 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 4652 | idle_work); |
| 4653 | struct drm_device *dev = dev_priv->dev; |
| 4654 | struct drm_crtc *crtc; |
| 4655 | struct intel_crtc *intel_crtc; |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4656 | int enabled = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4657 | |
| 4658 | if (!i915_powersave) |
| 4659 | return; |
| 4660 | |
| 4661 | mutex_lock(&dev->struct_mutex); |
| 4662 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 4663 | i915_update_gfx_val(dev_priv); |
| 4664 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4665 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4666 | /* Skip inactive CRTCs */ |
| 4667 | if (!crtc->fb) |
| 4668 | continue; |
| 4669 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4670 | enabled++; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4671 | intel_crtc = to_intel_crtc(crtc); |
| 4672 | if (!intel_crtc->busy) |
| 4673 | intel_decrease_pllclock(crtc); |
| 4674 | } |
| 4675 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 4676 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
| 4677 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); |
| 4678 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 4679 | } |
| 4680 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4681 | mutex_unlock(&dev->struct_mutex); |
| 4682 | } |
| 4683 | |
| 4684 | /** |
| 4685 | * intel_mark_busy - mark the GPU and possibly the display busy |
| 4686 | * @dev: drm device |
| 4687 | * @obj: object we're operating on |
| 4688 | * |
| 4689 | * Callers can use this function to indicate that the GPU is busy processing |
| 4690 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout |
| 4691 | * buffer), we'll also mark the display as busy, so we know to increase its |
| 4692 | * clock frequency. |
| 4693 | */ |
| 4694 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) |
| 4695 | { |
| 4696 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4697 | struct drm_crtc *crtc = NULL; |
| 4698 | struct intel_framebuffer *intel_fb; |
| 4699 | struct intel_crtc *intel_crtc; |
| 4700 | |
Zhenyu Wang | 5e17ee7 | 2009-09-03 09:30:06 +0800 | [diff] [blame] | 4701 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4702 | return; |
| 4703 | |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4704 | if (!dev_priv->busy) { |
| 4705 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 4706 | u32 fw_blc_self; |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 4707 | |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4708 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
| 4709 | fw_blc_self = I915_READ(FW_BLC_SELF); |
| 4710 | fw_blc_self &= ~FW_BLC_SELF_EN; |
| 4711 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); |
| 4712 | } |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 4713 | dev_priv->busy = true; |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4714 | } else |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 4715 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 4716 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4717 | |
| 4718 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4719 | if (!crtc->fb) |
| 4720 | continue; |
| 4721 | |
| 4722 | intel_crtc = to_intel_crtc(crtc); |
| 4723 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 4724 | if (intel_fb->obj == obj) { |
| 4725 | if (!intel_crtc->busy) { |
Li Peng | 060e645 | 2010-02-10 01:54:24 +0800 | [diff] [blame] | 4726 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 4727 | u32 fw_blc_self; |
| 4728 | |
| 4729 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
| 4730 | fw_blc_self = I915_READ(FW_BLC_SELF); |
| 4731 | fw_blc_self &= ~FW_BLC_SELF_EN; |
| 4732 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); |
| 4733 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4734 | /* Non-busy -> busy, upclock */ |
| 4735 | intel_increase_pllclock(crtc, true); |
| 4736 | intel_crtc->busy = true; |
| 4737 | } else { |
| 4738 | /* Busy -> busy, put off timer */ |
| 4739 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 4740 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 4741 | } |
| 4742 | } |
| 4743 | } |
| 4744 | } |
| 4745 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4746 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 4747 | { |
| 4748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4749 | |
| 4750 | drm_crtc_cleanup(crtc); |
| 4751 | kfree(intel_crtc); |
| 4752 | } |
| 4753 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4754 | struct intel_unpin_work { |
| 4755 | struct work_struct work; |
| 4756 | struct drm_device *dev; |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4757 | struct drm_gem_object *old_fb_obj; |
| 4758 | struct drm_gem_object *pending_flip_obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4759 | struct drm_pending_vblank_event *event; |
| 4760 | int pending; |
| 4761 | }; |
| 4762 | |
| 4763 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 4764 | { |
| 4765 | struct intel_unpin_work *work = |
| 4766 | container_of(__work, struct intel_unpin_work, work); |
| 4767 | |
| 4768 | mutex_lock(&work->dev->struct_mutex); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4769 | i915_gem_object_unpin(work->old_fb_obj); |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 4770 | drm_gem_object_unreference(work->pending_flip_obj); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4771 | drm_gem_object_unreference(work->old_fb_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4772 | mutex_unlock(&work->dev->struct_mutex); |
| 4773 | kfree(work); |
| 4774 | } |
| 4775 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4776 | static void do_intel_finish_page_flip(struct drm_device *dev, |
| 4777 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4778 | { |
| 4779 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4781 | struct intel_unpin_work *work; |
| 4782 | struct drm_i915_gem_object *obj_priv; |
| 4783 | struct drm_pending_vblank_event *e; |
| 4784 | struct timeval now; |
| 4785 | unsigned long flags; |
| 4786 | |
| 4787 | /* Ignore early vblank irqs */ |
| 4788 | if (intel_crtc == NULL) |
| 4789 | return; |
| 4790 | |
| 4791 | spin_lock_irqsave(&dev->event_lock, flags); |
| 4792 | work = intel_crtc->unpin_work; |
| 4793 | if (work == NULL || !work->pending) { |
| 4794 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4795 | return; |
| 4796 | } |
| 4797 | |
| 4798 | intel_crtc->unpin_work = NULL; |
| 4799 | drm_vblank_put(dev, intel_crtc->pipe); |
| 4800 | |
| 4801 | if (work->event) { |
| 4802 | e = work->event; |
| 4803 | do_gettimeofday(&now); |
| 4804 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); |
| 4805 | e->event.tv_sec = now.tv_sec; |
| 4806 | e->event.tv_usec = now.tv_usec; |
| 4807 | list_add_tail(&e->base.link, |
| 4808 | &e->base.file_priv->event_list); |
| 4809 | wake_up_interruptible(&e->base.file_priv->event_wait); |
| 4810 | } |
| 4811 | |
| 4812 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4813 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4814 | obj_priv = to_intel_bo(work->pending_flip_obj); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 4815 | |
| 4816 | /* Initial scanout buffer will have a 0 pending flip count */ |
| 4817 | if ((atomic_read(&obj_priv->pending_flip) == 0) || |
| 4818 | atomic_dec_and_test(&obj_priv->pending_flip)) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4819 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
| 4820 | schedule_work(&work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 4821 | |
| 4822 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4823 | } |
| 4824 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4825 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 4826 | { |
| 4827 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4828 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 4829 | |
| 4830 | do_intel_finish_page_flip(dev, crtc); |
| 4831 | } |
| 4832 | |
| 4833 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 4834 | { |
| 4835 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4836 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 4837 | |
| 4838 | do_intel_finish_page_flip(dev, crtc); |
| 4839 | } |
| 4840 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4841 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 4842 | { |
| 4843 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4844 | struct intel_crtc *intel_crtc = |
| 4845 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 4846 | unsigned long flags; |
| 4847 | |
| 4848 | spin_lock_irqsave(&dev->event_lock, flags); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 4849 | if (intel_crtc->unpin_work) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4850 | intel_crtc->unpin_work->pending = 1; |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 4851 | } else { |
| 4852 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
| 4853 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4854 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4855 | } |
| 4856 | |
| 4857 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 4858 | struct drm_framebuffer *fb, |
| 4859 | struct drm_pending_vblank_event *event) |
| 4860 | { |
| 4861 | struct drm_device *dev = crtc->dev; |
| 4862 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4863 | struct intel_framebuffer *intel_fb; |
| 4864 | struct drm_i915_gem_object *obj_priv; |
| 4865 | struct drm_gem_object *obj; |
| 4866 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4867 | struct intel_unpin_work *work; |
| 4868 | unsigned long flags; |
Zhenyu Wang | aacef09 | 2010-02-09 09:46:20 +0800 | [diff] [blame] | 4869 | int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; |
| 4870 | int ret, pipesrc; |
Jesse Barnes | 83f7fd0 | 2010-04-05 14:03:51 -0700 | [diff] [blame] | 4871 | u32 flip_mask; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4872 | |
| 4873 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 4874 | if (work == NULL) |
| 4875 | return -ENOMEM; |
| 4876 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4877 | work->event = event; |
| 4878 | work->dev = crtc->dev; |
| 4879 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4880 | work->old_fb_obj = intel_fb->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4881 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 4882 | |
| 4883 | /* We borrow the event spin lock for protecting unpin_work */ |
| 4884 | spin_lock_irqsave(&dev->event_lock, flags); |
| 4885 | if (intel_crtc->unpin_work) { |
| 4886 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4887 | kfree(work); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 4888 | |
| 4889 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4890 | return -EBUSY; |
| 4891 | } |
| 4892 | intel_crtc->unpin_work = work; |
| 4893 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4894 | |
| 4895 | intel_fb = to_intel_framebuffer(fb); |
| 4896 | obj = intel_fb->obj; |
| 4897 | |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 4898 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4899 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
| 4900 | if (ret != 0) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4901 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 4902 | |
| 4903 | spin_lock_irqsave(&dev->event_lock, flags); |
| 4904 | intel_crtc->unpin_work = NULL; |
| 4905 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 4906 | |
| 4907 | kfree(work); |
| 4908 | |
| 4909 | DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n", |
| 4910 | to_intel_bo(obj)); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4911 | return ret; |
| 4912 | } |
| 4913 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 4914 | /* Reference the objects for the scheduled work. */ |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4915 | drm_gem_object_reference(work->old_fb_obj); |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 4916 | drm_gem_object_reference(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4917 | |
| 4918 | crtc->fb = fb; |
| 4919 | i915_gem_object_flush_write_domain(obj); |
| 4920 | drm_vblank_get(dev, intel_crtc->pipe); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4921 | obj_priv = to_intel_bo(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4922 | atomic_inc(&obj_priv->pending_flip); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 4923 | work->pending_flip_obj = obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4924 | |
Jesse Barnes | 83f7fd0 | 2010-04-05 14:03:51 -0700 | [diff] [blame] | 4925 | if (intel_crtc->plane) |
| 4926 | flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 4927 | else |
| 4928 | flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; |
| 4929 | |
| 4930 | /* Wait for any previous flip to finish */ |
| 4931 | if (IS_GEN3(dev)) |
| 4932 | while (I915_READ(ISR) & flip_mask) |
| 4933 | ; |
| 4934 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4935 | BEGIN_LP_RING(4); |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 4936 | if (IS_I965G(dev)) { |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4937 | OUT_RING(MI_DISPLAY_FLIP | |
| 4938 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 4939 | OUT_RING(fb->pitch); |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 4940 | OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); |
Zhenyu Wang | aacef09 | 2010-02-09 09:46:20 +0800 | [diff] [blame] | 4941 | pipesrc = I915_READ(pipesrc_reg); |
| 4942 | OUT_RING(pipesrc & 0x0fff0fff); |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 4943 | } else { |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 4944 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
| 4945 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 4946 | OUT_RING(fb->pitch); |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 4947 | OUT_RING(obj_priv->gtt_offset); |
| 4948 | OUT_RING(MI_NOOP); |
| 4949 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4950 | ADVANCE_LP_RING(); |
| 4951 | |
| 4952 | mutex_unlock(&dev->struct_mutex); |
| 4953 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 4954 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 4955 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4956 | return 0; |
| 4957 | } |
| 4958 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4959 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
| 4960 | .dpms = intel_crtc_dpms, |
| 4961 | .mode_fixup = intel_crtc_mode_fixup, |
| 4962 | .mode_set = intel_crtc_mode_set, |
| 4963 | .mode_set_base = intel_pipe_set_base, |
| 4964 | .prepare = intel_crtc_prepare, |
| 4965 | .commit = intel_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 4966 | .load_lut = intel_crtc_load_lut, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4967 | }; |
| 4968 | |
| 4969 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 4970 | .cursor_set = intel_crtc_cursor_set, |
| 4971 | .cursor_move = intel_crtc_cursor_move, |
| 4972 | .gamma_set = intel_crtc_gamma_set, |
| 4973 | .set_config = drm_crtc_helper_set_config, |
| 4974 | .destroy = intel_crtc_destroy, |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4975 | .page_flip = intel_crtc_page_flip, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4976 | }; |
| 4977 | |
| 4978 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 4979 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4980 | { |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 4981 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4982 | struct intel_crtc *intel_crtc; |
| 4983 | int i; |
| 4984 | |
| 4985 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 4986 | if (intel_crtc == NULL) |
| 4987 | return; |
| 4988 | |
| 4989 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 4990 | |
| 4991 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
| 4992 | intel_crtc->pipe = pipe; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4993 | intel_crtc->plane = pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4994 | for (i = 0; i < 256; i++) { |
| 4995 | intel_crtc->lut_r[i] = i; |
| 4996 | intel_crtc->lut_g[i] = i; |
| 4997 | intel_crtc->lut_b[i] = i; |
| 4998 | } |
| 4999 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5000 | /* Swap pipes & planes for FBC on pre-965 */ |
| 5001 | intel_crtc->pipe = pipe; |
| 5002 | intel_crtc->plane = pipe; |
| 5003 | if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 5004 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5005 | intel_crtc->plane = ((pipe == 0) ? 1 : 0); |
| 5006 | } |
| 5007 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 5008 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 5009 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 5010 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 5011 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 5012 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5013 | intel_crtc->cursor_addr = 0; |
| 5014 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; |
| 5015 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 5016 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5017 | intel_crtc->busy = false; |
| 5018 | |
| 5019 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
| 5020 | (unsigned long)intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5021 | } |
| 5022 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5023 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 5024 | struct drm_file *file_priv) |
| 5025 | { |
| 5026 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5027 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5028 | struct drm_mode_object *drmmode_obj; |
| 5029 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5030 | |
| 5031 | if (!dev_priv) { |
| 5032 | DRM_ERROR("called with no initialization\n"); |
| 5033 | return -EINVAL; |
| 5034 | } |
| 5035 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5036 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 5037 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5038 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5039 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5040 | DRM_ERROR("no such CRTC id\n"); |
| 5041 | return -EINVAL; |
| 5042 | } |
| 5043 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5044 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 5045 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5046 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 5047 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 5048 | } |
| 5049 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5050 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
| 5051 | { |
| 5052 | struct drm_crtc *crtc = NULL; |
| 5053 | |
| 5054 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 5055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5056 | if (intel_crtc->pipe == pipe) |
| 5057 | break; |
| 5058 | } |
| 5059 | return crtc; |
| 5060 | } |
| 5061 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5062 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5063 | { |
| 5064 | int index_mask = 0; |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5065 | struct drm_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5066 | int entry = 0; |
| 5067 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5068 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 5069 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 5070 | if (type_mask & intel_encoder->clone_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5071 | index_mask |= (1 << entry); |
| 5072 | entry++; |
| 5073 | } |
| 5074 | return index_mask; |
| 5075 | } |
| 5076 | |
| 5077 | |
| 5078 | static void intel_setup_outputs(struct drm_device *dev) |
| 5079 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5080 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5081 | struct drm_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5082 | |
| 5083 | intel_crt_init(dev); |
| 5084 | |
| 5085 | /* Set up integrated LVDS */ |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 5086 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5087 | intel_lvds_init(dev); |
| 5088 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5089 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5090 | int found; |
| 5091 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5092 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
| 5093 | intel_dp_init(dev, DP_A); |
| 5094 | |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5095 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 5096 | /* PCH SDVOB multiplex with HDMIB */ |
| 5097 | found = intel_sdvo_init(dev, PCH_SDVOB); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5098 | if (!found) |
| 5099 | intel_hdmi_init(dev, HDMIB); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5100 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 5101 | intel_dp_init(dev, PCH_DP_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 5102 | } |
| 5103 | |
| 5104 | if (I915_READ(HDMIC) & PORT_DETECTED) |
| 5105 | intel_hdmi_init(dev, HDMIC); |
| 5106 | |
| 5107 | if (I915_READ(HDMID) & PORT_DETECTED) |
| 5108 | intel_hdmi_init(dev, HDMID); |
| 5109 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5110 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 5111 | intel_dp_init(dev, PCH_DP_C); |
| 5112 | |
| 5113 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
| 5114 | intel_dp_init(dev, PCH_DP_D); |
| 5115 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 5116 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5117 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 5118 | |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5119 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5120 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5121 | found = intel_sdvo_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5122 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 5123 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5124 | intel_hdmi_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5125 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5126 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5127 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
| 5128 | DRM_DEBUG_KMS("probing DP_B\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5129 | intel_dp_init(dev, DP_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5130 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5131 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 5132 | |
| 5133 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 5134 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5135 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
| 5136 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5137 | found = intel_sdvo_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5138 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5139 | |
| 5140 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
| 5141 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5142 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 5143 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5144 | intel_hdmi_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5145 | } |
| 5146 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 5147 | DRM_DEBUG_KMS("probing DP_C\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5148 | intel_dp_init(dev, DP_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5149 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 5150 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 5151 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5152 | if (SUPPORTS_INTEGRATED_DP(dev) && |
| 5153 | (I915_READ(DP_D) & DP_DETECTED)) { |
| 5154 | DRM_DEBUG_KMS("probing DP_D\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5155 | intel_dp_init(dev, DP_D); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 5156 | } |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5157 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5158 | intel_dvo_init(dev); |
| 5159 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 5160 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5161 | intel_tv_init(dev); |
| 5162 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5163 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 5164 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5165 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 5166 | encoder->possible_crtcs = intel_encoder->crtc_mask; |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 5167 | encoder->possible_clones = intel_encoder_clones(dev, |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 5168 | intel_encoder->clone_mask); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5169 | } |
| 5170 | } |
| 5171 | |
| 5172 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 5173 | { |
| 5174 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5175 | |
| 5176 | drm_framebuffer_cleanup(fb); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 5177 | drm_gem_object_unreference_unlocked(intel_fb->obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5178 | |
| 5179 | kfree(intel_fb); |
| 5180 | } |
| 5181 | |
| 5182 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 5183 | struct drm_file *file_priv, |
| 5184 | unsigned int *handle) |
| 5185 | { |
| 5186 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 5187 | struct drm_gem_object *object = intel_fb->obj; |
| 5188 | |
| 5189 | return drm_gem_handle_create(file_priv, object, handle); |
| 5190 | } |
| 5191 | |
| 5192 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 5193 | .destroy = intel_user_framebuffer_destroy, |
| 5194 | .create_handle = intel_user_framebuffer_create_handle, |
| 5195 | }; |
| 5196 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5197 | int intel_framebuffer_init(struct drm_device *dev, |
| 5198 | struct intel_framebuffer *intel_fb, |
| 5199 | struct drm_mode_fb_cmd *mode_cmd, |
| 5200 | struct drm_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5201 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5202 | int ret; |
| 5203 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5204 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 5205 | if (ret) { |
| 5206 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 5207 | return ret; |
| 5208 | } |
| 5209 | |
| 5210 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5211 | intel_fb->obj = obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5212 | return 0; |
| 5213 | } |
| 5214 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5215 | static struct drm_framebuffer * |
| 5216 | intel_user_framebuffer_create(struct drm_device *dev, |
| 5217 | struct drm_file *filp, |
| 5218 | struct drm_mode_fb_cmd *mode_cmd) |
| 5219 | { |
| 5220 | struct drm_gem_object *obj; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5221 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5222 | int ret; |
| 5223 | |
| 5224 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); |
| 5225 | if (!obj) |
| 5226 | return NULL; |
| 5227 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5228 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 5229 | if (!intel_fb) |
| 5230 | return NULL; |
| 5231 | |
| 5232 | ret = intel_framebuffer_init(dev, intel_fb, |
| 5233 | mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5234 | if (ret) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 5235 | drm_gem_object_unreference_unlocked(obj); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5236 | kfree(intel_fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5237 | return NULL; |
| 5238 | } |
| 5239 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5240 | return &intel_fb->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5241 | } |
| 5242 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5243 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5244 | .fb_create = intel_user_framebuffer_create, |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 5245 | .output_poll_changed = intel_fb_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5246 | }; |
| 5247 | |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5248 | static struct drm_gem_object * |
| 5249 | intel_alloc_power_context(struct drm_device *dev) |
| 5250 | { |
| 5251 | struct drm_gem_object *pwrctx; |
| 5252 | int ret; |
| 5253 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 5254 | pwrctx = i915_gem_alloc_object(dev, 4096); |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5255 | if (!pwrctx) { |
| 5256 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 5257 | return NULL; |
| 5258 | } |
| 5259 | |
| 5260 | mutex_lock(&dev->struct_mutex); |
| 5261 | ret = i915_gem_object_pin(pwrctx, 4096); |
| 5262 | if (ret) { |
| 5263 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 5264 | goto err_unref; |
| 5265 | } |
| 5266 | |
| 5267 | ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1); |
| 5268 | if (ret) { |
| 5269 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 5270 | goto err_unpin; |
| 5271 | } |
| 5272 | mutex_unlock(&dev->struct_mutex); |
| 5273 | |
| 5274 | return pwrctx; |
| 5275 | |
| 5276 | err_unpin: |
| 5277 | i915_gem_object_unpin(pwrctx); |
| 5278 | err_unref: |
| 5279 | drm_gem_object_unreference(pwrctx); |
| 5280 | mutex_unlock(&dev->struct_mutex); |
| 5281 | return NULL; |
| 5282 | } |
| 5283 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5284 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 5285 | { |
| 5286 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5287 | u16 rgvswctl; |
| 5288 | |
| 5289 | rgvswctl = I915_READ16(MEMSWCTL); |
| 5290 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 5291 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 5292 | return false; /* still busy with another command */ |
| 5293 | } |
| 5294 | |
| 5295 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 5296 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 5297 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 5298 | POSTING_READ16(MEMSWCTL); |
| 5299 | |
| 5300 | rgvswctl |= MEMCTL_CMD_STS; |
| 5301 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 5302 | |
| 5303 | return true; |
| 5304 | } |
| 5305 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5306 | void ironlake_enable_drps(struct drm_device *dev) |
| 5307 | { |
| 5308 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5309 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5310 | u8 fmax, fmin, fstart, vstart; |
| 5311 | int i = 0; |
| 5312 | |
| 5313 | /* 100ms RC evaluation intervals */ |
| 5314 | I915_WRITE(RCUPEI, 100000); |
| 5315 | I915_WRITE(RCDNEI, 100000); |
| 5316 | |
| 5317 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 5318 | I915_WRITE(RCBMAXAVG, 90000); |
| 5319 | I915_WRITE(RCBMINAVG, 80000); |
| 5320 | |
| 5321 | I915_WRITE(MEMIHYST, 1); |
| 5322 | |
| 5323 | /* Set up min, max, and cur for interrupt handling */ |
| 5324 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 5325 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 5326 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 5327 | MEMMODE_FSTART_SHIFT; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5328 | fstart = fmax; |
| 5329 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5330 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 5331 | PXVFREQ_PX_SHIFT; |
| 5332 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5333 | dev_priv->fmax = fstart; /* IPS callback will increase this */ |
| 5334 | dev_priv->fstart = fstart; |
| 5335 | |
| 5336 | dev_priv->max_delay = fmax; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5337 | dev_priv->min_delay = fmin; |
| 5338 | dev_priv->cur_delay = fstart; |
| 5339 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5340 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, |
| 5341 | fstart); |
| 5342 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5343 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 5344 | |
| 5345 | /* |
| 5346 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 5347 | */ |
| 5348 | |
| 5349 | I915_WRITE(VIDSTART, vstart); |
| 5350 | POSTING_READ(VIDSTART); |
| 5351 | |
| 5352 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 5353 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 5354 | |
| 5355 | while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { |
| 5356 | if (i++ > 100) { |
| 5357 | DRM_ERROR("stuck trying to change perf mode\n"); |
| 5358 | break; |
| 5359 | } |
| 5360 | msleep(1); |
| 5361 | } |
| 5362 | msleep(1); |
| 5363 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5364 | ironlake_set_drps(dev, fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5365 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5366 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
| 5367 | I915_READ(0x112e0); |
| 5368 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); |
| 5369 | dev_priv->last_count2 = I915_READ(0x112f4); |
| 5370 | getrawmonotonic(&dev_priv->last_time2); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5371 | } |
| 5372 | |
| 5373 | void ironlake_disable_drps(struct drm_device *dev) |
| 5374 | { |
| 5375 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5376 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5377 | |
| 5378 | /* Ack interrupts, disable EFC interrupt */ |
| 5379 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 5380 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 5381 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 5382 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 5383 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 5384 | |
| 5385 | /* Go back to the starting frequency */ |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5386 | ironlake_set_drps(dev, dev_priv->fstart); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5387 | msleep(1); |
| 5388 | rgvswctl |= MEMCTL_CMD_STS; |
| 5389 | I915_WRITE(MEMSWCTL, rgvswctl); |
| 5390 | msleep(1); |
| 5391 | |
| 5392 | } |
| 5393 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5394 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 5395 | { |
| 5396 | unsigned long freq; |
| 5397 | int div = (vidfreq & 0x3f0000) >> 16; |
| 5398 | int post = (vidfreq & 0x3000) >> 12; |
| 5399 | int pre = (vidfreq & 0x7); |
| 5400 | |
| 5401 | if (!pre) |
| 5402 | return 0; |
| 5403 | |
| 5404 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 5405 | |
| 5406 | return freq; |
| 5407 | } |
| 5408 | |
| 5409 | void intel_init_emon(struct drm_device *dev) |
| 5410 | { |
| 5411 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5412 | u32 lcfuse; |
| 5413 | u8 pxw[16]; |
| 5414 | int i; |
| 5415 | |
| 5416 | /* Disable to program */ |
| 5417 | I915_WRITE(ECR, 0); |
| 5418 | POSTING_READ(ECR); |
| 5419 | |
| 5420 | /* Program energy weights for various events */ |
| 5421 | I915_WRITE(SDEW, 0x15040d00); |
| 5422 | I915_WRITE(CSIEW0, 0x007f0000); |
| 5423 | I915_WRITE(CSIEW1, 0x1e220004); |
| 5424 | I915_WRITE(CSIEW2, 0x04000004); |
| 5425 | |
| 5426 | for (i = 0; i < 5; i++) |
| 5427 | I915_WRITE(PEW + (i * 4), 0); |
| 5428 | for (i = 0; i < 3; i++) |
| 5429 | I915_WRITE(DEW + (i * 4), 0); |
| 5430 | |
| 5431 | /* Program P-state weights to account for frequency power adjustment */ |
| 5432 | for (i = 0; i < 16; i++) { |
| 5433 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 5434 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 5435 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 5436 | PXVFREQ_PX_SHIFT; |
| 5437 | unsigned long val; |
| 5438 | |
| 5439 | val = vid * vid; |
| 5440 | val *= (freq / 1000); |
| 5441 | val *= 255; |
| 5442 | val /= (127*127*900); |
| 5443 | if (val > 0xff) |
| 5444 | DRM_ERROR("bad pxval: %ld\n", val); |
| 5445 | pxw[i] = val; |
| 5446 | } |
| 5447 | /* Render standby states get 0 weight */ |
| 5448 | pxw[14] = 0; |
| 5449 | pxw[15] = 0; |
| 5450 | |
| 5451 | for (i = 0; i < 4; i++) { |
| 5452 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 5453 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 5454 | I915_WRITE(PXW + (i * 4), val); |
| 5455 | } |
| 5456 | |
| 5457 | /* Adjust magic regs to magic values (more experimental results) */ |
| 5458 | I915_WRITE(OGW0, 0); |
| 5459 | I915_WRITE(OGW1, 0); |
| 5460 | I915_WRITE(EG0, 0x00007f00); |
| 5461 | I915_WRITE(EG1, 0x0000000e); |
| 5462 | I915_WRITE(EG2, 0x000e0000); |
| 5463 | I915_WRITE(EG3, 0x68000300); |
| 5464 | I915_WRITE(EG4, 0x42000000); |
| 5465 | I915_WRITE(EG5, 0x00140031); |
| 5466 | I915_WRITE(EG6, 0); |
| 5467 | I915_WRITE(EG7, 0); |
| 5468 | |
| 5469 | for (i = 0; i < 8; i++) |
| 5470 | I915_WRITE(PXWL + (i * 4), 0); |
| 5471 | |
| 5472 | /* Enable PMON + select events */ |
| 5473 | I915_WRITE(ECR, 0x80000019); |
| 5474 | |
| 5475 | lcfuse = I915_READ(LCFUSE02); |
| 5476 | |
| 5477 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
| 5478 | } |
| 5479 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5480 | void intel_init_clock_gating(struct drm_device *dev) |
| 5481 | { |
| 5482 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5483 | |
| 5484 | /* |
| 5485 | * Disable clock gating reported to work incorrectly according to the |
| 5486 | * specs, but enable as much else as we can. |
| 5487 | */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5488 | if (HAS_PCH_SPLIT(dev)) { |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 5489 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
| 5490 | |
| 5491 | if (IS_IRONLAKE(dev)) { |
| 5492 | /* Required for FBC */ |
| 5493 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; |
| 5494 | /* Required for CxSR */ |
| 5495 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
| 5496 | |
| 5497 | I915_WRITE(PCH_3DCGDIS0, |
| 5498 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 5499 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 5500 | } |
| 5501 | |
| 5502 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 5503 | |
| 5504 | /* |
| 5505 | * According to the spec the following bits should be set in |
| 5506 | * order to enable memory self-refresh |
| 5507 | * The bit 22/21 of 0x42004 |
| 5508 | * The bit 5 of 0x42020 |
| 5509 | * The bit 15 of 0x45000 |
| 5510 | */ |
| 5511 | if (IS_IRONLAKE(dev)) { |
| 5512 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5513 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5514 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
| 5515 | I915_WRITE(ILK_DSPCLK_GATE, |
| 5516 | (I915_READ(ILK_DSPCLK_GATE) | |
| 5517 | ILK_DPARB_CLK_GATE)); |
| 5518 | I915_WRITE(DISP_ARB_CTL, |
| 5519 | (I915_READ(DISP_ARB_CTL) | |
| 5520 | DISP_FBC_WM_DIS)); |
| 5521 | } |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 5522 | /* |
| 5523 | * Based on the document from hardware guys the following bits |
| 5524 | * should be set unconditionally in order to enable FBC. |
| 5525 | * The bit 22 of 0x42000 |
| 5526 | * The bit 22 of 0x42004 |
| 5527 | * The bit 7,8,9 of 0x42020. |
| 5528 | */ |
| 5529 | if (IS_IRONLAKE_M(dev)) { |
| 5530 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5531 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5532 | ILK_FBCQ_DIS); |
| 5533 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5534 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5535 | ILK_DPARB_GATE); |
| 5536 | I915_WRITE(ILK_DSPCLK_GATE, |
| 5537 | I915_READ(ILK_DSPCLK_GATE) | |
| 5538 | ILK_DPFC_DIS1 | |
| 5539 | ILK_DPFC_DIS2 | |
| 5540 | ILK_CLK_FBC); |
| 5541 | } |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 5542 | return; |
| 5543 | } else if (IS_G4X(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5544 | uint32_t dspclk_gate; |
| 5545 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 5546 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 5547 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 5548 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 5549 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5550 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 5551 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 5552 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 5553 | if (IS_GM45(dev)) |
| 5554 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 5555 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
| 5556 | } else if (IS_I965GM(dev)) { |
| 5557 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 5558 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 5559 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 5560 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5561 | I915_WRITE16(DEUC, 0); |
| 5562 | } else if (IS_I965G(dev)) { |
| 5563 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 5564 | I965_RCC_CLOCK_GATE_DISABLE | |
| 5565 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 5566 | I965_ISC_CLOCK_GATE_DISABLE | |
| 5567 | I965_FBC_CLOCK_GATE_DISABLE); |
| 5568 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 5569 | } else if (IS_I9XX(dev)) { |
| 5570 | u32 dstate = I915_READ(D_STATE); |
| 5571 | |
| 5572 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 5573 | DSTATE_DOT_CLOCK_GATING; |
| 5574 | I915_WRITE(D_STATE, dstate); |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 5575 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5576 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 5577 | } else if (IS_I830(dev)) { |
| 5578 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 5579 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5580 | |
| 5581 | /* |
| 5582 | * GPU can automatically power down the render unit if given a page |
| 5583 | * to save state. |
| 5584 | */ |
Andrew Lutomirski | 1d3c36ad | 2009-12-21 10:10:22 -0500 | [diff] [blame] | 5585 | if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5586 | struct drm_i915_gem_object *obj_priv = NULL; |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5587 | |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5588 | if (dev_priv->pwrctx) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5589 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5590 | } else { |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5591 | struct drm_gem_object *pwrctx; |
| 5592 | |
| 5593 | pwrctx = intel_alloc_power_context(dev); |
| 5594 | if (pwrctx) { |
| 5595 | dev_priv->pwrctx = pwrctx; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5596 | obj_priv = to_intel_bo(pwrctx); |
Andrew Lutomirski | 7e8b60f | 2009-11-08 13:49:51 -0500 | [diff] [blame] | 5597 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5598 | } |
| 5599 | |
Chris Wilson | 9ea8d05 | 2010-01-04 18:57:56 +0000 | [diff] [blame] | 5600 | if (obj_priv) { |
| 5601 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); |
| 5602 | I915_WRITE(MCHBAR_RENDER_STANDBY, |
| 5603 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); |
| 5604 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5605 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5606 | } |
| 5607 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5608 | /* Set up chip specific display functions */ |
| 5609 | static void intel_init_display(struct drm_device *dev) |
| 5610 | { |
| 5611 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5612 | |
| 5613 | /* We always want a DPMS function */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5614 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5615 | dev_priv->display.dpms = ironlake_crtc_dpms; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5616 | else |
| 5617 | dev_priv->display.dpms = i9xx_crtc_dpms; |
| 5618 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 5619 | if (I915_HAS_FBC(dev)) { |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 5620 | if (IS_IRONLAKE_M(dev)) { |
| 5621 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 5622 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
| 5623 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 5624 | } else if (IS_GM45(dev)) { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 5625 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 5626 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 5627 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
Robert Hooker | 8d06a1e | 2010-03-19 15:13:27 -0400 | [diff] [blame] | 5628 | } else if (IS_I965GM(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5629 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 5630 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 5631 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 5632 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 5633 | /* 855GM needs testing */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5634 | } |
| 5635 | |
| 5636 | /* Returns the core display clock speed */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5637 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5638 | dev_priv->display.get_display_clock_speed = |
| 5639 | i945_get_display_clock_speed; |
| 5640 | else if (IS_I915G(dev)) |
| 5641 | dev_priv->display.get_display_clock_speed = |
| 5642 | i915_get_display_clock_speed; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5643 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5644 | dev_priv->display.get_display_clock_speed = |
| 5645 | i9xx_misc_get_display_clock_speed; |
| 5646 | else if (IS_I915GM(dev)) |
| 5647 | dev_priv->display.get_display_clock_speed = |
| 5648 | i915gm_get_display_clock_speed; |
| 5649 | else if (IS_I865G(dev)) |
| 5650 | dev_priv->display.get_display_clock_speed = |
| 5651 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 5652 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5653 | dev_priv->display.get_display_clock_speed = |
| 5654 | i855_get_display_clock_speed; |
| 5655 | else /* 852, 830 */ |
| 5656 | dev_priv->display.get_display_clock_speed = |
| 5657 | i830_get_display_clock_speed; |
| 5658 | |
| 5659 | /* For FIFO watermark updates */ |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 5660 | if (HAS_PCH_SPLIT(dev)) { |
| 5661 | if (IS_IRONLAKE(dev)) { |
| 5662 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
| 5663 | dev_priv->display.update_wm = ironlake_update_wm; |
| 5664 | else { |
| 5665 | DRM_DEBUG_KMS("Failed to get proper latency. " |
| 5666 | "Disable CxSR\n"); |
| 5667 | dev_priv->display.update_wm = NULL; |
| 5668 | } |
| 5669 | } else |
| 5670 | dev_priv->display.update_wm = NULL; |
| 5671 | } else if (IS_PINEVIEW(dev)) { |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5672 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5673 | dev_priv->is_ddr3, |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5674 | dev_priv->fsb_freq, |
| 5675 | dev_priv->mem_freq)) { |
| 5676 | DRM_INFO("failed to find known CxSR latency " |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5677 | "(found ddr%s fsb freq %d, mem freq %d), " |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5678 | "disabling CxSR\n", |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 5679 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 5680 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 5681 | /* Disable CxSR and never update its watermark again */ |
| 5682 | pineview_disable_cxsr(dev); |
| 5683 | dev_priv->display.update_wm = NULL; |
| 5684 | } else |
| 5685 | dev_priv->display.update_wm = pineview_update_wm; |
| 5686 | } else if (IS_G4X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5687 | dev_priv->display.update_wm = g4x_update_wm; |
| 5688 | else if (IS_I965G(dev)) |
| 5689 | dev_priv->display.update_wm = i965_update_wm; |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 5690 | else if (IS_I9XX(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5691 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5692 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 5693 | } else if (IS_I85X(dev)) { |
| 5694 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5695 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5696 | } else { |
Adam Jackson | 8f4695e | 2010-04-16 18:20:57 -0400 | [diff] [blame] | 5697 | dev_priv->display.update_wm = i830_update_wm; |
| 5698 | if (IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5699 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 5700 | else |
| 5701 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5702 | } |
| 5703 | } |
| 5704 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5705 | void intel_modeset_init(struct drm_device *dev) |
| 5706 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5707 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5708 | int i; |
| 5709 | |
| 5710 | drm_mode_config_init(dev); |
| 5711 | |
| 5712 | dev->mode_config.min_width = 0; |
| 5713 | dev->mode_config.min_height = 0; |
| 5714 | |
| 5715 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
| 5716 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5717 | intel_init_display(dev); |
| 5718 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5719 | if (IS_I965G(dev)) { |
| 5720 | dev->mode_config.max_width = 8192; |
| 5721 | dev->mode_config.max_height = 8192; |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 5722 | } else if (IS_I9XX(dev)) { |
| 5723 | dev->mode_config.max_width = 4096; |
| 5724 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5725 | } else { |
| 5726 | dev->mode_config.max_width = 2048; |
| 5727 | dev->mode_config.max_height = 2048; |
| 5728 | } |
| 5729 | |
| 5730 | /* set memory base */ |
| 5731 | if (IS_I9XX(dev)) |
| 5732 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); |
| 5733 | else |
| 5734 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
| 5735 | |
| 5736 | if (IS_MOBILE(dev) || IS_I9XX(dev)) |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 5737 | dev_priv->num_pipe = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5738 | else |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 5739 | dev_priv->num_pipe = 1; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 5740 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 5741 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5742 | |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 5743 | for (i = 0; i < dev_priv->num_pipe; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5744 | intel_crtc_init(dev, i); |
| 5745 | } |
| 5746 | |
| 5747 | intel_setup_outputs(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5748 | |
| 5749 | intel_init_clock_gating(dev); |
| 5750 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5751 | if (IS_IRONLAKE_M(dev)) { |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5752 | ironlake_enable_drps(dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5753 | intel_init_emon(dev); |
| 5754 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5755 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5756 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
| 5757 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
| 5758 | (unsigned long)dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 5759 | |
| 5760 | intel_setup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5761 | } |
| 5762 | |
| 5763 | void intel_modeset_cleanup(struct drm_device *dev) |
| 5764 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5765 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5766 | struct drm_crtc *crtc; |
| 5767 | struct intel_crtc *intel_crtc; |
| 5768 | |
| 5769 | mutex_lock(&dev->struct_mutex); |
| 5770 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 5771 | drm_kms_helper_poll_fini(dev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 5772 | intel_fbdev_fini(dev); |
| 5773 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5774 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 5775 | /* Skip inactive CRTCs */ |
| 5776 | if (!crtc->fb) |
| 5777 | continue; |
| 5778 | |
| 5779 | intel_crtc = to_intel_crtc(crtc); |
| 5780 | intel_increase_pllclock(crtc, false); |
| 5781 | del_timer_sync(&intel_crtc->idle_timer); |
| 5782 | } |
| 5783 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5784 | del_timer_sync(&dev_priv->idle_timer); |
| 5785 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 5786 | if (dev_priv->display.disable_fbc) |
| 5787 | dev_priv->display.disable_fbc(dev); |
| 5788 | |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5789 | if (dev_priv->pwrctx) { |
Kristian Høgsberg | c1b5dea | 2009-11-11 12:19:18 -0500 | [diff] [blame] | 5790 | struct drm_i915_gem_object *obj_priv; |
| 5791 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 5792 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
Kristian Høgsberg | c1b5dea | 2009-11-11 12:19:18 -0500 | [diff] [blame] | 5793 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); |
| 5794 | I915_READ(PWRCTXA); |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 5795 | i915_gem_object_unpin(dev_priv->pwrctx); |
| 5796 | drm_gem_object_unreference(dev_priv->pwrctx); |
| 5797 | } |
| 5798 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 5799 | if (IS_IRONLAKE_M(dev)) |
| 5800 | ironlake_disable_drps(dev); |
| 5801 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 5802 | mutex_unlock(&dev->struct_mutex); |
| 5803 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5804 | drm_mode_config_cleanup(dev); |
| 5805 | } |
| 5806 | |
| 5807 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 5808 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 5809 | * Return which encoder is currently attached for connector. |
| 5810 | */ |
| 5811 | struct drm_encoder *intel_attached_encoder (struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5812 | { |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 5813 | struct drm_mode_object *obj; |
| 5814 | struct drm_encoder *encoder; |
| 5815 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5816 | |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 5817 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { |
| 5818 | if (connector->encoder_ids[i] == 0) |
| 5819 | break; |
| 5820 | |
| 5821 | obj = drm_mode_object_find(connector->dev, |
| 5822 | connector->encoder_ids[i], |
| 5823 | DRM_MODE_OBJECT_ENCODER); |
| 5824 | if (!obj) |
| 5825 | continue; |
| 5826 | |
| 5827 | encoder = obj_to_encoder(obj); |
| 5828 | return encoder; |
| 5829 | } |
| 5830 | return NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5831 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 5832 | |
| 5833 | /* |
| 5834 | * set vga decode state - true == enable VGA decode |
| 5835 | */ |
| 5836 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 5837 | { |
| 5838 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5839 | u16 gmch_ctrl; |
| 5840 | |
| 5841 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
| 5842 | if (state) |
| 5843 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 5844 | else |
| 5845 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 5846 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
| 5847 | return 0; |
| 5848 | } |