blob: 679b349d9b66695f65bb3597b2a530e3e9709600 [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Vinod Koul90b44f82011-07-25 19:57:52 +053026#include <linux/scatterlist.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100027#include <linux/bitmap.h>
28#include <asm/page.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000029
Chris Leechc13c8262006-05-23 17:18:44 -070030/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070031 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070032 *
33 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 */
35typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070036#define DMA_MIN_COOKIE 1
37#define DMA_MAX_COOKIE INT_MAX
Chris Leechc13c8262006-05-23 17:18:44 -070038
39#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
40
41/**
42 * enum dma_status - DMA transaction status
43 * @DMA_SUCCESS: transaction completed successfully
44 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070045 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070046 * @DMA_ERROR: transaction failed
47 */
48enum dma_status {
49 DMA_SUCCESS,
50 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070051 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070052 DMA_ERROR,
53};
54
55/**
Dan Williams7405f742007-01-02 11:10:43 -070056 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070057 *
58 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
59 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070060 */
61enum dma_transaction_type {
62 DMA_MEMCPY,
63 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070064 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070065 DMA_XOR_VAL,
66 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070067 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070068 DMA_INTERRUPT,
Ira Snydera86ee032010-09-30 11:46:44 +000069 DMA_SG,
Dan Williams59b5ec22009-01-06 11:38:15 -070070 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070071 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070072 DMA_SLAVE,
Sascha Hauer782bc952010-09-30 13:56:32 +000073 DMA_CYCLIC,
Jassi Brarb14dab72011-10-13 12:33:30 +053074 DMA_INTERLEAVE,
Dan Williams7405f742007-01-02 11:10:43 -070075/* last transaction type for creation of the capabilities mask */
Jassi Brarb14dab72011-10-13 12:33:30 +053076 DMA_TX_TYPE_END,
77};
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070078
Vinod Koul49920bc2011-10-13 15:15:27 +053079/**
80 * enum dma_transfer_direction - dma transfer mode and direction indicator
81 * @DMA_MEM_TO_MEM: Async/Memcpy mode
82 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
83 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
84 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
85 */
86enum dma_transfer_direction {
87 DMA_MEM_TO_MEM,
88 DMA_MEM_TO_DEV,
89 DMA_DEV_TO_MEM,
90 DMA_DEV_TO_DEV,
Shawn Guo62268ce2011-12-13 23:48:03 +080091 DMA_TRANS_NONE,
Vinod Koul49920bc2011-10-13 15:15:27 +053092};
Dan Williams7405f742007-01-02 11:10:43 -070093
94/**
Jassi Brarb14dab72011-10-13 12:33:30 +053095 * Interleaved Transfer Request
96 * ----------------------------
97 * A chunk is collection of contiguous bytes to be transfered.
98 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
99 * ICGs may or maynot change between chunks.
100 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
101 * that when repeated an integral number of times, specifies the transfer.
102 * A transfer template is specification of a Frame, the number of times
103 * it is to be repeated and other per-transfer attributes.
104 *
105 * Practically, a client driver would have ready a template for each
106 * type of transfer it is going to need during its lifetime and
107 * set only 'src_start' and 'dst_start' before submitting the requests.
108 *
109 *
110 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
111 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
112 *
113 * == Chunk size
114 * ... ICG
115 */
116
117/**
118 * struct data_chunk - Element of scatter-gather list that makes a frame.
119 * @size: Number of bytes to read from source.
120 * size_dst := fn(op, size_src), so doesn't mean much for destination.
121 * @icg: Number of bytes to jump after last src/dst address of this
122 * chunk and before first src/dst address for next chunk.
123 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
124 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
125 */
126struct data_chunk {
127 size_t size;
128 size_t icg;
129};
130
131/**
132 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
133 * and attributes.
134 * @src_start: Bus address of source for the first chunk.
135 * @dst_start: Bus address of destination for the first chunk.
136 * @dir: Specifies the type of Source and Destination.
137 * @src_inc: If the source address increments after reading from it.
138 * @dst_inc: If the destination address increments after writing to it.
139 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
140 * Otherwise, source is read contiguously (icg ignored).
141 * Ignored if src_inc is false.
142 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
143 * Otherwise, destination is filled contiguously (icg ignored).
144 * Ignored if dst_inc is false.
145 * @numf: Number of frames in this template.
146 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
147 * @sgl: Array of {chunk,icg} pairs that make up a frame.
148 */
149struct dma_interleaved_template {
150 dma_addr_t src_start;
151 dma_addr_t dst_start;
152 enum dma_transfer_direction dir;
153 bool src_inc;
154 bool dst_inc;
155 bool src_sgl;
156 bool dst_sgl;
157 size_t numf;
158 size_t frame_size;
159 struct data_chunk sgl[0];
160};
161
162/**
Dan Williams636bdea2008-04-17 20:17:26 -0700163 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700164 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -0700165 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700166 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +0100167 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700168 * acknowledges receipt, i.e. has has a chance to establish any dependency
169 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -0700170 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
171 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200172 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
173 * (if not set, do the source dma-unmapping as page)
174 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
175 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700176 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
177 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
178 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
179 * sources that were the result of a previous operation, in the case of a PQ
180 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -0700181 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
182 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -0700183 */
Dan Williams636bdea2008-04-17 20:17:26 -0700184enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700185 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700186 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700187 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
188 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200189 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
190 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700191 DMA_PREP_PQ_DISABLE_P = (1 << 6),
192 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
193 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700194 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700195};
196
197/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700198 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
199 * on a running channel.
200 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
201 * @DMA_PAUSE: pause ongoing transfers
202 * @DMA_RESUME: resume paused transfer
Linus Walleijc156d0a2010-08-04 13:37:33 +0200203 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
204 * that need to runtime reconfigure the slave channels (as opposed to passing
205 * configuration data in statically from the platform). An additional
206 * argument of struct dma_slave_config must be passed in with this
207 * command.
Ira Snyder968f19a2010-09-30 11:46:46 +0000208 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
209 * into external start mode.
Linus Walleijc3635c72010-03-26 16:44:01 -0700210 */
211enum dma_ctrl_cmd {
212 DMA_TERMINATE_ALL,
213 DMA_PAUSE,
214 DMA_RESUME,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200215 DMA_SLAVE_CONFIG,
Ira Snyder968f19a2010-09-30 11:46:46 +0000216 FSLDMA_EXTERNAL_START,
Linus Walleijc3635c72010-03-26 16:44:01 -0700217};
218
219/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700220 * enum sum_check_bits - bit position of pq_check_flags
221 */
222enum sum_check_bits {
223 SUM_CHECK_P = 0,
224 SUM_CHECK_Q = 1,
225};
226
227/**
228 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
229 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
230 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
231 */
232enum sum_check_flags {
233 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
234 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
235};
236
237
238/**
Dan Williams7405f742007-01-02 11:10:43 -0700239 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
240 * See linux/cpumask.h
241 */
242typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
243
244/**
Chris Leechc13c8262006-05-23 17:18:44 -0700245 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700246 * @memcpy_count: transaction counter
247 * @bytes_transferred: byte counter
248 */
249
250struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700251 /* stats */
252 unsigned long memcpy_count;
253 unsigned long bytes_transferred;
254};
255
256/**
257 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700258 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700259 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700260 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700261 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700262 * @device_node: used to add this to the device chan list
263 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700264 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700265 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800266 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700267 */
268struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700269 struct dma_device *device;
270 dma_cookie_t cookie;
271
272 /* sysfs */
273 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700274 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700275
Chris Leechc13c8262006-05-23 17:18:44 -0700276 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900277 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700278 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700279 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800280 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700281};
282
Dan Williams41d5e592009-01-06 11:38:21 -0700283/**
284 * struct dma_chan_dev - relate sysfs device node to backing channel device
285 * @chan - driver channel device
286 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700287 * @dev_id - parent dma_device dev_id
288 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700289 */
290struct dma_chan_dev {
291 struct dma_chan *chan;
292 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700293 int dev_id;
294 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700295};
296
Linus Walleijc156d0a2010-08-04 13:37:33 +0200297/**
298 * enum dma_slave_buswidth - defines bus with of the DMA slave
299 * device, source or target buses
300 */
301enum dma_slave_buswidth {
302 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
303 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
304 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
305 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
306 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
307};
308
309/**
310 * struct dma_slave_config - dma slave channel runtime config
311 * @direction: whether the data shall go in or out on this slave
312 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
313 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
314 * need to differentiate source and target addresses.
315 * @src_addr: this is the physical address where DMA slave data
316 * should be read (RX), if the source is memory this argument is
317 * ignored.
318 * @dst_addr: this is the physical address where DMA slave data
319 * should be written (TX), if the source is memory this argument
320 * is ignored.
321 * @src_addr_width: this is the width in bytes of the source (RX)
322 * register where DMA data shall be read. If the source
323 * is memory this may be ignored depending on architecture.
324 * Legal values: 1, 2, 4, 8.
325 * @dst_addr_width: same as src_addr_width but for destination
326 * target (TX) mutatis mutandis.
327 * @src_maxburst: the maximum number of words (note: words, as in
328 * units of the src_addr_width member, not bytes) that can be sent
329 * in one burst to the device. Typically something like half the
330 * FIFO depth on I/O peripherals so you don't overflow it. This
331 * may or may not be applicable on memory sources.
332 * @dst_maxburst: same as src_maxburst but for destination target
333 * mutatis mutandis.
334 *
335 * This struct is passed in as configuration data to a DMA engine
336 * in order to set up a certain channel for DMA transport at runtime.
337 * The DMA device/engine has to provide support for an additional
338 * command in the channel config interface, DMA_SLAVE_CONFIG
339 * and this struct will then be passed in as an argument to the
340 * DMA engine device_control() function.
341 *
342 * The rationale for adding configuration information to this struct
343 * is as follows: if it is likely that most DMA slave controllers in
344 * the world will support the configuration option, then make it
345 * generic. If not: if it is fixed so that it be sent in static from
346 * the platform data, then prefer to do that. Else, if it is neither
347 * fixed at runtime, nor generic enough (such as bus mastership on
348 * some CPU family and whatnot) then create a custom slave config
349 * struct and pass that, then make this config a member of that
350 * struct, if applicable.
351 */
352struct dma_slave_config {
Vinod Koul49920bc2011-10-13 15:15:27 +0530353 enum dma_transfer_direction direction;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200354 dma_addr_t src_addr;
355 dma_addr_t dst_addr;
356 enum dma_slave_buswidth src_addr_width;
357 enum dma_slave_buswidth dst_addr_width;
358 u32 src_maxburst;
359 u32 dst_maxburst;
360};
361
Dan Williams41d5e592009-01-06 11:38:21 -0700362static inline const char *dma_chan_name(struct dma_chan *chan)
363{
364 return dev_name(&chan->dev->device);
365}
Dan Williamsd379b012007-07-09 11:56:42 -0700366
Chris Leechc13c8262006-05-23 17:18:44 -0700367void dma_chan_cleanup(struct kref *kref);
368
Chris Leechc13c8262006-05-23 17:18:44 -0700369/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700370 * typedef dma_filter_fn - callback filter for dma_request_channel
371 * @chan: channel to be reviewed
372 * @filter_param: opaque parameter passed through dma_request_channel
373 *
374 * When this optional parameter is specified in a call to dma_request_channel a
375 * suitable channel is passed to this routine for further dispositioning before
376 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700377 * satisfies the given capability mask. It returns 'true' to indicate that the
378 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700379 */
Dan Williams7dd60252009-01-06 11:38:19 -0700380typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700381
Dan Williams7405f742007-01-02 11:10:43 -0700382typedef void (*dma_async_tx_callback)(void *dma_async_param);
383/**
384 * struct dma_async_tx_descriptor - async transaction descriptor
385 * ---dma generic offload fields---
386 * @cookie: tracking cookie for this transaction, set to -EBUSY if
387 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700388 * @flags: flags to augment operation preparation, control completion, and
389 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700390 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700391 * @chan: target channel for this operation
392 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700393 * @callback: routine to call after this operation is complete
394 * @callback_param: general parameter to pass to the callback routine
395 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700396 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700397 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700398 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700399 */
400struct dma_async_tx_descriptor {
401 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700402 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700403 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700404 struct dma_chan *chan;
405 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700406 dma_async_tx_callback callback;
407 void *callback_param;
Dan Williams5fc6d892010-10-07 16:44:50 -0700408#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams19242d72008-04-17 20:17:25 -0700409 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700410 struct dma_async_tx_descriptor *parent;
411 spinlock_t lock;
Dan Williamscaa20d972010-05-17 16:24:16 -0700412#endif
Dan Williams7405f742007-01-02 11:10:43 -0700413};
414
Dan Williams5fc6d892010-10-07 16:44:50 -0700415#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williamscaa20d972010-05-17 16:24:16 -0700416static inline void txd_lock(struct dma_async_tx_descriptor *txd)
417{
418}
419static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
420{
421}
422static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
423{
424 BUG();
425}
426static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
427{
428}
429static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
430{
431}
432static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
433{
434 return NULL;
435}
436static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
437{
438 return NULL;
439}
440
441#else
442static inline void txd_lock(struct dma_async_tx_descriptor *txd)
443{
444 spin_lock_bh(&txd->lock);
445}
446static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
447{
448 spin_unlock_bh(&txd->lock);
449}
450static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
451{
452 txd->next = next;
453 next->parent = txd;
454}
455static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
456{
457 txd->parent = NULL;
458}
459static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
460{
461 txd->next = NULL;
462}
463static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
464{
465 return txd->parent;
466}
467static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
468{
469 return txd->next;
470}
471#endif
472
Chris Leechc13c8262006-05-23 17:18:44 -0700473/**
Linus Walleij07934482010-03-26 16:50:49 -0700474 * struct dma_tx_state - filled in to report the status of
475 * a transfer.
476 * @last: last completed DMA cookie
477 * @used: last issued DMA cookie (i.e. the one in progress)
478 * @residue: the remaining number of bytes left to transmit
479 * on the selected transfer for states DMA_IN_PROGRESS and
480 * DMA_PAUSED if this is implemented in the driver, else 0
481 */
482struct dma_tx_state {
483 dma_cookie_t last;
484 dma_cookie_t used;
485 u32 residue;
486};
487
488/**
Chris Leechc13c8262006-05-23 17:18:44 -0700489 * struct dma_device - info on the entity supplying DMA services
490 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900491 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700492 * @channels: the list of struct dma_chan
493 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700494 * @cap_mask: one or more dma_capability flags
495 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700496 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700497 * @copy_align: alignment shift for memcpy operations
498 * @xor_align: alignment shift for xor operations
499 * @pq_align: alignment shift for pq operations
500 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700501 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700502 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700503 * @device_alloc_chan_resources: allocate resources and return the
504 * number of allocated descriptors
505 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700506 * @device_prep_dma_memcpy: prepares a memcpy operation
507 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700508 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700509 * @device_prep_dma_pq: prepares a pq operation
510 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700511 * @device_prep_dma_memset: prepares a memset operation
512 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700513 * @device_prep_slave_sg: prepares a slave dma operation
Sascha Hauer782bc952010-09-30 13:56:32 +0000514 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
515 * The function takes a buffer of size buf_len. The callback function will
516 * be called after period_len bytes have been transferred.
Jassi Brarb14dab72011-10-13 12:33:30 +0530517 * @device_prep_interleaved_dma: Transfer expression in a generic way.
Linus Walleijc3635c72010-03-26 16:44:01 -0700518 * @device_control: manipulate all pending operations on a channel, returns
519 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700520 * @device_tx_status: poll for transaction completion, the optional
521 * txstate parameter can be supplied with a pointer to get a
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300522 * struct with auxiliary transfer status information, otherwise the call
Linus Walleij07934482010-03-26 16:50:49 -0700523 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700524 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700525 */
526struct dma_device {
527
528 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900529 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700530 struct list_head channels;
531 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700532 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700533 unsigned short max_xor;
534 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700535 u8 copy_align;
536 u8 xor_align;
537 u8 pq_align;
538 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700539 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700540
Chris Leechc13c8262006-05-23 17:18:44 -0700541 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700542 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700543
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700544 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700545 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700546
547 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700548 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700549 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700550 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700551 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700552 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700553 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700554 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700555 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700556 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
557 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
558 unsigned int src_cnt, const unsigned char *scf,
559 size_t len, unsigned long flags);
560 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
561 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
562 unsigned int src_cnt, const unsigned char *scf, size_t len,
563 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700564 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700565 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700566 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700567 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700568 struct dma_chan *chan, unsigned long flags);
Ira Snydera86ee032010-09-30 11:46:44 +0000569 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
570 struct dma_chan *chan,
571 struct scatterlist *dst_sg, unsigned int dst_nents,
572 struct scatterlist *src_sg, unsigned int src_nents,
573 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700574
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700575 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
576 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Koul49920bc2011-10-13 15:15:27 +0530577 unsigned int sg_len, enum dma_transfer_direction direction,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700578 unsigned long flags);
Sascha Hauer782bc952010-09-30 13:56:32 +0000579 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
580 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Vinod Koul49920bc2011-10-13 15:15:27 +0530581 size_t period_len, enum dma_transfer_direction direction);
Jassi Brarb14dab72011-10-13 12:33:30 +0530582 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
583 struct dma_chan *chan, struct dma_interleaved_template *xt,
584 unsigned long flags);
Linus Walleij05827632010-05-17 16:30:42 -0700585 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
586 unsigned long arg);
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700587
Linus Walleij07934482010-03-26 16:50:49 -0700588 enum dma_status (*device_tx_status)(struct dma_chan *chan,
589 dma_cookie_t cookie,
590 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700591 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700592};
593
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000594static inline int dmaengine_device_control(struct dma_chan *chan,
595 enum dma_ctrl_cmd cmd,
596 unsigned long arg)
597{
598 return chan->device->device_control(chan, cmd, arg);
599}
600
601static inline int dmaengine_slave_config(struct dma_chan *chan,
602 struct dma_slave_config *config)
603{
604 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
605 (unsigned long)config);
606}
607
Vinod Koul90b44f82011-07-25 19:57:52 +0530608static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
609 struct dma_chan *chan, void *buf, size_t len,
Vinod Koul49920bc2011-10-13 15:15:27 +0530610 enum dma_transfer_direction dir, unsigned long flags)
Vinod Koul90b44f82011-07-25 19:57:52 +0530611{
612 struct scatterlist sg;
613 sg_init_one(&sg, buf, len);
614
615 return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
616}
617
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000618static inline int dmaengine_terminate_all(struct dma_chan *chan)
619{
620 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
621}
622
623static inline int dmaengine_pause(struct dma_chan *chan)
624{
625 return dmaengine_device_control(chan, DMA_PAUSE, 0);
626}
627
628static inline int dmaengine_resume(struct dma_chan *chan)
629{
630 return dmaengine_device_control(chan, DMA_RESUME, 0);
631}
632
Russell King - ARM Linux98d530f2011-01-01 23:00:23 +0000633static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000634{
635 return desc->tx_submit(desc);
636}
637
Dan Williams83544ae2009-09-08 17:42:53 -0700638static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
639{
640 size_t mask;
641
642 if (!align)
643 return true;
644 mask = (1 << align) - 1;
645 if (mask & (off1 | off2 | len))
646 return false;
647 return true;
648}
649
650static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
651 size_t off2, size_t len)
652{
653 return dmaengine_check_align(dev->copy_align, off1, off2, len);
654}
655
656static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
657 size_t off2, size_t len)
658{
659 return dmaengine_check_align(dev->xor_align, off1, off2, len);
660}
661
662static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
663 size_t off2, size_t len)
664{
665 return dmaengine_check_align(dev->pq_align, off1, off2, len);
666}
667
668static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
669 size_t off2, size_t len)
670{
671 return dmaengine_check_align(dev->fill_align, off1, off2, len);
672}
673
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700674static inline void
675dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
676{
677 dma->max_pq = maxpq;
678 if (has_pq_continue)
679 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
680}
681
682static inline bool dmaf_continue(enum dma_ctrl_flags flags)
683{
684 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
685}
686
687static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
688{
689 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
690
691 return (flags & mask) == mask;
692}
693
694static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
695{
696 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
697}
698
Mathieu Lacaged3f3cf82010-08-14 15:02:44 +0200699static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700700{
701 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
702}
703
704/* dma_maxpq - reduce maxpq in the face of continued operations
705 * @dma - dma device with PQ capability
706 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
707 *
708 * When an engine does not support native continuation we need 3 extra
709 * source slots to reuse P and Q with the following coefficients:
710 * 1/ {00} * P : remove P from Q', but use it as a source for P'
711 * 2/ {01} * Q : use Q to continue Q' calculation
712 * 3/ {00} * Q : subtract Q from P' to cancel (2)
713 *
714 * In the case where P is disabled we only need 1 extra source:
715 * 1/ {01} * Q : use Q to continue Q' calculation
716 */
717static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
718{
719 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
720 return dma_dev_to_maxpq(dma);
721 else if (dmaf_p_disabled_continue(flags))
722 return dma_dev_to_maxpq(dma) - 1;
723 else if (dmaf_continue(flags))
724 return dma_dev_to_maxpq(dma) - 3;
725 BUG();
726}
727
Chris Leechc13c8262006-05-23 17:18:44 -0700728/* --- public DMA engine API --- */
729
Dan Williams649274d2009-01-11 00:20:39 -0800730#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700731void dmaengine_get(void);
732void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800733#else
734static inline void dmaengine_get(void)
735{
736}
737static inline void dmaengine_put(void)
738{
739}
740#endif
741
David S. Millerb4bd07c2009-02-06 22:06:43 -0800742#ifdef CONFIG_NET_DMA
743#define net_dmaengine_get() dmaengine_get()
744#define net_dmaengine_put() dmaengine_put()
745#else
746static inline void net_dmaengine_get(void)
747{
748}
749static inline void net_dmaengine_put(void)
750{
751}
752#endif
753
Dan Williams729b5d12009-03-25 09:13:25 -0700754#ifdef CONFIG_ASYNC_TX_DMA
755#define async_dmaengine_get() dmaengine_get()
756#define async_dmaengine_put() dmaengine_put()
Dan Williams5fc6d892010-10-07 16:44:50 -0700757#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -0700758#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
759#else
Dan Williams729b5d12009-03-25 09:13:25 -0700760#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams5fc6d892010-10-07 16:44:50 -0700761#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700762#else
763static inline void async_dmaengine_get(void)
764{
765}
766static inline void async_dmaengine_put(void)
767{
768}
769static inline struct dma_chan *
770async_dma_find_channel(enum dma_transaction_type type)
771{
772 return NULL;
773}
Dan Williams138f4c32009-09-08 17:42:51 -0700774#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700775
Dan Williams7405f742007-01-02 11:10:43 -0700776dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
777 void *dest, void *src, size_t len);
778dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
779 struct page *page, unsigned int offset, void *kdata, size_t len);
780dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700781 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700782 unsigned int src_off, size_t len);
783void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
784 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700785
Dan Williams08398752008-07-17 17:59:56 -0700786static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700787{
Dan Williams636bdea2008-04-17 20:17:26 -0700788 tx->flags |= DMA_CTRL_ACK;
789}
790
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700791static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
792{
793 tx->flags &= ~DMA_CTRL_ACK;
794}
795
Dan Williams08398752008-07-17 17:59:56 -0700796static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700797{
Dan Williams08398752008-07-17 17:59:56 -0700798 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700799}
800
Dan Williams7405f742007-01-02 11:10:43 -0700801#define first_dma_cap(mask) __first_dma_cap(&(mask))
802static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
803{
804 return min_t(int, DMA_TX_TYPE_END,
805 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
806}
807
808#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
809static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
810{
811 return min_t(int, DMA_TX_TYPE_END,
812 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
813}
814
815#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
816static inline void
817__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
818{
819 set_bit(tx_type, dstp->bits);
820}
821
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900822#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
823static inline void
824__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
825{
826 clear_bit(tx_type, dstp->bits);
827}
828
Dan Williams33df8ca2009-01-06 11:38:15 -0700829#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
830static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
831{
832 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
833}
834
Dan Williams7405f742007-01-02 11:10:43 -0700835#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
836static inline int
837__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
838{
839 return test_bit(tx_type, srcp->bits);
840}
841
842#define for_each_dma_cap_mask(cap, mask) \
843 for ((cap) = first_dma_cap(mask); \
844 (cap) < DMA_TX_TYPE_END; \
845 (cap) = next_dma_cap((cap), (mask)))
846
Chris Leechc13c8262006-05-23 17:18:44 -0700847/**
Dan Williams7405f742007-01-02 11:10:43 -0700848 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700849 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700850 *
851 * This allows drivers to push copies to HW in batches,
852 * reducing MMIO writes where possible.
853 */
Dan Williams7405f742007-01-02 11:10:43 -0700854static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700855{
Dan Williamsec8670f2008-03-01 07:51:29 -0700856 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700857}
858
Dan Williams7405f742007-01-02 11:10:43 -0700859#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
860
Chris Leechc13c8262006-05-23 17:18:44 -0700861/**
Dan Williams7405f742007-01-02 11:10:43 -0700862 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700863 * @chan: DMA channel
864 * @cookie: transaction identifier to check status of
865 * @last: returns last completed cookie, can be NULL
866 * @used: returns last issued cookie, can be NULL
867 *
868 * If @last and @used are passed in, upon return they reflect the driver
869 * internal state and can be used with dma_async_is_complete() to check
870 * the status of multiple cookies without re-checking hardware state.
871 */
Dan Williams7405f742007-01-02 11:10:43 -0700872static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700873 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
874{
Linus Walleij07934482010-03-26 16:50:49 -0700875 struct dma_tx_state state;
876 enum dma_status status;
877
878 status = chan->device->device_tx_status(chan, cookie, &state);
879 if (last)
880 *last = state.last;
881 if (used)
882 *used = state.used;
883 return status;
Chris Leechc13c8262006-05-23 17:18:44 -0700884}
885
Dan Williams7405f742007-01-02 11:10:43 -0700886#define dma_async_memcpy_complete(chan, cookie, last, used)\
887 dma_async_is_tx_complete(chan, cookie, last, used)
888
Chris Leechc13c8262006-05-23 17:18:44 -0700889/**
890 * dma_async_is_complete - test a cookie against chan state
891 * @cookie: transaction identifier to test status of
892 * @last_complete: last know completed transaction
893 * @last_used: last cookie value handed out
894 *
895 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000896 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700897 */
898static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
899 dma_cookie_t last_complete, dma_cookie_t last_used)
900{
901 if (last_complete <= last_used) {
902 if ((cookie <= last_complete) || (cookie > last_used))
903 return DMA_SUCCESS;
904 } else {
905 if ((cookie <= last_complete) && (cookie > last_used))
906 return DMA_SUCCESS;
907 }
908 return DMA_IN_PROGRESS;
909}
910
Dan Williamsbca34692010-03-26 16:52:10 -0700911static inline void
912dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
913{
914 if (st) {
915 st->last = last;
916 st->used = used;
917 st->residue = residue;
918 }
919}
920
Dan Williams7405f742007-01-02 11:10:43 -0700921enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700922#ifdef CONFIG_DMA_ENGINE
923enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -0700924void dma_issue_pending_all(void);
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100925struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
926void dma_release_channel(struct dma_chan *chan);
Dan Williams07f22112009-01-05 17:14:31 -0700927#else
928static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
929{
930 return DMA_SUCCESS;
931}
Dan Williamsc50331e2009-01-19 15:33:14 -0700932static inline void dma_issue_pending_all(void)
933{
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100934}
935static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
936 dma_filter_fn fn, void *fn_param)
937{
938 return NULL;
939}
940static inline void dma_release_channel(struct dma_chan *chan)
941{
Dan Williamsc50331e2009-01-19 15:33:14 -0700942}
Dan Williams07f22112009-01-05 17:14:31 -0700943#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700944
945/* --- DMA device --- */
946
947int dma_async_device_register(struct dma_device *device);
948void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -0700949void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -0700950struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dan Williams59b5ec22009-01-06 11:38:15 -0700951#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
Chris Leechc13c8262006-05-23 17:18:44 -0700952
Chris Leechde5506e2006-05-23 17:50:37 -0700953/* --- Helper iov-locking functions --- */
954
955struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000956 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700957 int nr_pages;
958 struct page **pages;
959};
960
961struct dma_pinned_list {
962 int nr_iovecs;
963 struct dma_page_list page_list[0];
964};
965
966struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
967void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
968
969dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
970 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
971dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
972 struct dma_pinned_list *pinned_list, struct page *page,
973 unsigned int offset, size_t len);
974
Chris Leechc13c8262006-05-23 17:18:44 -0700975#endif /* DMAENGINE_H */