blob: fe36966f7e347dedd4781cef96fcec5ff79e62f3 [file] [log] [blame]
Akira Iguchia619f981b2007-01-26 16:28:18 +09001/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
Alan Coxab771632008-10-27 15:09:10 +000011 * Copyright (C) 2003 Red Hat Inc
Akira Iguchia619f981b2007-01-26 16:28:18 +090012 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040046#define DRV_VERSION "0.3"
Akira Iguchia619f981b2007-01-26 16:28:18 +090047
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50/* PCI BARs */
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54/* offset of CTRL registers */
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69/* offset of BMID registers */
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89/* register value */
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120/* PIO transfer mode table */
121/* JCHST */
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125};
126
127/* JCHHT */
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131};
132
133/* JCHCT */
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137};
138
139/* DMA transfer mode table */
140/* JCHDCTM/JCHDCTS */
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144};
145
146/* JCSTWTM/JCSTWTS */
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150};
151
152/* JCTSS */
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156};
157
158/* JCENVT */
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162};
163
164/* JCACTSELS/JCACTSELM */
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
Peter Hueweaf4d6e22010-07-15 20:39:43 +0200171 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
Akira Iguchia619f981b2007-01-26 16:28:18 +0900172 { } /* terminate list */
173};
174
175/**
176 * scc_set_piomode - Initialize host controller PATA PIO timings
177 * @ap: Port whose timings we are configuring
178 * @adev: um
179 *
180 * Set PIO mode for device.
181 *
182 * LOCKING:
183 * None (inherited from caller).
184 */
185
186static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
187{
188 unsigned int pio = adev->pio_mode - XFER_PIO_0;
189 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
190 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
191 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
192 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
193 unsigned long reg;
194 int offset;
195
196 reg = in_be32(cckctrl_port);
197 if (reg & CCKCTRL_ATACLKOEN)
198 offset = 1; /* 133MHz */
199 else
200 offset = 0; /* 100MHz */
201
202 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
203 out_be32(piosht_port, reg);
204 reg = JCHCTtbl[offset][pio];
205 out_be32(pioct_port, reg);
206}
207
208/**
209 * scc_set_dmamode - Initialize host controller PATA DMA timings
210 * @ap: Port whose timings we are configuring
211 * @adev: um
Akira Iguchia619f981b2007-01-26 16:28:18 +0900212 *
213 * Set UDMA mode for device.
214 *
215 * LOCKING:
216 * None (inherited from caller).
217 */
218
219static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
220{
221 unsigned int udma = adev->dma_mode;
222 unsigned int is_slave = (adev->devno != 0);
223 u8 speed = udma;
224 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
225 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
226 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
227 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
228 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
229 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
230 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
231 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
232 int offset, idx;
233
Jeff Garzika84471f2007-02-26 05:51:33 -0500234 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900235 offset = 1; /* 133MHz */
236 else
237 offset = 0; /* 100MHz */
238
239 if (speed >= XFER_UDMA_0)
240 idx = speed - XFER_UDMA_0;
241 else
242 return;
243
244 if (is_slave) {
245 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
246 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
247 out_be32(tdvhsel_port,
248 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
249 } else {
250 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
251 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
252 out_be32(tdvhsel_port,
253 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
254 }
255 out_be32(udenvt_port,
256 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
257}
258
Akira Iguchidcd03442007-07-17 12:10:17 +0900259unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
260{
261 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
262 if (adev->class == ATA_DEV_ATAPI &&
263 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
264 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
265 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
266 }
Tejun Heoc7087652010-05-10 21:41:34 +0200267 return mask;
Akira Iguchidcd03442007-07-17 12:10:17 +0900268}
269
Akira Iguchia619f981b2007-01-26 16:28:18 +0900270/**
271 * scc_tf_load - send taskfile registers to host controller
272 * @ap: Port to which output is sent
273 * @tf: ATA taskfile register set
274 *
Tejun Heo9363c382008-04-07 22:47:16 +0900275 * Note: Original code is ata_sff_tf_load().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900276 */
277
278static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
279{
280 struct ata_ioports *ioaddr = &ap->ioaddr;
281 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
282
283 if (tf->ctl != ap->last_ctl) {
284 out_be32(ioaddr->ctl_addr, tf->ctl);
285 ap->last_ctl = tf->ctl;
286 ata_wait_idle(ap);
287 }
288
289 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
290 out_be32(ioaddr->feature_addr, tf->hob_feature);
291 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
292 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
293 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
294 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
295 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
296 tf->hob_feature,
297 tf->hob_nsect,
298 tf->hob_lbal,
299 tf->hob_lbam,
300 tf->hob_lbah);
301 }
302
303 if (is_addr) {
304 out_be32(ioaddr->feature_addr, tf->feature);
305 out_be32(ioaddr->nsect_addr, tf->nsect);
306 out_be32(ioaddr->lbal_addr, tf->lbal);
307 out_be32(ioaddr->lbam_addr, tf->lbam);
308 out_be32(ioaddr->lbah_addr, tf->lbah);
309 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
310 tf->feature,
311 tf->nsect,
312 tf->lbal,
313 tf->lbam,
314 tf->lbah);
315 }
316
317 if (tf->flags & ATA_TFLAG_DEVICE) {
318 out_be32(ioaddr->device_addr, tf->device);
319 VPRINTK("device 0x%X\n", tf->device);
320 }
321
322 ata_wait_idle(ap);
323}
324
325/**
326 * scc_check_status - Read device status reg & clear interrupt
327 * @ap: port where the device is
328 *
329 * Note: Original code is ata_check_status().
330 */
331
332static u8 scc_check_status (struct ata_port *ap)
333{
334 return in_be32(ap->ioaddr.status_addr);
335}
336
337/**
338 * scc_tf_read - input device's ATA taskfile shadow registers
339 * @ap: Port from which input is read
340 * @tf: ATA taskfile register set for storing input
341 *
Tejun Heo9363c382008-04-07 22:47:16 +0900342 * Note: Original code is ata_sff_tf_read().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900343 */
344
345static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
346{
347 struct ata_ioports *ioaddr = &ap->ioaddr;
348
349 tf->command = scc_check_status(ap);
350 tf->feature = in_be32(ioaddr->error_addr);
351 tf->nsect = in_be32(ioaddr->nsect_addr);
352 tf->lbal = in_be32(ioaddr->lbal_addr);
353 tf->lbam = in_be32(ioaddr->lbam_addr);
354 tf->lbah = in_be32(ioaddr->lbah_addr);
355 tf->device = in_be32(ioaddr->device_addr);
356
357 if (tf->flags & ATA_TFLAG_LBA48) {
358 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
359 tf->hob_feature = in_be32(ioaddr->error_addr);
360 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
361 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
362 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
363 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
Petr Vandrovecfe36cb52007-07-20 07:44:44 -0400364 out_be32(ioaddr->ctl_addr, tf->ctl);
365 ap->last_ctl = tf->ctl;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900366 }
367}
368
369/**
370 * scc_exec_command - issue ATA command to host controller
371 * @ap: port to which command is being issued
372 * @tf: ATA taskfile register set
373 *
Tejun Heo9363c382008-04-07 22:47:16 +0900374 * Note: Original code is ata_sff_exec_command().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900375 */
376
377static void scc_exec_command (struct ata_port *ap,
378 const struct ata_taskfile *tf)
379{
Tejun Heo878d4fe2007-02-21 16:36:33 +0900380 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900381
382 out_be32(ap->ioaddr.command_addr, tf->command);
Tejun Heo9363c382008-04-07 22:47:16 +0900383 ata_sff_pause(ap);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900384}
385
386/**
387 * scc_check_altstatus - Read device alternate status reg
388 * @ap: port where the device is
389 */
390
391static u8 scc_check_altstatus (struct ata_port *ap)
392{
393 return in_be32(ap->ioaddr.altstatus_addr);
394}
395
396/**
Tejun Heo9363c382008-04-07 22:47:16 +0900397 * scc_dev_select - Select device 0/1 on ATA bus
Akira Iguchia619f981b2007-01-26 16:28:18 +0900398 * @ap: ATA channel to manipulate
399 * @device: ATA device (numbered from zero) to select
400 *
Tejun Heo9363c382008-04-07 22:47:16 +0900401 * Note: Original code is ata_sff_dev_select().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900402 */
403
Tejun Heo9363c382008-04-07 22:47:16 +0900404static void scc_dev_select (struct ata_port *ap, unsigned int device)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900405{
406 u8 tmp;
407
408 if (device == 0)
409 tmp = ATA_DEVICE_OBS;
410 else
411 tmp = ATA_DEVICE_OBS | ATA_DEV1;
412
413 out_be32(ap->ioaddr.device_addr, tmp);
Tejun Heo9363c382008-04-07 22:47:16 +0900414 ata_sff_pause(ap);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900415}
416
417/**
Sergei Shtylyov41dec292010-05-07 22:47:50 +0400418 * scc_set_devctl - Write device control reg
419 * @ap: port where the device is
420 * @ctl: value to write
421 */
422
423static void scc_set_devctl(struct ata_port *ap, u8 ctl)
424{
425 out_be32(ap->ioaddr.ctl_addr, ctl);
426}
427
428/**
Akira Iguchia619f981b2007-01-26 16:28:18 +0900429 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
430 * @qc: Info associated with this ATA transaction.
431 *
432 * Note: Original code is ata_bmdma_setup().
433 */
434
435static void scc_bmdma_setup (struct ata_queued_cmd *qc)
436{
437 struct ata_port *ap = qc->ap;
438 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
439 u8 dmactl;
440 void __iomem *mmio = ap->ioaddr.bmdma_addr;
441
442 /* load PRD table addr */
Tejun Heof60d7012010-05-10 21:41:41 +0200443 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900444
445 /* specify data direction, triple-check start bit is clear */
446 dmactl = in_be32(mmio + SCC_DMA_CMD);
447 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
448 if (!rw)
449 dmactl |= ATA_DMA_WR;
450 out_be32(mmio + SCC_DMA_CMD, dmactl);
451
452 /* issue r/w command */
Tejun Heo5682ed32008-04-07 22:47:16 +0900453 ap->ops->sff_exec_command(ap, &qc->tf);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900454}
455
456/**
457 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
458 * @qc: Info associated with this ATA transaction.
459 *
460 * Note: Original code is ata_bmdma_start().
461 */
462
463static void scc_bmdma_start (struct ata_queued_cmd *qc)
464{
465 struct ata_port *ap = qc->ap;
466 u8 dmactl;
467 void __iomem *mmio = ap->ioaddr.bmdma_addr;
468
469 /* start host DMA transaction */
470 dmactl = in_be32(mmio + SCC_DMA_CMD);
471 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
472}
473
474/**
475 * scc_devchk - PATA device presence detection
476 * @ap: ATA channel to examine
477 * @device: Device to examine (starting at zero)
478 *
479 * Note: Original code is ata_devchk().
480 */
481
482static unsigned int scc_devchk (struct ata_port *ap,
483 unsigned int device)
484{
485 struct ata_ioports *ioaddr = &ap->ioaddr;
486 u8 nsect, lbal;
487
Tejun Heo5682ed32008-04-07 22:47:16 +0900488 ap->ops->sff_dev_select(ap, device);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900489
490 out_be32(ioaddr->nsect_addr, 0x55);
491 out_be32(ioaddr->lbal_addr, 0xaa);
492
493 out_be32(ioaddr->nsect_addr, 0xaa);
494 out_be32(ioaddr->lbal_addr, 0x55);
495
496 out_be32(ioaddr->nsect_addr, 0x55);
497 out_be32(ioaddr->lbal_addr, 0xaa);
498
499 nsect = in_be32(ioaddr->nsect_addr);
500 lbal = in_be32(ioaddr->lbal_addr);
501
502 if ((nsect == 0x55) && (lbal == 0xaa))
503 return 1; /* we found a device */
504
505 return 0; /* nothing found */
506}
507
508/**
Tejun Heo705e76b2008-04-07 22:47:19 +0900509 * scc_wait_after_reset - wait for devices to become ready after reset
Akira Iguchia619f981b2007-01-26 16:28:18 +0900510 *
Tejun Heo705e76b2008-04-07 22:47:19 +0900511 * Note: Original code is ata_sff_wait_after_reset
Akira Iguchia619f981b2007-01-26 16:28:18 +0900512 */
513
Sergei Shtylyovfe6005b2010-04-24 20:29:45 +0400514static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
515 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900516{
Tejun Heo705e76b2008-04-07 22:47:19 +0900517 struct ata_port *ap = link->ap;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900518 struct ata_ioports *ioaddr = &ap->ioaddr;
519 unsigned int dev0 = devmask & (1 << 0);
520 unsigned int dev1 = devmask & (1 << 1);
Tejun Heo705e76b2008-04-07 22:47:19 +0900521 int rc, ret = 0;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900522
Tejun Heo705e76b2008-04-07 22:47:19 +0900523 /* Spec mandates ">= 2ms" before checking status. We wait
524 * 150ms, because that was the magic delay used for ATAPI
525 * devices in Hale Landis's ATADRVR, for the period of time
526 * between when the ATA command register is written, and then
527 * status is checked. Because waiting for "a while" before
528 * checking status is fine, post SRST, we perform this magic
529 * delay here as well.
530 *
531 * Old drivers/ide uses the 2mS rule and then waits for ready.
Akira Iguchia619f981b2007-01-26 16:28:18 +0900532 */
Tejun Heo705e76b2008-04-07 22:47:19 +0900533 msleep(150);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900534
Tejun Heo705e76b2008-04-07 22:47:19 +0900535 /* always check readiness of the master device */
536 rc = ata_sff_wait_ready(link, deadline);
537 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
538 * and TF status is 0xff, bail out on it too.
Akira Iguchia619f981b2007-01-26 16:28:18 +0900539 */
Tejun Heo705e76b2008-04-07 22:47:19 +0900540 if (rc)
541 return rc;
542
543 /* if device 1 was found in ata_devchk, wait for register
544 * access briefly, then wait for BSY to clear.
545 */
546 if (dev1) {
547 int i;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900548
Tejun Heo5682ed32008-04-07 22:47:16 +0900549 ap->ops->sff_dev_select(ap, 1);
Tejun Heo705e76b2008-04-07 22:47:19 +0900550
551 /* Wait for register access. Some ATAPI devices fail
552 * to set nsect/lbal after reset, so don't waste too
553 * much time on it. We're gonna wait for !BSY anyway.
554 */
555 for (i = 0; i < 2; i++) {
556 u8 nsect, lbal;
557
558 nsect = in_be32(ioaddr->nsect_addr);
559 lbal = in_be32(ioaddr->lbal_addr);
560 if ((nsect == 1) && (lbal == 1))
561 break;
562 msleep(50); /* give drive a breather */
563 }
564
565 rc = ata_sff_wait_ready(link, deadline);
566 if (rc) {
567 if (rc != -ENODEV)
568 return rc;
569 ret = rc;
570 }
Tony Breeds7e068372007-05-23 14:26:43 -0700571 }
Akira Iguchia619f981b2007-01-26 16:28:18 +0900572
573 /* is all this really necessary? */
Tejun Heo5682ed32008-04-07 22:47:16 +0900574 ap->ops->sff_dev_select(ap, 0);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900575 if (dev1)
Tejun Heo5682ed32008-04-07 22:47:16 +0900576 ap->ops->sff_dev_select(ap, 1);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900577 if (dev0)
Tejun Heo5682ed32008-04-07 22:47:16 +0900578 ap->ops->sff_dev_select(ap, 0);
Tony Breeds7e068372007-05-23 14:26:43 -0700579
Tejun Heo705e76b2008-04-07 22:47:19 +0900580 return ret;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900581}
582
583/**
584 * scc_bus_softreset - PATA device software reset
585 *
586 * Note: Original code is ata_bus_softreset().
587 */
588
Tony Breeds7e068372007-05-23 14:26:43 -0700589static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
590 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900591{
592 struct ata_ioports *ioaddr = &ap->ioaddr;
593
Tejun Heo878d4fe2007-02-21 16:36:33 +0900594 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900595
596 /* software reset. causes dev0 to be selected */
597 out_be32(ioaddr->ctl_addr, ap->ctl);
598 udelay(20);
599 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
600 udelay(20);
601 out_be32(ioaddr->ctl_addr, ap->ctl);
602
Stephen Rothwelle50e3ce2008-04-09 13:34:40 +1000603 scc_wait_after_reset(&ap->link, devmask, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900604
605 return 0;
606}
607
608/**
Tejun Heo9363c382008-04-07 22:47:16 +0900609 * scc_softreset - reset host port via ATA SRST
Akira Iguchia619f981b2007-01-26 16:28:18 +0900610 * @ap: port to reset
611 * @classes: resulting classes of attached devices
Tony Breeds7e068372007-05-23 14:26:43 -0700612 * @deadline: deadline jiffies for the operation
Akira Iguchia619f981b2007-01-26 16:28:18 +0900613 *
Tejun Heo9363c382008-04-07 22:47:16 +0900614 * Note: Original code is ata_sff_softreset().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900615 */
616
Tejun Heo9363c382008-04-07 22:47:16 +0900617static int scc_softreset(struct ata_link *link, unsigned int *classes,
618 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900619{
Satyam Sharmab90fe232007-09-22 08:20:09 +0530620 struct ata_port *ap = link->ap;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900621 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
622 unsigned int devmask = 0, err_mask;
623 u8 err;
624
625 DPRINTK("ENTER\n");
626
Akira Iguchia619f981b2007-01-26 16:28:18 +0900627 /* determine if device 0/1 are present */
628 if (scc_devchk(ap, 0))
629 devmask |= (1 << 0);
630 if (slave_possible && scc_devchk(ap, 1))
631 devmask |= (1 << 1);
632
633 /* select device 0 again */
Tejun Heo5682ed32008-04-07 22:47:16 +0900634 ap->ops->sff_dev_select(ap, 0);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900635
636 /* issue bus reset */
637 DPRINTK("about to softreset, devmask=%x\n", devmask);
Tony Breeds7e068372007-05-23 14:26:43 -0700638 err_mask = scc_bus_softreset(ap, devmask, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900639 if (err_mask) {
640 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
641 err_mask);
642 return -EIO;
643 }
644
645 /* determine by signature whether we have ATA or ATAPI devices */
Tejun Heo9363c382008-04-07 22:47:16 +0900646 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
Tejun Heo3f198592007-09-02 23:23:57 +0900647 devmask & (1 << 0), &err);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900648 if (slave_possible && err != 0x81)
Tejun Heo9363c382008-04-07 22:47:16 +0900649 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
Tejun Heo3f198592007-09-02 23:23:57 +0900650 devmask & (1 << 1), &err);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900651
Akira Iguchia619f981b2007-01-26 16:28:18 +0900652 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
653 return 0;
654}
655
656/**
657 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
658 * @qc: Command we are ending DMA for
659 */
660
661static void scc_bmdma_stop (struct ata_queued_cmd *qc)
662{
663 struct ata_port *ap = qc->ap;
664 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
665 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
666 u32 reg;
667
668 while (1) {
669 reg = in_be32(bmid_base + SCC_DMA_INTST);
670
671 if (reg & INTSTS_SERROR) {
672 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
673 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
674 out_be32(bmid_base + SCC_DMA_CMD,
675 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
676 continue;
677 }
678
679 if (reg & INTSTS_PRERR) {
680 u32 maea0, maec0;
681 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
682 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
683 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
684 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
685 out_be32(bmid_base + SCC_DMA_CMD,
686 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
687 continue;
688 }
689
690 if (reg & INTSTS_RERR) {
691 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
692 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
693 out_be32(bmid_base + SCC_DMA_CMD,
694 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
695 continue;
696 }
697
698 if (reg & INTSTS_ICERR) {
699 out_be32(bmid_base + SCC_DMA_CMD,
700 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
701 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
702 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
703 continue;
704 }
705
706 if (reg & INTSTS_BMSINT) {
707 unsigned int classes;
Tejun Heo341c2c92008-05-20 02:17:51 +0900708 unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900709 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
710 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
711 /* TBD: SW reset */
Tejun Heo9363c382008-04-07 22:47:16 +0900712 scc_softreset(&ap->link, &classes, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900713 continue;
714 }
715
716 if (reg & INTSTS_BMHE) {
717 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
718 continue;
719 }
720
721 if (reg & INTSTS_ACTEINT) {
722 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
723 continue;
724 }
725
726 if (reg & INTSTS_IOIRQS) {
727 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
728 continue;
729 }
730 break;
731 }
732
733 /* clear start/stop bit */
734 out_be32(bmid_base + SCC_DMA_CMD,
735 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
736
737 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
Alan Coxa57c1ba2008-05-29 22:10:58 +0100738 ata_sff_dma_pause(ap); /* dummy read */
Akira Iguchia619f981b2007-01-26 16:28:18 +0900739}
740
741/**
742 * scc_bmdma_status - Read PCI IDE BMDMA status
743 * @ap: Port associated with this ATA transaction.
744 */
745
746static u8 scc_bmdma_status (struct ata_port *ap)
747{
Akira Iguchia619f981b2007-01-26 16:28:18 +0900748 void __iomem *mmio = ap->ioaddr.bmdma_addr;
Akira Iguchifae57d32007-07-10 18:29:34 +0900749 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
750 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
Satyam Sharmab90fe232007-09-22 08:20:09 +0530751 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Akira Iguchifae57d32007-07-10 18:29:34 +0900752 static int retry = 0;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900753
Akira Iguchifae57d32007-07-10 18:29:34 +0900754 /* return if IOS_SS is cleared */
755 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
756 return host_stat;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900757
Akira Iguchifae57d32007-07-10 18:29:34 +0900758 /* errata A252,A308 workaround: Step4 */
Alan Coxa57c1ba2008-05-29 22:10:58 +0100759 if ((scc_check_altstatus(ap) & ATA_ERR)
760 && (int_status & INTSTS_INTRQ))
Akira Iguchifae57d32007-07-10 18:29:34 +0900761 return (host_stat | ATA_DMA_INTR);
762
763 /* errata A308 workaround Step5 */
764 if (int_status & INTSTS_IOIRQS) {
765 host_stat |= ATA_DMA_INTR;
766
767 /* We don't check ATAPI DMA because it is limited to UDMA4 */
768 if ((qc->tf.protocol == ATA_PROT_DMA &&
769 qc->dev->xfer_mode > XFER_UDMA_4)) {
770 if (!(int_status & INTSTS_ACTEINT)) {
Akira Iguchidcd03442007-07-17 12:10:17 +0900771 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
772 ap->print_id);
Akira Iguchifae57d32007-07-10 18:29:34 +0900773 host_stat |= ATA_DMA_ERR;
774 if (retry++)
Akira Iguchidcd03442007-07-17 12:10:17 +0900775 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
Akira Iguchifae57d32007-07-10 18:29:34 +0900776 } else
777 retry = 0;
778 }
Akira Iguchia619f981b2007-01-26 16:28:18 +0900779 }
780
781 return host_stat;
782}
783
784/**
785 * scc_data_xfer - Transfer data by PIO
Tejun Heo55dba312007-12-05 16:43:07 +0900786 * @dev: device for this I/O
Akira Iguchia619f981b2007-01-26 16:28:18 +0900787 * @buf: data buffer
788 * @buflen: buffer length
Tejun Heo55dba312007-12-05 16:43:07 +0900789 * @rw: read/write
Akira Iguchia619f981b2007-01-26 16:28:18 +0900790 *
Tejun Heo9363c382008-04-07 22:47:16 +0900791 * Note: Original code is ata_sff_data_xfer().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900792 */
793
Tejun Heo55dba312007-12-05 16:43:07 +0900794static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
795 unsigned int buflen, int rw)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900796{
Tejun Heo55dba312007-12-05 16:43:07 +0900797 struct ata_port *ap = dev->link->ap;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900798 unsigned int words = buflen >> 1;
799 unsigned int i;
Al Viro826cd152008-03-25 05:18:11 +0000800 __le16 *buf16 = (__le16 *) buf;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900801 void __iomem *mmio = ap->ioaddr.data_addr;
802
803 /* Transfer multiple of 2 bytes */
Tejun Heo55dba312007-12-05 16:43:07 +0900804 if (rw == READ)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900805 for (i = 0; i < words; i++)
Al Viro826cd152008-03-25 05:18:11 +0000806 buf16[i] = cpu_to_le16(in_be32(mmio));
Tejun Heo55dba312007-12-05 16:43:07 +0900807 else
808 for (i = 0; i < words; i++)
Al Viro826cd152008-03-25 05:18:11 +0000809 out_be32(mmio, le16_to_cpu(buf16[i]));
Akira Iguchia619f981b2007-01-26 16:28:18 +0900810
811 /* Transfer trailing 1 byte, if any. */
812 if (unlikely(buflen & 0x01)) {
Al Viro826cd152008-03-25 05:18:11 +0000813 __le16 align_buf[1] = { 0 };
Akira Iguchia619f981b2007-01-26 16:28:18 +0900814 unsigned char *trailing_buf = buf + buflen - 1;
815
Tejun Heo55dba312007-12-05 16:43:07 +0900816 if (rw == READ) {
Al Viro826cd152008-03-25 05:18:11 +0000817 align_buf[0] = cpu_to_le16(in_be32(mmio));
Akira Iguchia619f981b2007-01-26 16:28:18 +0900818 memcpy(trailing_buf, align_buf, 1);
Tejun Heo55dba312007-12-05 16:43:07 +0900819 } else {
820 memcpy(align_buf, trailing_buf, 1);
Al Viro826cd152008-03-25 05:18:11 +0000821 out_be32(mmio, le16_to_cpu(align_buf[0]));
Akira Iguchia619f981b2007-01-26 16:28:18 +0900822 }
Tejun Heo55dba312007-12-05 16:43:07 +0900823 words++;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900824 }
Tejun Heo55dba312007-12-05 16:43:07 +0900825
826 return words << 1;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900827}
828
829/**
Akira Iguchia619f981b2007-01-26 16:28:18 +0900830 * scc_pata_prereset - prepare for reset
831 * @ap: ATA port to be reset
Tony Breeds7e068372007-05-23 14:26:43 -0700832 * @deadline: deadline jiffies for the operation
Akira Iguchia619f981b2007-01-26 16:28:18 +0900833 */
834
Satyam Sharmab90fe232007-09-22 08:20:09 +0530835static int scc_pata_prereset(struct ata_link *link, unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900836{
Satyam Sharmab90fe232007-09-22 08:20:09 +0530837 link->ap->cbl = ATA_CBL_PATA80;
Tejun Heo9363c382008-04-07 22:47:16 +0900838 return ata_sff_prereset(link, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900839}
840
841/**
Tejun Heo9363c382008-04-07 22:47:16 +0900842 * scc_postreset - standard postreset callback
Akira Iguchia619f981b2007-01-26 16:28:18 +0900843 * @ap: the target ata_port
844 * @classes: classes of attached devices
845 *
Tejun Heo9363c382008-04-07 22:47:16 +0900846 * Note: Original code is ata_sff_postreset().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900847 */
848
Tejun Heo9363c382008-04-07 22:47:16 +0900849static void scc_postreset(struct ata_link *link, unsigned int *classes)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900850{
Satyam Sharmab90fe232007-09-22 08:20:09 +0530851 struct ata_port *ap = link->ap;
852
Akira Iguchia619f981b2007-01-26 16:28:18 +0900853 DPRINTK("ENTER\n");
854
Akira Iguchia619f981b2007-01-26 16:28:18 +0900855 /* is double-select really necessary? */
856 if (classes[0] != ATA_DEV_NONE)
Tejun Heo5682ed32008-04-07 22:47:16 +0900857 ap->ops->sff_dev_select(ap, 1);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900858 if (classes[1] != ATA_DEV_NONE)
Tejun Heo5682ed32008-04-07 22:47:16 +0900859 ap->ops->sff_dev_select(ap, 0);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900860
861 /* bail out if no device is present */
862 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
863 DPRINTK("EXIT, no device\n");
864 return;
865 }
866
867 /* set up device control */
Sergei Shtylyovec86c812010-04-24 20:29:58 +0400868 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900869
870 DPRINTK("EXIT\n");
871}
872
873/**
Tejun Heo9363c382008-04-07 22:47:16 +0900874 * scc_irq_clear - Clear PCI IDE BMDMA interrupt.
Akira Iguchia619f981b2007-01-26 16:28:18 +0900875 * @ap: Port associated with this ATA transaction.
876 *
Tejun Heo37f65b82010-05-19 22:10:20 +0200877 * Note: Original code is ata_bmdma_irq_clear().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900878 */
879
Tejun Heo9363c382008-04-07 22:47:16 +0900880static void scc_irq_clear (struct ata_port *ap)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900881{
882 void __iomem *mmio = ap->ioaddr.bmdma_addr;
883
884 if (!mmio)
885 return;
886
887 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
888}
889
890/**
891 * scc_port_start - Set port up for dma.
892 * @ap: Port to initialize
893 *
Tejun Heoc7087652010-05-10 21:41:34 +0200894 * Allocate space for PRD table using ata_bmdma_port_start().
Akira Iguchia619f981b2007-01-26 16:28:18 +0900895 * Set PRD table address for PTERADD. (PRD Transfer End Read)
896 */
897
898static int scc_port_start (struct ata_port *ap)
899{
900 void __iomem *mmio = ap->ioaddr.bmdma_addr;
901 int rc;
902
Tejun Heoc7087652010-05-10 21:41:34 +0200903 rc = ata_bmdma_port_start(ap);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900904 if (rc)
905 return rc;
906
Tejun Heof60d7012010-05-10 21:41:41 +0200907 out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900908 return 0;
909}
910
911/**
912 * scc_port_stop - Undo scc_port_start()
913 * @ap: Port to shut down
914 *
915 * Reset PTERADD.
916 */
917
918static void scc_port_stop (struct ata_port *ap)
919{
920 void __iomem *mmio = ap->ioaddr.bmdma_addr;
921
922 out_be32(mmio + SCC_DMA_PTERADD, 0);
923}
924
925static struct scsi_host_template scc_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900926 ATA_BMDMA_SHT(DRV_NAME),
Akira Iguchia619f981b2007-01-26 16:28:18 +0900927};
928
Tejun Heoc1796d92008-03-27 19:44:24 +0900929static struct ata_port_operations scc_pata_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900930 .inherits = &ata_bmdma_port_ops,
931
Akira Iguchia619f981b2007-01-26 16:28:18 +0900932 .set_piomode = scc_set_piomode,
933 .set_dmamode = scc_set_dmamode,
Akira Iguchidcd03442007-07-17 12:10:17 +0900934 .mode_filter = scc_mode_filter,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900935
Tejun Heo5682ed32008-04-07 22:47:16 +0900936 .sff_tf_load = scc_tf_load,
937 .sff_tf_read = scc_tf_read,
938 .sff_exec_command = scc_exec_command,
939 .sff_check_status = scc_check_status,
940 .sff_check_altstatus = scc_check_altstatus,
941 .sff_dev_select = scc_dev_select,
Sergei Shtylyov41dec292010-05-07 22:47:50 +0400942 .sff_set_devctl = scc_set_devctl,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900943
944 .bmdma_setup = scc_bmdma_setup,
945 .bmdma_start = scc_bmdma_start,
946 .bmdma_stop = scc_bmdma_stop,
947 .bmdma_status = scc_bmdma_status,
Tejun Heo5682ed32008-04-07 22:47:16 +0900948 .sff_data_xfer = scc_data_xfer,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900949
Tejun Heoa1efdab2008-03-25 12:22:50 +0900950 .prereset = scc_pata_prereset,
Tejun Heo9363c382008-04-07 22:47:16 +0900951 .softreset = scc_softreset,
952 .postreset = scc_postreset,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900953
Tejun Heo5682ed32008-04-07 22:47:16 +0900954 .sff_irq_clear = scc_irq_clear,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900955
956 .port_start = scc_port_start,
957 .port_stop = scc_port_stop,
958};
959
960static struct ata_port_info scc_port_info[] = {
961 {
Akira Iguchia619f981b2007-01-26 16:28:18 +0900962 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100963 .pio_mask = ATA_PIO4,
964 /* No MWDMA */
Akira Iguchia619f981b2007-01-26 16:28:18 +0900965 .udma_mask = ATA_UDMA6,
966 .port_ops = &scc_pata_ops,
967 },
968};
969
970/**
971 * scc_reset_controller - initialize SCC PATA controller.
972 */
973
Tejun Heo5d728822007-04-17 23:44:08 +0900974static int scc_reset_controller(struct ata_host *host)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900975{
Tejun Heo5d728822007-04-17 23:44:08 +0900976 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
977 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
Akira Iguchia619f981b2007-01-26 16:28:18 +0900978 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
979 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
980 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
981 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
982 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
983 u32 reg = 0;
984
985 out_be32(cckctrl_port, reg);
986 reg |= CCKCTRL_ATACLKOEN;
987 out_be32(cckctrl_port, reg);
988 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
989 out_be32(cckctrl_port, reg);
990 reg |= CCKCTRL_CRST;
991 out_be32(cckctrl_port, reg);
992
993 for (;;) {
994 reg = in_be32(cckctrl_port);
995 if (reg & CCKCTRL_CRST)
996 break;
997 udelay(5000);
998 }
999
1000 reg |= CCKCTRL_ATARESET;
1001 out_be32(cckctrl_port, reg);
1002 out_be32(ecmode_port, ECMODE_VALUE);
1003 out_be32(mode_port, MODE_JCUSFEN);
1004 out_be32(intmask_port, INTMASK_MSK);
1005
1006 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1007 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1008 return -EIO;
1009 }
1010
1011 return 0;
1012}
1013
1014/**
1015 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1016 * @ioaddr: IO address structure to be initialized
1017 * @base: base address of BMID region
1018 */
1019
1020static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1021{
1022 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1023 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1024 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1025 ioaddr->bmdma_addr = base;
1026 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1027 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1028 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1029 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1030 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1031 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1032 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1033 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1034 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1035 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1036}
1037
Tejun Heo5d728822007-04-17 23:44:08 +09001038static int scc_host_init(struct ata_host *host)
Akira Iguchia619f981b2007-01-26 16:28:18 +09001039{
Tejun Heo5d728822007-04-17 23:44:08 +09001040 struct pci_dev *pdev = to_pci_dev(host->dev);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001041 int rc;
1042
Tejun Heo5d728822007-04-17 23:44:08 +09001043 rc = scc_reset_controller(host);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001044 if (rc)
1045 return rc;
1046
Akira Iguchia619f981b2007-01-26 16:28:18 +09001047 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1048 if (rc)
1049 return rc;
1050 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1051 if (rc)
1052 return rc;
1053
Tejun Heo5d728822007-04-17 23:44:08 +09001054 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001055
1056 pci_set_master(pdev);
1057
1058 return 0;
1059}
1060
1061/**
1062 * scc_init_one - Register SCC PATA device with kernel services
1063 * @pdev: PCI device to register
1064 * @ent: Entry in scc_pci_tbl matching with @pdev
1065 *
1066 * LOCKING:
1067 * Inherited from PCI layer (may sleep).
1068 *
1069 * RETURNS:
1070 * Zero on success, or -ERRNO value.
1071 */
1072
1073static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1074{
1075 static int printed_version;
1076 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +09001077 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
Alexey Dobriyan0397bad2007-05-03 23:44:59 +04001078 struct ata_host *host;
Akira Iguchia619f981b2007-01-26 16:28:18 +09001079 int rc;
1080
1081 if (!printed_version++)
1082 dev_printk(KERN_DEBUG, &pdev->dev,
1083 "version " DRV_VERSION "\n");
1084
Alexey Dobriyan0397bad2007-05-03 23:44:59 +04001085 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
Tejun Heo5d728822007-04-17 23:44:08 +09001086 if (!host)
1087 return -ENOMEM;
1088
Akira Iguchia619f981b2007-01-26 16:28:18 +09001089 rc = pcim_enable_device(pdev);
1090 if (rc)
1091 return rc;
1092
1093 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1094 if (rc == -EBUSY)
1095 pcim_pin_device(pdev);
1096 if (rc)
1097 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +09001098 host->iomap = pcim_iomap_table(pdev);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001099
Tejun Heocbcdd872007-08-18 13:14:55 +09001100 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1101 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1102
Tejun Heo5d728822007-04-17 23:44:08 +09001103 rc = scc_host_init(host);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001104 if (rc)
1105 return rc;
1106
Tejun Heoc3b28892010-05-19 22:10:21 +02001107 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
Tejun Heo9363c382008-04-07 22:47:16 +09001108 IRQF_SHARED, &scc_sht);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001109}
1110
1111static struct pci_driver scc_pci_driver = {
1112 .name = DRV_NAME,
1113 .id_table = scc_pci_tbl,
1114 .probe = scc_init_one,
1115 .remove = ata_pci_remove_one,
1116#ifdef CONFIG_PM
1117 .suspend = ata_pci_device_suspend,
1118 .resume = ata_pci_device_resume,
1119#endif
1120};
1121
1122static int __init scc_init (void)
1123{
1124 int rc;
1125
1126 DPRINTK("pci_register_driver\n");
1127 rc = pci_register_driver(&scc_pci_driver);
1128 if (rc)
1129 return rc;
1130
1131 DPRINTK("done\n");
1132 return 0;
1133}
1134
1135static void __exit scc_exit (void)
1136{
1137 pci_unregister_driver(&scc_pci_driver);
1138}
1139
1140module_init(scc_init);
1141module_exit(scc_exit);
1142
1143MODULE_AUTHOR("Toshiba corp");
1144MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1145MODULE_LICENSE("GPL");
1146MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1147MODULE_VERSION(DRV_VERSION);