Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator |
| 3 | * |
| 4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
| 5 | * Rabeeh Khoury <rabeeh@solid-run.com> |
| 6 | * |
| 7 | * References: |
| 8 | * [1] "Si5351A/B/C Data Sheet" |
| 9 | * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf |
| 10 | * [2] "Manually Generating an Si5351 Register Map" |
| 11 | * http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify it |
| 14 | * under the terms of the GNU General Public License as published by the |
| 15 | * Free Software Foundation; either version 2 of the License, or (at your |
| 16 | * option) any later version. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/clkdev.h> |
| 22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/err.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/rational.h> |
| 27 | #include <linux/i2c.h> |
| 28 | #include <linux/of_platform.h> |
| 29 | #include <linux/platform_data/si5351.h> |
| 30 | #include <linux/regmap.h> |
| 31 | #include <linux/slab.h> |
| 32 | #include <linux/string.h> |
| 33 | #include <asm/div64.h> |
| 34 | |
| 35 | #include "clk-si5351.h" |
| 36 | |
| 37 | struct si5351_driver_data; |
| 38 | |
| 39 | struct si5351_parameters { |
| 40 | unsigned long p1; |
| 41 | unsigned long p2; |
| 42 | unsigned long p3; |
| 43 | int valid; |
| 44 | }; |
| 45 | |
| 46 | struct si5351_hw_data { |
| 47 | struct clk_hw hw; |
| 48 | struct si5351_driver_data *drvdata; |
| 49 | struct si5351_parameters params; |
| 50 | unsigned char num; |
| 51 | }; |
| 52 | |
| 53 | struct si5351_driver_data { |
| 54 | enum si5351_variant variant; |
| 55 | struct i2c_client *client; |
| 56 | struct regmap *regmap; |
| 57 | struct clk_onecell_data onecell; |
| 58 | |
| 59 | struct clk *pxtal; |
| 60 | const char *pxtal_name; |
| 61 | struct clk_hw xtal; |
| 62 | struct clk *pclkin; |
| 63 | const char *pclkin_name; |
| 64 | struct clk_hw clkin; |
| 65 | |
| 66 | struct si5351_hw_data pll[2]; |
| 67 | struct si5351_hw_data *msynth; |
| 68 | struct si5351_hw_data *clkout; |
| 69 | }; |
| 70 | |
| 71 | static const char const *si5351_input_names[] = { |
| 72 | "xtal", "clkin" |
| 73 | }; |
| 74 | static const char const *si5351_pll_names[] = { |
| 75 | "plla", "pllb", "vxco" |
| 76 | }; |
| 77 | static const char const *si5351_msynth_names[] = { |
| 78 | "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7" |
| 79 | }; |
| 80 | static const char const *si5351_clkout_names[] = { |
| 81 | "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7" |
| 82 | }; |
| 83 | |
| 84 | /* |
| 85 | * Si5351 i2c regmap |
| 86 | */ |
| 87 | static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg) |
| 88 | { |
| 89 | u32 val; |
| 90 | int ret; |
| 91 | |
| 92 | ret = regmap_read(drvdata->regmap, reg, &val); |
| 93 | if (ret) { |
| 94 | dev_err(&drvdata->client->dev, |
| 95 | "unable to read from reg%02x\n", reg); |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | return (u8)val; |
| 100 | } |
| 101 | |
| 102 | static inline int si5351_bulk_read(struct si5351_driver_data *drvdata, |
| 103 | u8 reg, u8 count, u8 *buf) |
| 104 | { |
| 105 | return regmap_bulk_read(drvdata->regmap, reg, buf, count); |
| 106 | } |
| 107 | |
| 108 | static inline int si5351_reg_write(struct si5351_driver_data *drvdata, |
| 109 | u8 reg, u8 val) |
| 110 | { |
| 111 | return regmap_write(drvdata->regmap, reg, val); |
| 112 | } |
| 113 | |
| 114 | static inline int si5351_bulk_write(struct si5351_driver_data *drvdata, |
| 115 | u8 reg, u8 count, const u8 *buf) |
| 116 | { |
| 117 | return regmap_raw_write(drvdata->regmap, reg, buf, count); |
| 118 | } |
| 119 | |
| 120 | static inline int si5351_set_bits(struct si5351_driver_data *drvdata, |
| 121 | u8 reg, u8 mask, u8 val) |
| 122 | { |
| 123 | return regmap_update_bits(drvdata->regmap, reg, mask, val); |
| 124 | } |
| 125 | |
| 126 | static inline u8 si5351_msynth_params_address(int num) |
| 127 | { |
| 128 | if (num > 5) |
| 129 | return SI5351_CLK6_PARAMETERS + (num - 6); |
| 130 | return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num); |
| 131 | } |
| 132 | |
| 133 | static void si5351_read_parameters(struct si5351_driver_data *drvdata, |
| 134 | u8 reg, struct si5351_parameters *params) |
| 135 | { |
| 136 | u8 buf[SI5351_PARAMETERS_LENGTH]; |
| 137 | |
| 138 | switch (reg) { |
| 139 | case SI5351_CLK6_PARAMETERS: |
| 140 | case SI5351_CLK7_PARAMETERS: |
| 141 | buf[0] = si5351_reg_read(drvdata, reg); |
| 142 | params->p1 = buf[0]; |
| 143 | params->p2 = 0; |
| 144 | params->p3 = 1; |
| 145 | break; |
| 146 | default: |
| 147 | si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); |
| 148 | params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; |
| 149 | params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7]; |
| 150 | params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1]; |
| 151 | } |
| 152 | params->valid = 1; |
| 153 | } |
| 154 | |
| 155 | static void si5351_write_parameters(struct si5351_driver_data *drvdata, |
| 156 | u8 reg, struct si5351_parameters *params) |
| 157 | { |
| 158 | u8 buf[SI5351_PARAMETERS_LENGTH]; |
| 159 | |
| 160 | switch (reg) { |
| 161 | case SI5351_CLK6_PARAMETERS: |
| 162 | case SI5351_CLK7_PARAMETERS: |
| 163 | buf[0] = params->p1 & 0xff; |
| 164 | si5351_reg_write(drvdata, reg, buf[0]); |
| 165 | break; |
| 166 | default: |
| 167 | buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff; |
| 168 | buf[1] = params->p3 & 0xff; |
| 169 | /* save rdiv and divby4 */ |
| 170 | buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03; |
| 171 | buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; |
| 172 | buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; |
| 173 | buf[4] = params->p1 & 0xff; |
| 174 | buf[5] = ((params->p3 & 0xf0000) >> 12) | |
| 175 | ((params->p2 & 0xf0000) >> 16); |
| 176 | buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff; |
| 177 | buf[7] = params->p2 & 0xff; |
| 178 | si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg) |
| 183 | { |
| 184 | switch (reg) { |
| 185 | case SI5351_DEVICE_STATUS: |
| 186 | case SI5351_INTERRUPT_STATUS: |
| 187 | case SI5351_PLL_RESET: |
| 188 | return true; |
| 189 | } |
| 190 | return false; |
| 191 | } |
| 192 | |
| 193 | static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg) |
| 194 | { |
| 195 | /* reserved registers */ |
| 196 | if (reg >= 4 && reg <= 8) |
| 197 | return false; |
| 198 | if (reg >= 10 && reg <= 14) |
| 199 | return false; |
| 200 | if (reg >= 173 && reg <= 176) |
| 201 | return false; |
| 202 | if (reg >= 178 && reg <= 182) |
| 203 | return false; |
| 204 | /* read-only */ |
| 205 | if (reg == SI5351_DEVICE_STATUS) |
| 206 | return false; |
| 207 | return true; |
| 208 | } |
| 209 | |
| 210 | static struct regmap_config si5351_regmap_config = { |
| 211 | .reg_bits = 8, |
| 212 | .val_bits = 8, |
| 213 | .cache_type = REGCACHE_RBTREE, |
| 214 | .max_register = 187, |
| 215 | .writeable_reg = si5351_regmap_is_writeable, |
| 216 | .volatile_reg = si5351_regmap_is_volatile, |
| 217 | }; |
| 218 | |
| 219 | /* |
| 220 | * Si5351 xtal clock input |
| 221 | */ |
| 222 | static int si5351_xtal_prepare(struct clk_hw *hw) |
| 223 | { |
| 224 | struct si5351_driver_data *drvdata = |
| 225 | container_of(hw, struct si5351_driver_data, xtal); |
| 226 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, |
| 227 | SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE); |
| 228 | return 0; |
| 229 | } |
| 230 | |
| 231 | static void si5351_xtal_unprepare(struct clk_hw *hw) |
| 232 | { |
| 233 | struct si5351_driver_data *drvdata = |
| 234 | container_of(hw, struct si5351_driver_data, xtal); |
| 235 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, |
| 236 | SI5351_XTAL_ENABLE, 0); |
| 237 | } |
| 238 | |
| 239 | static const struct clk_ops si5351_xtal_ops = { |
| 240 | .prepare = si5351_xtal_prepare, |
| 241 | .unprepare = si5351_xtal_unprepare, |
| 242 | }; |
| 243 | |
| 244 | /* |
| 245 | * Si5351 clkin clock input (Si5351C only) |
| 246 | */ |
| 247 | static int si5351_clkin_prepare(struct clk_hw *hw) |
| 248 | { |
| 249 | struct si5351_driver_data *drvdata = |
| 250 | container_of(hw, struct si5351_driver_data, clkin); |
| 251 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, |
| 252 | SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE); |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | static void si5351_clkin_unprepare(struct clk_hw *hw) |
| 257 | { |
| 258 | struct si5351_driver_data *drvdata = |
| 259 | container_of(hw, struct si5351_driver_data, clkin); |
| 260 | si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, |
| 261 | SI5351_CLKIN_ENABLE, 0); |
| 262 | } |
| 263 | |
| 264 | /* |
| 265 | * CMOS clock source constraints: |
| 266 | * The input frequency range of the PLL is 10Mhz to 40MHz. |
| 267 | * If CLKIN is >40MHz, the input divider must be used. |
| 268 | */ |
| 269 | static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw, |
| 270 | unsigned long parent_rate) |
| 271 | { |
| 272 | struct si5351_driver_data *drvdata = |
| 273 | container_of(hw, struct si5351_driver_data, clkin); |
| 274 | unsigned long rate; |
| 275 | unsigned char idiv; |
| 276 | |
| 277 | rate = parent_rate; |
| 278 | if (parent_rate > 160000000) { |
| 279 | idiv = SI5351_CLKIN_DIV_8; |
| 280 | rate /= 8; |
| 281 | } else if (parent_rate > 80000000) { |
| 282 | idiv = SI5351_CLKIN_DIV_4; |
| 283 | rate /= 4; |
| 284 | } else if (parent_rate > 40000000) { |
| 285 | idiv = SI5351_CLKIN_DIV_2; |
| 286 | rate /= 2; |
| 287 | } else { |
| 288 | idiv = SI5351_CLKIN_DIV_1; |
| 289 | } |
| 290 | |
| 291 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, |
| 292 | SI5351_CLKIN_DIV_MASK, idiv); |
| 293 | |
| 294 | dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n", |
| 295 | __func__, (1 << (idiv >> 6)), rate); |
| 296 | |
| 297 | return rate; |
| 298 | } |
| 299 | |
| 300 | static const struct clk_ops si5351_clkin_ops = { |
| 301 | .prepare = si5351_clkin_prepare, |
| 302 | .unprepare = si5351_clkin_unprepare, |
| 303 | .recalc_rate = si5351_clkin_recalc_rate, |
| 304 | }; |
| 305 | |
| 306 | /* |
| 307 | * Si5351 vxco clock input (Si5351B only) |
| 308 | */ |
| 309 | |
| 310 | static int si5351_vxco_prepare(struct clk_hw *hw) |
| 311 | { |
| 312 | struct si5351_hw_data *hwdata = |
| 313 | container_of(hw, struct si5351_hw_data, hw); |
| 314 | |
| 315 | dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n"); |
| 316 | |
| 317 | return 0; |
| 318 | } |
| 319 | |
| 320 | static void si5351_vxco_unprepare(struct clk_hw *hw) |
| 321 | { |
| 322 | } |
| 323 | |
| 324 | static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw, |
| 325 | unsigned long parent_rate) |
| 326 | { |
| 327 | return 0; |
| 328 | } |
| 329 | |
| 330 | static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate, |
| 331 | unsigned long parent) |
| 332 | { |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | static const struct clk_ops si5351_vxco_ops = { |
| 337 | .prepare = si5351_vxco_prepare, |
| 338 | .unprepare = si5351_vxco_unprepare, |
| 339 | .recalc_rate = si5351_vxco_recalc_rate, |
| 340 | .set_rate = si5351_vxco_set_rate, |
| 341 | }; |
| 342 | |
| 343 | /* |
| 344 | * Si5351 pll a/b |
| 345 | * |
| 346 | * Feedback Multisynth Divider Equations [2] |
| 347 | * |
| 348 | * fVCO = fIN * (a + b/c) |
| 349 | * |
| 350 | * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and |
| 351 | * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV |
| 352 | * |
| 353 | * Feedback Multisynth Register Equations |
| 354 | * |
| 355 | * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 |
| 356 | * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c |
| 357 | * (3) MSNx_P3[19:0] = c |
| 358 | * |
| 359 | * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c |
| 360 | * |
| 361 | * Using (4) on (1) yields: |
| 362 | * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512 |
| 363 | * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c |
| 364 | * |
| 365 | * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128 |
| 366 | * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3) |
| 367 | * |
| 368 | */ |
| 369 | static int _si5351_pll_reparent(struct si5351_driver_data *drvdata, |
| 370 | int num, enum si5351_pll_src parent) |
| 371 | { |
| 372 | u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; |
| 373 | |
| 374 | if (parent == SI5351_PLL_SRC_DEFAULT) |
| 375 | return 0; |
| 376 | |
| 377 | if (num > 2) |
| 378 | return -EINVAL; |
| 379 | |
| 380 | if (drvdata->variant != SI5351_VARIANT_C && |
| 381 | parent != SI5351_PLL_SRC_XTAL) |
| 382 | return -EINVAL; |
| 383 | |
| 384 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask, |
| 385 | (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask); |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static unsigned char si5351_pll_get_parent(struct clk_hw *hw) |
| 390 | { |
| 391 | struct si5351_hw_data *hwdata = |
| 392 | container_of(hw, struct si5351_hw_data, hw); |
| 393 | u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; |
| 394 | u8 val; |
| 395 | |
| 396 | val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); |
| 397 | |
| 398 | return (val & mask) ? 1 : 0; |
| 399 | } |
| 400 | |
| 401 | static int si5351_pll_set_parent(struct clk_hw *hw, u8 index) |
| 402 | { |
| 403 | struct si5351_hw_data *hwdata = |
| 404 | container_of(hw, struct si5351_hw_data, hw); |
| 405 | |
| 406 | if (hwdata->drvdata->variant != SI5351_VARIANT_C && |
| 407 | index > 0) |
| 408 | return -EPERM; |
| 409 | |
| 410 | if (index > 1) |
| 411 | return -EINVAL; |
| 412 | |
| 413 | return _si5351_pll_reparent(hwdata->drvdata, hwdata->num, |
| 414 | (index == 0) ? SI5351_PLL_SRC_XTAL : |
| 415 | SI5351_PLL_SRC_CLKIN); |
| 416 | } |
| 417 | |
| 418 | static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw, |
| 419 | unsigned long parent_rate) |
| 420 | { |
| 421 | struct si5351_hw_data *hwdata = |
| 422 | container_of(hw, struct si5351_hw_data, hw); |
| 423 | u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : |
| 424 | SI5351_PLLB_PARAMETERS; |
| 425 | unsigned long long rate; |
| 426 | |
| 427 | if (!hwdata->params.valid) |
| 428 | si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); |
| 429 | |
| 430 | if (hwdata->params.p3 == 0) |
| 431 | return parent_rate; |
| 432 | |
| 433 | /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */ |
| 434 | rate = hwdata->params.p1 * hwdata->params.p3; |
| 435 | rate += 512 * hwdata->params.p3; |
| 436 | rate += hwdata->params.p2; |
| 437 | rate *= parent_rate; |
| 438 | do_div(rate, 128 * hwdata->params.p3); |
| 439 | |
| 440 | dev_dbg(&hwdata->drvdata->client->dev, |
| 441 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", |
| 442 | __func__, __clk_get_name(hwdata->hw.clk), |
| 443 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
| 444 | parent_rate, (unsigned long)rate); |
| 445 | |
| 446 | return (unsigned long)rate; |
| 447 | } |
| 448 | |
| 449 | static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
| 450 | unsigned long *parent_rate) |
| 451 | { |
| 452 | struct si5351_hw_data *hwdata = |
| 453 | container_of(hw, struct si5351_hw_data, hw); |
| 454 | unsigned long rfrac, denom, a, b, c; |
| 455 | unsigned long long lltmp; |
| 456 | |
| 457 | if (rate < SI5351_PLL_VCO_MIN) |
| 458 | rate = SI5351_PLL_VCO_MIN; |
| 459 | if (rate > SI5351_PLL_VCO_MAX) |
| 460 | rate = SI5351_PLL_VCO_MAX; |
| 461 | |
| 462 | /* determine integer part of feedback equation */ |
| 463 | a = rate / *parent_rate; |
| 464 | |
| 465 | if (a < SI5351_PLL_A_MIN) |
| 466 | rate = *parent_rate * SI5351_PLL_A_MIN; |
| 467 | if (a > SI5351_PLL_A_MAX) |
| 468 | rate = *parent_rate * SI5351_PLL_A_MAX; |
| 469 | |
| 470 | /* find best approximation for b/c = fVCO mod fIN */ |
| 471 | denom = 1000 * 1000; |
| 472 | lltmp = rate % (*parent_rate); |
| 473 | lltmp *= denom; |
| 474 | do_div(lltmp, *parent_rate); |
| 475 | rfrac = (unsigned long)lltmp; |
| 476 | |
| 477 | b = 0; |
| 478 | c = 1; |
| 479 | if (rfrac) |
| 480 | rational_best_approximation(rfrac, denom, |
| 481 | SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c); |
| 482 | |
| 483 | /* calculate parameters */ |
| 484 | hwdata->params.p3 = c; |
| 485 | hwdata->params.p2 = (128 * b) % c; |
| 486 | hwdata->params.p1 = 128 * a; |
| 487 | hwdata->params.p1 += (128 * b / c); |
| 488 | hwdata->params.p1 -= 512; |
| 489 | |
| 490 | /* recalculate rate by fIN * (a + b/c) */ |
| 491 | lltmp = *parent_rate; |
| 492 | lltmp *= b; |
| 493 | do_div(lltmp, c); |
| 494 | |
| 495 | rate = (unsigned long)lltmp; |
| 496 | rate += *parent_rate * a; |
| 497 | |
| 498 | dev_dbg(&hwdata->drvdata->client->dev, |
| 499 | "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", |
| 500 | __func__, __clk_get_name(hwdata->hw.clk), a, b, c, |
| 501 | *parent_rate, rate); |
| 502 | |
| 503 | return rate; |
| 504 | } |
| 505 | |
| 506 | static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
| 507 | unsigned long parent_rate) |
| 508 | { |
| 509 | struct si5351_hw_data *hwdata = |
| 510 | container_of(hw, struct si5351_hw_data, hw); |
| 511 | u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : |
| 512 | SI5351_PLLB_PARAMETERS; |
| 513 | |
| 514 | /* write multisynth parameters */ |
| 515 | si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); |
| 516 | |
| 517 | /* plla/pllb ctrl is in clk6/clk7 ctrl registers */ |
| 518 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num, |
| 519 | SI5351_CLK_INTEGER_MODE, |
| 520 | (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); |
| 521 | |
| 522 | dev_dbg(&hwdata->drvdata->client->dev, |
| 523 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", |
| 524 | __func__, __clk_get_name(hwdata->hw.clk), |
| 525 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
| 526 | parent_rate, rate); |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | static const struct clk_ops si5351_pll_ops = { |
| 532 | .set_parent = si5351_pll_set_parent, |
| 533 | .get_parent = si5351_pll_get_parent, |
| 534 | .recalc_rate = si5351_pll_recalc_rate, |
| 535 | .round_rate = si5351_pll_round_rate, |
| 536 | .set_rate = si5351_pll_set_rate, |
| 537 | }; |
| 538 | |
| 539 | /* |
| 540 | * Si5351 multisync divider |
| 541 | * |
| 542 | * for fOUT <= 150 MHz: |
| 543 | * |
| 544 | * fOUT = (fIN * (a + b/c)) / CLKOUTDIV |
| 545 | * |
| 546 | * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and |
| 547 | * fIN = fVCO0, fVCO1 |
| 548 | * |
| 549 | * Output Clock Multisynth Register Equations |
| 550 | * |
| 551 | * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 |
| 552 | * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c |
| 553 | * MSx_P3[19:0] = c |
| 554 | * |
| 555 | * MS[6,7] are integer (P1) divide only, P2 = 0, P3 = 0 |
| 556 | * |
| 557 | * for 150MHz < fOUT <= 160MHz: |
| 558 | * |
| 559 | * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b |
| 560 | */ |
| 561 | static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata, |
| 562 | int num, enum si5351_multisynth_src parent) |
| 563 | { |
| 564 | if (parent == SI5351_MULTISYNTH_SRC_DEFAULT) |
| 565 | return 0; |
| 566 | |
| 567 | if (num > 8) |
| 568 | return -EINVAL; |
| 569 | |
| 570 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT, |
| 571 | (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 : |
| 572 | SI5351_CLK_PLL_SELECT); |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | static unsigned char si5351_msynth_get_parent(struct clk_hw *hw) |
| 577 | { |
| 578 | struct si5351_hw_data *hwdata = |
| 579 | container_of(hw, struct si5351_hw_data, hw); |
| 580 | u8 val; |
| 581 | |
| 582 | val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); |
| 583 | |
| 584 | return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0; |
| 585 | } |
| 586 | |
| 587 | static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index) |
| 588 | { |
| 589 | struct si5351_hw_data *hwdata = |
| 590 | container_of(hw, struct si5351_hw_data, hw); |
| 591 | |
| 592 | return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num, |
| 593 | (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 : |
| 594 | SI5351_MULTISYNTH_SRC_VCO1); |
| 595 | } |
| 596 | |
| 597 | static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw, |
| 598 | unsigned long parent_rate) |
| 599 | { |
| 600 | struct si5351_hw_data *hwdata = |
| 601 | container_of(hw, struct si5351_hw_data, hw); |
| 602 | u8 reg = si5351_msynth_params_address(hwdata->num); |
| 603 | unsigned long long rate; |
| 604 | unsigned long m; |
| 605 | |
| 606 | if (!hwdata->params.valid) |
| 607 | si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); |
| 608 | |
| 609 | if (hwdata->params.p3 == 0) |
| 610 | return parent_rate; |
| 611 | |
| 612 | /* |
| 613 | * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3) |
| 614 | * multisync6-7: fOUT = fIN / P1 |
| 615 | */ |
| 616 | rate = parent_rate; |
| 617 | if (hwdata->num > 5) { |
| 618 | m = hwdata->params.p1; |
| 619 | } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & |
| 620 | SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) { |
| 621 | m = 4; |
| 622 | } else { |
| 623 | rate *= 128 * hwdata->params.p3; |
| 624 | m = hwdata->params.p1 * hwdata->params.p3; |
| 625 | m += hwdata->params.p2; |
| 626 | m += 512 * hwdata->params.p3; |
| 627 | } |
| 628 | |
| 629 | if (m == 0) |
| 630 | return 0; |
| 631 | do_div(rate, m); |
| 632 | |
| 633 | dev_dbg(&hwdata->drvdata->client->dev, |
| 634 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", |
| 635 | __func__, __clk_get_name(hwdata->hw.clk), |
| 636 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
| 637 | m, parent_rate, (unsigned long)rate); |
| 638 | |
| 639 | return (unsigned long)rate; |
| 640 | } |
| 641 | |
| 642 | static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, |
| 643 | unsigned long *parent_rate) |
| 644 | { |
| 645 | struct si5351_hw_data *hwdata = |
| 646 | container_of(hw, struct si5351_hw_data, hw); |
| 647 | unsigned long long lltmp; |
| 648 | unsigned long a, b, c; |
| 649 | int divby4; |
| 650 | |
| 651 | /* multisync6-7 can only handle freqencies < 150MHz */ |
| 652 | if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ) |
| 653 | rate = SI5351_MULTISYNTH67_MAX_FREQ; |
| 654 | |
| 655 | /* multisync frequency is 1MHz .. 160MHz */ |
| 656 | if (rate > SI5351_MULTISYNTH_MAX_FREQ) |
| 657 | rate = SI5351_MULTISYNTH_MAX_FREQ; |
| 658 | if (rate < SI5351_MULTISYNTH_MIN_FREQ) |
| 659 | rate = SI5351_MULTISYNTH_MIN_FREQ; |
| 660 | |
| 661 | divby4 = 0; |
| 662 | if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) |
| 663 | divby4 = 1; |
| 664 | |
| 665 | /* multisync can set pll */ |
| 666 | if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { |
| 667 | /* |
| 668 | * find largest integer divider for max |
| 669 | * vco frequency and given target rate |
| 670 | */ |
| 671 | if (divby4 == 0) { |
| 672 | lltmp = SI5351_PLL_VCO_MAX; |
| 673 | do_div(lltmp, rate); |
| 674 | a = (unsigned long)lltmp; |
| 675 | } else |
| 676 | a = 4; |
| 677 | |
| 678 | b = 0; |
| 679 | c = 1; |
| 680 | |
| 681 | *parent_rate = a * rate; |
| 682 | } else { |
| 683 | unsigned long rfrac, denom; |
| 684 | |
| 685 | /* disable divby4 */ |
| 686 | if (divby4) { |
| 687 | rate = SI5351_MULTISYNTH_DIVBY4_FREQ; |
| 688 | divby4 = 0; |
| 689 | } |
| 690 | |
| 691 | /* determine integer part of divider equation */ |
| 692 | a = *parent_rate / rate; |
| 693 | if (a < SI5351_MULTISYNTH_A_MIN) |
| 694 | a = SI5351_MULTISYNTH_A_MIN; |
| 695 | if (hwdata->num >= 6 && a > SI5351_MULTISYNTH67_A_MAX) |
| 696 | a = SI5351_MULTISYNTH67_A_MAX; |
| 697 | else if (a > SI5351_MULTISYNTH_A_MAX) |
| 698 | a = SI5351_MULTISYNTH_A_MAX; |
| 699 | |
| 700 | /* find best approximation for b/c = fVCO mod fOUT */ |
| 701 | denom = 1000 * 1000; |
| 702 | lltmp = (*parent_rate) % rate; |
| 703 | lltmp *= denom; |
| 704 | do_div(lltmp, rate); |
| 705 | rfrac = (unsigned long)lltmp; |
| 706 | |
| 707 | b = 0; |
| 708 | c = 1; |
| 709 | if (rfrac) |
| 710 | rational_best_approximation(rfrac, denom, |
| 711 | SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX, |
| 712 | &b, &c); |
| 713 | } |
| 714 | |
| 715 | /* recalculate rate by fOUT = fIN / (a + b/c) */ |
| 716 | lltmp = *parent_rate; |
| 717 | lltmp *= c; |
| 718 | do_div(lltmp, a * c + b); |
| 719 | rate = (unsigned long)lltmp; |
| 720 | |
| 721 | /* calculate parameters */ |
| 722 | if (divby4) { |
| 723 | hwdata->params.p3 = 1; |
| 724 | hwdata->params.p2 = 0; |
| 725 | hwdata->params.p1 = 0; |
| 726 | } else { |
| 727 | hwdata->params.p3 = c; |
| 728 | hwdata->params.p2 = (128 * b) % c; |
| 729 | hwdata->params.p1 = 128 * a; |
| 730 | hwdata->params.p1 += (128 * b / c); |
| 731 | hwdata->params.p1 -= 512; |
| 732 | } |
| 733 | |
| 734 | dev_dbg(&hwdata->drvdata->client->dev, |
| 735 | "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", |
| 736 | __func__, __clk_get_name(hwdata->hw.clk), a, b, c, divby4, |
| 737 | *parent_rate, rate); |
| 738 | |
| 739 | return rate; |
| 740 | } |
| 741 | |
| 742 | static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate, |
| 743 | unsigned long parent_rate) |
| 744 | { |
| 745 | struct si5351_hw_data *hwdata = |
| 746 | container_of(hw, struct si5351_hw_data, hw); |
| 747 | u8 reg = si5351_msynth_params_address(hwdata->num); |
| 748 | int divby4 = 0; |
| 749 | |
| 750 | /* write multisynth parameters */ |
| 751 | si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); |
| 752 | |
| 753 | if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) |
| 754 | divby4 = 1; |
| 755 | |
| 756 | /* enable/disable integer mode and divby4 on multisynth0-5 */ |
| 757 | if (hwdata->num < 6) { |
| 758 | si5351_set_bits(hwdata->drvdata, reg + 2, |
| 759 | SI5351_OUTPUT_CLK_DIVBY4, |
| 760 | (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); |
| 761 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, |
| 762 | SI5351_CLK_INTEGER_MODE, |
| 763 | (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); |
| 764 | } |
| 765 | |
| 766 | dev_dbg(&hwdata->drvdata->client->dev, |
| 767 | "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", |
| 768 | __func__, __clk_get_name(hwdata->hw.clk), |
| 769 | hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, |
| 770 | divby4, parent_rate, rate); |
| 771 | |
| 772 | return 0; |
| 773 | } |
| 774 | |
| 775 | static const struct clk_ops si5351_msynth_ops = { |
| 776 | .set_parent = si5351_msynth_set_parent, |
| 777 | .get_parent = si5351_msynth_get_parent, |
| 778 | .recalc_rate = si5351_msynth_recalc_rate, |
| 779 | .round_rate = si5351_msynth_round_rate, |
| 780 | .set_rate = si5351_msynth_set_rate, |
| 781 | }; |
| 782 | |
| 783 | /* |
| 784 | * Si5351 clkout divider |
| 785 | */ |
| 786 | static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata, |
| 787 | int num, enum si5351_clkout_src parent) |
| 788 | { |
| 789 | u8 val; |
| 790 | |
| 791 | if (num > 8) |
| 792 | return -EINVAL; |
| 793 | |
| 794 | switch (parent) { |
| 795 | case SI5351_CLKOUT_SRC_MSYNTH_N: |
| 796 | val = SI5351_CLK_INPUT_MULTISYNTH_N; |
| 797 | break; |
| 798 | case SI5351_CLKOUT_SRC_MSYNTH_0_4: |
| 799 | /* clk0/clk4 can only connect to its own multisync */ |
| 800 | if (num == 0 || num == 4) |
| 801 | val = SI5351_CLK_INPUT_MULTISYNTH_N; |
| 802 | else |
| 803 | val = SI5351_CLK_INPUT_MULTISYNTH_0_4; |
| 804 | break; |
| 805 | case SI5351_CLKOUT_SRC_XTAL: |
| 806 | val = SI5351_CLK_INPUT_XTAL; |
| 807 | break; |
| 808 | case SI5351_CLKOUT_SRC_CLKIN: |
| 809 | if (drvdata->variant != SI5351_VARIANT_C) |
| 810 | return -EINVAL; |
| 811 | |
| 812 | val = SI5351_CLK_INPUT_CLKIN; |
| 813 | break; |
| 814 | default: |
| 815 | return 0; |
| 816 | } |
| 817 | |
| 818 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, |
| 819 | SI5351_CLK_INPUT_MASK, val); |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | static int _si5351_clkout_set_drive_strength( |
| 824 | struct si5351_driver_data *drvdata, int num, |
| 825 | enum si5351_drive_strength drive) |
| 826 | { |
| 827 | u8 mask; |
| 828 | |
| 829 | if (num > 8) |
| 830 | return -EINVAL; |
| 831 | |
| 832 | switch (drive) { |
| 833 | case SI5351_DRIVE_2MA: |
| 834 | mask = SI5351_CLK_DRIVE_STRENGTH_2MA; |
| 835 | break; |
| 836 | case SI5351_DRIVE_4MA: |
| 837 | mask = SI5351_CLK_DRIVE_STRENGTH_4MA; |
| 838 | break; |
| 839 | case SI5351_DRIVE_6MA: |
| 840 | mask = SI5351_CLK_DRIVE_STRENGTH_6MA; |
| 841 | break; |
| 842 | case SI5351_DRIVE_8MA: |
| 843 | mask = SI5351_CLK_DRIVE_STRENGTH_8MA; |
| 844 | break; |
| 845 | default: |
| 846 | return 0; |
| 847 | } |
| 848 | |
| 849 | si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, |
| 850 | SI5351_CLK_DRIVE_STRENGTH_MASK, mask); |
| 851 | return 0; |
| 852 | } |
| 853 | |
Sebastian Hesselbarth | 1a0483d | 2013-05-03 07:33:27 +0200 | [diff] [blame] | 854 | static int _si5351_clkout_set_disable_state( |
| 855 | struct si5351_driver_data *drvdata, int num, |
| 856 | enum si5351_disable_state state) |
| 857 | { |
| 858 | u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE : |
| 859 | SI5351_CLK7_4_DISABLE_STATE; |
| 860 | u8 shift = (num < 4) ? (2 * num) : (2 * (num-4)); |
| 861 | u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift; |
| 862 | u8 val; |
| 863 | |
| 864 | if (num > 8) |
| 865 | return -EINVAL; |
| 866 | |
| 867 | switch (state) { |
| 868 | case SI5351_DISABLE_LOW: |
| 869 | val = SI5351_CLK_DISABLE_STATE_LOW; |
| 870 | break; |
| 871 | case SI5351_DISABLE_HIGH: |
| 872 | val = SI5351_CLK_DISABLE_STATE_HIGH; |
| 873 | break; |
| 874 | case SI5351_DISABLE_FLOATING: |
| 875 | val = SI5351_CLK_DISABLE_STATE_FLOAT; |
| 876 | break; |
| 877 | case SI5351_DISABLE_NEVER: |
| 878 | val = SI5351_CLK_DISABLE_STATE_NEVER; |
| 879 | break; |
| 880 | default: |
| 881 | return 0; |
| 882 | } |
| 883 | |
| 884 | si5351_set_bits(drvdata, reg, mask, val << shift); |
| 885 | |
| 886 | return 0; |
| 887 | } |
| 888 | |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 889 | static int si5351_clkout_prepare(struct clk_hw *hw) |
| 890 | { |
| 891 | struct si5351_hw_data *hwdata = |
| 892 | container_of(hw, struct si5351_hw_data, hw); |
| 893 | |
| 894 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, |
| 895 | SI5351_CLK_POWERDOWN, 0); |
| 896 | si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, |
| 897 | (1 << hwdata->num), 0); |
| 898 | return 0; |
| 899 | } |
| 900 | |
| 901 | static void si5351_clkout_unprepare(struct clk_hw *hw) |
| 902 | { |
| 903 | struct si5351_hw_data *hwdata = |
| 904 | container_of(hw, struct si5351_hw_data, hw); |
| 905 | |
| 906 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, |
| 907 | SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN); |
| 908 | si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, |
| 909 | (1 << hwdata->num), (1 << hwdata->num)); |
| 910 | } |
| 911 | |
| 912 | static u8 si5351_clkout_get_parent(struct clk_hw *hw) |
| 913 | { |
| 914 | struct si5351_hw_data *hwdata = |
| 915 | container_of(hw, struct si5351_hw_data, hw); |
| 916 | int index = 0; |
| 917 | unsigned char val; |
| 918 | |
| 919 | val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); |
| 920 | switch (val & SI5351_CLK_INPUT_MASK) { |
| 921 | case SI5351_CLK_INPUT_MULTISYNTH_N: |
| 922 | index = 0; |
| 923 | break; |
| 924 | case SI5351_CLK_INPUT_MULTISYNTH_0_4: |
| 925 | index = 1; |
| 926 | break; |
| 927 | case SI5351_CLK_INPUT_XTAL: |
| 928 | index = 2; |
| 929 | break; |
| 930 | case SI5351_CLK_INPUT_CLKIN: |
| 931 | index = 3; |
| 932 | break; |
| 933 | } |
| 934 | |
| 935 | return index; |
| 936 | } |
| 937 | |
| 938 | static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index) |
| 939 | { |
| 940 | struct si5351_hw_data *hwdata = |
| 941 | container_of(hw, struct si5351_hw_data, hw); |
| 942 | enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT; |
| 943 | |
| 944 | switch (index) { |
| 945 | case 0: |
| 946 | parent = SI5351_CLKOUT_SRC_MSYNTH_N; |
| 947 | break; |
| 948 | case 1: |
| 949 | parent = SI5351_CLKOUT_SRC_MSYNTH_0_4; |
| 950 | break; |
| 951 | case 2: |
| 952 | parent = SI5351_CLKOUT_SRC_XTAL; |
| 953 | break; |
| 954 | case 3: |
| 955 | parent = SI5351_CLKOUT_SRC_CLKIN; |
| 956 | break; |
| 957 | } |
| 958 | |
| 959 | return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent); |
| 960 | } |
| 961 | |
| 962 | static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, |
| 963 | unsigned long parent_rate) |
| 964 | { |
| 965 | struct si5351_hw_data *hwdata = |
| 966 | container_of(hw, struct si5351_hw_data, hw); |
| 967 | unsigned char reg; |
| 968 | unsigned char rdiv; |
| 969 | |
| 970 | if (hwdata->num > 5) |
| 971 | reg = si5351_msynth_params_address(hwdata->num) + 2; |
| 972 | else |
| 973 | reg = SI5351_CLK6_7_OUTPUT_DIVIDER; |
| 974 | |
| 975 | rdiv = si5351_reg_read(hwdata->drvdata, reg); |
| 976 | if (hwdata->num == 6) { |
| 977 | rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; |
| 978 | } else { |
| 979 | rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; |
| 980 | rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; |
| 981 | } |
| 982 | |
| 983 | return parent_rate >> rdiv; |
| 984 | } |
| 985 | |
| 986 | static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, |
| 987 | unsigned long *parent_rate) |
| 988 | { |
| 989 | struct si5351_hw_data *hwdata = |
| 990 | container_of(hw, struct si5351_hw_data, hw); |
| 991 | unsigned char rdiv; |
| 992 | |
| 993 | /* clkout6/7 can only handle output freqencies < 150MHz */ |
| 994 | if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ) |
| 995 | rate = SI5351_CLKOUT67_MAX_FREQ; |
| 996 | |
| 997 | /* clkout freqency is 8kHz - 160MHz */ |
| 998 | if (rate > SI5351_CLKOUT_MAX_FREQ) |
| 999 | rate = SI5351_CLKOUT_MAX_FREQ; |
| 1000 | if (rate < SI5351_CLKOUT_MIN_FREQ) |
| 1001 | rate = SI5351_CLKOUT_MIN_FREQ; |
| 1002 | |
| 1003 | /* request frequency if multisync master */ |
| 1004 | if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { |
| 1005 | /* use r divider for frequencies below 1MHz */ |
| 1006 | rdiv = SI5351_OUTPUT_CLK_DIV_1; |
| 1007 | while (rate < SI5351_MULTISYNTH_MIN_FREQ && |
| 1008 | rdiv < SI5351_OUTPUT_CLK_DIV_128) { |
| 1009 | rdiv += 1; |
| 1010 | rate *= 2; |
| 1011 | } |
| 1012 | *parent_rate = rate; |
| 1013 | } else { |
| 1014 | unsigned long new_rate, new_err, err; |
| 1015 | |
| 1016 | /* round to closed rdiv */ |
| 1017 | rdiv = SI5351_OUTPUT_CLK_DIV_1; |
| 1018 | new_rate = *parent_rate; |
| 1019 | err = abs(new_rate - rate); |
| 1020 | do { |
| 1021 | new_rate >>= 1; |
| 1022 | new_err = abs(new_rate - rate); |
| 1023 | if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) |
| 1024 | break; |
| 1025 | rdiv++; |
| 1026 | err = new_err; |
| 1027 | } while (1); |
| 1028 | } |
| 1029 | rate = *parent_rate >> rdiv; |
| 1030 | |
| 1031 | dev_dbg(&hwdata->drvdata->client->dev, |
| 1032 | "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", |
| 1033 | __func__, __clk_get_name(hwdata->hw.clk), (1 << rdiv), |
| 1034 | *parent_rate, rate); |
| 1035 | |
| 1036 | return rate; |
| 1037 | } |
| 1038 | |
| 1039 | static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, |
| 1040 | unsigned long parent_rate) |
| 1041 | { |
| 1042 | struct si5351_hw_data *hwdata = |
| 1043 | container_of(hw, struct si5351_hw_data, hw); |
| 1044 | unsigned long new_rate, new_err, err; |
| 1045 | unsigned char rdiv; |
| 1046 | |
| 1047 | /* round to closed rdiv */ |
| 1048 | rdiv = SI5351_OUTPUT_CLK_DIV_1; |
| 1049 | new_rate = parent_rate; |
| 1050 | err = abs(new_rate - rate); |
| 1051 | do { |
| 1052 | new_rate >>= 1; |
| 1053 | new_err = abs(new_rate - rate); |
| 1054 | if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) |
| 1055 | break; |
| 1056 | rdiv++; |
| 1057 | err = new_err; |
| 1058 | } while (1); |
| 1059 | |
| 1060 | /* write output divider */ |
| 1061 | switch (hwdata->num) { |
| 1062 | case 6: |
| 1063 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, |
| 1064 | SI5351_OUTPUT_CLK6_DIV_MASK, rdiv); |
| 1065 | break; |
| 1066 | case 7: |
| 1067 | si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, |
| 1068 | SI5351_OUTPUT_CLK_DIV_MASK, |
| 1069 | rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); |
| 1070 | break; |
| 1071 | default: |
| 1072 | si5351_set_bits(hwdata->drvdata, |
| 1073 | si5351_msynth_params_address(hwdata->num) + 2, |
| 1074 | SI5351_OUTPUT_CLK_DIV_MASK, |
| 1075 | rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); |
| 1076 | } |
| 1077 | |
| 1078 | /* powerup clkout */ |
| 1079 | si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, |
| 1080 | SI5351_CLK_POWERDOWN, 0); |
| 1081 | |
| 1082 | dev_dbg(&hwdata->drvdata->client->dev, |
| 1083 | "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", |
| 1084 | __func__, __clk_get_name(hwdata->hw.clk), (1 << rdiv), |
| 1085 | parent_rate, rate); |
| 1086 | |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
| 1090 | static const struct clk_ops si5351_clkout_ops = { |
| 1091 | .prepare = si5351_clkout_prepare, |
| 1092 | .unprepare = si5351_clkout_unprepare, |
| 1093 | .set_parent = si5351_clkout_set_parent, |
| 1094 | .get_parent = si5351_clkout_get_parent, |
| 1095 | .recalc_rate = si5351_clkout_recalc_rate, |
| 1096 | .round_rate = si5351_clkout_round_rate, |
| 1097 | .set_rate = si5351_clkout_set_rate, |
| 1098 | }; |
| 1099 | |
| 1100 | /* |
| 1101 | * Si5351 i2c probe and DT |
| 1102 | */ |
| 1103 | #ifdef CONFIG_OF |
| 1104 | static const struct of_device_id si5351_dt_ids[] = { |
| 1105 | { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, }, |
| 1106 | { .compatible = "silabs,si5351a-msop", |
| 1107 | .data = (void *)SI5351_VARIANT_A3, }, |
| 1108 | { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, }, |
| 1109 | { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, }, |
| 1110 | { } |
| 1111 | }; |
| 1112 | MODULE_DEVICE_TABLE(of, si5351_dt_ids); |
| 1113 | |
| 1114 | static int si5351_dt_parse(struct i2c_client *client) |
| 1115 | { |
| 1116 | struct device_node *child, *np = client->dev.of_node; |
| 1117 | struct si5351_platform_data *pdata; |
| 1118 | const struct of_device_id *match; |
| 1119 | struct property *prop; |
| 1120 | const __be32 *p; |
| 1121 | int num = 0; |
| 1122 | u32 val; |
| 1123 | |
| 1124 | if (np == NULL) |
| 1125 | return 0; |
| 1126 | |
| 1127 | match = of_match_node(si5351_dt_ids, np); |
| 1128 | if (match == NULL) |
| 1129 | return -EINVAL; |
| 1130 | |
| 1131 | pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); |
| 1132 | if (!pdata) |
| 1133 | return -ENOMEM; |
| 1134 | |
| 1135 | pdata->variant = (enum si5351_variant)match->data; |
| 1136 | pdata->clk_xtal = of_clk_get(np, 0); |
| 1137 | if (!IS_ERR(pdata->clk_xtal)) |
| 1138 | clk_put(pdata->clk_xtal); |
| 1139 | pdata->clk_clkin = of_clk_get(np, 1); |
| 1140 | if (!IS_ERR(pdata->clk_clkin)) |
| 1141 | clk_put(pdata->clk_clkin); |
| 1142 | |
| 1143 | /* |
| 1144 | * property silabs,pll-source : <num src>, [<..>] |
| 1145 | * allow to selectively set pll source |
| 1146 | */ |
| 1147 | of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) { |
| 1148 | if (num >= 2) { |
| 1149 | dev_err(&client->dev, |
| 1150 | "invalid pll %d on pll-source prop\n", num); |
| 1151 | return -EINVAL; |
| 1152 | } |
| 1153 | |
| 1154 | p = of_prop_next_u32(prop, p, &val); |
| 1155 | if (!p) { |
| 1156 | dev_err(&client->dev, |
| 1157 | "missing pll-source for pll %d\n", num); |
| 1158 | return -EINVAL; |
| 1159 | } |
| 1160 | |
| 1161 | switch (val) { |
| 1162 | case 0: |
| 1163 | pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; |
| 1164 | break; |
| 1165 | case 1: |
| 1166 | if (pdata->variant != SI5351_VARIANT_C) { |
| 1167 | dev_err(&client->dev, |
| 1168 | "invalid parent %d for pll %d\n", |
| 1169 | val, num); |
| 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN; |
| 1173 | break; |
| 1174 | default: |
| 1175 | dev_err(&client->dev, |
| 1176 | "invalid parent %d for pll %d\n", val, num); |
| 1177 | return -EINVAL; |
| 1178 | } |
| 1179 | } |
| 1180 | |
| 1181 | /* per clkout properties */ |
| 1182 | for_each_child_of_node(np, child) { |
| 1183 | if (of_property_read_u32(child, "reg", &num)) { |
| 1184 | dev_err(&client->dev, "missing reg property of %s\n", |
| 1185 | child->name); |
| 1186 | return -EINVAL; |
| 1187 | } |
| 1188 | |
| 1189 | if (num >= 8 || |
| 1190 | (pdata->variant == SI5351_VARIANT_A3 && num >= 3)) { |
| 1191 | dev_err(&client->dev, "invalid clkout %d\n", num); |
| 1192 | return -EINVAL; |
| 1193 | } |
| 1194 | |
| 1195 | if (!of_property_read_u32(child, "silabs,multisynth-source", |
| 1196 | &val)) { |
| 1197 | switch (val) { |
| 1198 | case 0: |
| 1199 | pdata->clkout[num].multisynth_src = |
| 1200 | SI5351_MULTISYNTH_SRC_VCO0; |
| 1201 | break; |
| 1202 | case 1: |
| 1203 | pdata->clkout[num].multisynth_src = |
| 1204 | SI5351_MULTISYNTH_SRC_VCO1; |
| 1205 | break; |
| 1206 | default: |
| 1207 | dev_err(&client->dev, |
| 1208 | "invalid parent %d for multisynth %d\n", |
| 1209 | val, num); |
| 1210 | return -EINVAL; |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | if (!of_property_read_u32(child, "silabs,clock-source", &val)) { |
| 1215 | switch (val) { |
| 1216 | case 0: |
| 1217 | pdata->clkout[num].clkout_src = |
| 1218 | SI5351_CLKOUT_SRC_MSYNTH_N; |
| 1219 | break; |
| 1220 | case 1: |
| 1221 | pdata->clkout[num].clkout_src = |
| 1222 | SI5351_CLKOUT_SRC_MSYNTH_0_4; |
| 1223 | break; |
| 1224 | case 2: |
| 1225 | pdata->clkout[num].clkout_src = |
| 1226 | SI5351_CLKOUT_SRC_XTAL; |
| 1227 | break; |
| 1228 | case 3: |
| 1229 | if (pdata->variant != SI5351_VARIANT_C) { |
| 1230 | dev_err(&client->dev, |
| 1231 | "invalid parent %d for clkout %d\n", |
| 1232 | val, num); |
| 1233 | return -EINVAL; |
| 1234 | } |
| 1235 | pdata->clkout[num].clkout_src = |
| 1236 | SI5351_CLKOUT_SRC_CLKIN; |
| 1237 | break; |
| 1238 | default: |
| 1239 | dev_err(&client->dev, |
| 1240 | "invalid parent %d for clkout %d\n", |
| 1241 | val, num); |
| 1242 | return -EINVAL; |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | if (!of_property_read_u32(child, "silabs,drive-strength", |
| 1247 | &val)) { |
| 1248 | switch (val) { |
| 1249 | case SI5351_DRIVE_2MA: |
| 1250 | case SI5351_DRIVE_4MA: |
| 1251 | case SI5351_DRIVE_6MA: |
| 1252 | case SI5351_DRIVE_8MA: |
| 1253 | pdata->clkout[num].drive = val; |
| 1254 | break; |
| 1255 | default: |
| 1256 | dev_err(&client->dev, |
| 1257 | "invalid drive strength %d for clkout %d\n", |
| 1258 | val, num); |
| 1259 | return -EINVAL; |
| 1260 | } |
| 1261 | } |
| 1262 | |
Sebastian Hesselbarth | 1a0483d | 2013-05-03 07:33:27 +0200 | [diff] [blame] | 1263 | if (!of_property_read_u32(child, "silabs,disable-state", |
| 1264 | &val)) { |
| 1265 | switch (val) { |
| 1266 | case 0: |
| 1267 | pdata->clkout[num].disable_state = |
| 1268 | SI5351_DISABLE_LOW; |
| 1269 | break; |
| 1270 | case 1: |
| 1271 | pdata->clkout[num].disable_state = |
| 1272 | SI5351_DISABLE_HIGH; |
| 1273 | break; |
| 1274 | case 2: |
| 1275 | pdata->clkout[num].disable_state = |
| 1276 | SI5351_DISABLE_FLOATING; |
| 1277 | break; |
| 1278 | case 3: |
| 1279 | pdata->clkout[num].disable_state = |
| 1280 | SI5351_DISABLE_NEVER; |
| 1281 | break; |
| 1282 | default: |
| 1283 | dev_err(&client->dev, |
| 1284 | "invalid disable state %d for clkout %d\n", |
| 1285 | val, num); |
| 1286 | return -EINVAL; |
| 1287 | } |
| 1288 | } |
| 1289 | |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1290 | if (!of_property_read_u32(child, "clock-frequency", &val)) |
| 1291 | pdata->clkout[num].rate = val; |
| 1292 | |
| 1293 | pdata->clkout[num].pll_master = |
| 1294 | of_property_read_bool(child, "silabs,pll-master"); |
| 1295 | } |
| 1296 | client->dev.platform_data = pdata; |
| 1297 | |
| 1298 | return 0; |
| 1299 | } |
| 1300 | #else |
| 1301 | static int si5351_dt_parse(struct i2c_client *client) |
| 1302 | { |
| 1303 | return 0; |
| 1304 | } |
| 1305 | #endif /* CONFIG_OF */ |
| 1306 | |
| 1307 | static int si5351_i2c_probe(struct i2c_client *client, |
| 1308 | const struct i2c_device_id *id) |
| 1309 | { |
| 1310 | struct si5351_platform_data *pdata; |
| 1311 | struct si5351_driver_data *drvdata; |
| 1312 | struct clk_init_data init; |
| 1313 | struct clk *clk; |
| 1314 | const char *parent_names[4]; |
| 1315 | u8 num_parents, num_clocks; |
| 1316 | int ret, n; |
| 1317 | |
| 1318 | ret = si5351_dt_parse(client); |
| 1319 | if (ret) |
| 1320 | return ret; |
| 1321 | |
| 1322 | pdata = client->dev.platform_data; |
| 1323 | if (!pdata) |
| 1324 | return -EINVAL; |
| 1325 | |
| 1326 | drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL); |
| 1327 | if (drvdata == NULL) { |
| 1328 | dev_err(&client->dev, "unable to allocate driver data\n"); |
| 1329 | return -ENOMEM; |
| 1330 | } |
| 1331 | |
| 1332 | i2c_set_clientdata(client, drvdata); |
| 1333 | drvdata->client = client; |
| 1334 | drvdata->variant = pdata->variant; |
| 1335 | drvdata->pxtal = pdata->clk_xtal; |
| 1336 | drvdata->pclkin = pdata->clk_clkin; |
| 1337 | |
| 1338 | drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); |
| 1339 | if (IS_ERR(drvdata->regmap)) { |
| 1340 | dev_err(&client->dev, "failed to allocate register map\n"); |
| 1341 | return PTR_ERR(drvdata->regmap); |
| 1342 | } |
| 1343 | |
| 1344 | /* Disable interrupts */ |
| 1345 | si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0); |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1346 | /* Ensure pll select is on XTAL for Si5351A/B */ |
| 1347 | if (drvdata->variant != SI5351_VARIANT_C) |
| 1348 | si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, |
| 1349 | SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0); |
| 1350 | |
| 1351 | /* setup clock configuration */ |
| 1352 | for (n = 0; n < 2; n++) { |
| 1353 | ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]); |
| 1354 | if (ret) { |
| 1355 | dev_err(&client->dev, |
| 1356 | "failed to reparent pll %d to %d\n", |
| 1357 | n, pdata->pll_src[n]); |
| 1358 | return ret; |
| 1359 | } |
| 1360 | } |
| 1361 | |
| 1362 | for (n = 0; n < 8; n++) { |
| 1363 | ret = _si5351_msynth_reparent(drvdata, n, |
| 1364 | pdata->clkout[n].multisynth_src); |
| 1365 | if (ret) { |
| 1366 | dev_err(&client->dev, |
| 1367 | "failed to reparent multisynth %d to %d\n", |
| 1368 | n, pdata->clkout[n].multisynth_src); |
| 1369 | return ret; |
| 1370 | } |
| 1371 | |
| 1372 | ret = _si5351_clkout_reparent(drvdata, n, |
| 1373 | pdata->clkout[n].clkout_src); |
| 1374 | if (ret) { |
| 1375 | dev_err(&client->dev, |
| 1376 | "failed to reparent clkout %d to %d\n", |
| 1377 | n, pdata->clkout[n].clkout_src); |
| 1378 | return ret; |
| 1379 | } |
| 1380 | |
| 1381 | ret = _si5351_clkout_set_drive_strength(drvdata, n, |
| 1382 | pdata->clkout[n].drive); |
| 1383 | if (ret) { |
| 1384 | dev_err(&client->dev, |
| 1385 | "failed set drive strength of clkout%d to %d\n", |
| 1386 | n, pdata->clkout[n].drive); |
| 1387 | return ret; |
| 1388 | } |
Sebastian Hesselbarth | 1a0483d | 2013-05-03 07:33:27 +0200 | [diff] [blame] | 1389 | |
| 1390 | ret = _si5351_clkout_set_disable_state(drvdata, n, |
| 1391 | pdata->clkout[n].disable_state); |
| 1392 | if (ret) { |
| 1393 | dev_err(&client->dev, |
| 1394 | "failed set disable state of clkout%d to %d\n", |
| 1395 | n, pdata->clkout[n].disable_state); |
| 1396 | return ret; |
| 1397 | } |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1398 | } |
| 1399 | |
| 1400 | /* register xtal input clock gate */ |
| 1401 | memset(&init, 0, sizeof(init)); |
| 1402 | init.name = si5351_input_names[0]; |
| 1403 | init.ops = &si5351_xtal_ops; |
| 1404 | init.flags = 0; |
| 1405 | if (!IS_ERR(drvdata->pxtal)) { |
| 1406 | drvdata->pxtal_name = __clk_get_name(drvdata->pxtal); |
| 1407 | init.parent_names = &drvdata->pxtal_name; |
| 1408 | init.num_parents = 1; |
| 1409 | } |
| 1410 | drvdata->xtal.init = &init; |
| 1411 | clk = devm_clk_register(&client->dev, &drvdata->xtal); |
| 1412 | if (IS_ERR(clk)) { |
| 1413 | dev_err(&client->dev, "unable to register %s\n", init.name); |
| 1414 | return PTR_ERR(clk); |
| 1415 | } |
| 1416 | |
| 1417 | /* register clkin input clock gate */ |
| 1418 | if (drvdata->variant == SI5351_VARIANT_C) { |
| 1419 | memset(&init, 0, sizeof(init)); |
| 1420 | init.name = si5351_input_names[1]; |
| 1421 | init.ops = &si5351_clkin_ops; |
| 1422 | if (!IS_ERR(drvdata->pclkin)) { |
| 1423 | drvdata->pclkin_name = __clk_get_name(drvdata->pclkin); |
| 1424 | init.parent_names = &drvdata->pclkin_name; |
| 1425 | init.num_parents = 1; |
| 1426 | } |
| 1427 | drvdata->clkin.init = &init; |
| 1428 | clk = devm_clk_register(&client->dev, &drvdata->clkin); |
| 1429 | if (IS_ERR(clk)) { |
| 1430 | dev_err(&client->dev, "unable to register %s\n", |
| 1431 | init.name); |
| 1432 | return PTR_ERR(clk); |
| 1433 | } |
| 1434 | } |
| 1435 | |
| 1436 | /* Si5351C allows to mux either xtal or clkin to PLL input */ |
| 1437 | num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1; |
| 1438 | parent_names[0] = si5351_input_names[0]; |
| 1439 | parent_names[1] = si5351_input_names[1]; |
| 1440 | |
| 1441 | /* register PLLA */ |
| 1442 | drvdata->pll[0].num = 0; |
| 1443 | drvdata->pll[0].drvdata = drvdata; |
| 1444 | drvdata->pll[0].hw.init = &init; |
| 1445 | memset(&init, 0, sizeof(init)); |
| 1446 | init.name = si5351_pll_names[0]; |
| 1447 | init.ops = &si5351_pll_ops; |
| 1448 | init.flags = 0; |
| 1449 | init.parent_names = parent_names; |
| 1450 | init.num_parents = num_parents; |
| 1451 | clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw); |
| 1452 | if (IS_ERR(clk)) { |
| 1453 | dev_err(&client->dev, "unable to register %s\n", init.name); |
| 1454 | return -EINVAL; |
| 1455 | } |
| 1456 | |
| 1457 | /* register PLLB or VXCO (Si5351B) */ |
| 1458 | drvdata->pll[1].num = 1; |
| 1459 | drvdata->pll[1].drvdata = drvdata; |
| 1460 | drvdata->pll[1].hw.init = &init; |
| 1461 | memset(&init, 0, sizeof(init)); |
| 1462 | if (drvdata->variant == SI5351_VARIANT_B) { |
| 1463 | init.name = si5351_pll_names[2]; |
| 1464 | init.ops = &si5351_vxco_ops; |
| 1465 | init.flags = CLK_IS_ROOT; |
| 1466 | init.parent_names = NULL; |
| 1467 | init.num_parents = 0; |
| 1468 | } else { |
| 1469 | init.name = si5351_pll_names[1]; |
| 1470 | init.ops = &si5351_pll_ops; |
| 1471 | init.flags = 0; |
| 1472 | init.parent_names = parent_names; |
| 1473 | init.num_parents = num_parents; |
| 1474 | } |
| 1475 | clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw); |
| 1476 | if (IS_ERR(clk)) { |
| 1477 | dev_err(&client->dev, "unable to register %s\n", init.name); |
| 1478 | return -EINVAL; |
| 1479 | } |
| 1480 | |
| 1481 | /* register clk multisync and clk out divider */ |
| 1482 | num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8; |
| 1483 | parent_names[0] = si5351_pll_names[0]; |
| 1484 | if (drvdata->variant == SI5351_VARIANT_B) |
| 1485 | parent_names[1] = si5351_pll_names[2]; |
| 1486 | else |
| 1487 | parent_names[1] = si5351_pll_names[1]; |
| 1488 | |
| 1489 | drvdata->msynth = devm_kzalloc(&client->dev, num_clocks * |
| 1490 | sizeof(*drvdata->msynth), GFP_KERNEL); |
| 1491 | drvdata->clkout = devm_kzalloc(&client->dev, num_clocks * |
| 1492 | sizeof(*drvdata->clkout), GFP_KERNEL); |
| 1493 | |
| 1494 | drvdata->onecell.clk_num = num_clocks; |
| 1495 | drvdata->onecell.clks = devm_kzalloc(&client->dev, |
| 1496 | num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL); |
| 1497 | |
| 1498 | if (WARN_ON(!drvdata->msynth || !drvdata->clkout || |
| 1499 | !drvdata->onecell.clks)) |
| 1500 | return -ENOMEM; |
| 1501 | |
| 1502 | for (n = 0; n < num_clocks; n++) { |
| 1503 | drvdata->msynth[n].num = n; |
| 1504 | drvdata->msynth[n].drvdata = drvdata; |
| 1505 | drvdata->msynth[n].hw.init = &init; |
| 1506 | memset(&init, 0, sizeof(init)); |
| 1507 | init.name = si5351_msynth_names[n]; |
| 1508 | init.ops = &si5351_msynth_ops; |
| 1509 | init.flags = 0; |
| 1510 | if (pdata->clkout[n].pll_master) |
| 1511 | init.flags |= CLK_SET_RATE_PARENT; |
| 1512 | init.parent_names = parent_names; |
| 1513 | init.num_parents = 2; |
| 1514 | clk = devm_clk_register(&client->dev, &drvdata->msynth[n].hw); |
| 1515 | if (IS_ERR(clk)) { |
| 1516 | dev_err(&client->dev, "unable to register %s\n", |
| 1517 | init.name); |
| 1518 | return -EINVAL; |
| 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3; |
| 1523 | parent_names[2] = si5351_input_names[0]; |
| 1524 | parent_names[3] = si5351_input_names[1]; |
| 1525 | for (n = 0; n < num_clocks; n++) { |
| 1526 | parent_names[0] = si5351_msynth_names[n]; |
| 1527 | parent_names[1] = (n < 4) ? si5351_msynth_names[0] : |
| 1528 | si5351_msynth_names[4]; |
| 1529 | |
| 1530 | drvdata->clkout[n].num = n; |
| 1531 | drvdata->clkout[n].drvdata = drvdata; |
| 1532 | drvdata->clkout[n].hw.init = &init; |
| 1533 | memset(&init, 0, sizeof(init)); |
| 1534 | init.name = si5351_clkout_names[n]; |
| 1535 | init.ops = &si5351_clkout_ops; |
| 1536 | init.flags = 0; |
| 1537 | if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N) |
| 1538 | init.flags |= CLK_SET_RATE_PARENT; |
| 1539 | init.parent_names = parent_names; |
| 1540 | init.num_parents = num_parents; |
| 1541 | clk = devm_clk_register(&client->dev, &drvdata->clkout[n].hw); |
| 1542 | if (IS_ERR(clk)) { |
| 1543 | dev_err(&client->dev, "unable to register %s\n", |
| 1544 | init.name); |
| 1545 | return -EINVAL; |
| 1546 | } |
| 1547 | drvdata->onecell.clks[n] = clk; |
| 1548 | } |
| 1549 | |
| 1550 | ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, |
| 1551 | &drvdata->onecell); |
| 1552 | if (ret) { |
| 1553 | dev_err(&client->dev, "unable to add clk provider\n"); |
| 1554 | return ret; |
| 1555 | } |
| 1556 | |
| 1557 | return 0; |
| 1558 | } |
| 1559 | |
| 1560 | static const struct i2c_device_id si5351_i2c_ids[] = { |
Jean-Francois Moine | 9807362b | 2013-05-16 17:49:16 +0200 | [diff] [blame^] | 1561 | { "si5351a", 0 }, |
| 1562 | { "si5351a-msop", 0 }, |
| 1563 | { "si5351b", 0 }, |
| 1564 | { "si5351c", 0 }, |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 1565 | { } |
| 1566 | }; |
| 1567 | MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); |
| 1568 | |
| 1569 | static struct i2c_driver si5351_driver = { |
| 1570 | .driver = { |
| 1571 | .name = "si5351", |
| 1572 | .of_match_table = of_match_ptr(si5351_dt_ids), |
| 1573 | }, |
| 1574 | .probe = si5351_i2c_probe, |
| 1575 | .id_table = si5351_i2c_ids, |
| 1576 | }; |
| 1577 | module_i2c_driver(si5351_driver); |
| 1578 | |
| 1579 | MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com"); |
| 1580 | MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver"); |
| 1581 | MODULE_LICENSE("GPL"); |