Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform |
| 3 | * driver source file |
| 4 | * |
Sujit Reddy Thumma | bf1aecc | 2014-01-10 10:58:54 +0530 | [diff] [blame] | 5 | * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 and |
| 9 | * only version 2 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/mmc/host.h> |
| 20 | #include <linux/mmc/card.h> |
| 21 | #include <linux/mmc/sdio_func.h> |
| 22 | #include <linux/gfp.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/of_gpio.h> |
| 25 | #include <linux/regulator/consumer.h> |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/input.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/wait.h> |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 30 | #include <linux/io.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/scatterlist.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/mmc/mmc.h> |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 35 | #include <linux/mmc/slot-gpio.h> |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 36 | #include <linux/dma-mapping.h> |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 37 | #include <linux/iopoll.h> |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 38 | #include <linux/pinctrl/consumer.h> |
| 39 | #include <linux/iopoll.h> |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 40 | #include <linux/msm-bus.h> |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 41 | |
| 42 | #include "sdhci-pltfm.h" |
| 43 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 44 | #define SDHCI_VER_100 0x2B |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 45 | |
| 46 | #define CORE_VERSION_MAJOR_MASK 0xF0000000 |
| 47 | #define CORE_VERSION_MAJOR_SHIFT 28 |
| 48 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 49 | #define CORE_HC_MODE 0x78 |
| 50 | #define HC_MODE_EN 0x1 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 51 | #define FF_CLK_SW_RST_DIS (1 << 13) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 52 | |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 53 | #define CORE_GENERICS 0x70 |
| 54 | #define SWITCHABLE_SIGNALLING_VOL (1 << 29) |
| 55 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 56 | #define CORE_POWER 0x0 |
| 57 | #define CORE_SW_RST (1 << 7) |
| 58 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 59 | #define CORE_MCI_VERSION 0x050 |
| 60 | #define CORE_TESTBUS_CONFIG 0x0CC |
| 61 | #define CORE_TESTBUS_ENA (1 << 3) |
| 62 | #define CORE_SDCC_DEBUG_REG 0x124 |
| 63 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 64 | #define CORE_PWRCTL_STATUS 0xDC |
| 65 | #define CORE_PWRCTL_MASK 0xE0 |
| 66 | #define CORE_PWRCTL_CLEAR 0xE4 |
| 67 | #define CORE_PWRCTL_CTL 0xE8 |
| 68 | |
| 69 | #define CORE_PWRCTL_BUS_OFF 0x01 |
| 70 | #define CORE_PWRCTL_BUS_ON (1 << 1) |
| 71 | #define CORE_PWRCTL_IO_LOW (1 << 2) |
| 72 | #define CORE_PWRCTL_IO_HIGH (1 << 3) |
| 73 | |
| 74 | #define CORE_PWRCTL_BUS_SUCCESS 0x01 |
| 75 | #define CORE_PWRCTL_BUS_FAIL (1 << 1) |
| 76 | #define CORE_PWRCTL_IO_SUCCESS (1 << 2) |
| 77 | #define CORE_PWRCTL_IO_FAIL (1 << 3) |
| 78 | |
| 79 | #define INT_MASK 0xF |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 80 | #define MAX_PHASES 16 |
| 81 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 82 | #define CORE_DLL_CONFIG 0x100 |
| 83 | #define CORE_CMD_DAT_TRACK_SEL (1 << 0) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 84 | #define CORE_DLL_EN (1 << 16) |
| 85 | #define CORE_CDR_EN (1 << 17) |
| 86 | #define CORE_CK_OUT_EN (1 << 18) |
| 87 | #define CORE_CDR_EXT_EN (1 << 19) |
| 88 | #define CORE_DLL_PDN (1 << 29) |
| 89 | #define CORE_DLL_RST (1 << 30) |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 90 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 91 | #define CORE_DLL_STATUS 0x108 |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 92 | #define CORE_DLL_LOCK (1 << 7) |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 93 | #define CORE_DDR_DLL_LOCK (1 << 11) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 94 | |
| 95 | #define CORE_VENDOR_SPEC 0x10C |
| 96 | #define CORE_CLK_PWRSAVE (1 << 1) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 97 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
| 98 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) |
| 99 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 100 | #define CORE_HC_AUTO_CMD21_EN (1 << 6) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 101 | #define CORE_IO_PAD_PWR_SWITCH (1 << 16) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 102 | #define CORE_HC_SELECT_IN_EN (1 << 18) |
| 103 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) |
| 104 | #define CORE_HC_SELECT_IN_MASK (7 << 19) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 105 | |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 106 | #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11C |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 107 | #define CORE_8_BIT_SUPPORT (1 << 18) |
| 108 | #define CORE_3_3V_SUPPORT (1 << 24) |
| 109 | #define CORE_3_0V_SUPPORT (1 << 25) |
| 110 | #define CORE_1_8V_SUPPORT (1 << 26) |
Gilad Broner | 2a10ca0 | 2014-10-02 17:20:35 +0300 | [diff] [blame] | 111 | #define CORE_SYS_BUS_SUPPORT_64_BIT BIT(28) |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 112 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 113 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 |
| 114 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 |
| 115 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 116 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
| 117 | #define CORE_SW_TRIG_FULL_CALIB (1 << 16) |
| 118 | #define CORE_HW_AUTOCAL_ENA (1 << 17) |
| 119 | |
| 120 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 |
| 121 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 |
| 122 | #define CORE_TIMER_ENA (1 << 16) |
| 123 | |
| 124 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C |
| 125 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 |
| 126 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 |
| 127 | #define CORE_CDC_OFFSET_CFG 0x14C |
| 128 | #define CORE_CSR_CDC_DELAY_CFG 0x150 |
| 129 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 |
| 130 | #define CORE_CSR_CDC_STATUS0 0x164 |
| 131 | #define CORE_CALIBRATION_DONE (1 << 0) |
| 132 | |
| 133 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 |
| 134 | |
| 135 | #define CORE_CSR_CDC_GEN_CFG 0x178 |
| 136 | #define CORE_CDC_SWITCH_BYPASS_OFF (1 << 0) |
| 137 | #define CORE_CDC_SWITCH_RC_EN (1 << 1) |
| 138 | |
| 139 | #define CORE_DDR_200_CFG 0x184 |
| 140 | #define CORE_CDC_T4_DLY_SEL (1 << 0) |
| 141 | #define CORE_START_CDC_TRAFFIC (1 << 6) |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 142 | #define CORE_VENDOR_SPEC3 0x1B0 |
| 143 | #define CORE_PWRSAVE_DLL (1 << 3) |
| 144 | |
| 145 | #define CORE_DLL_CONFIG_2 0x1B4 |
| 146 | #define CORE_DDR_CAL_EN (1 << 0) |
| 147 | |
| 148 | #define CORE_DDR_CONFIG 0x1B8 |
| 149 | #define DDR_CONFIG_POR_VAL 0x80040853 |
| 150 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 151 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 152 | #define CORE_MCI_DATA_CNT 0x30 |
| 153 | #define CORE_MCI_STATUS 0x34 |
| 154 | #define CORE_MCI_FIFO_CNT 0x44 |
| 155 | |
| 156 | #define CORE_TESTBUS_SEL2_BIT 4 |
| 157 | #define CORE_TESTBUS_SEL2 (1 << CORE_TESTBUS_SEL2_BIT) |
| 158 | |
Venkat Gopalakrishnan | 450745e | 2014-07-24 20:39:34 -0700 | [diff] [blame] | 159 | /* 512 descriptors */ |
| 160 | #define SDHCI_MSM_MAX_SEGMENTS (1 << 9) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 161 | #define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 162 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 163 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
| 164 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 165 | #define INVALID_TUNING_PHASE -1 |
| 166 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 167 | #define CORE_VERSION_TARGET_MASK 0x000000FF |
| 168 | |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 169 | #define NUM_TUNING_PHASES 16 |
| 170 | #define MAX_DRV_TYPES_SUPPORTED_HS200 3 |
| 171 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 172 | static const u32 tuning_block_64[] = { |
| 173 | 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE, |
| 174 | 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777, |
| 175 | 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF, |
| 176 | 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7 |
| 177 | }; |
| 178 | |
| 179 | static const u32 tuning_block_128[] = { |
| 180 | 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC, |
| 181 | 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF, |
| 182 | 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF, |
| 183 | 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB, |
| 184 | 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC, |
| 185 | 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF, |
| 186 | 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB, |
| 187 | 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77 |
| 188 | }; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 189 | |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 190 | static int disable_slots; |
| 191 | /* root can write, others read */ |
| 192 | module_param(disable_slots, int, S_IRUGO|S_IWUSR); |
| 193 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 194 | /* This structure keeps information per regulator */ |
| 195 | struct sdhci_msm_reg_data { |
| 196 | /* voltage regulator handle */ |
| 197 | struct regulator *reg; |
| 198 | /* regulator name */ |
| 199 | const char *name; |
| 200 | /* voltage level to be set */ |
| 201 | u32 low_vol_level; |
| 202 | u32 high_vol_level; |
| 203 | /* Load values for low power and high power mode */ |
| 204 | u32 lpm_uA; |
| 205 | u32 hpm_uA; |
| 206 | |
| 207 | /* is this regulator enabled? */ |
| 208 | bool is_enabled; |
| 209 | /* is this regulator needs to be always on? */ |
| 210 | bool is_always_on; |
| 211 | /* is low power mode setting required for this regulator? */ |
| 212 | bool lpm_sup; |
| 213 | bool set_voltage_sup; |
| 214 | }; |
| 215 | |
Asutosh Das | 598a4d4 | 2014-02-05 16:38:23 +0530 | [diff] [blame] | 216 | #define MSM_MMC_DEFAULT_CPU_DMA_LATENCY 200 /* usecs */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 217 | /* |
| 218 | * This structure keeps information for all the |
| 219 | * regulators required for a SDCC slot. |
| 220 | */ |
| 221 | struct sdhci_msm_slot_reg_data { |
| 222 | /* keeps VDD/VCC regulator info */ |
| 223 | struct sdhci_msm_reg_data *vdd_data; |
| 224 | /* keeps VDD IO regulator info */ |
| 225 | struct sdhci_msm_reg_data *vdd_io_data; |
| 226 | }; |
| 227 | |
| 228 | struct sdhci_msm_gpio { |
| 229 | u32 no; |
| 230 | const char *name; |
| 231 | bool is_enabled; |
| 232 | }; |
| 233 | |
| 234 | struct sdhci_msm_gpio_data { |
| 235 | struct sdhci_msm_gpio *gpio; |
| 236 | u8 size; |
| 237 | }; |
| 238 | |
| 239 | struct sdhci_msm_pin_data { |
| 240 | /* |
| 241 | * = 1 if controller pins are using gpios |
| 242 | * = 0 if controller has dedicated MSM pads |
| 243 | */ |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 244 | u8 is_gpio; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 245 | struct sdhci_msm_gpio_data *gpio_data; |
| 246 | }; |
| 247 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 248 | struct sdhci_pinctrl_data { |
| 249 | struct pinctrl *pctrl; |
| 250 | struct pinctrl_state *pins_active; |
| 251 | struct pinctrl_state *pins_sleep; |
| 252 | }; |
| 253 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 254 | struct sdhci_msm_bus_voting_data { |
| 255 | struct msm_bus_scale_pdata *bus_pdata; |
| 256 | unsigned int *bw_vecs; |
| 257 | unsigned int bw_vecs_size; |
| 258 | }; |
| 259 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 260 | struct sdhci_msm_pltfm_data { |
| 261 | /* Supported UHS-I Modes */ |
| 262 | u32 caps; |
| 263 | |
| 264 | /* More capabilities */ |
| 265 | u32 caps2; |
| 266 | |
| 267 | unsigned long mmc_bus_width; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 268 | struct sdhci_msm_slot_reg_data *vreg_data; |
| 269 | bool nonremovable; |
Guoping Yu | f7c9133 | 2014-08-20 16:56:18 +0800 | [diff] [blame] | 270 | bool nonhotplug; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 271 | bool pin_cfg_sts; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 272 | struct sdhci_msm_pin_data *pin_data; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 273 | struct sdhci_pinctrl_data *pctrl_data; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 274 | u32 cpu_dma_latency_us; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 275 | int status_gpio; /* card detection GPIO that is configured as IRQ */ |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 276 | struct sdhci_msm_bus_voting_data *voting_data; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 277 | u32 *sup_clk_table; |
| 278 | unsigned char sup_clk_cnt; |
Maya Erez | 994cf2f | 2014-10-21 20:22:04 +0300 | [diff] [blame^] | 279 | enum pm_qos_req_type cpu_affinity_type; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | struct sdhci_msm_bus_vote { |
| 283 | uint32_t client_handle; |
| 284 | uint32_t curr_vote; |
| 285 | int min_bw_vote; |
| 286 | int max_bw_vote; |
| 287 | bool is_max_bw_needed; |
| 288 | struct delayed_work vote_work; |
| 289 | struct device_attribute max_bus_bw; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | struct sdhci_msm_host { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 293 | struct platform_device *pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 294 | void __iomem *core_mem; /* MSM SDCC mapped address */ |
| 295 | struct clk *clk; /* main SD/MMC bus clock */ |
| 296 | struct clk *pclk; /* SDHC peripheral bus clock */ |
| 297 | struct clk *bus_clk; /* SDHC bus voter clock */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 298 | struct clk *ff_clk; /* CDC calibration fixed feedback clock */ |
| 299 | struct clk *sleep_clk; /* CDC calibration sleep clock */ |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 300 | atomic_t clks_on; /* Set if clocks are enabled */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 301 | struct sdhci_msm_pltfm_data *pdata; |
| 302 | struct mmc_host *mmc; |
| 303 | struct sdhci_pltfm_data sdhci_msm_pdata; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 304 | u32 curr_pwr_state; |
| 305 | u32 curr_io_level; |
| 306 | struct completion pwr_irq_completion; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 307 | struct sdhci_msm_bus_vote msm_bus_vote; |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 308 | struct device_attribute polling; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 309 | u32 clk_rate; /* Keeps track of current clock rate that is set */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 310 | bool tuning_done; |
| 311 | bool calibration_done; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 312 | u8 saved_tuning_phase; |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 313 | bool en_auto_cmd21; |
| 314 | struct device_attribute auto_cmd21_attr; |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 315 | atomic_t controller_clock; |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 316 | bool use_cdclp533; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | enum vdd_io_level { |
| 320 | /* set vdd_io_data->low_vol_level */ |
| 321 | VDD_IO_LOW, |
| 322 | /* set vdd_io_data->high_vol_level */ |
| 323 | VDD_IO_HIGH, |
| 324 | /* |
| 325 | * set whatever there in voltage_level (third argument) of |
| 326 | * sdhci_msm_set_vdd_io_vol() function. |
| 327 | */ |
| 328 | VDD_IO_SET_LEVEL, |
| 329 | }; |
| 330 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 331 | /* MSM platform specific tuning */ |
| 332 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, |
| 333 | u8 poll) |
| 334 | { |
| 335 | int rc = 0; |
| 336 | u32 wait_cnt = 50; |
| 337 | u8 ck_out_en = 0; |
| 338 | struct mmc_host *mmc = host->mmc; |
| 339 | |
| 340 | /* poll for CK_OUT_EN bit. max. poll time = 50us */ |
| 341 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & |
| 342 | CORE_CK_OUT_EN); |
| 343 | |
| 344 | while (ck_out_en != poll) { |
| 345 | if (--wait_cnt == 0) { |
| 346 | pr_err("%s: %s: CK_OUT_EN bit is not %d\n", |
| 347 | mmc_hostname(mmc), __func__, poll); |
| 348 | rc = -ETIMEDOUT; |
| 349 | goto out; |
| 350 | } |
| 351 | udelay(1); |
| 352 | |
| 353 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
| 354 | CORE_DLL_CONFIG) & CORE_CK_OUT_EN); |
| 355 | } |
| 356 | out: |
| 357 | return rc; |
| 358 | } |
| 359 | |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 360 | /* |
| 361 | * Enable CDR to track changes of DAT lines and adjust sampling |
| 362 | * point according to voltage/temperature variations |
| 363 | */ |
| 364 | static int msm_enable_cdr_cm_sdc4_dll(struct sdhci_host *host) |
| 365 | { |
| 366 | int rc = 0; |
| 367 | u32 config; |
| 368 | |
| 369 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 370 | config |= CORE_CDR_EN; |
| 371 | config &= ~(CORE_CDR_EXT_EN | CORE_CK_OUT_EN); |
| 372 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 373 | |
| 374 | rc = msm_dll_poll_ck_out_en(host, 0); |
| 375 | if (rc) |
| 376 | goto err; |
| 377 | |
| 378 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) | |
| 379 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 380 | |
| 381 | rc = msm_dll_poll_ck_out_en(host, 1); |
| 382 | if (rc) |
| 383 | goto err; |
| 384 | goto out; |
| 385 | err: |
| 386 | pr_err("%s: %s: failed\n", mmc_hostname(host->mmc), __func__); |
| 387 | out: |
| 388 | return rc; |
| 389 | } |
| 390 | |
| 391 | static ssize_t store_auto_cmd21(struct device *dev, struct device_attribute |
| 392 | *attr, const char *buf, size_t count) |
| 393 | { |
| 394 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 395 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 396 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 397 | u32 tmp; |
| 398 | unsigned long flags; |
| 399 | |
| 400 | if (!kstrtou32(buf, 0, &tmp)) { |
| 401 | spin_lock_irqsave(&host->lock, flags); |
| 402 | msm_host->en_auto_cmd21 = !!tmp; |
| 403 | spin_unlock_irqrestore(&host->lock, flags); |
| 404 | } |
| 405 | return count; |
| 406 | } |
| 407 | |
| 408 | static ssize_t show_auto_cmd21(struct device *dev, |
| 409 | struct device_attribute *attr, char *buf) |
| 410 | { |
| 411 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 413 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 414 | |
| 415 | return snprintf(buf, PAGE_SIZE, "%d\n", msm_host->en_auto_cmd21); |
| 416 | } |
| 417 | |
| 418 | /* MSM auto-tuning handler */ |
| 419 | static int sdhci_msm_config_auto_tuning_cmd(struct sdhci_host *host, |
| 420 | bool enable, |
| 421 | u32 type) |
| 422 | { |
| 423 | int rc = 0; |
| 424 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 425 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 426 | u32 val = 0; |
| 427 | |
| 428 | if (!msm_host->en_auto_cmd21) |
| 429 | return 0; |
| 430 | |
| 431 | if (type == MMC_SEND_TUNING_BLOCK_HS200) |
| 432 | val = CORE_HC_AUTO_CMD21_EN; |
| 433 | else |
| 434 | return 0; |
| 435 | |
| 436 | if (enable) { |
| 437 | rc = msm_enable_cdr_cm_sdc4_dll(host); |
| 438 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | |
| 439 | val, host->ioaddr + CORE_VENDOR_SPEC); |
| 440 | } else { |
| 441 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 442 | ~val, host->ioaddr + CORE_VENDOR_SPEC); |
| 443 | } |
| 444 | return rc; |
| 445 | } |
| 446 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 447 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) |
| 448 | { |
| 449 | int rc = 0; |
| 450 | u8 grey_coded_phase_table[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, |
| 451 | 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, |
| 452 | 0x8}; |
| 453 | unsigned long flags; |
| 454 | u32 config; |
| 455 | struct mmc_host *mmc = host->mmc; |
| 456 | |
| 457 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 458 | spin_lock_irqsave(&host->lock, flags); |
| 459 | |
| 460 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 461 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); |
| 462 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); |
| 463 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 464 | |
| 465 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ |
| 466 | rc = msm_dll_poll_ck_out_en(host, 0); |
| 467 | if (rc) |
| 468 | goto err_out; |
| 469 | |
| 470 | /* |
| 471 | * Write the selected DLL clock output phase (0 ... 15) |
| 472 | * to CDR_SELEXT bit field of DLL_CONFIG register. |
| 473 | */ |
| 474 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 475 | & ~(0xF << 20)) |
| 476 | | (grey_coded_phase_table[phase] << 20)), |
| 477 | host->ioaddr + CORE_DLL_CONFIG); |
| 478 | |
| 479 | /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ |
| 480 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 481 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 482 | |
| 483 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ |
| 484 | rc = msm_dll_poll_ck_out_en(host, 1); |
| 485 | if (rc) |
| 486 | goto err_out; |
| 487 | |
| 488 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 489 | config |= CORE_CDR_EN; |
| 490 | config &= ~CORE_CDR_EXT_EN; |
| 491 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 492 | goto out; |
| 493 | |
| 494 | err_out: |
| 495 | pr_err("%s: %s: Failed to set DLL phase: %d\n", |
| 496 | mmc_hostname(mmc), __func__, phase); |
| 497 | out: |
| 498 | spin_unlock_irqrestore(&host->lock, flags); |
| 499 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 500 | return rc; |
| 501 | } |
| 502 | |
| 503 | /* |
| 504 | * Find out the greatest range of consecuitive selected |
| 505 | * DLL clock output phases that can be used as sampling |
| 506 | * setting for SD3.0 UHS-I card read operation (in SDR104 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 507 | * timing mode) or for eMMC4.5 card read operation (in |
| 508 | * HS400/HS200 timing mode). |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 509 | * Select the 3/4 of the range and configure the DLL with the |
| 510 | * selected DLL clock output phase. |
| 511 | */ |
| 512 | |
| 513 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, |
| 514 | u8 *phase_table, u8 total_phases) |
| 515 | { |
| 516 | int ret; |
| 517 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; |
| 518 | u8 phases_per_row[MAX_PHASES] = {0}; |
| 519 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; |
| 520 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; |
| 521 | bool phase_0_found = false, phase_15_found = false; |
| 522 | struct mmc_host *mmc = host->mmc; |
| 523 | |
| 524 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 525 | if (!total_phases || (total_phases > MAX_PHASES)) { |
| 526 | pr_err("%s: %s: invalid argument: total_phases=%d\n", |
| 527 | mmc_hostname(mmc), __func__, total_phases); |
| 528 | return -EINVAL; |
| 529 | } |
| 530 | |
| 531 | for (cnt = 0; cnt < total_phases; cnt++) { |
| 532 | ranges[row_index][col_index] = phase_table[cnt]; |
| 533 | phases_per_row[row_index] += 1; |
| 534 | col_index++; |
| 535 | |
| 536 | if ((cnt + 1) == total_phases) { |
| 537 | continue; |
| 538 | /* check if next phase in phase_table is consecutive or not */ |
| 539 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { |
| 540 | row_index++; |
| 541 | col_index = 0; |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | if (row_index >= MAX_PHASES) |
| 546 | return -EINVAL; |
| 547 | |
| 548 | /* Check if phase-0 is present in first valid window? */ |
| 549 | if (!ranges[0][0]) { |
| 550 | phase_0_found = true; |
| 551 | phase_0_raw_index = 0; |
| 552 | /* Check if cycle exist between 2 valid windows */ |
| 553 | for (cnt = 1; cnt <= row_index; cnt++) { |
| 554 | if (phases_per_row[cnt]) { |
| 555 | for (i = 0; i < phases_per_row[cnt]; i++) { |
| 556 | if (ranges[cnt][i] == 15) { |
| 557 | phase_15_found = true; |
| 558 | phase_15_raw_index = cnt; |
| 559 | break; |
| 560 | } |
| 561 | } |
| 562 | } |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | /* If 2 valid windows form cycle then merge them as single window */ |
| 567 | if (phase_0_found && phase_15_found) { |
| 568 | /* number of phases in raw where phase 0 is present */ |
| 569 | u8 phases_0 = phases_per_row[phase_0_raw_index]; |
| 570 | /* number of phases in raw where phase 15 is present */ |
| 571 | u8 phases_15 = phases_per_row[phase_15_raw_index]; |
| 572 | |
| 573 | if (phases_0 + phases_15 >= MAX_PHASES) |
| 574 | /* |
| 575 | * If there are more than 1 phase windows then total |
| 576 | * number of phases in both the windows should not be |
| 577 | * more than or equal to MAX_PHASES. |
| 578 | */ |
| 579 | return -EINVAL; |
| 580 | |
| 581 | /* Merge 2 cyclic windows */ |
| 582 | i = phases_15; |
| 583 | for (cnt = 0; cnt < phases_0; cnt++) { |
| 584 | ranges[phase_15_raw_index][i] = |
| 585 | ranges[phase_0_raw_index][cnt]; |
| 586 | if (++i >= MAX_PHASES) |
| 587 | break; |
| 588 | } |
| 589 | |
| 590 | phases_per_row[phase_0_raw_index] = 0; |
| 591 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; |
| 592 | } |
| 593 | |
| 594 | for (cnt = 0; cnt <= row_index; cnt++) { |
| 595 | if (phases_per_row[cnt] > curr_max) { |
| 596 | curr_max = phases_per_row[cnt]; |
| 597 | selected_row_index = cnt; |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | i = ((curr_max * 3) / 4); |
| 602 | if (i) |
| 603 | i--; |
| 604 | |
| 605 | ret = (int)ranges[selected_row_index][i]; |
| 606 | |
| 607 | if (ret >= MAX_PHASES) { |
| 608 | ret = -EINVAL; |
| 609 | pr_err("%s: %s: invalid phase selected=%d\n", |
| 610 | mmc_hostname(mmc), __func__, ret); |
| 611 | } |
| 612 | |
| 613 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 614 | return ret; |
| 615 | } |
| 616 | |
| 617 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) |
| 618 | { |
| 619 | u32 mclk_freq = 0; |
| 620 | |
| 621 | /* Program the MCLK value to MCLK_FREQ bit field */ |
| 622 | if (host->clock <= 112000000) |
| 623 | mclk_freq = 0; |
| 624 | else if (host->clock <= 125000000) |
| 625 | mclk_freq = 1; |
| 626 | else if (host->clock <= 137000000) |
| 627 | mclk_freq = 2; |
| 628 | else if (host->clock <= 150000000) |
| 629 | mclk_freq = 3; |
| 630 | else if (host->clock <= 162000000) |
| 631 | mclk_freq = 4; |
| 632 | else if (host->clock <= 175000000) |
| 633 | mclk_freq = 5; |
| 634 | else if (host->clock <= 187000000) |
| 635 | mclk_freq = 6; |
| 636 | else if (host->clock <= 200000000) |
| 637 | mclk_freq = 7; |
| 638 | |
| 639 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 640 | & ~(7 << 24)) | (mclk_freq << 24)), |
| 641 | host->ioaddr + CORE_DLL_CONFIG); |
| 642 | } |
| 643 | |
| 644 | /* Initialize the DLL (Programmable Delay Line ) */ |
| 645 | static int msm_init_cm_dll(struct sdhci_host *host) |
| 646 | { |
| 647 | struct mmc_host *mmc = host->mmc; |
| 648 | int rc = 0; |
| 649 | unsigned long flags; |
| 650 | u32 wait_cnt; |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 651 | bool prev_pwrsave, curr_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 652 | |
| 653 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 654 | spin_lock_irqsave(&host->lock, flags); |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 655 | prev_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 656 | CORE_CLK_PWRSAVE); |
| 657 | curr_pwrsave = prev_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 658 | /* |
| 659 | * Make sure that clock is always enabled when DLL |
| 660 | * tuning is in progress. Keeping PWRSAVE ON may |
| 661 | * turn off the clock. So let's disable the PWRSAVE |
| 662 | * here and re-enable it once tuning is completed. |
| 663 | */ |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 664 | if (prev_pwrsave) { |
| 665 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 666 | & ~CORE_CLK_PWRSAVE), |
| 667 | host->ioaddr + CORE_VENDOR_SPEC); |
| 668 | curr_pwrsave = false; |
| 669 | } |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 670 | |
| 671 | /* Write 1 to DLL_RST bit of DLL_CONFIG register */ |
| 672 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 673 | | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 674 | |
| 675 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 676 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 677 | | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 678 | msm_cm_dll_set_freq(host); |
| 679 | |
| 680 | /* Write 0 to DLL_RST bit of DLL_CONFIG register */ |
| 681 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 682 | & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 683 | |
| 684 | /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ |
| 685 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 686 | & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 687 | |
| 688 | /* Set DLL_EN bit to 1. */ |
| 689 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 690 | | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 691 | |
| 692 | /* Set CK_OUT_EN bit to 1. */ |
| 693 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 694 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 695 | |
| 696 | wait_cnt = 50; |
| 697 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ |
| 698 | while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & |
| 699 | CORE_DLL_LOCK)) { |
| 700 | /* max. wait for 50us sec for LOCK bit to be set */ |
| 701 | if (--wait_cnt == 0) { |
| 702 | pr_err("%s: %s: DLL failed to LOCK\n", |
| 703 | mmc_hostname(mmc), __func__); |
| 704 | rc = -ETIMEDOUT; |
| 705 | goto out; |
| 706 | } |
| 707 | /* wait for 1us before polling again */ |
| 708 | udelay(1); |
| 709 | } |
| 710 | |
| 711 | out: |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 712 | /* Restore the correct PWRSAVE state */ |
| 713 | if (prev_pwrsave ^ curr_pwrsave) { |
| 714 | u32 reg = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
| 715 | |
| 716 | if (prev_pwrsave) |
| 717 | reg |= CORE_CLK_PWRSAVE; |
| 718 | else |
| 719 | reg &= ~CORE_CLK_PWRSAVE; |
| 720 | |
| 721 | writel_relaxed(reg, host->ioaddr + CORE_VENDOR_SPEC); |
| 722 | } |
| 723 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 724 | spin_unlock_irqrestore(&host->lock, flags); |
| 725 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 726 | return rc; |
| 727 | } |
| 728 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 729 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
| 730 | { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 731 | u32 calib_done; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 732 | int ret = 0; |
| 733 | int cdc_err = 0; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 734 | |
| 735 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 736 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 737 | /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */ |
| 738 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 739 | & ~CORE_CDC_T4_DLY_SEL), |
| 740 | host->ioaddr + CORE_DDR_200_CFG); |
| 741 | |
| 742 | /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */ |
| 743 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) |
| 744 | & ~CORE_CDC_SWITCH_BYPASS_OFF), |
| 745 | host->ioaddr + CORE_CSR_CDC_GEN_CFG); |
| 746 | |
| 747 | /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */ |
| 748 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) |
| 749 | | CORE_CDC_SWITCH_RC_EN), |
| 750 | host->ioaddr + CORE_CSR_CDC_GEN_CFG); |
| 751 | |
| 752 | /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ |
| 753 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 754 | & ~CORE_START_CDC_TRAFFIC), |
| 755 | host->ioaddr + CORE_DDR_200_CFG); |
| 756 | |
| 757 | /* |
| 758 | * Perform CDC Register Initialization Sequence |
| 759 | * |
| 760 | * CORE_CSR_CDC_CTLR_CFG0 0x11800EC |
| 761 | * CORE_CSR_CDC_CTLR_CFG1 0x3011111 |
| 762 | * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000 |
| 763 | * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4 |
| 764 | * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020 |
| 765 | * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19 |
| 766 | * CORE_CSR_CDC_DELAY_CFG 0x3AC |
| 767 | * CORE_CDC_OFFSET_CFG 0x0 |
| 768 | * CORE_CDC_SLAVE_DDA_CFG 0x16334 |
| 769 | */ |
| 770 | |
| 771 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 772 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); |
| 773 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); |
| 774 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); |
| 775 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); |
| 776 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); |
Subhash Jadavani | be406d9 | 2014-06-17 16:47:48 -0700 | [diff] [blame] | 777 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 778 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
| 779 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); |
| 780 | |
| 781 | /* CDC HW Calibration */ |
| 782 | |
| 783 | /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 784 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 785 | | CORE_SW_TRIG_FULL_CALIB), |
| 786 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 787 | |
| 788 | /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 789 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 790 | & ~CORE_SW_TRIG_FULL_CALIB), |
| 791 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 792 | |
| 793 | /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 794 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 795 | | CORE_HW_AUTOCAL_ENA), |
| 796 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 797 | |
| 798 | /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */ |
| 799 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 800 | CORE_CSR_CDC_CAL_TIMER_CFG0) | CORE_TIMER_ENA), |
| 801 | host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); |
| 802 | |
| 803 | mb(); |
| 804 | |
| 805 | /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */ |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 806 | ret = readl_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, |
| 807 | calib_done, (calib_done & CORE_CALIBRATION_DONE), 1, 50); |
| 808 | |
| 809 | if (ret == -ETIMEDOUT) { |
| 810 | pr_err("%s: %s: CDC Calibration was not completed\n", |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 811 | mmc_hostname(host->mmc), __func__); |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 812 | goto out; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 813 | } |
| 814 | |
| 815 | /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */ |
| 816 | cdc_err = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) |
| 817 | & CORE_CDC_ERROR_CODE_MASK; |
| 818 | if (cdc_err) { |
| 819 | pr_err("%s: %s: CDC Error Code %d\n", |
| 820 | mmc_hostname(host->mmc), __func__, cdc_err); |
| 821 | ret = -EINVAL; |
| 822 | goto out; |
| 823 | } |
| 824 | |
| 825 | /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ |
| 826 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 827 | | CORE_START_CDC_TRAFFIC), |
| 828 | host->ioaddr + CORE_DDR_200_CFG); |
| 829 | out: |
| 830 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 831 | __func__, ret); |
| 832 | return ret; |
| 833 | } |
| 834 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 835 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
| 836 | { |
| 837 | u32 dll_status; |
| 838 | int ret = 0; |
| 839 | |
| 840 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 841 | |
| 842 | /* |
| 843 | * Currently the CORE_DDR_CONFIG register defaults to desired |
| 844 | * configuration on reset. Currently reprogramming the power on |
| 845 | * reset (POR) value in case it might have been modified by |
| 846 | * bootloaders. In the future, if this changes, then the desired |
| 847 | * values will need to be programmed appropriately. |
| 848 | */ |
| 849 | writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG); |
| 850 | |
| 851 | /* Write 1 to DDR_CAL_EN field in CORE_DLL_CONFIG_2 */ |
| 852 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2) |
| 853 | | CORE_DDR_CAL_EN), |
| 854 | host->ioaddr + CORE_DLL_CONFIG_2); |
| 855 | |
| 856 | /* Poll on DDR_DLL_LOCK bit in CORE_DLL_STATUS to be set */ |
| 857 | ret = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS, |
| 858 | dll_status, (dll_status & CORE_DDR_DLL_LOCK), 10, 1000); |
| 859 | |
| 860 | if (ret == -ETIMEDOUT) { |
| 861 | pr_err("%s: %s: CM_DLL_SDC4 Calibration was not completed\n", |
| 862 | mmc_hostname(host->mmc), __func__); |
| 863 | goto out; |
| 864 | } |
| 865 | |
| 866 | /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */ |
| 867 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3) |
| 868 | | CORE_PWRSAVE_DLL), |
| 869 | host->ioaddr + CORE_VENDOR_SPEC3); |
| 870 | mb(); |
| 871 | out: |
| 872 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 873 | __func__, ret); |
| 874 | return ret; |
| 875 | } |
| 876 | |
| 877 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) |
| 878 | { |
| 879 | int ret = 0; |
| 880 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 881 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 882 | |
| 883 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 884 | |
| 885 | /* |
| 886 | * Retuning in HS400 (DDR mode) will fail, just reset the |
| 887 | * tuning block and restore the saved tuning phase. |
| 888 | */ |
| 889 | ret = msm_init_cm_dll(host); |
| 890 | if (ret) |
| 891 | goto out; |
| 892 | |
| 893 | /* Set the selected phase in delay line hw block */ |
| 894 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); |
| 895 | if (ret) |
| 896 | goto out; |
| 897 | |
Krishna Konda | 0e8efba | 2014-06-23 14:50:38 -0700 | [diff] [blame] | 898 | /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */ |
| 899 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 900 | | CORE_CMD_DAT_TRACK_SEL), |
| 901 | host->ioaddr + CORE_DLL_CONFIG); |
| 902 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 903 | if (msm_host->use_cdclp533) |
| 904 | /* Calibrate CDCLP533 DLL HW */ |
| 905 | ret = sdhci_msm_cdclp533_calibration(host); |
| 906 | else |
| 907 | /* Calibrate CM_DLL_SDC4 HW */ |
| 908 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); |
| 909 | out: |
| 910 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 911 | __func__, ret); |
| 912 | return ret; |
| 913 | } |
| 914 | |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 915 | static void sdhci_msm_set_mmc_drv_type(struct sdhci_host *host, u32 opcode, |
| 916 | u8 drv_type) |
| 917 | { |
| 918 | struct mmc_command cmd = {0}; |
| 919 | struct mmc_request mrq = {NULL}; |
| 920 | struct mmc_host *mmc = host->mmc; |
| 921 | u8 val = ((drv_type << 4) | 2); |
| 922 | |
| 923 | cmd.opcode = MMC_SWITCH; |
| 924 | cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | |
| 925 | (EXT_CSD_HS_TIMING << 16) | |
| 926 | (val << 8) | |
| 927 | EXT_CSD_CMD_SET_NORMAL; |
| 928 | cmd.flags = MMC_CMD_AC | MMC_RSP_R1B; |
| 929 | /* 1 sec */ |
| 930 | cmd.busy_timeout = 1000 * 1000; |
| 931 | |
| 932 | memset(cmd.resp, 0, sizeof(cmd.resp)); |
| 933 | cmd.retries = 3; |
| 934 | |
| 935 | mrq.cmd = &cmd; |
| 936 | cmd.data = NULL; |
| 937 | |
| 938 | mmc_wait_for_req(mmc, &mrq); |
| 939 | pr_debug("%s: %s: set card drive type to %d\n", |
| 940 | mmc_hostname(mmc), __func__, |
| 941 | drv_type); |
| 942 | } |
| 943 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 944 | int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) |
| 945 | { |
| 946 | unsigned long flags; |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 947 | int tuning_seq_cnt = 3; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 948 | u8 phase, *data_buf, tuned_phases[NUM_TUNING_PHASES], tuned_phase_cnt; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 949 | const u32 *tuning_block_pattern = tuning_block_64; |
| 950 | int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */ |
| 951 | int rc; |
| 952 | struct mmc_host *mmc = host->mmc; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 953 | struct mmc_ios ios = host->mmc->ios; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 954 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 955 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 956 | u8 drv_type = 0; |
| 957 | bool drv_type_changed = false; |
| 958 | struct mmc_card *card = host->mmc->card; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 959 | |
| 960 | /* |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 961 | * Tuning is required for SDR104, HS200 and HS400 cards and |
| 962 | * if clock frequency is greater than 100MHz in these modes. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 963 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 964 | if (host->clock <= CORE_FREQ_100MHZ || |
| 965 | !((ios.timing == MMC_TIMING_MMC_HS400) || |
| 966 | (ios.timing == MMC_TIMING_MMC_HS200) || |
| 967 | (ios.timing == MMC_TIMING_UHS_SDR104))) |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 968 | return 0; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 969 | |
| 970 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 971 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 972 | /* CDC/SDC4 DLL HW calibration is only required for HS400 mode*/ |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 973 | if (msm_host->tuning_done && !msm_host->calibration_done && |
| 974 | (mmc->ios.timing == MMC_TIMING_MMC_HS400)) { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 975 | rc = sdhci_msm_hs400_dll_calibration(host); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 976 | spin_lock_irqsave(&host->lock, flags); |
| 977 | if (!rc) |
| 978 | msm_host->calibration_done = true; |
| 979 | spin_unlock_irqrestore(&host->lock, flags); |
| 980 | goto out; |
| 981 | } |
| 982 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 983 | spin_lock_irqsave(&host->lock, flags); |
| 984 | |
| 985 | if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) && |
| 986 | (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) { |
| 987 | tuning_block_pattern = tuning_block_128; |
| 988 | size = sizeof(tuning_block_128); |
| 989 | } |
| 990 | spin_unlock_irqrestore(&host->lock, flags); |
| 991 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 992 | data_buf = kmalloc(size, GFP_KERNEL); |
| 993 | if (!data_buf) { |
| 994 | rc = -ENOMEM; |
| 995 | goto out; |
| 996 | } |
| 997 | |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 998 | retry: |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 999 | tuned_phase_cnt = 0; |
| 1000 | |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 1001 | /* first of all reset the tuning block */ |
| 1002 | rc = msm_init_cm_dll(host); |
| 1003 | if (rc) |
| 1004 | goto kfree; |
| 1005 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1006 | phase = 0; |
| 1007 | do { |
| 1008 | struct mmc_command cmd = {0}; |
| 1009 | struct mmc_data data = {0}; |
| 1010 | struct mmc_request mrq = { |
| 1011 | .cmd = &cmd, |
| 1012 | .data = &data |
| 1013 | }; |
| 1014 | struct scatterlist sg; |
| 1015 | |
| 1016 | /* set the phase in delay line hw block */ |
| 1017 | rc = msm_config_cm_dll_phase(host, phase); |
| 1018 | if (rc) |
| 1019 | goto kfree; |
| 1020 | |
| 1021 | cmd.opcode = opcode; |
| 1022 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 1023 | |
| 1024 | data.blksz = size; |
| 1025 | data.blocks = 1; |
| 1026 | data.flags = MMC_DATA_READ; |
| 1027 | data.timeout_ns = 1000 * 1000 * 1000; /* 1 sec */ |
| 1028 | |
| 1029 | data.sg = &sg; |
| 1030 | data.sg_len = 1; |
| 1031 | sg_init_one(&sg, data_buf, size); |
| 1032 | memset(data_buf, 0, size); |
| 1033 | mmc_wait_for_req(mmc, &mrq); |
| 1034 | |
| 1035 | if (!cmd.error && !data.error && |
| 1036 | !memcmp(data_buf, tuning_block_pattern, size)) { |
| 1037 | /* tuning is successful at this tuning point */ |
| 1038 | tuned_phases[tuned_phase_cnt++] = phase; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 1039 | pr_debug("%s: %s: found *** good *** phase = %d\n", |
| 1040 | mmc_hostname(mmc), __func__, phase); |
| 1041 | } else { |
| 1042 | pr_debug("%s: %s: found ## bad ## phase = %d\n", |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1043 | mmc_hostname(mmc), __func__, phase); |
| 1044 | } |
| 1045 | } while (++phase < 16); |
| 1046 | |
Sahitya Tummala | dfdb4af | 2014-04-01 14:29:13 +0530 | [diff] [blame] | 1047 | if ((tuned_phase_cnt == NUM_TUNING_PHASES) && |
| 1048 | card && mmc_card_mmc(card)) { |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 1049 | /* |
| 1050 | * If all phases pass then its a problem. So change the card's |
| 1051 | * drive type to a different value, if supported and repeat |
| 1052 | * tuning until at least one phase fails. Then set the original |
| 1053 | * drive type back. |
| 1054 | * |
| 1055 | * If all the phases still pass after trying all possible |
| 1056 | * drive types, then one of those 16 phases will be picked. |
| 1057 | * This is no different from what was going on before the |
| 1058 | * modification to change drive type and retune. |
| 1059 | */ |
| 1060 | pr_debug("%s: tuned phases count: %d\n", mmc_hostname(mmc), |
| 1061 | tuned_phase_cnt); |
| 1062 | |
| 1063 | /* set drive type to other value . default setting is 0x0 */ |
| 1064 | while (++drv_type <= MAX_DRV_TYPES_SUPPORTED_HS200) { |
| 1065 | if (card->ext_csd.raw_driver_strength & |
| 1066 | (1 << drv_type)) { |
| 1067 | sdhci_msm_set_mmc_drv_type(host, opcode, |
| 1068 | drv_type); |
| 1069 | if (!drv_type_changed) |
| 1070 | drv_type_changed = true; |
| 1071 | goto retry; |
| 1072 | } |
| 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | /* reset drive type to default (50 ohm) if changed */ |
| 1077 | if (drv_type_changed) |
| 1078 | sdhci_msm_set_mmc_drv_type(host, opcode, 0); |
| 1079 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1080 | if (tuned_phase_cnt) { |
| 1081 | rc = msm_find_most_appropriate_phase(host, tuned_phases, |
| 1082 | tuned_phase_cnt); |
| 1083 | if (rc < 0) |
| 1084 | goto kfree; |
| 1085 | else |
| 1086 | phase = (u8)rc; |
| 1087 | |
| 1088 | /* |
| 1089 | * Finally set the selected phase in delay |
| 1090 | * line hw block. |
| 1091 | */ |
| 1092 | rc = msm_config_cm_dll_phase(host, phase); |
| 1093 | if (rc) |
| 1094 | goto kfree; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 1095 | msm_host->saved_tuning_phase = phase; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1096 | pr_debug("%s: %s: finally setting the tuning phase to %d\n", |
| 1097 | mmc_hostname(mmc), __func__, phase); |
| 1098 | } else { |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 1099 | if (--tuning_seq_cnt) |
| 1100 | goto retry; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1101 | /* tuning failed */ |
| 1102 | pr_err("%s: %s: no tuning point found\n", |
| 1103 | mmc_hostname(mmc), __func__); |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 1104 | rc = -EIO; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1105 | } |
| 1106 | |
| 1107 | kfree: |
| 1108 | kfree(data_buf); |
| 1109 | out: |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 1110 | spin_lock_irqsave(&host->lock, flags); |
| 1111 | if (!rc) |
| 1112 | msm_host->tuning_done = true; |
| 1113 | spin_unlock_irqrestore(&host->lock, flags); |
| 1114 | pr_debug("%s: Exit %s, err(%d)\n", mmc_hostname(mmc), __func__, rc); |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1115 | return rc; |
| 1116 | } |
| 1117 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1118 | static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 1119 | { |
| 1120 | struct sdhci_msm_gpio_data *curr; |
| 1121 | int i, ret = 0; |
| 1122 | |
| 1123 | curr = pdata->pin_data->gpio_data; |
| 1124 | for (i = 0; i < curr->size; i++) { |
| 1125 | if (!gpio_is_valid(curr->gpio[i].no)) { |
| 1126 | ret = -EINVAL; |
| 1127 | pr_err("%s: Invalid gpio = %d\n", __func__, |
| 1128 | curr->gpio[i].no); |
| 1129 | goto free_gpios; |
| 1130 | } |
| 1131 | if (enable) { |
| 1132 | ret = gpio_request(curr->gpio[i].no, |
| 1133 | curr->gpio[i].name); |
| 1134 | if (ret) { |
| 1135 | pr_err("%s: gpio_request(%d, %s) failed %d\n", |
| 1136 | __func__, curr->gpio[i].no, |
| 1137 | curr->gpio[i].name, ret); |
| 1138 | goto free_gpios; |
| 1139 | } |
| 1140 | curr->gpio[i].is_enabled = true; |
| 1141 | } else { |
| 1142 | gpio_free(curr->gpio[i].no); |
| 1143 | curr->gpio[i].is_enabled = false; |
| 1144 | } |
| 1145 | } |
| 1146 | return ret; |
| 1147 | |
| 1148 | free_gpios: |
| 1149 | for (i--; i >= 0; i--) { |
| 1150 | gpio_free(curr->gpio[i].no); |
| 1151 | curr->gpio[i].is_enabled = false; |
| 1152 | } |
| 1153 | return ret; |
| 1154 | } |
| 1155 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1156 | static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata, |
| 1157 | bool enable) |
| 1158 | { |
| 1159 | int ret = 0; |
| 1160 | |
| 1161 | if (enable) |
| 1162 | ret = pinctrl_select_state(pdata->pctrl_data->pctrl, |
| 1163 | pdata->pctrl_data->pins_active); |
| 1164 | else |
| 1165 | ret = pinctrl_select_state(pdata->pctrl_data->pctrl, |
| 1166 | pdata->pctrl_data->pins_sleep); |
| 1167 | |
| 1168 | if (ret < 0) |
| 1169 | pr_err("%s state for pinctrl failed with %d\n", |
| 1170 | enable ? "Enabling" : "Disabling", ret); |
| 1171 | |
| 1172 | return ret; |
| 1173 | } |
| 1174 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1175 | static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 1176 | { |
| 1177 | int ret = 0; |
| 1178 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1179 | if (pdata->pin_cfg_sts == enable) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1180 | return 0; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1181 | } else if (pdata->pctrl_data) { |
| 1182 | ret = sdhci_msm_setup_pinctrl(pdata, enable); |
| 1183 | goto out; |
| 1184 | } else if (!pdata->pin_data) { |
| 1185 | return 0; |
| 1186 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1187 | |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1188 | if (pdata->pin_data->is_gpio) |
| 1189 | ret = sdhci_msm_setup_gpio(pdata, enable); |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1190 | out: |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1191 | if (!ret) |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1192 | pdata->pin_cfg_sts = enable; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1193 | |
| 1194 | return ret; |
| 1195 | } |
| 1196 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1197 | static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name, |
| 1198 | u32 **out, int *len, u32 size) |
| 1199 | { |
| 1200 | int ret = 0; |
| 1201 | struct device_node *np = dev->of_node; |
| 1202 | size_t sz; |
| 1203 | u32 *arr = NULL; |
| 1204 | |
| 1205 | if (!of_get_property(np, prop_name, len)) { |
| 1206 | ret = -EINVAL; |
| 1207 | goto out; |
| 1208 | } |
| 1209 | sz = *len = *len / sizeof(*arr); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 1210 | if (sz <= 0 || (size > 0 && (sz > size))) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1211 | dev_err(dev, "%s invalid size\n", prop_name); |
| 1212 | ret = -EINVAL; |
| 1213 | goto out; |
| 1214 | } |
| 1215 | |
| 1216 | arr = devm_kzalloc(dev, sz * sizeof(*arr), GFP_KERNEL); |
| 1217 | if (!arr) { |
| 1218 | dev_err(dev, "%s failed allocating memory\n", prop_name); |
| 1219 | ret = -ENOMEM; |
| 1220 | goto out; |
| 1221 | } |
| 1222 | |
| 1223 | ret = of_property_read_u32_array(np, prop_name, arr, sz); |
| 1224 | if (ret < 0) { |
| 1225 | dev_err(dev, "%s failed reading array %d\n", prop_name, ret); |
| 1226 | goto out; |
| 1227 | } |
| 1228 | *out = arr; |
| 1229 | out: |
| 1230 | if (ret) |
| 1231 | *len = 0; |
| 1232 | return ret; |
| 1233 | } |
| 1234 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1235 | #define MAX_PROP_SIZE 32 |
| 1236 | static int sdhci_msm_dt_parse_vreg_info(struct device *dev, |
| 1237 | struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) |
| 1238 | { |
| 1239 | int len, ret = 0; |
| 1240 | const __be32 *prop; |
| 1241 | char prop_name[MAX_PROP_SIZE]; |
| 1242 | struct sdhci_msm_reg_data *vreg; |
| 1243 | struct device_node *np = dev->of_node; |
| 1244 | |
| 1245 | snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); |
| 1246 | if (!of_parse_phandle(np, prop_name, 0)) { |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1247 | dev_info(dev, "No vreg data found for %s\n", vreg_name); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1248 | return ret; |
| 1249 | } |
| 1250 | |
| 1251 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
| 1252 | if (!vreg) { |
| 1253 | dev_err(dev, "No memory for vreg: %s\n", vreg_name); |
| 1254 | ret = -ENOMEM; |
| 1255 | return ret; |
| 1256 | } |
| 1257 | |
| 1258 | vreg->name = vreg_name; |
| 1259 | |
| 1260 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1261 | "qcom,%s-always-on", vreg_name); |
| 1262 | if (of_get_property(np, prop_name, NULL)) |
| 1263 | vreg->is_always_on = true; |
| 1264 | |
| 1265 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1266 | "qcom,%s-lpm-sup", vreg_name); |
| 1267 | if (of_get_property(np, prop_name, NULL)) |
| 1268 | vreg->lpm_sup = true; |
| 1269 | |
| 1270 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1271 | "qcom,%s-voltage-level", vreg_name); |
| 1272 | prop = of_get_property(np, prop_name, &len); |
| 1273 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 1274 | dev_warn(dev, "%s %s property\n", |
| 1275 | prop ? "invalid format" : "no", prop_name); |
| 1276 | } else { |
| 1277 | vreg->low_vol_level = be32_to_cpup(&prop[0]); |
| 1278 | vreg->high_vol_level = be32_to_cpup(&prop[1]); |
| 1279 | } |
| 1280 | |
| 1281 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1282 | "qcom,%s-current-level", vreg_name); |
| 1283 | prop = of_get_property(np, prop_name, &len); |
| 1284 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 1285 | dev_warn(dev, "%s %s property\n", |
| 1286 | prop ? "invalid format" : "no", prop_name); |
| 1287 | } else { |
| 1288 | vreg->lpm_uA = be32_to_cpup(&prop[0]); |
| 1289 | vreg->hpm_uA = be32_to_cpup(&prop[1]); |
| 1290 | } |
| 1291 | |
| 1292 | *vreg_data = vreg; |
| 1293 | dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n", |
| 1294 | vreg->name, vreg->is_always_on ? "always_on," : "", |
| 1295 | vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level, |
| 1296 | vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA); |
| 1297 | |
| 1298 | return ret; |
| 1299 | } |
| 1300 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1301 | static int sdhci_msm_parse_pinctrl_info(struct device *dev, |
| 1302 | struct sdhci_msm_pltfm_data *pdata) |
| 1303 | { |
| 1304 | struct sdhci_pinctrl_data *pctrl_data; |
| 1305 | struct pinctrl *pctrl; |
| 1306 | int ret = 0; |
| 1307 | |
| 1308 | /* Try to obtain pinctrl handle */ |
| 1309 | pctrl = devm_pinctrl_get(dev); |
| 1310 | if (IS_ERR(pctrl)) { |
| 1311 | ret = PTR_ERR(pctrl); |
| 1312 | goto out; |
| 1313 | } |
| 1314 | pctrl_data = devm_kzalloc(dev, sizeof(*pctrl_data), GFP_KERNEL); |
| 1315 | if (!pctrl_data) { |
| 1316 | dev_err(dev, "No memory for sdhci_pinctrl_data\n"); |
| 1317 | ret = -ENOMEM; |
| 1318 | goto out; |
| 1319 | } |
| 1320 | pctrl_data->pctrl = pctrl; |
| 1321 | /* Look-up and keep the states handy to be used later */ |
| 1322 | pctrl_data->pins_active = pinctrl_lookup_state( |
| 1323 | pctrl_data->pctrl, "active"); |
| 1324 | if (IS_ERR(pctrl_data->pins_active)) { |
| 1325 | ret = PTR_ERR(pctrl_data->pins_active); |
| 1326 | dev_err(dev, "Could not get active pinstates, err:%d\n", ret); |
| 1327 | goto out; |
| 1328 | } |
| 1329 | pctrl_data->pins_sleep = pinctrl_lookup_state( |
| 1330 | pctrl_data->pctrl, "sleep"); |
| 1331 | if (IS_ERR(pctrl_data->pins_sleep)) { |
| 1332 | ret = PTR_ERR(pctrl_data->pins_sleep); |
| 1333 | dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret); |
| 1334 | goto out; |
| 1335 | } |
| 1336 | pdata->pctrl_data = pctrl_data; |
| 1337 | out: |
| 1338 | return ret; |
| 1339 | } |
| 1340 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1341 | #define GPIO_NAME_MAX_LEN 32 |
| 1342 | static int sdhci_msm_dt_parse_gpio_info(struct device *dev, |
| 1343 | struct sdhci_msm_pltfm_data *pdata) |
| 1344 | { |
| 1345 | int ret = 0, cnt, i; |
| 1346 | struct sdhci_msm_pin_data *pin_data; |
| 1347 | struct device_node *np = dev->of_node; |
| 1348 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1349 | ret = sdhci_msm_parse_pinctrl_info(dev, pdata); |
| 1350 | if (!ret) { |
| 1351 | goto out; |
| 1352 | } else if (ret == -EPROBE_DEFER) { |
| 1353 | dev_err(dev, "Pinctrl framework not registered, err:%d\n", ret); |
| 1354 | goto out; |
| 1355 | } else { |
| 1356 | dev_err(dev, "Parsing Pinctrl failed with %d, falling back on GPIO lib\n", |
| 1357 | ret); |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1358 | ret = 0; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1359 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1360 | pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL); |
| 1361 | if (!pin_data) { |
| 1362 | dev_err(dev, "No memory for pin_data\n"); |
| 1363 | ret = -ENOMEM; |
| 1364 | goto out; |
| 1365 | } |
| 1366 | |
| 1367 | cnt = of_gpio_count(np); |
| 1368 | if (cnt > 0) { |
| 1369 | pin_data->gpio_data = devm_kzalloc(dev, |
| 1370 | sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL); |
| 1371 | if (!pin_data->gpio_data) { |
| 1372 | dev_err(dev, "No memory for gpio_data\n"); |
| 1373 | ret = -ENOMEM; |
| 1374 | goto out; |
| 1375 | } |
| 1376 | pin_data->gpio_data->size = cnt; |
| 1377 | pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt * |
| 1378 | sizeof(struct sdhci_msm_gpio), GFP_KERNEL); |
| 1379 | |
| 1380 | if (!pin_data->gpio_data->gpio) { |
| 1381 | dev_err(dev, "No memory for gpio\n"); |
| 1382 | ret = -ENOMEM; |
| 1383 | goto out; |
| 1384 | } |
| 1385 | |
| 1386 | for (i = 0; i < cnt; i++) { |
| 1387 | const char *name = NULL; |
| 1388 | char result[GPIO_NAME_MAX_LEN]; |
| 1389 | pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i); |
| 1390 | of_property_read_string_index(np, |
| 1391 | "qcom,gpio-names", i, &name); |
| 1392 | |
| 1393 | snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s", |
| 1394 | dev_name(dev), name ? name : "?"); |
| 1395 | pin_data->gpio_data->gpio[i].name = result; |
| 1396 | dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__, |
| 1397 | pin_data->gpio_data->gpio[i].name, |
| 1398 | pin_data->gpio_data->gpio[i].no); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1399 | } |
| 1400 | } |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1401 | pdata->pin_data = pin_data; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1402 | out: |
| 1403 | if (ret) |
| 1404 | dev_err(dev, "%s failed with err %d\n", __func__, ret); |
| 1405 | return ret; |
| 1406 | } |
| 1407 | |
Maya Erez | 994cf2f | 2014-10-21 20:22:04 +0300 | [diff] [blame^] | 1408 | #ifdef CONFIG_SMP |
| 1409 | static void sdhci_msm_populate_affinity_type(struct sdhci_msm_pltfm_data *pdata, |
| 1410 | struct device_node *np) |
| 1411 | { |
| 1412 | const char *cpu_affinity = NULL; |
| 1413 | |
| 1414 | pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_IRQ; |
| 1415 | if (!of_property_read_string(np, "qcom,cpu-affinity", |
| 1416 | &cpu_affinity)) { |
| 1417 | if (!strcmp(cpu_affinity, "all_cores")) |
| 1418 | pdata->cpu_affinity_type = PM_QOS_REQ_ALL_CORES; |
| 1419 | else if (!strcmp(cpu_affinity, "affine_cores")) |
| 1420 | pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_CORES; |
| 1421 | else if (!strcmp(cpu_affinity, "affine_irq")) |
| 1422 | pdata->cpu_affinity_type = PM_QOS_REQ_AFFINE_IRQ; |
| 1423 | } |
| 1424 | } |
| 1425 | #else |
| 1426 | static void sdhci_msm_populate_affinity_type(struct sdhci_msm_pltfm_data *pdata, |
| 1427 | struct device_node *np) |
| 1428 | { |
| 1429 | } |
| 1430 | #endif |
| 1431 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1432 | /* Parse platform data */ |
| 1433 | static struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev) |
| 1434 | { |
| 1435 | struct sdhci_msm_pltfm_data *pdata = NULL; |
| 1436 | struct device_node *np = dev->of_node; |
| 1437 | u32 bus_width = 0; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 1438 | u32 cpu_dma_latency; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1439 | int len, i; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1440 | int clk_table_len; |
| 1441 | u32 *clk_table = NULL; |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 1442 | enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1443 | |
| 1444 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 1445 | if (!pdata) { |
| 1446 | dev_err(dev, "failed to allocate memory for platform data\n"); |
| 1447 | goto out; |
| 1448 | } |
| 1449 | |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 1450 | pdata->status_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags); |
| 1451 | if (gpio_is_valid(pdata->status_gpio) & !(flags & OF_GPIO_ACTIVE_LOW)) |
| 1452 | pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 1453 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1454 | of_property_read_u32(np, "qcom,bus-width", &bus_width); |
| 1455 | if (bus_width == 8) |
| 1456 | pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA; |
| 1457 | else if (bus_width == 4) |
| 1458 | pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA; |
| 1459 | else { |
| 1460 | dev_notice(dev, "invalid bus-width, default to 1-bit mode\n"); |
| 1461 | pdata->mmc_bus_width = 0; |
| 1462 | } |
| 1463 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 1464 | if (!of_property_read_u32(np, "qcom,cpu-dma-latency-us", |
| 1465 | &cpu_dma_latency)) |
| 1466 | pdata->cpu_dma_latency_us = cpu_dma_latency; |
Asutosh Das | 598a4d4 | 2014-02-05 16:38:23 +0530 | [diff] [blame] | 1467 | else |
| 1468 | pdata->cpu_dma_latency_us = MSM_MMC_DEFAULT_CPU_DMA_LATENCY; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1469 | if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates", |
| 1470 | &clk_table, &clk_table_len, 0)) { |
| 1471 | dev_err(dev, "failed parsing supported clock rates\n"); |
| 1472 | goto out; |
| 1473 | } |
| 1474 | if (!clk_table || !clk_table_len) { |
| 1475 | dev_err(dev, "Invalid clock table\n"); |
| 1476 | goto out; |
| 1477 | } |
| 1478 | pdata->sup_clk_table = clk_table; |
| 1479 | pdata->sup_clk_cnt = clk_table_len; |
| 1480 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1481 | pdata->vreg_data = devm_kzalloc(dev, sizeof(struct |
| 1482 | sdhci_msm_slot_reg_data), |
| 1483 | GFP_KERNEL); |
| 1484 | if (!pdata->vreg_data) { |
| 1485 | dev_err(dev, "failed to allocate memory for vreg data\n"); |
| 1486 | goto out; |
| 1487 | } |
| 1488 | |
| 1489 | if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data, |
| 1490 | "vdd")) { |
| 1491 | dev_err(dev, "failed parsing vdd data\n"); |
| 1492 | goto out; |
| 1493 | } |
| 1494 | if (sdhci_msm_dt_parse_vreg_info(dev, |
| 1495 | &pdata->vreg_data->vdd_io_data, |
| 1496 | "vdd-io")) { |
| 1497 | dev_err(dev, "failed parsing vdd-io data\n"); |
| 1498 | goto out; |
| 1499 | } |
| 1500 | |
| 1501 | if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) { |
| 1502 | dev_err(dev, "failed parsing gpio data\n"); |
| 1503 | goto out; |
| 1504 | } |
| 1505 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1506 | len = of_property_count_strings(np, "qcom,bus-speed-mode"); |
| 1507 | |
| 1508 | for (i = 0; i < len; i++) { |
| 1509 | const char *name = NULL; |
| 1510 | |
| 1511 | of_property_read_string_index(np, |
| 1512 | "qcom,bus-speed-mode", i, &name); |
| 1513 | if (!name) |
| 1514 | continue; |
| 1515 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 1516 | if (!strncmp(name, "HS400_1p8v", sizeof("HS400_1p8v"))) |
| 1517 | pdata->caps2 |= MMC_CAP2_HS400_1_8V; |
| 1518 | else if (!strncmp(name, "HS400_1p2v", sizeof("HS400_1p2v"))) |
| 1519 | pdata->caps2 |= MMC_CAP2_HS400_1_2V; |
| 1520 | else if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v"))) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1521 | pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; |
| 1522 | else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v"))) |
| 1523 | pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; |
| 1524 | else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v"))) |
| 1525 | pdata->caps |= MMC_CAP_1_8V_DDR |
| 1526 | | MMC_CAP_UHS_DDR50; |
| 1527 | else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v"))) |
| 1528 | pdata->caps |= MMC_CAP_1_2V_DDR |
| 1529 | | MMC_CAP_UHS_DDR50; |
| 1530 | } |
| 1531 | |
| 1532 | if (of_get_property(np, "qcom,nonremovable", NULL)) |
| 1533 | pdata->nonremovable = true; |
| 1534 | |
Guoping Yu | f7c9133 | 2014-08-20 16:56:18 +0800 | [diff] [blame] | 1535 | if (of_get_property(np, "qcom,nonhotplug", NULL)) |
| 1536 | pdata->nonhotplug = true; |
| 1537 | |
Maya Erez | 994cf2f | 2014-10-21 20:22:04 +0300 | [diff] [blame^] | 1538 | sdhci_msm_populate_affinity_type(pdata, np); |
| 1539 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1540 | return pdata; |
| 1541 | out: |
| 1542 | return NULL; |
| 1543 | } |
| 1544 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1545 | /* Returns required bandwidth in Bytes per Sec */ |
| 1546 | static unsigned int sdhci_get_bw_required(struct sdhci_host *host, |
| 1547 | struct mmc_ios *ios) |
| 1548 | { |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1549 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1550 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1551 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1552 | unsigned int bw; |
| 1553 | |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1554 | bw = msm_host->clk_rate; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1555 | /* |
| 1556 | * For DDR mode, SDCC controller clock will be at |
| 1557 | * the double rate than the actual clock that goes to card. |
| 1558 | */ |
| 1559 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1560 | bw /= 2; |
| 1561 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1562 | bw /= 8; |
| 1563 | |
| 1564 | return bw; |
| 1565 | } |
| 1566 | |
| 1567 | static int sdhci_msm_bus_get_vote_for_bw(struct sdhci_msm_host *host, |
| 1568 | unsigned int bw) |
| 1569 | { |
| 1570 | unsigned int *table = host->pdata->voting_data->bw_vecs; |
| 1571 | unsigned int size = host->pdata->voting_data->bw_vecs_size; |
| 1572 | int i; |
| 1573 | |
| 1574 | if (host->msm_bus_vote.is_max_bw_needed && bw) |
| 1575 | return host->msm_bus_vote.max_bw_vote; |
| 1576 | |
| 1577 | for (i = 0; i < size; i++) { |
| 1578 | if (bw <= table[i]) |
| 1579 | break; |
| 1580 | } |
| 1581 | |
| 1582 | if (i && (i == size)) |
| 1583 | i--; |
| 1584 | |
| 1585 | return i; |
| 1586 | } |
| 1587 | |
| 1588 | /* |
| 1589 | * This function must be called with host lock acquired. |
| 1590 | * Caller of this function should also ensure that msm bus client |
| 1591 | * handle is not null. |
| 1592 | */ |
| 1593 | static inline int sdhci_msm_bus_set_vote(struct sdhci_msm_host *msm_host, |
| 1594 | int vote, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1595 | unsigned long *flags) |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1596 | { |
| 1597 | struct sdhci_host *host = platform_get_drvdata(msm_host->pdev); |
| 1598 | int rc = 0; |
| 1599 | |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1600 | BUG_ON(!flags); |
| 1601 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1602 | if (vote != msm_host->msm_bus_vote.curr_vote) { |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1603 | spin_unlock_irqrestore(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1604 | rc = msm_bus_scale_client_update_request( |
| 1605 | msm_host->msm_bus_vote.client_handle, vote); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1606 | spin_lock_irqsave(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1607 | if (rc) { |
| 1608 | pr_err("%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n", |
| 1609 | mmc_hostname(host->mmc), |
| 1610 | msm_host->msm_bus_vote.client_handle, vote, rc); |
| 1611 | goto out; |
| 1612 | } |
| 1613 | msm_host->msm_bus_vote.curr_vote = vote; |
| 1614 | } |
| 1615 | out: |
| 1616 | return rc; |
| 1617 | } |
| 1618 | |
| 1619 | /* |
| 1620 | * Internal work. Work to set 0 bandwidth for msm bus. |
| 1621 | */ |
| 1622 | static void sdhci_msm_bus_work(struct work_struct *work) |
| 1623 | { |
| 1624 | struct sdhci_msm_host *msm_host; |
| 1625 | struct sdhci_host *host; |
| 1626 | unsigned long flags; |
| 1627 | |
| 1628 | msm_host = container_of(work, struct sdhci_msm_host, |
| 1629 | msm_bus_vote.vote_work.work); |
| 1630 | host = platform_get_drvdata(msm_host->pdev); |
| 1631 | |
| 1632 | if (!msm_host->msm_bus_vote.client_handle) |
| 1633 | return; |
| 1634 | |
| 1635 | spin_lock_irqsave(&host->lock, flags); |
| 1636 | /* don't vote for 0 bandwidth if any request is in progress */ |
| 1637 | if (!host->mrq) { |
| 1638 | sdhci_msm_bus_set_vote(msm_host, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1639 | msm_host->msm_bus_vote.min_bw_vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1640 | } else |
| 1641 | pr_warning("%s: %s: Transfer in progress. skipping bus voting to 0 bandwidth\n", |
| 1642 | mmc_hostname(host->mmc), __func__); |
| 1643 | spin_unlock_irqrestore(&host->lock, flags); |
| 1644 | } |
| 1645 | |
| 1646 | /* |
| 1647 | * This function cancels any scheduled delayed work and sets the bus |
| 1648 | * vote based on bw (bandwidth) argument. |
| 1649 | */ |
| 1650 | static void sdhci_msm_bus_cancel_work_and_set_vote(struct sdhci_host *host, |
| 1651 | unsigned int bw) |
| 1652 | { |
| 1653 | int vote; |
| 1654 | unsigned long flags; |
| 1655 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1656 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1657 | |
| 1658 | cancel_delayed_work_sync(&msm_host->msm_bus_vote.vote_work); |
| 1659 | spin_lock_irqsave(&host->lock, flags); |
| 1660 | vote = sdhci_msm_bus_get_vote_for_bw(msm_host, bw); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1661 | sdhci_msm_bus_set_vote(msm_host, vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1662 | spin_unlock_irqrestore(&host->lock, flags); |
| 1663 | } |
| 1664 | |
| 1665 | #define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */ |
| 1666 | |
| 1667 | /* This function queues a work which will set the bandwidth requiement to 0 */ |
| 1668 | static void sdhci_msm_bus_queue_work(struct sdhci_host *host) |
| 1669 | { |
| 1670 | unsigned long flags; |
| 1671 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1672 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1673 | |
| 1674 | spin_lock_irqsave(&host->lock, flags); |
| 1675 | if (msm_host->msm_bus_vote.min_bw_vote != |
| 1676 | msm_host->msm_bus_vote.curr_vote) |
| 1677 | queue_delayed_work(system_wq, |
| 1678 | &msm_host->msm_bus_vote.vote_work, |
| 1679 | msecs_to_jiffies(MSM_MMC_BUS_VOTING_DELAY)); |
| 1680 | spin_unlock_irqrestore(&host->lock, flags); |
| 1681 | } |
| 1682 | |
| 1683 | static int sdhci_msm_bus_register(struct sdhci_msm_host *host, |
| 1684 | struct platform_device *pdev) |
| 1685 | { |
| 1686 | int rc = 0; |
| 1687 | struct msm_bus_scale_pdata *bus_pdata; |
| 1688 | |
| 1689 | struct sdhci_msm_bus_voting_data *data; |
| 1690 | struct device *dev = &pdev->dev; |
| 1691 | |
| 1692 | data = devm_kzalloc(dev, |
| 1693 | sizeof(struct sdhci_msm_bus_voting_data), GFP_KERNEL); |
| 1694 | if (!data) { |
| 1695 | dev_err(&pdev->dev, |
| 1696 | "%s: failed to allocate memory\n", __func__); |
| 1697 | rc = -ENOMEM; |
| 1698 | goto out; |
| 1699 | } |
| 1700 | data->bus_pdata = msm_bus_cl_get_pdata(pdev); |
| 1701 | if (data->bus_pdata) { |
| 1702 | rc = sdhci_msm_dt_get_array(dev, "qcom,bus-bw-vectors-bps", |
| 1703 | &data->bw_vecs, &data->bw_vecs_size, 0); |
| 1704 | if (rc) { |
| 1705 | dev_err(&pdev->dev, |
| 1706 | "%s: Failed to get bus-bw-vectors-bps\n", |
| 1707 | __func__); |
| 1708 | goto out; |
| 1709 | } |
| 1710 | host->pdata->voting_data = data; |
| 1711 | } |
| 1712 | if (host->pdata->voting_data && |
| 1713 | host->pdata->voting_data->bus_pdata && |
| 1714 | host->pdata->voting_data->bw_vecs && |
| 1715 | host->pdata->voting_data->bw_vecs_size) { |
| 1716 | |
| 1717 | bus_pdata = host->pdata->voting_data->bus_pdata; |
| 1718 | host->msm_bus_vote.client_handle = |
| 1719 | msm_bus_scale_register_client(bus_pdata); |
| 1720 | if (!host->msm_bus_vote.client_handle) { |
| 1721 | dev_err(&pdev->dev, "msm_bus_scale_register_client()\n"); |
| 1722 | rc = -EFAULT; |
| 1723 | goto out; |
| 1724 | } |
| 1725 | /* cache the vote index for minimum and maximum bandwidth */ |
| 1726 | host->msm_bus_vote.min_bw_vote = |
| 1727 | sdhci_msm_bus_get_vote_for_bw(host, 0); |
| 1728 | host->msm_bus_vote.max_bw_vote = |
| 1729 | sdhci_msm_bus_get_vote_for_bw(host, UINT_MAX); |
| 1730 | } else { |
| 1731 | devm_kfree(dev, data); |
| 1732 | } |
| 1733 | |
| 1734 | out: |
| 1735 | return rc; |
| 1736 | } |
| 1737 | |
| 1738 | static void sdhci_msm_bus_unregister(struct sdhci_msm_host *host) |
| 1739 | { |
| 1740 | if (host->msm_bus_vote.client_handle) |
| 1741 | msm_bus_scale_unregister_client( |
| 1742 | host->msm_bus_vote.client_handle); |
| 1743 | } |
| 1744 | |
| 1745 | static void sdhci_msm_bus_voting(struct sdhci_host *host, u32 enable) |
| 1746 | { |
| 1747 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1748 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1749 | struct mmc_ios *ios = &host->mmc->ios; |
| 1750 | unsigned int bw; |
| 1751 | |
| 1752 | if (!msm_host->msm_bus_vote.client_handle) |
| 1753 | return; |
| 1754 | |
| 1755 | bw = sdhci_get_bw_required(host, ios); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1756 | if (enable) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1757 | sdhci_msm_bus_cancel_work_and_set_vote(host, bw); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1758 | } else { |
| 1759 | /* |
| 1760 | * If clock gating is enabled, then remove the vote |
| 1761 | * immediately because clocks will be disabled only |
| 1762 | * after SDHCI_MSM_MMC_CLK_GATE_DELAY and thus no |
| 1763 | * additional delay is required to remove the bus vote. |
| 1764 | */ |
| 1765 | #ifdef CONFIG_MMC_CLKGATE |
| 1766 | if (host->mmc->clkgate_delay) |
| 1767 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 1768 | else |
| 1769 | #endif |
| 1770 | sdhci_msm_bus_queue_work(host); |
| 1771 | } |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1772 | } |
| 1773 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1774 | /* Regulator utility functions */ |
| 1775 | static int sdhci_msm_vreg_init_reg(struct device *dev, |
| 1776 | struct sdhci_msm_reg_data *vreg) |
| 1777 | { |
| 1778 | int ret = 0; |
| 1779 | |
| 1780 | /* check if regulator is already initialized? */ |
| 1781 | if (vreg->reg) |
| 1782 | goto out; |
| 1783 | |
| 1784 | /* Get the regulator handle */ |
| 1785 | vreg->reg = devm_regulator_get(dev, vreg->name); |
| 1786 | if (IS_ERR(vreg->reg)) { |
| 1787 | ret = PTR_ERR(vreg->reg); |
| 1788 | pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n", |
| 1789 | __func__, vreg->name, ret); |
| 1790 | goto out; |
| 1791 | } |
| 1792 | |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1793 | if (regulator_count_voltages(vreg->reg) > 0) { |
| 1794 | vreg->set_voltage_sup = true; |
| 1795 | /* sanity check */ |
| 1796 | if (!vreg->high_vol_level || !vreg->hpm_uA) { |
| 1797 | pr_err("%s: %s invalid constraints specified\n", |
| 1798 | __func__, vreg->name); |
| 1799 | ret = -EINVAL; |
| 1800 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1801 | } |
| 1802 | |
| 1803 | out: |
| 1804 | return ret; |
| 1805 | } |
| 1806 | |
| 1807 | static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg) |
| 1808 | { |
| 1809 | if (vreg->reg) |
| 1810 | devm_regulator_put(vreg->reg); |
| 1811 | } |
| 1812 | |
| 1813 | static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data |
| 1814 | *vreg, int uA_load) |
| 1815 | { |
| 1816 | int ret = 0; |
| 1817 | |
| 1818 | /* |
| 1819 | * regulators that do not support regulator_set_voltage also |
| 1820 | * do not support regulator_set_optimum_mode |
| 1821 | */ |
| 1822 | if (vreg->set_voltage_sup) { |
| 1823 | ret = regulator_set_load(vreg->reg, uA_load); |
| 1824 | if (ret < 0) |
| 1825 | pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n", |
| 1826 | __func__, vreg->name, uA_load, ret); |
| 1827 | else |
| 1828 | /* |
| 1829 | * regulator_set_load() can return non zero |
| 1830 | * value even for success case. |
| 1831 | */ |
| 1832 | ret = 0; |
| 1833 | } |
| 1834 | return ret; |
| 1835 | } |
| 1836 | |
| 1837 | static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg, |
| 1838 | int min_uV, int max_uV) |
| 1839 | { |
| 1840 | int ret = 0; |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1841 | if (vreg->set_voltage_sup) { |
| 1842 | ret = regulator_set_voltage(vreg->reg, min_uV, max_uV); |
| 1843 | if (ret) { |
| 1844 | pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n", |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1845 | __func__, vreg->name, min_uV, max_uV, ret); |
| 1846 | } |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1847 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1848 | |
| 1849 | return ret; |
| 1850 | } |
| 1851 | |
| 1852 | static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg) |
| 1853 | { |
| 1854 | int ret = 0; |
| 1855 | |
| 1856 | /* Put regulator in HPM (high power mode) */ |
| 1857 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA); |
| 1858 | if (ret < 0) |
| 1859 | return ret; |
| 1860 | |
| 1861 | if (!vreg->is_enabled) { |
| 1862 | /* Set voltage level */ |
| 1863 | ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level, |
| 1864 | vreg->high_vol_level); |
| 1865 | if (ret) |
| 1866 | return ret; |
| 1867 | } |
| 1868 | ret = regulator_enable(vreg->reg); |
| 1869 | if (ret) { |
| 1870 | pr_err("%s: regulator_enable(%s) failed. ret=%d\n", |
| 1871 | __func__, vreg->name, ret); |
| 1872 | return ret; |
| 1873 | } |
| 1874 | vreg->is_enabled = true; |
| 1875 | return ret; |
| 1876 | } |
| 1877 | |
| 1878 | static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg) |
| 1879 | { |
| 1880 | int ret = 0; |
| 1881 | |
| 1882 | /* Never disable regulator marked as always_on */ |
| 1883 | if (vreg->is_enabled && !vreg->is_always_on) { |
| 1884 | ret = regulator_disable(vreg->reg); |
| 1885 | if (ret) { |
| 1886 | pr_err("%s: regulator_disable(%s) failed. ret=%d\n", |
| 1887 | __func__, vreg->name, ret); |
| 1888 | goto out; |
| 1889 | } |
| 1890 | vreg->is_enabled = false; |
| 1891 | |
| 1892 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0); |
| 1893 | if (ret < 0) |
| 1894 | goto out; |
| 1895 | |
| 1896 | /* Set min. voltage level to 0 */ |
| 1897 | ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level); |
| 1898 | if (ret) |
| 1899 | goto out; |
| 1900 | } else if (vreg->is_enabled && vreg->is_always_on) { |
| 1901 | if (vreg->lpm_sup) { |
| 1902 | /* Put always_on regulator in LPM (low power mode) */ |
| 1903 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, |
| 1904 | vreg->lpm_uA); |
| 1905 | if (ret < 0) |
| 1906 | goto out; |
| 1907 | } |
| 1908 | } |
| 1909 | out: |
| 1910 | return ret; |
| 1911 | } |
| 1912 | |
| 1913 | static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata, |
| 1914 | bool enable, bool is_init) |
| 1915 | { |
| 1916 | int ret = 0, i; |
| 1917 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1918 | struct sdhci_msm_reg_data *vreg_table[2]; |
| 1919 | |
| 1920 | curr_slot = pdata->vreg_data; |
| 1921 | if (!curr_slot) { |
| 1922 | pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n", |
| 1923 | __func__); |
| 1924 | goto out; |
| 1925 | } |
| 1926 | |
| 1927 | vreg_table[0] = curr_slot->vdd_data; |
| 1928 | vreg_table[1] = curr_slot->vdd_io_data; |
| 1929 | |
| 1930 | for (i = 0; i < ARRAY_SIZE(vreg_table); i++) { |
| 1931 | if (vreg_table[i]) { |
| 1932 | if (enable) |
| 1933 | ret = sdhci_msm_vreg_enable(vreg_table[i]); |
| 1934 | else |
| 1935 | ret = sdhci_msm_vreg_disable(vreg_table[i]); |
| 1936 | if (ret) |
| 1937 | goto out; |
| 1938 | } |
| 1939 | } |
| 1940 | out: |
| 1941 | return ret; |
| 1942 | } |
| 1943 | |
| 1944 | /* |
| 1945 | * Reset vreg by ensuring it is off during probe. A call |
| 1946 | * to enable vreg is needed to balance disable vreg |
| 1947 | */ |
| 1948 | static int sdhci_msm_vreg_reset(struct sdhci_msm_pltfm_data *pdata) |
| 1949 | { |
| 1950 | int ret; |
| 1951 | |
| 1952 | ret = sdhci_msm_setup_vreg(pdata, 1, true); |
| 1953 | if (ret) |
| 1954 | return ret; |
| 1955 | ret = sdhci_msm_setup_vreg(pdata, 0, true); |
| 1956 | return ret; |
| 1957 | } |
| 1958 | |
| 1959 | /* This init function should be called only once for each SDHC slot */ |
| 1960 | static int sdhci_msm_vreg_init(struct device *dev, |
| 1961 | struct sdhci_msm_pltfm_data *pdata, |
| 1962 | bool is_init) |
| 1963 | { |
| 1964 | int ret = 0; |
| 1965 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1966 | struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg; |
| 1967 | |
| 1968 | curr_slot = pdata->vreg_data; |
| 1969 | if (!curr_slot) |
| 1970 | goto out; |
| 1971 | |
| 1972 | curr_vdd_reg = curr_slot->vdd_data; |
| 1973 | curr_vdd_io_reg = curr_slot->vdd_io_data; |
| 1974 | |
| 1975 | if (!is_init) |
| 1976 | /* Deregister all regulators from regulator framework */ |
| 1977 | goto vdd_io_reg_deinit; |
| 1978 | |
| 1979 | /* |
| 1980 | * Get the regulator handle from voltage regulator framework |
| 1981 | * and then try to set the voltage level for the regulator |
| 1982 | */ |
| 1983 | if (curr_vdd_reg) { |
| 1984 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg); |
| 1985 | if (ret) |
| 1986 | goto out; |
| 1987 | } |
| 1988 | if (curr_vdd_io_reg) { |
| 1989 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg); |
| 1990 | if (ret) |
| 1991 | goto vdd_reg_deinit; |
| 1992 | } |
| 1993 | ret = sdhci_msm_vreg_reset(pdata); |
| 1994 | if (ret) |
| 1995 | dev_err(dev, "vreg reset failed (%d)\n", ret); |
| 1996 | goto out; |
| 1997 | |
| 1998 | vdd_io_reg_deinit: |
| 1999 | if (curr_vdd_io_reg) |
| 2000 | sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg); |
| 2001 | vdd_reg_deinit: |
| 2002 | if (curr_vdd_reg) |
| 2003 | sdhci_msm_vreg_deinit_reg(curr_vdd_reg); |
| 2004 | out: |
| 2005 | return ret; |
| 2006 | } |
| 2007 | |
| 2008 | |
| 2009 | static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata, |
| 2010 | enum vdd_io_level level, |
| 2011 | unsigned int voltage_level) |
| 2012 | { |
| 2013 | int ret = 0; |
| 2014 | int set_level; |
| 2015 | struct sdhci_msm_reg_data *vdd_io_reg; |
| 2016 | |
| 2017 | if (!pdata->vreg_data) |
| 2018 | return ret; |
| 2019 | |
| 2020 | vdd_io_reg = pdata->vreg_data->vdd_io_data; |
| 2021 | if (vdd_io_reg && vdd_io_reg->is_enabled) { |
| 2022 | switch (level) { |
| 2023 | case VDD_IO_LOW: |
| 2024 | set_level = vdd_io_reg->low_vol_level; |
| 2025 | break; |
| 2026 | case VDD_IO_HIGH: |
| 2027 | set_level = vdd_io_reg->high_vol_level; |
| 2028 | break; |
| 2029 | case VDD_IO_SET_LEVEL: |
| 2030 | set_level = voltage_level; |
| 2031 | break; |
| 2032 | default: |
| 2033 | pr_err("%s: invalid argument level = %d", |
| 2034 | __func__, level); |
| 2035 | ret = -EINVAL; |
| 2036 | return ret; |
| 2037 | } |
| 2038 | ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level, |
| 2039 | set_level); |
| 2040 | } |
| 2041 | return ret; |
| 2042 | } |
| 2043 | |
| 2044 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) |
| 2045 | { |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2046 | struct sdhci_host *host = (struct sdhci_host *)data; |
| 2047 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2048 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2049 | u8 irq_status = 0; |
| 2050 | u8 irq_ack = 0; |
| 2051 | int ret = 0; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2052 | int pwr_state = 0, io_level = 0; |
| 2053 | unsigned long flags; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2054 | |
| 2055 | irq_status = readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 2056 | pr_debug("%s: Received IRQ(%d), status=0x%x\n", |
| 2057 | mmc_hostname(msm_host->mmc), irq, irq_status); |
| 2058 | |
| 2059 | /* Clear the interrupt */ |
| 2060 | writeb_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 2061 | /* |
| 2062 | * SDHC has core_mem and hc_mem device memory and these memory |
| 2063 | * addresses do not fall within 1KB region. Hence, any update to |
| 2064 | * core_mem address space would require an mb() to ensure this gets |
| 2065 | * completed before its next update to registers within hc_mem. |
| 2066 | */ |
| 2067 | mb(); |
| 2068 | |
| 2069 | /* Handle BUS ON/OFF*/ |
| 2070 | if (irq_status & CORE_PWRCTL_BUS_ON) { |
| 2071 | ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2072 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2073 | ret = sdhci_msm_setup_pins(msm_host->pdata, true); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2074 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 2075 | VDD_IO_HIGH, 0); |
| 2076 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2077 | if (ret) |
| 2078 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 2079 | else |
| 2080 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2081 | |
| 2082 | pwr_state = REQ_BUS_ON; |
| 2083 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2084 | } |
| 2085 | if (irq_status & CORE_PWRCTL_BUS_OFF) { |
| 2086 | ret = sdhci_msm_setup_vreg(msm_host->pdata, false, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2087 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2088 | ret = sdhci_msm_setup_pins(msm_host->pdata, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2089 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 2090 | VDD_IO_LOW, 0); |
| 2091 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2092 | if (ret) |
| 2093 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 2094 | else |
| 2095 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2096 | |
| 2097 | pwr_state = REQ_BUS_OFF; |
| 2098 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2099 | } |
| 2100 | /* Handle IO LOW/HIGH */ |
| 2101 | if (irq_status & CORE_PWRCTL_IO_LOW) { |
| 2102 | /* Switch voltage Low */ |
| 2103 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); |
| 2104 | if (ret) |
| 2105 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 2106 | else |
| 2107 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2108 | |
| 2109 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2110 | } |
| 2111 | if (irq_status & CORE_PWRCTL_IO_HIGH) { |
| 2112 | /* Switch voltage High */ |
| 2113 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); |
| 2114 | if (ret) |
| 2115 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 2116 | else |
| 2117 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2118 | |
| 2119 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2120 | } |
| 2121 | |
| 2122 | /* ACK status to the core */ |
| 2123 | writeb_relaxed(irq_ack, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 2124 | /* |
| 2125 | * SDHC has core_mem and hc_mem device memory and these memory |
| 2126 | * addresses do not fall within 1KB region. Hence, any update to |
| 2127 | * core_mem address space would require an mb() to ensure this gets |
| 2128 | * completed before its next update to registers within hc_mem. |
| 2129 | */ |
| 2130 | mb(); |
| 2131 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2132 | if (io_level & REQ_IO_HIGH) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2133 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2134 | ~CORE_IO_PAD_PWR_SWITCH), |
| 2135 | host->ioaddr + CORE_VENDOR_SPEC); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2136 | else if (io_level & REQ_IO_LOW) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2137 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | |
| 2138 | CORE_IO_PAD_PWR_SWITCH), |
| 2139 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2140 | mb(); |
| 2141 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2142 | pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n", |
| 2143 | mmc_hostname(msm_host->mmc), irq, ret, irq_ack); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2144 | spin_lock_irqsave(&host->lock, flags); |
| 2145 | if (pwr_state) |
| 2146 | msm_host->curr_pwr_state = pwr_state; |
| 2147 | if (io_level) |
| 2148 | msm_host->curr_io_level = io_level; |
| 2149 | complete(&msm_host->pwr_irq_completion); |
| 2150 | spin_unlock_irqrestore(&host->lock, flags); |
| 2151 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2152 | return IRQ_HANDLED; |
| 2153 | } |
| 2154 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2155 | static ssize_t |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 2156 | show_polling(struct device *dev, struct device_attribute *attr, char *buf) |
| 2157 | { |
| 2158 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2159 | int poll; |
| 2160 | unsigned long flags; |
| 2161 | |
| 2162 | spin_lock_irqsave(&host->lock, flags); |
| 2163 | poll = !!(host->mmc->caps & MMC_CAP_NEEDS_POLL); |
| 2164 | spin_unlock_irqrestore(&host->lock, flags); |
| 2165 | |
| 2166 | return snprintf(buf, PAGE_SIZE, "%d\n", poll); |
| 2167 | } |
| 2168 | |
| 2169 | static ssize_t |
| 2170 | store_polling(struct device *dev, struct device_attribute *attr, |
| 2171 | const char *buf, size_t count) |
| 2172 | { |
| 2173 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2174 | int value; |
| 2175 | unsigned long flags; |
| 2176 | |
| 2177 | if (!kstrtou32(buf, 0, &value)) { |
| 2178 | spin_lock_irqsave(&host->lock, flags); |
| 2179 | if (value) { |
| 2180 | host->mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 2181 | mmc_detect_change(host->mmc, 0); |
| 2182 | } else { |
| 2183 | host->mmc->caps &= ~MMC_CAP_NEEDS_POLL; |
| 2184 | } |
| 2185 | spin_unlock_irqrestore(&host->lock, flags); |
| 2186 | } |
| 2187 | return count; |
| 2188 | } |
| 2189 | |
| 2190 | static ssize_t |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2191 | show_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 2192 | char *buf) |
| 2193 | { |
| 2194 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2195 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2196 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2197 | |
| 2198 | return snprintf(buf, PAGE_SIZE, "%u\n", |
| 2199 | msm_host->msm_bus_vote.is_max_bw_needed); |
| 2200 | } |
| 2201 | |
| 2202 | static ssize_t |
| 2203 | store_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 2204 | const char *buf, size_t count) |
| 2205 | { |
| 2206 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2207 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2208 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2209 | uint32_t value; |
| 2210 | unsigned long flags; |
| 2211 | |
| 2212 | if (!kstrtou32(buf, 0, &value)) { |
| 2213 | spin_lock_irqsave(&host->lock, flags); |
| 2214 | msm_host->msm_bus_vote.is_max_bw_needed = !!value; |
| 2215 | spin_unlock_irqrestore(&host->lock, flags); |
| 2216 | } |
| 2217 | return count; |
| 2218 | } |
| 2219 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2220 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2221 | { |
| 2222 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2223 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2224 | unsigned long flags; |
| 2225 | bool done = false; |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 2226 | u32 io_sig_sts; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2227 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2228 | spin_lock_irqsave(&host->lock, flags); |
| 2229 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", |
| 2230 | mmc_hostname(host->mmc), __func__, req_type, |
| 2231 | msm_host->curr_pwr_state, msm_host->curr_io_level); |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 2232 | io_sig_sts = readl_relaxed(msm_host->core_mem + CORE_GENERICS); |
| 2233 | /* |
| 2234 | * The IRQ for request type IO High/Low will be generated when - |
| 2235 | * 1. SWITCHABLE_SIGNALLING_VOL is enabled in HW. |
| 2236 | * 2. If 1 is true and when there is a state change in 1.8V enable |
| 2237 | * bit (bit 3) of SDHCI_HOST_CONTROL2 register. The reset state of |
| 2238 | * that bit is 0 which indicates 3.3V IO voltage. So, when MMC core |
| 2239 | * layer tries to set it to 3.3V before card detection happens, the |
| 2240 | * IRQ doesn't get triggered as there is no state change in this bit. |
| 2241 | * The driver already handles this case by changing the IO voltage |
| 2242 | * level to high as part of controller power up sequence. Hence, check |
| 2243 | * for host->pwr to handle a case where IO voltage high request is |
| 2244 | * issued even before controller power up. |
| 2245 | */ |
| 2246 | if (req_type & (REQ_IO_HIGH | REQ_IO_LOW)) { |
| 2247 | if (!(io_sig_sts & SWITCHABLE_SIGNALLING_VOL) || |
| 2248 | ((req_type & REQ_IO_HIGH) && !host->pwr)) { |
| 2249 | pr_debug("%s: do not wait for power IRQ that never comes\n", |
| 2250 | mmc_hostname(host->mmc)); |
| 2251 | spin_unlock_irqrestore(&host->lock, flags); |
| 2252 | return; |
| 2253 | } |
| 2254 | } |
| 2255 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2256 | if ((req_type & msm_host->curr_pwr_state) || |
| 2257 | (req_type & msm_host->curr_io_level)) |
| 2258 | done = true; |
| 2259 | spin_unlock_irqrestore(&host->lock, flags); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2260 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2261 | /* |
| 2262 | * This is needed here to hanlde a case where IRQ gets |
| 2263 | * triggered even before this function is called so that |
| 2264 | * x->done counter of completion gets reset. Otherwise, |
| 2265 | * next call to wait_for_completion returns immediately |
| 2266 | * without actually waiting for the IRQ to be handled. |
| 2267 | */ |
| 2268 | if (done) |
| 2269 | init_completion(&msm_host->pwr_irq_completion); |
| 2270 | else |
| 2271 | wait_for_completion(&msm_host->pwr_irq_completion); |
| 2272 | |
| 2273 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), |
| 2274 | __func__, req_type); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2275 | } |
| 2276 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2277 | static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable) |
| 2278 | { |
| 2279 | if (enable) |
| 2280 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2281 | CORE_DLL_CONFIG) | CORE_CDR_EN), |
| 2282 | host->ioaddr + CORE_DLL_CONFIG); |
| 2283 | else |
| 2284 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2285 | CORE_DLL_CONFIG) & ~CORE_CDR_EN), |
| 2286 | host->ioaddr + CORE_DLL_CONFIG); |
| 2287 | } |
| 2288 | |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 2289 | static unsigned int sdhci_msm_max_segs(void) |
| 2290 | { |
| 2291 | return SDHCI_MSM_MAX_SEGMENTS; |
| 2292 | } |
| 2293 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2294 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2295 | { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2296 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2297 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2298 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2299 | return msm_host->pdata->sup_clk_table[0]; |
| 2300 | } |
| 2301 | |
| 2302 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
| 2303 | { |
| 2304 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2305 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2306 | int max_clk_index = msm_host->pdata->sup_clk_cnt; |
| 2307 | |
| 2308 | return msm_host->pdata->sup_clk_table[max_clk_index - 1]; |
| 2309 | } |
| 2310 | |
| 2311 | static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host, |
| 2312 | u32 req_clk) |
| 2313 | { |
| 2314 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2315 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2316 | unsigned int sel_clk = -1; |
| 2317 | unsigned char cnt; |
| 2318 | |
| 2319 | if (req_clk < sdhci_msm_get_min_clock(host)) { |
| 2320 | sel_clk = sdhci_msm_get_min_clock(host); |
| 2321 | return sel_clk; |
| 2322 | } |
| 2323 | |
| 2324 | for (cnt = 0; cnt < msm_host->pdata->sup_clk_cnt; cnt++) { |
| 2325 | if (msm_host->pdata->sup_clk_table[cnt] > req_clk) { |
| 2326 | break; |
| 2327 | } else if (msm_host->pdata->sup_clk_table[cnt] == req_clk) { |
| 2328 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 2329 | break; |
| 2330 | } else { |
| 2331 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 2332 | } |
| 2333 | } |
| 2334 | return sel_clk; |
| 2335 | } |
| 2336 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2337 | static int sdhci_msm_enable_controller_clock(struct sdhci_host *host) |
| 2338 | { |
| 2339 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2340 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2341 | int rc = 0; |
| 2342 | |
| 2343 | if (atomic_read(&msm_host->controller_clock)) |
| 2344 | return 0; |
| 2345 | |
| 2346 | sdhci_msm_bus_voting(host, 1); |
| 2347 | |
| 2348 | if (!IS_ERR(msm_host->pclk)) { |
| 2349 | rc = clk_prepare_enable(msm_host->pclk); |
| 2350 | if (rc) { |
| 2351 | pr_err("%s: %s: failed to enable the pclk with error %d\n", |
| 2352 | mmc_hostname(host->mmc), __func__, rc); |
| 2353 | goto remove_vote; |
| 2354 | } |
| 2355 | } |
| 2356 | |
| 2357 | rc = clk_prepare_enable(msm_host->clk); |
| 2358 | if (rc) { |
| 2359 | pr_err("%s: %s: failed to enable the host-clk with error %d\n", |
| 2360 | mmc_hostname(host->mmc), __func__, rc); |
| 2361 | goto disable_pclk; |
| 2362 | } |
| 2363 | |
| 2364 | atomic_set(&msm_host->controller_clock, 1); |
| 2365 | pr_debug("%s: %s: enabled controller clock\n", |
| 2366 | mmc_hostname(host->mmc), __func__); |
| 2367 | goto out; |
| 2368 | |
| 2369 | disable_pclk: |
| 2370 | if (!IS_ERR(msm_host->pclk)) |
| 2371 | clk_disable_unprepare(msm_host->pclk); |
| 2372 | remove_vote: |
| 2373 | if (msm_host->msm_bus_vote.client_handle) |
| 2374 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 2375 | out: |
| 2376 | return rc; |
| 2377 | } |
| 2378 | |
| 2379 | |
| 2380 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2381 | static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable) |
| 2382 | { |
| 2383 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2384 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2385 | int rc = 0; |
| 2386 | |
| 2387 | if (enable && !atomic_read(&msm_host->clks_on)) { |
| 2388 | pr_debug("%s: request to enable clocks\n", |
| 2389 | mmc_hostname(host->mmc)); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2390 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2391 | /* |
| 2392 | * The bus-width or the clock rate might have changed |
| 2393 | * after controller clocks are enbaled, update bus vote |
| 2394 | * in such case. |
| 2395 | */ |
| 2396 | if (atomic_read(&msm_host->controller_clock)) |
| 2397 | sdhci_msm_bus_voting(host, 1); |
| 2398 | |
| 2399 | rc = sdhci_msm_enable_controller_clock(host); |
| 2400 | if (rc) |
| 2401 | goto remove_vote; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2402 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2403 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 2404 | rc = clk_prepare_enable(msm_host->bus_clk); |
| 2405 | if (rc) { |
| 2406 | pr_err("%s: %s: failed to enable the bus-clock with error %d\n", |
| 2407 | mmc_hostname(host->mmc), __func__, rc); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2408 | goto disable_controller_clk; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2409 | } |
| 2410 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2411 | if (!IS_ERR(msm_host->ff_clk)) { |
| 2412 | rc = clk_prepare_enable(msm_host->ff_clk); |
| 2413 | if (rc) { |
| 2414 | pr_err("%s: %s: failed to enable the ff_clk with error %d\n", |
| 2415 | mmc_hostname(host->mmc), __func__, rc); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2416 | goto disable_bus_clk; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2417 | } |
| 2418 | } |
| 2419 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 2420 | rc = clk_prepare_enable(msm_host->sleep_clk); |
| 2421 | if (rc) { |
| 2422 | pr_err("%s: %s: failed to enable the sleep_clk with error %d\n", |
| 2423 | mmc_hostname(host->mmc), __func__, rc); |
| 2424 | goto disable_ff_clk; |
| 2425 | } |
| 2426 | } |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2427 | mb(); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2428 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2429 | } else if (!enable && atomic_read(&msm_host->clks_on)) { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2430 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
| 2431 | mb(); |
Sahitya Tummala | dc18298 | 2013-08-20 15:32:09 +0530 | [diff] [blame] | 2432 | /* |
| 2433 | * During 1.8V signal switching the clock source must |
| 2434 | * still be ON as it requires accessing SDHC |
| 2435 | * registers (SDHCi host control2 register bit 3 must |
| 2436 | * be written and polled after stopping the SDCLK). |
| 2437 | */ |
| 2438 | if (host->mmc->card_clock_off) |
| 2439 | return 0; |
| 2440 | pr_debug("%s: request to disable clocks\n", |
| 2441 | mmc_hostname(host->mmc)); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2442 | if (!IS_ERR_OR_NULL(msm_host->sleep_clk)) |
| 2443 | clk_disable_unprepare(msm_host->sleep_clk); |
| 2444 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 2445 | clk_disable_unprepare(msm_host->ff_clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2446 | clk_disable_unprepare(msm_host->clk); |
| 2447 | if (!IS_ERR(msm_host->pclk)) |
| 2448 | clk_disable_unprepare(msm_host->pclk); |
| 2449 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 2450 | clk_disable_unprepare(msm_host->bus_clk); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2451 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2452 | atomic_set(&msm_host->controller_clock, 0); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2453 | sdhci_msm_bus_voting(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2454 | } |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2455 | atomic_set(&msm_host->clks_on, enable); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2456 | goto out; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2457 | disable_ff_clk: |
| 2458 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 2459 | clk_disable_unprepare(msm_host->ff_clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2460 | disable_bus_clk: |
| 2461 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 2462 | clk_disable_unprepare(msm_host->bus_clk); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2463 | disable_controller_clk: |
| 2464 | if (!IS_ERR_OR_NULL(msm_host->clk)) |
| 2465 | clk_disable_unprepare(msm_host->clk); |
| 2466 | if (!IS_ERR_OR_NULL(msm_host->pclk)) |
| 2467 | clk_disable_unprepare(msm_host->pclk); |
| 2468 | atomic_set(&msm_host->controller_clock, 0); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2469 | remove_vote: |
| 2470 | if (msm_host->msm_bus_vote.client_handle) |
| 2471 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2472 | out: |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2473 | return rc; |
| 2474 | } |
| 2475 | |
| 2476 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
| 2477 | { |
| 2478 | int rc; |
| 2479 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2480 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2481 | struct mmc_ios curr_ios = host->mmc->ios; |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2482 | u32 sup_clock, ddr_clock, dll_lock; |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2483 | bool curr_pwrsave; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2484 | |
| 2485 | if (!clock) { |
Sujit Reddy Thumma | bf1aecc | 2014-01-10 10:58:54 +0530 | [diff] [blame] | 2486 | /* |
| 2487 | * disable pwrsave to ensure clock is not auto-gated until |
| 2488 | * the rate is >400KHz (initialization complete). |
| 2489 | */ |
| 2490 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2491 | ~CORE_CLK_PWRSAVE, host->ioaddr + CORE_VENDOR_SPEC); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2492 | sdhci_msm_prepare_clocks(host, false); |
| 2493 | host->clock = clock; |
| 2494 | goto out; |
| 2495 | } |
| 2496 | |
| 2497 | rc = sdhci_msm_prepare_clocks(host, true); |
| 2498 | if (rc) |
| 2499 | goto out; |
| 2500 | |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2501 | curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2502 | CORE_CLK_PWRSAVE); |
Sahitya Tummala | e000b24 | 2013-08-29 16:21:08 +0530 | [diff] [blame] | 2503 | if ((clock > 400000) && |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2504 | !curr_pwrsave && mmc_host_may_gate_card(host->mmc->card)) |
| 2505 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2506 | | CORE_CLK_PWRSAVE, |
| 2507 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2508 | /* |
| 2509 | * Disable pwrsave for a newly added card if doesn't allow clock |
| 2510 | * gating. |
| 2511 | */ |
| 2512 | else if (curr_pwrsave && !mmc_host_may_gate_card(host->mmc->card)) |
| 2513 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2514 | & ~CORE_CLK_PWRSAVE, |
| 2515 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2516 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2517 | sup_clock = sdhci_msm_get_sup_clk_rate(host, clock); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2518 | if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || |
| 2519 | (curr_ios.timing == MMC_TIMING_MMC_HS400)) { |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2520 | /* |
| 2521 | * The SDHC requires internal clock frequency to be double the |
| 2522 | * actual clock that will be set for DDR mode. The controller |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2523 | * uses the faster clock(100/400MHz) for some of its parts and |
| 2524 | * send the actual required clock (50/200MHz) to the card. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2525 | */ |
| 2526 | ddr_clock = clock * 2; |
| 2527 | sup_clock = sdhci_msm_get_sup_clk_rate(host, |
| 2528 | ddr_clock); |
| 2529 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2530 | |
| 2531 | /* |
| 2532 | * In general all timing modes are controlled via UHS mode select in |
| 2533 | * Host Control2 register. eMMC specific HS200/HS400 doesn't have |
| 2534 | * their respective modes defined here, hence we use these values. |
| 2535 | * |
| 2536 | * HS200 - SDR104 (Since they both are equivalent in functionality) |
| 2537 | * HS400 - This involves multiple configurations |
| 2538 | * Initially SDR104 - when tuning is required as HS200 |
| 2539 | * Then when switching to DDR @ 400MHz (HS400) we use |
| 2540 | * the vendor specific HC_SELECT_IN to control the mode. |
| 2541 | * |
| 2542 | * In addition to controlling the modes we also need to select the |
| 2543 | * correct input clock for DLL depending on the mode. |
| 2544 | * |
| 2545 | * HS400 - divided clock (free running MCLK/2) |
| 2546 | * All other modes - default (free running MCLK) |
| 2547 | */ |
| 2548 | if (curr_ios.timing == MMC_TIMING_MMC_HS400) { |
| 2549 | /* Select the divided clock (free running MCLK/2) */ |
| 2550 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2551 | & ~CORE_HC_MCLK_SEL_MASK) |
| 2552 | | CORE_HC_MCLK_SEL_HS400), |
| 2553 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2554 | /* |
| 2555 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC |
| 2556 | * register |
| 2557 | */ |
| 2558 | if (msm_host->tuning_done && !msm_host->calibration_done) { |
| 2559 | /* |
| 2560 | * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN |
| 2561 | * field in VENDOR_SPEC_FUNC |
| 2562 | */ |
| 2563 | writel_relaxed((readl_relaxed(host->ioaddr + \ |
| 2564 | CORE_VENDOR_SPEC) |
| 2565 | | CORE_HC_SELECT_IN_HS400 |
| 2566 | | CORE_HC_SELECT_IN_EN), |
| 2567 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2568 | } |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2569 | if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) { |
| 2570 | /* |
| 2571 | * Poll on DLL_LOCK and DDR_DLL_LOCK bits in |
| 2572 | * CORE_DLL_STATUS to be set. This should get set |
| 2573 | * with in 15 us at 200 MHz. |
| 2574 | */ |
| 2575 | rc = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS, |
| 2576 | dll_lock, (dll_lock & (CORE_DLL_LOCK | |
| 2577 | CORE_DDR_DLL_LOCK)), 10, 1000); |
| 2578 | if (rc == -ETIMEDOUT) |
| 2579 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", |
| 2580 | mmc_hostname(host->mmc), |
| 2581 | dll_lock); |
| 2582 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2583 | } else { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2584 | if (!msm_host->use_cdclp533) |
| 2585 | /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */ |
| 2586 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2587 | CORE_VENDOR_SPEC3) & ~CORE_PWRSAVE_DLL), |
| 2588 | host->ioaddr + CORE_VENDOR_SPEC3); |
| 2589 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2590 | /* Select the default clock (free running MCLK) */ |
| 2591 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2592 | & ~CORE_HC_MCLK_SEL_MASK) |
| 2593 | | CORE_HC_MCLK_SEL_DFLT), |
| 2594 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2595 | |
| 2596 | /* |
| 2597 | * Disable HC_SELECT_IN to be able to use the UHS mode select |
| 2598 | * configuration from Host Control2 register for all other |
| 2599 | * modes. |
| 2600 | * |
| 2601 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field |
| 2602 | * in VENDOR_SPEC_FUNC |
| 2603 | */ |
| 2604 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2605 | & ~CORE_HC_SELECT_IN_EN |
| 2606 | & ~CORE_HC_SELECT_IN_MASK), |
| 2607 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2608 | } |
| 2609 | mb(); |
| 2610 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2611 | if (sup_clock != msm_host->clk_rate) { |
| 2612 | pr_debug("%s: %s: setting clk rate to %u\n", |
| 2613 | mmc_hostname(host->mmc), __func__, sup_clock); |
| 2614 | rc = clk_set_rate(msm_host->clk, sup_clock); |
| 2615 | if (rc) { |
| 2616 | pr_err("%s: %s: Failed to set rate %u for host-clk : %d\n", |
| 2617 | mmc_hostname(host->mmc), __func__, |
| 2618 | sup_clock, rc); |
| 2619 | goto out; |
| 2620 | } |
| 2621 | msm_host->clk_rate = sup_clock; |
| 2622 | host->clock = clock; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2623 | /* |
| 2624 | * Update the bus vote in case of frequency change due to |
| 2625 | * clock scaling. |
| 2626 | */ |
| 2627 | sdhci_msm_bus_voting(host, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2628 | } |
| 2629 | out: |
| 2630 | sdhci_set_clock(host, clock); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2631 | } |
| 2632 | |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2633 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
| 2634 | unsigned int uhs) |
| 2635 | { |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2636 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2637 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2638 | u16 ctrl_2; |
| 2639 | |
| 2640 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2641 | /* Select Bus Speed Mode for host */ |
| 2642 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2643 | if (uhs == MMC_TIMING_MMC_HS400) |
| 2644 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2645 | else if (uhs == MMC_TIMING_MMC_HS200) |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2646 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2647 | else if (uhs == MMC_TIMING_UHS_SDR12) |
| 2648 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 2649 | else if (uhs == MMC_TIMING_UHS_SDR25) |
| 2650 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 2651 | else if (uhs == MMC_TIMING_UHS_SDR50) |
| 2652 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 2653 | else if (uhs == MMC_TIMING_UHS_SDR104) |
| 2654 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2655 | else if (uhs == MMC_TIMING_UHS_DDR50) |
| 2656 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2657 | /* |
| 2658 | * When clock frquency is less than 100MHz, the feedback clock must be |
| 2659 | * provided and DLL must not be used so that tuning can be skipped. To |
| 2660 | * provide feedback clock, the mode selection can be any value less |
| 2661 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. |
| 2662 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2663 | if (host->clock <= CORE_FREQ_100MHZ) { |
| 2664 | if ((uhs == MMC_TIMING_MMC_HS400) || |
| 2665 | (uhs == MMC_TIMING_MMC_HS200) || |
| 2666 | (uhs == MMC_TIMING_UHS_SDR104)) |
| 2667 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2668 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2669 | /* |
| 2670 | * Make sure DLL is disabled when not required |
| 2671 | * |
| 2672 | * Write 1 to DLL_RST bit of DLL_CONFIG register |
| 2673 | */ |
| 2674 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2675 | | CORE_DLL_RST), |
| 2676 | host->ioaddr + CORE_DLL_CONFIG); |
| 2677 | |
| 2678 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 2679 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2680 | | CORE_DLL_PDN), |
| 2681 | host->ioaddr + CORE_DLL_CONFIG); |
| 2682 | mb(); |
| 2683 | |
| 2684 | /* |
| 2685 | * The DLL needs to be restored and CDCLP533 recalibrated |
| 2686 | * when the clock frequency is set back to 400MHz. |
| 2687 | */ |
| 2688 | msm_host->calibration_done = false; |
| 2689 | } |
| 2690 | |
| 2691 | pr_debug("%s: %s-clock:%u uhs mode:%u ctrl_2:0x%x\n", |
| 2692 | mmc_hostname(host->mmc), __func__, host->clock, uhs, ctrl_2); |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2693 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 2694 | |
| 2695 | } |
| 2696 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2697 | #define MAX_TEST_BUS 20 |
| 2698 | |
| 2699 | void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) |
| 2700 | { |
| 2701 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2702 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2703 | int tbsel, tbsel2; |
| 2704 | int i, index = 0; |
| 2705 | u32 test_bus_val = 0; |
| 2706 | u32 debug_reg[MAX_TEST_BUS] = {0}; |
| 2707 | |
| 2708 | pr_info("----------- VENDOR REGISTER DUMP -----------\n"); |
| 2709 | pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n", |
| 2710 | readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT), |
| 2711 | readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT), |
| 2712 | readl_relaxed(msm_host->core_mem + CORE_MCI_STATUS)); |
| 2713 | pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n", |
| 2714 | readl_relaxed(host->ioaddr + CORE_DLL_CONFIG), |
| 2715 | readl_relaxed(host->ioaddr + CORE_DLL_STATUS), |
| 2716 | readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION)); |
| 2717 | pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n", |
| 2718 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC), |
| 2719 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), |
| 2720 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); |
| 2721 | |
| 2722 | /* |
| 2723 | * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits |
| 2724 | * of CORE_TESTBUS_CONFIG register. |
| 2725 | * |
| 2726 | * To select test bus 0 to 7 use tbsel and to select any test bus |
| 2727 | * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg, |
| 2728 | * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register |
| 2729 | * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110. |
| 2730 | */ |
| 2731 | for (tbsel2 = 0; tbsel2 < 3; tbsel2++) { |
| 2732 | for (tbsel = 0; tbsel < 8; tbsel++) { |
| 2733 | if (index >= MAX_TEST_BUS) |
| 2734 | break; |
| 2735 | test_bus_val = (tbsel2 << CORE_TESTBUS_SEL2_BIT) | |
| 2736 | tbsel | CORE_TESTBUS_ENA; |
| 2737 | writel_relaxed(test_bus_val, |
| 2738 | msm_host->core_mem + CORE_TESTBUS_CONFIG); |
| 2739 | debug_reg[index++] = readl_relaxed(msm_host->core_mem + |
| 2740 | CORE_SDCC_DEBUG_REG); |
| 2741 | } |
| 2742 | } |
| 2743 | for (i = 0; i < MAX_TEST_BUS; i = i + 4) |
| 2744 | pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 2745 | i, i + 3, debug_reg[i], debug_reg[i+1], |
| 2746 | debug_reg[i+2], debug_reg[i+3]); |
| 2747 | /* Disable test bus */ |
| 2748 | writel_relaxed(~CORE_TESTBUS_ENA, msm_host->core_mem + |
| 2749 | CORE_TESTBUS_CONFIG); |
| 2750 | } |
| 2751 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2752 | static struct sdhci_ops sdhci_msm_ops = { |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2753 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2754 | .check_power_status = sdhci_msm_check_power_status, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2755 | .platform_execute_tuning = sdhci_msm_execute_tuning, |
| 2756 | .toggle_cdr = sdhci_msm_toggle_cdr, |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 2757 | .get_max_segments = sdhci_msm_max_segs, |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2758 | .set_clock = sdhci_msm_set_clock, |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2759 | .get_min_clock = sdhci_msm_get_min_clock, |
| 2760 | .get_max_clock = sdhci_msm_get_max_clock, |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2761 | .dump_vendor_regs = sdhci_msm_dump_vendor_regs, |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 2762 | .config_auto_tuning_cmd = sdhci_msm_config_auto_tuning_cmd, |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2763 | .enable_controller_clock = sdhci_msm_enable_controller_clock, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2764 | }; |
| 2765 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2766 | static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, |
| 2767 | struct sdhci_host *host) |
| 2768 | { |
| 2769 | u32 version, caps; |
| 2770 | u16 minor; |
| 2771 | u8 major; |
| 2772 | |
| 2773 | version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); |
| 2774 | major = (version & CORE_VERSION_MAJOR_MASK) >> |
| 2775 | CORE_VERSION_MAJOR_SHIFT; |
| 2776 | minor = version & CORE_VERSION_TARGET_MASK; |
| 2777 | |
| 2778 | /* |
| 2779 | * Starting with SDCC 5 controller (core major version = 1) |
Venkat Gopalakrishnan | 3ac8fd3 | 2014-08-28 18:15:45 -0700 | [diff] [blame] | 2780 | * controller won't advertise 3.0v, 1.8v and 8-bit features |
| 2781 | * except for some targets. |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2782 | */ |
| 2783 | if (major >= 1 && minor != 0x11 && minor != 0x12) { |
Venkat Gopalakrishnan | 3ac8fd3 | 2014-08-28 18:15:45 -0700 | [diff] [blame] | 2784 | struct sdhci_msm_reg_data *vdd_io_reg; |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2785 | caps = CORE_3_0V_SUPPORT; |
Venkat Gopalakrishnan | 3ac8fd3 | 2014-08-28 18:15:45 -0700 | [diff] [blame] | 2786 | /* |
| 2787 | * Enable 1.8V support capability on controllers that |
| 2788 | * support dual voltage |
| 2789 | */ |
| 2790 | vdd_io_reg = msm_host->pdata->vreg_data->vdd_io_data; |
| 2791 | if (vdd_io_reg && |
| 2792 | (vdd_io_reg->low_vol_level != vdd_io_reg->high_vol_level)) |
| 2793 | caps |= CORE_1_8V_SUPPORT; |
Pratibhasagar V | ada4799 | 2013-12-09 20:42:32 +0530 | [diff] [blame] | 2794 | if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA) |
| 2795 | caps |= CORE_8_BIT_SUPPORT; |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2796 | writel_relaxed( |
| 2797 | (readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | |
| 2798 | caps), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); |
| 2799 | } |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2800 | |
| 2801 | /* |
| 2802 | * SDCC 5 controller with major version 1, minor version 0x34 and later |
| 2803 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. |
| 2804 | */ |
| 2805 | if ((major == 1) && (minor < 0x34)) |
| 2806 | msm_host->use_cdclp533 = true; |
Gilad Broner | 2a10ca0 | 2014-10-02 17:20:35 +0300 | [diff] [blame] | 2807 | |
| 2808 | /* |
| 2809 | * Mask 64-bit support for controller with 32-bit address bus so that |
| 2810 | * smaller descriptor size will be used and improve memory consumption. |
| 2811 | * In case bus addressing ever changes, controller version should be |
| 2812 | * used in order to decide whether or not to mask 64-bit support. |
| 2813 | */ |
| 2814 | caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); |
| 2815 | caps &= ~CORE_SYS_BUS_SUPPORT_64_BIT; |
| 2816 | writel_relaxed(caps, host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2817 | } |
| 2818 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2819 | static int sdhci_msm_probe(struct platform_device *pdev) |
| 2820 | { |
| 2821 | struct sdhci_host *host; |
| 2822 | struct sdhci_pltfm_host *pltfm_host; |
| 2823 | struct sdhci_msm_host *msm_host; |
| 2824 | struct resource *core_memres = NULL; |
| 2825 | int ret = 0, pwr_irq = 0, dead = 0; |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 2826 | u16 host_version; |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2827 | u32 pwr, irq_status, irq_ctl; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2828 | |
| 2829 | pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); |
| 2830 | msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), |
| 2831 | GFP_KERNEL); |
| 2832 | if (!msm_host) { |
| 2833 | ret = -ENOMEM; |
| 2834 | goto out; |
| 2835 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2836 | |
| 2837 | msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops; |
| 2838 | host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0); |
| 2839 | if (IS_ERR(host)) { |
| 2840 | ret = PTR_ERR(host); |
| 2841 | goto out; |
| 2842 | } |
| 2843 | |
| 2844 | pltfm_host = sdhci_priv(host); |
| 2845 | pltfm_host->priv = msm_host; |
| 2846 | msm_host->mmc = host->mmc; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2847 | msm_host->pdev = pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2848 | |
| 2849 | /* Extract platform data */ |
| 2850 | if (pdev->dev.of_node) { |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 2851 | ret = of_alias_get_id(pdev->dev.of_node, "sdhc"); |
| 2852 | if (ret < 0) { |
| 2853 | dev_err(&pdev->dev, "Failed to get slot index %d\n", |
| 2854 | ret); |
| 2855 | goto pltfm_free; |
| 2856 | } |
| 2857 | if (disable_slots & (1 << (ret - 1))) { |
| 2858 | dev_info(&pdev->dev, "%s: Slot %d disabled\n", __func__, |
| 2859 | ret); |
| 2860 | ret = -ENODEV; |
| 2861 | goto pltfm_free; |
| 2862 | } |
| 2863 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2864 | msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev); |
| 2865 | if (!msm_host->pdata) { |
| 2866 | dev_err(&pdev->dev, "DT parsing error\n"); |
| 2867 | goto pltfm_free; |
| 2868 | } |
| 2869 | } else { |
| 2870 | dev_err(&pdev->dev, "No device tree node\n"); |
| 2871 | goto pltfm_free; |
| 2872 | } |
| 2873 | |
| 2874 | /* Setup Clocks */ |
| 2875 | |
| 2876 | /* Setup SDCC bus voter clock. */ |
| 2877 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); |
| 2878 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 2879 | /* Vote for max. clk rate for max. performance */ |
| 2880 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); |
| 2881 | if (ret) |
| 2882 | goto pltfm_free; |
| 2883 | ret = clk_prepare_enable(msm_host->bus_clk); |
| 2884 | if (ret) |
| 2885 | goto pltfm_free; |
| 2886 | } |
| 2887 | |
| 2888 | /* Setup main peripheral bus clock */ |
| 2889 | msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); |
| 2890 | if (!IS_ERR(msm_host->pclk)) { |
| 2891 | ret = clk_prepare_enable(msm_host->pclk); |
| 2892 | if (ret) |
| 2893 | goto bus_clk_disable; |
| 2894 | } |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2895 | atomic_set(&msm_host->controller_clock, 1); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2896 | |
| 2897 | /* Setup SDC MMC clock */ |
| 2898 | msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); |
| 2899 | if (IS_ERR(msm_host->clk)) { |
| 2900 | ret = PTR_ERR(msm_host->clk); |
| 2901 | goto pclk_disable; |
| 2902 | } |
| 2903 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2904 | /* Set to the minimum supported clock frequency */ |
| 2905 | ret = clk_set_rate(msm_host->clk, sdhci_msm_get_min_clock(host)); |
| 2906 | if (ret) { |
| 2907 | dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret); |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2908 | goto pclk_disable; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2909 | } |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2910 | ret = clk_prepare_enable(msm_host->clk); |
| 2911 | if (ret) |
| 2912 | goto pclk_disable; |
| 2913 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2914 | msm_host->clk_rate = sdhci_msm_get_min_clock(host); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2915 | atomic_set(&msm_host->clks_on, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2916 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2917 | /* Setup CDC calibration fixed feedback clock */ |
| 2918 | msm_host->ff_clk = devm_clk_get(&pdev->dev, "cal_clk"); |
| 2919 | if (!IS_ERR(msm_host->ff_clk)) { |
| 2920 | ret = clk_prepare_enable(msm_host->ff_clk); |
| 2921 | if (ret) |
| 2922 | goto clk_disable; |
| 2923 | } |
| 2924 | |
| 2925 | /* Setup CDC calibration sleep clock */ |
| 2926 | msm_host->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk"); |
| 2927 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 2928 | ret = clk_prepare_enable(msm_host->sleep_clk); |
| 2929 | if (ret) |
| 2930 | goto ff_clk_disable; |
| 2931 | } |
| 2932 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 2933 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
| 2934 | |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2935 | ret = sdhci_msm_bus_register(msm_host, pdev); |
| 2936 | if (ret) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2937 | goto sleep_clk_disable; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2938 | |
| 2939 | if (msm_host->msm_bus_vote.client_handle) |
| 2940 | INIT_DELAYED_WORK(&msm_host->msm_bus_vote.vote_work, |
| 2941 | sdhci_msm_bus_work); |
| 2942 | sdhci_msm_bus_voting(host, 1); |
| 2943 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2944 | /* Setup regulators */ |
| 2945 | ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true); |
| 2946 | if (ret) { |
| 2947 | dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2948 | goto bus_unregister; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2949 | } |
| 2950 | |
| 2951 | /* Reset the core and Enable SDHC mode */ |
| 2952 | core_memres = platform_get_resource_byname(pdev, |
| 2953 | IORESOURCE_MEM, "core_mem"); |
Asutosh Das | 890bdee | 2014-08-08 23:01:42 +0530 | [diff] [blame] | 2954 | if (!core_memres) { |
| 2955 | dev_err(&pdev->dev, "Failed to get iomem resource\n"); |
| 2956 | goto vreg_deinit; |
| 2957 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2958 | msm_host->core_mem = devm_ioremap(&pdev->dev, core_memres->start, |
| 2959 | resource_size(core_memres)); |
| 2960 | |
| 2961 | if (!msm_host->core_mem) { |
| 2962 | dev_err(&pdev->dev, "Failed to remap registers\n"); |
| 2963 | ret = -ENOMEM; |
| 2964 | goto vreg_deinit; |
| 2965 | } |
| 2966 | |
Stepan Moskovchenko | a4d0fa7 | 2013-09-13 22:19:33 -0700 | [diff] [blame] | 2967 | /* Unset HC_MODE_EN bit in HC_MODE register */ |
| 2968 | writel_relaxed(0, (msm_host->core_mem + CORE_HC_MODE)); |
| 2969 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2970 | /* Set SW_RST bit in POWER register (Offset 0x0) */ |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 2971 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | |
| 2972 | CORE_SW_RST, msm_host->core_mem + CORE_POWER); |
| 2973 | /* |
| 2974 | * SW reset can take upto 10HCLK + 15MCLK cycles. |
| 2975 | * Calculating based on min clk rates (hclk = 27MHz, |
| 2976 | * mclk = 400KHz) it comes to ~40us. Let's poll for |
| 2977 | * max. 1ms for reset completion. |
| 2978 | */ |
| 2979 | ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER, |
Matt Wagantall | c7097a2 | 2014-04-29 15:48:15 -0700 | [diff] [blame] | 2980 | pwr, !(pwr & CORE_SW_RST), 10, 1000); |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 2981 | |
| 2982 | if (ret) { |
| 2983 | dev_err(&pdev->dev, "reset failed (%d)\n", ret); |
| 2984 | goto vreg_deinit; |
| 2985 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2986 | /* Set HC_MODE_EN bit in HC_MODE register */ |
| 2987 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |
| 2988 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2989 | /* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */ |
| 2990 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_HC_MODE) | |
| 2991 | FF_CLK_SW_RST_DIS, msm_host->core_mem + CORE_HC_MODE); |
| 2992 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2993 | sdhci_set_default_hw_caps(msm_host, host); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2994 | /* |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2995 | * CORE_SW_RST above may trigger power irq if previous status of PWRCTL |
| 2996 | * was either BUS_ON or IO_HIGH_V. So before we enable the power irq |
| 2997 | * interrupt in GIC (by registering the interrupt handler), we need to |
| 2998 | * ensure that any pending power irq interrupt status is acknowledged |
| 2999 | * otherwise power irq interrupt handler would be fired prematurely. |
| 3000 | */ |
| 3001 | irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 3002 | writel_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 3003 | irq_ctl = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL); |
| 3004 | if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) |
| 3005 | irq_ctl |= CORE_PWRCTL_BUS_SUCCESS; |
| 3006 | if (irq_status & (CORE_PWRCTL_IO_HIGH | CORE_PWRCTL_IO_LOW)) |
| 3007 | irq_ctl |= CORE_PWRCTL_IO_SUCCESS; |
| 3008 | writel_relaxed(irq_ctl, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 3009 | /* |
| 3010 | * Ensure that above writes are propogated before interrupt enablement |
| 3011 | * in GIC. |
| 3012 | */ |
| 3013 | mb(); |
| 3014 | |
| 3015 | /* |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3016 | * Following are the deviations from SDHC spec v3.0 - |
| 3017 | * 1. Card detection is handled using separate GPIO. |
| 3018 | * 2. Bus power control is handled by interacting with PMIC. |
| 3019 | */ |
| 3020 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 3021 | host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 3022 | host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; |
| 3023 | host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK; |
Sahitya Tummala | 87d4394 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 3024 | host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD; |
Sahitya Tummala | 314162c | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 3025 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE; |
Sahitya Tummala | 7c9780d | 2013-04-12 11:59:25 +0530 | [diff] [blame] | 3026 | host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3027 | |
Sahitya Tummala | a5733ab5 | 2013-06-10 16:32:51 +0530 | [diff] [blame] | 3028 | if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) |
| 3029 | host->quirks2 |= SDHCI_QUIRK2_DIVIDE_TOUT_BY_4; |
| 3030 | |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 3031 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 3032 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", |
| 3033 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 3034 | SDHCI_VENDOR_VER_SHIFT)); |
| 3035 | if (((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 3036 | SDHCI_VENDOR_VER_SHIFT) == SDHCI_VER_100) { |
| 3037 | /* |
| 3038 | * Add 40us delay in interrupt handler when |
| 3039 | * operating at initialization frequency(400KHz). |
| 3040 | */ |
| 3041 | host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; |
| 3042 | /* |
| 3043 | * Set Software Reset for DAT line in Software |
| 3044 | * Reset Register (Bit 2). |
| 3045 | */ |
| 3046 | host->quirks2 |= SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT; |
| 3047 | } |
| 3048 | |
Asutosh Das | 214b966 | 2013-06-13 14:27:42 +0530 | [diff] [blame] | 3049 | host->quirks2 |= SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR; |
| 3050 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 3051 | /* Setup PWRCTL irq */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3052 | pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); |
| 3053 | if (pwr_irq < 0) { |
| 3054 | dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", |
| 3055 | pwr_irq); |
| 3056 | goto vreg_deinit; |
| 3057 | } |
| 3058 | ret = devm_request_threaded_irq(&pdev->dev, pwr_irq, NULL, |
| 3059 | sdhci_msm_pwr_irq, IRQF_ONESHOT, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 3060 | dev_name(&pdev->dev), host); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3061 | if (ret) { |
| 3062 | dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n", |
| 3063 | pwr_irq, ret); |
| 3064 | goto vreg_deinit; |
| 3065 | } |
| 3066 | |
| 3067 | /* Enable pwr irq interrupts */ |
| 3068 | writel_relaxed(INT_MASK, (msm_host->core_mem + CORE_PWRCTL_MASK)); |
| 3069 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 3070 | #ifdef CONFIG_MMC_CLKGATE |
| 3071 | /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ |
| 3072 | msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; |
| 3073 | #endif |
| 3074 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3075 | /* Set host capabilities */ |
| 3076 | msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; |
| 3077 | msm_host->mmc->caps |= msm_host->pdata->caps; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3078 | msm_host->mmc->caps2 |= msm_host->pdata->caps2; |
| 3079 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR; |
| 3080 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR_CONTROL; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 3081 | msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE; |
Subhash Jadavani | 6d472b2 | 2013-05-29 15:52:10 +0530 | [diff] [blame] | 3082 | msm_host->mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE; |
Asutosh Das | bea115d | 2013-06-24 18:20:45 +0530 | [diff] [blame] | 3083 | msm_host->mmc->pm_caps |= MMC_PM_KEEP_POWER; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3084 | |
| 3085 | if (msm_host->pdata->nonremovable) |
| 3086 | msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 3087 | |
Guoping Yu | f7c9133 | 2014-08-20 16:56:18 +0800 | [diff] [blame] | 3088 | if (msm_host->pdata->nonhotplug) |
| 3089 | msm_host->mmc->caps2 |= MMC_CAP2_NONHOTPLUG; |
| 3090 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 3091 | host->cpu_dma_latency_us = msm_host->pdata->cpu_dma_latency_us; |
Maya Erez | 994cf2f | 2014-10-21 20:22:04 +0300 | [diff] [blame^] | 3092 | host->pm_qos_req_dma.type = msm_host->pdata->cpu_affinity_type; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 3093 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 3094 | init_completion(&msm_host->pwr_irq_completion); |
| 3095 | |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3096 | if (gpio_is_valid(msm_host->pdata->status_gpio)) { |
Sahitya Tummala | 6ddabb4 | 2014-06-05 13:26:55 +0530 | [diff] [blame] | 3097 | /* |
| 3098 | * Set up the card detect GPIO in active configuration before |
| 3099 | * configuring it as an IRQ. Otherwise, it can be in some |
| 3100 | * weird/inconsistent state resulting in flood of interrupts. |
| 3101 | */ |
| 3102 | sdhci_msm_setup_pins(msm_host->pdata, true); |
| 3103 | |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3104 | ret = mmc_gpio_request_cd(msm_host->mmc, |
| 3105 | msm_host->pdata->status_gpio, 0); |
| 3106 | if (ret) { |
| 3107 | dev_err(&pdev->dev, "%s: Failed to request card detection IRQ %d\n", |
| 3108 | __func__, ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 3109 | goto vreg_deinit; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3110 | } |
| 3111 | } |
| 3112 | |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 3113 | if ((sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) && |
| 3114 | (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(64)))) { |
| 3115 | host->dma_mask = DMA_BIT_MASK(64); |
| 3116 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 3117 | } else if (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(32))) { |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 3118 | host->dma_mask = DMA_BIT_MASK(32); |
| 3119 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 3120 | } else { |
| 3121 | dev_err(&pdev->dev, "%s: Failed to set dma mask\n", __func__); |
| 3122 | } |
| 3123 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3124 | ret = sdhci_add_host(host); |
| 3125 | if (ret) { |
| 3126 | dev_err(&pdev->dev, "Add host failed (%d)\n", ret); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3127 | goto vreg_deinit; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3128 | } |
| 3129 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3130 | msm_host->msm_bus_vote.max_bus_bw.show = show_sdhci_max_bus_bw; |
| 3131 | msm_host->msm_bus_vote.max_bus_bw.store = store_sdhci_max_bus_bw; |
| 3132 | sysfs_attr_init(&msm_host->msm_bus_vote.max_bus_bw.attr); |
| 3133 | msm_host->msm_bus_vote.max_bus_bw.attr.name = "max_bus_bw"; |
| 3134 | msm_host->msm_bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR; |
| 3135 | ret = device_create_file(&pdev->dev, |
| 3136 | &msm_host->msm_bus_vote.max_bus_bw); |
| 3137 | if (ret) |
| 3138 | goto remove_host; |
| 3139 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3140 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) { |
| 3141 | msm_host->polling.show = show_polling; |
| 3142 | msm_host->polling.store = store_polling; |
| 3143 | sysfs_attr_init(&msm_host->polling.attr); |
| 3144 | msm_host->polling.attr.name = "polling"; |
| 3145 | msm_host->polling.attr.mode = S_IRUGO | S_IWUSR; |
| 3146 | ret = device_create_file(&pdev->dev, &msm_host->polling); |
| 3147 | if (ret) |
| 3148 | goto remove_max_bus_bw_file; |
| 3149 | } |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 3150 | |
| 3151 | msm_host->auto_cmd21_attr.show = show_auto_cmd21; |
| 3152 | msm_host->auto_cmd21_attr.store = store_auto_cmd21; |
| 3153 | sysfs_attr_init(&msm_host->auto_cmd21_attr.attr); |
| 3154 | msm_host->auto_cmd21_attr.attr.name = "enable_auto_cmd21"; |
| 3155 | msm_host->auto_cmd21_attr.attr.mode = S_IRUGO | S_IWUSR; |
| 3156 | ret = device_create_file(&pdev->dev, &msm_host->auto_cmd21_attr); |
| 3157 | if (ret) { |
| 3158 | pr_err("%s: %s: failed creating auto-cmd21 attr: %d\n", |
| 3159 | mmc_hostname(host->mmc), __func__, ret); |
| 3160 | device_remove_file(&pdev->dev, &msm_host->auto_cmd21_attr); |
| 3161 | } |
| 3162 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3163 | /* Successful initialization */ |
| 3164 | goto out; |
| 3165 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3166 | remove_max_bus_bw_file: |
| 3167 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3168 | remove_host: |
| 3169 | dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 3170 | sdhci_remove_host(host, dead); |
| 3171 | vreg_deinit: |
| 3172 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 3173 | bus_unregister: |
| 3174 | if (msm_host->msm_bus_vote.client_handle) |
| 3175 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 3176 | sdhci_msm_bus_unregister(msm_host); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 3177 | sleep_clk_disable: |
| 3178 | if (!IS_ERR(msm_host->sleep_clk)) |
| 3179 | clk_disable_unprepare(msm_host->sleep_clk); |
| 3180 | ff_clk_disable: |
| 3181 | if (!IS_ERR(msm_host->ff_clk)) |
| 3182 | clk_disable_unprepare(msm_host->ff_clk); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3183 | clk_disable: |
| 3184 | if (!IS_ERR(msm_host->clk)) |
| 3185 | clk_disable_unprepare(msm_host->clk); |
| 3186 | pclk_disable: |
| 3187 | if (!IS_ERR(msm_host->pclk)) |
| 3188 | clk_disable_unprepare(msm_host->pclk); |
| 3189 | bus_clk_disable: |
| 3190 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 3191 | clk_disable_unprepare(msm_host->bus_clk); |
| 3192 | pltfm_free: |
| 3193 | sdhci_pltfm_free(pdev); |
| 3194 | out: |
| 3195 | pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__); |
| 3196 | return ret; |
| 3197 | } |
| 3198 | |
| 3199 | static int sdhci_msm_remove(struct platform_device *pdev) |
| 3200 | { |
| 3201 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 3202 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 3203 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 3204 | struct sdhci_msm_pltfm_data *pdata = msm_host->pdata; |
| 3205 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
| 3206 | 0xffffffff); |
| 3207 | |
| 3208 | pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__); |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3209 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) |
| 3210 | device_remove_file(&pdev->dev, &msm_host->polling); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3211 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3212 | sdhci_remove_host(host, dead); |
| 3213 | sdhci_pltfm_free(pdev); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3214 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3215 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 3216 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 3217 | sdhci_msm_setup_pins(pdata, true); |
| 3218 | sdhci_msm_setup_pins(pdata, false); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3219 | |
| 3220 | if (msm_host->msm_bus_vote.client_handle) { |
| 3221 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 3222 | sdhci_msm_bus_unregister(msm_host); |
| 3223 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3224 | return 0; |
| 3225 | } |
| 3226 | |
| 3227 | static const struct of_device_id sdhci_msm_dt_match[] = { |
| 3228 | {.compatible = "qcom,sdhci-msm"}, |
| 3229 | }; |
| 3230 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); |
| 3231 | |
| 3232 | static struct platform_driver sdhci_msm_driver = { |
| 3233 | .probe = sdhci_msm_probe, |
| 3234 | .remove = sdhci_msm_remove, |
| 3235 | .driver = { |
| 3236 | .name = "sdhci_msm", |
| 3237 | .owner = THIS_MODULE, |
| 3238 | .of_match_table = sdhci_msm_dt_match, |
| 3239 | }, |
| 3240 | }; |
| 3241 | |
| 3242 | module_platform_driver(sdhci_msm_driver); |
| 3243 | |
| 3244 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver"); |
| 3245 | MODULE_LICENSE("GPL v2"); |