Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 19 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 20 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 21 | #include <plat/mcspi.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 22 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 23 | #include "omap_hwmod_common_data.h" |
| 24 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 25 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 26 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 27 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 28 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 29 | /* |
| 30 | * OMAP2420 hardware module integration data |
| 31 | * |
| 32 | * ALl of the data in this section should be autogeneratable from the |
| 33 | * TI hardware database or other technical documentation. Data that |
| 34 | * is driver-specific or driver-kernel integration-specific belongs |
| 35 | * elsewhere. |
| 36 | */ |
| 37 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 38 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 39 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 40 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 41 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 42 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 43 | static struct omap_hwmod omap2420_gpio1_hwmod; |
| 44 | static struct omap_hwmod omap2420_gpio2_hwmod; |
| 45 | static struct omap_hwmod omap2420_gpio3_hwmod; |
| 46 | static struct omap_hwmod omap2420_gpio4_hwmod; |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 47 | static struct omap_hwmod omap2420_dma_system_hwmod; |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 48 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
| 49 | static struct omap_hwmod omap2420_mcspi2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 50 | |
| 51 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 52 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 53 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 54 | .slave = &omap2420_l4_core_hwmod, |
| 55 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 56 | }; |
| 57 | |
| 58 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 59 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 60 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 61 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 62 | .user = OCP_USER_MPU, |
| 63 | }; |
| 64 | |
| 65 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 66 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 67 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 71 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 72 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 76 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 77 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 78 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 79 | .masters = omap2420_l3_main_masters, |
| 80 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 81 | .slaves = omap2420_l3_main_slaves, |
| 82 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 83 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 84 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 88 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 89 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 90 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 91 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 92 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 93 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 94 | /* l4 core -> mcspi1 interface */ |
| 95 | static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { |
| 96 | { |
| 97 | .pa_start = 0x48098000, |
| 98 | .pa_end = 0x480980ff, |
| 99 | .flags = ADDR_TYPE_RT, |
| 100 | }, |
| 101 | }; |
| 102 | |
| 103 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
| 104 | .master = &omap2420_l4_core_hwmod, |
| 105 | .slave = &omap2420_mcspi1_hwmod, |
| 106 | .clk = "mcspi1_ick", |
| 107 | .addr = omap2420_mcspi1_addr_space, |
| 108 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), |
| 109 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 110 | }; |
| 111 | |
| 112 | /* l4 core -> mcspi2 interface */ |
| 113 | static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { |
| 114 | { |
| 115 | .pa_start = 0x4809a000, |
| 116 | .pa_end = 0x4809a0ff, |
| 117 | .flags = ADDR_TYPE_RT, |
| 118 | }, |
| 119 | }; |
| 120 | |
| 121 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
| 122 | .master = &omap2420_l4_core_hwmod, |
| 123 | .slave = &omap2420_mcspi2_hwmod, |
| 124 | .clk = "mcspi2_ick", |
| 125 | .addr = omap2420_mcspi2_addr_space, |
| 126 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), |
| 127 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 128 | }; |
| 129 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 130 | /* L4_CORE -> L4_WKUP interface */ |
| 131 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 132 | .master = &omap2420_l4_core_hwmod, |
| 133 | .slave = &omap2420_l4_wkup_hwmod, |
| 134 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 135 | }; |
| 136 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 137 | /* L4 CORE -> UART1 interface */ |
| 138 | static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { |
| 139 | { |
| 140 | .pa_start = OMAP2_UART1_BASE, |
| 141 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 142 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 143 | }, |
| 144 | }; |
| 145 | |
| 146 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 147 | .master = &omap2420_l4_core_hwmod, |
| 148 | .slave = &omap2420_uart1_hwmod, |
| 149 | .clk = "uart1_ick", |
| 150 | .addr = omap2420_uart1_addr_space, |
| 151 | .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), |
| 152 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 153 | }; |
| 154 | |
| 155 | /* L4 CORE -> UART2 interface */ |
| 156 | static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { |
| 157 | { |
| 158 | .pa_start = OMAP2_UART2_BASE, |
| 159 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 160 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 161 | }, |
| 162 | }; |
| 163 | |
| 164 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 165 | .master = &omap2420_l4_core_hwmod, |
| 166 | .slave = &omap2420_uart2_hwmod, |
| 167 | .clk = "uart2_ick", |
| 168 | .addr = omap2420_uart2_addr_space, |
| 169 | .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), |
| 170 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 171 | }; |
| 172 | |
| 173 | /* L4 PER -> UART3 interface */ |
| 174 | static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { |
| 175 | { |
| 176 | .pa_start = OMAP2_UART3_BASE, |
| 177 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 178 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 179 | }, |
| 180 | }; |
| 181 | |
| 182 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 183 | .master = &omap2420_l4_core_hwmod, |
| 184 | .slave = &omap2420_uart3_hwmod, |
| 185 | .clk = "uart3_ick", |
| 186 | .addr = omap2420_uart3_addr_space, |
| 187 | .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), |
| 188 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 189 | }; |
| 190 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 191 | /* I2C IP block address space length (in bytes) */ |
| 192 | #define OMAP2_I2C_AS_LEN 128 |
| 193 | |
| 194 | /* L4 CORE -> I2C1 interface */ |
| 195 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { |
| 196 | { |
| 197 | .pa_start = 0x48070000, |
| 198 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 199 | .flags = ADDR_TYPE_RT, |
| 200 | }, |
| 201 | }; |
| 202 | |
| 203 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 204 | .master = &omap2420_l4_core_hwmod, |
| 205 | .slave = &omap2420_i2c1_hwmod, |
| 206 | .clk = "i2c1_ick", |
| 207 | .addr = omap2420_i2c1_addr_space, |
| 208 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), |
| 209 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 210 | }; |
| 211 | |
| 212 | /* L4 CORE -> I2C2 interface */ |
| 213 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { |
| 214 | { |
| 215 | .pa_start = 0x48072000, |
| 216 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 217 | .flags = ADDR_TYPE_RT, |
| 218 | }, |
| 219 | }; |
| 220 | |
| 221 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 222 | .master = &omap2420_l4_core_hwmod, |
| 223 | .slave = &omap2420_i2c2_hwmod, |
| 224 | .clk = "i2c2_ick", |
| 225 | .addr = omap2420_i2c2_addr_space, |
| 226 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), |
| 227 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 228 | }; |
| 229 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 230 | /* Slave interfaces on the L4_CORE interconnect */ |
| 231 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 232 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 233 | }; |
| 234 | |
| 235 | /* Master interfaces on the L4_CORE interconnect */ |
| 236 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 237 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 238 | &omap2_l4_core__uart1, |
| 239 | &omap2_l4_core__uart2, |
| 240 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 241 | &omap2420_l4_core__i2c1, |
| 242 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | /* L4 CORE */ |
| 246 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 247 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 248 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 249 | .masters = omap2420_l4_core_masters, |
| 250 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 251 | .slaves = omap2420_l4_core_slaves, |
| 252 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 253 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 254 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 258 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 259 | &omap2420_l4_core__l4_wkup, |
| 260 | }; |
| 261 | |
| 262 | /* Master interfaces on the L4_WKUP interconnect */ |
| 263 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 264 | }; |
| 265 | |
| 266 | /* L4 WKUP */ |
| 267 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 268 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 269 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 270 | .masters = omap2420_l4_wkup_masters, |
| 271 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 272 | .slaves = omap2420_l4_wkup_slaves, |
| 273 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 275 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | /* Master interfaces on the MPU device */ |
| 279 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 280 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | /* MPU */ |
| 284 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 285 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 286 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 287 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 288 | .masters = omap2420_mpu_masters, |
| 289 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 290 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 291 | }; |
| 292 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 293 | /* |
| 294 | * IVA1 interface data |
| 295 | */ |
| 296 | |
| 297 | /* IVA <- L3 interface */ |
| 298 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 299 | .master = &omap2420_l3_main_hwmod, |
| 300 | .slave = &omap2420_iva_hwmod, |
| 301 | .clk = "iva1_ifck", |
| 302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 303 | }; |
| 304 | |
| 305 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 306 | &omap2420_l3__iva, |
| 307 | }; |
| 308 | |
| 309 | /* |
| 310 | * IVA2 (IVA2) |
| 311 | */ |
| 312 | |
| 313 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 314 | .name = "iva", |
| 315 | .class = &iva_hwmod_class, |
| 316 | .masters = omap2420_iva_masters, |
| 317 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 318 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 319 | }; |
| 320 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 321 | /* l4_wkup -> wd_timer2 */ |
| 322 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 323 | { |
| 324 | .pa_start = 0x48022000, |
| 325 | .pa_end = 0x4802207f, |
| 326 | .flags = ADDR_TYPE_RT |
| 327 | }, |
| 328 | }; |
| 329 | |
| 330 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 331 | .master = &omap2420_l4_wkup_hwmod, |
| 332 | .slave = &omap2420_wd_timer2_hwmod, |
| 333 | .clk = "mpu_wdt_ick", |
| 334 | .addr = omap2420_wd_timer2_addrs, |
| 335 | .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), |
| 336 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 337 | }; |
| 338 | |
| 339 | /* |
| 340 | * 'wd_timer' class |
| 341 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 342 | * overflow condition |
| 343 | */ |
| 344 | |
| 345 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 346 | .rev_offs = 0x0000, |
| 347 | .sysc_offs = 0x0010, |
| 348 | .syss_offs = 0x0014, |
| 349 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 350 | SYSC_HAS_AUTOIDLE), |
| 351 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 352 | }; |
| 353 | |
| 354 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 355 | .name = "wd_timer", |
| 356 | .sysc = &omap2420_wd_timer_sysc, |
| 357 | .pre_shutdown = &omap2_wd_timer_disable |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | /* wd_timer2 */ |
| 361 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 362 | &omap2420_l4_wkup__wd_timer2, |
| 363 | }; |
| 364 | |
| 365 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 366 | .name = "wd_timer2", |
| 367 | .class = &omap2420_wd_timer_hwmod_class, |
| 368 | .main_clk = "mpu_wdt_fck", |
| 369 | .prcm = { |
| 370 | .omap2 = { |
| 371 | .prcm_reg_id = 1, |
| 372 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 373 | .module_offs = WKUP_MOD, |
| 374 | .idlest_reg_id = 1, |
| 375 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 376 | }, |
| 377 | }, |
| 378 | .slaves = omap2420_wd_timer2_slaves, |
| 379 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 380 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 381 | }; |
| 382 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 383 | /* UART */ |
| 384 | |
| 385 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 386 | .rev_offs = 0x50, |
| 387 | .sysc_offs = 0x54, |
| 388 | .syss_offs = 0x58, |
| 389 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 390 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 391 | SYSC_HAS_AUTOIDLE), |
| 392 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 393 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 394 | }; |
| 395 | |
| 396 | static struct omap_hwmod_class uart_class = { |
| 397 | .name = "uart", |
| 398 | .sysc = &uart_sysc, |
| 399 | }; |
| 400 | |
| 401 | /* UART1 */ |
| 402 | |
| 403 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 404 | { .irq = INT_24XX_UART1_IRQ, }, |
| 405 | }; |
| 406 | |
| 407 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 408 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 409 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 410 | }; |
| 411 | |
| 412 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 413 | &omap2_l4_core__uart1, |
| 414 | }; |
| 415 | |
| 416 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 417 | .name = "uart1", |
| 418 | .mpu_irqs = uart1_mpu_irqs, |
| 419 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 420 | .sdma_reqs = uart1_sdma_reqs, |
| 421 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 422 | .main_clk = "uart1_fck", |
| 423 | .prcm = { |
| 424 | .omap2 = { |
| 425 | .module_offs = CORE_MOD, |
| 426 | .prcm_reg_id = 1, |
| 427 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 428 | .idlest_reg_id = 1, |
| 429 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 430 | }, |
| 431 | }, |
| 432 | .slaves = omap2420_uart1_slaves, |
| 433 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 434 | .class = &uart_class, |
| 435 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 436 | }; |
| 437 | |
| 438 | /* UART2 */ |
| 439 | |
| 440 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 441 | { .irq = INT_24XX_UART2_IRQ, }, |
| 442 | }; |
| 443 | |
| 444 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 445 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 446 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 447 | }; |
| 448 | |
| 449 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 450 | &omap2_l4_core__uart2, |
| 451 | }; |
| 452 | |
| 453 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 454 | .name = "uart2", |
| 455 | .mpu_irqs = uart2_mpu_irqs, |
| 456 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 457 | .sdma_reqs = uart2_sdma_reqs, |
| 458 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 459 | .main_clk = "uart2_fck", |
| 460 | .prcm = { |
| 461 | .omap2 = { |
| 462 | .module_offs = CORE_MOD, |
| 463 | .prcm_reg_id = 1, |
| 464 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 465 | .idlest_reg_id = 1, |
| 466 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 467 | }, |
| 468 | }, |
| 469 | .slaves = omap2420_uart2_slaves, |
| 470 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 471 | .class = &uart_class, |
| 472 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 473 | }; |
| 474 | |
| 475 | /* UART3 */ |
| 476 | |
| 477 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 478 | { .irq = INT_24XX_UART3_IRQ, }, |
| 479 | }; |
| 480 | |
| 481 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 482 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 483 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 484 | }; |
| 485 | |
| 486 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 487 | &omap2_l4_core__uart3, |
| 488 | }; |
| 489 | |
| 490 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 491 | .name = "uart3", |
| 492 | .mpu_irqs = uart3_mpu_irqs, |
| 493 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 494 | .sdma_reqs = uart3_sdma_reqs, |
| 495 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 496 | .main_clk = "uart3_fck", |
| 497 | .prcm = { |
| 498 | .omap2 = { |
| 499 | .module_offs = CORE_MOD, |
| 500 | .prcm_reg_id = 2, |
| 501 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 502 | .idlest_reg_id = 2, |
| 503 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 504 | }, |
| 505 | }, |
| 506 | .slaves = omap2420_uart3_slaves, |
| 507 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 508 | .class = &uart_class, |
| 509 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 510 | }; |
| 511 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 512 | /* I2C common */ |
| 513 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 514 | .rev_offs = 0x00, |
| 515 | .sysc_offs = 0x20, |
| 516 | .syss_offs = 0x10, |
| 517 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 518 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 519 | }; |
| 520 | |
| 521 | static struct omap_hwmod_class i2c_class = { |
| 522 | .name = "i2c", |
| 523 | .sysc = &i2c_sysc, |
| 524 | }; |
| 525 | |
| 526 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 527 | |
| 528 | /* I2C1 */ |
| 529 | |
| 530 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 531 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 532 | }; |
| 533 | |
| 534 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 535 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 536 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 537 | }; |
| 538 | |
| 539 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 540 | &omap2420_l4_core__i2c1, |
| 541 | }; |
| 542 | |
| 543 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 544 | .name = "i2c1", |
| 545 | .mpu_irqs = i2c1_mpu_irqs, |
| 546 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 547 | .sdma_reqs = i2c1_sdma_reqs, |
| 548 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 549 | .main_clk = "i2c1_fck", |
| 550 | .prcm = { |
| 551 | .omap2 = { |
| 552 | .module_offs = CORE_MOD, |
| 553 | .prcm_reg_id = 1, |
| 554 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 555 | .idlest_reg_id = 1, |
| 556 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 557 | }, |
| 558 | }, |
| 559 | .slaves = omap2420_i2c1_slaves, |
| 560 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 561 | .class = &i2c_class, |
| 562 | .dev_attr = &i2c_dev_attr, |
| 563 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 564 | .flags = HWMOD_16BIT_REG, |
| 565 | }; |
| 566 | |
| 567 | /* I2C2 */ |
| 568 | |
| 569 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 570 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 571 | }; |
| 572 | |
| 573 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 574 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 575 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 576 | }; |
| 577 | |
| 578 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 579 | &omap2420_l4_core__i2c2, |
| 580 | }; |
| 581 | |
| 582 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 583 | .name = "i2c2", |
| 584 | .mpu_irqs = i2c2_mpu_irqs, |
| 585 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 586 | .sdma_reqs = i2c2_sdma_reqs, |
| 587 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 588 | .main_clk = "i2c2_fck", |
| 589 | .prcm = { |
| 590 | .omap2 = { |
| 591 | .module_offs = CORE_MOD, |
| 592 | .prcm_reg_id = 1, |
| 593 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 594 | .idlest_reg_id = 1, |
| 595 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 596 | }, |
| 597 | }, |
| 598 | .slaves = omap2420_i2c2_slaves, |
| 599 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 600 | .class = &i2c_class, |
| 601 | .dev_attr = &i2c_dev_attr, |
| 602 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 603 | .flags = HWMOD_16BIT_REG, |
| 604 | }; |
| 605 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 606 | /* l4_wkup -> gpio1 */ |
| 607 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 608 | { |
| 609 | .pa_start = 0x48018000, |
| 610 | .pa_end = 0x480181ff, |
| 611 | .flags = ADDR_TYPE_RT |
| 612 | }, |
| 613 | }; |
| 614 | |
| 615 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 616 | .master = &omap2420_l4_wkup_hwmod, |
| 617 | .slave = &omap2420_gpio1_hwmod, |
| 618 | .clk = "gpios_ick", |
| 619 | .addr = omap2420_gpio1_addr_space, |
| 620 | .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), |
| 621 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 622 | }; |
| 623 | |
| 624 | /* l4_wkup -> gpio2 */ |
| 625 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 626 | { |
| 627 | .pa_start = 0x4801a000, |
| 628 | .pa_end = 0x4801a1ff, |
| 629 | .flags = ADDR_TYPE_RT |
| 630 | }, |
| 631 | }; |
| 632 | |
| 633 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 634 | .master = &omap2420_l4_wkup_hwmod, |
| 635 | .slave = &omap2420_gpio2_hwmod, |
| 636 | .clk = "gpios_ick", |
| 637 | .addr = omap2420_gpio2_addr_space, |
| 638 | .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), |
| 639 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 640 | }; |
| 641 | |
| 642 | /* l4_wkup -> gpio3 */ |
| 643 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 644 | { |
| 645 | .pa_start = 0x4801c000, |
| 646 | .pa_end = 0x4801c1ff, |
| 647 | .flags = ADDR_TYPE_RT |
| 648 | }, |
| 649 | }; |
| 650 | |
| 651 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 652 | .master = &omap2420_l4_wkup_hwmod, |
| 653 | .slave = &omap2420_gpio3_hwmod, |
| 654 | .clk = "gpios_ick", |
| 655 | .addr = omap2420_gpio3_addr_space, |
| 656 | .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), |
| 657 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 658 | }; |
| 659 | |
| 660 | /* l4_wkup -> gpio4 */ |
| 661 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 662 | { |
| 663 | .pa_start = 0x4801e000, |
| 664 | .pa_end = 0x4801e1ff, |
| 665 | .flags = ADDR_TYPE_RT |
| 666 | }, |
| 667 | }; |
| 668 | |
| 669 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 670 | .master = &omap2420_l4_wkup_hwmod, |
| 671 | .slave = &omap2420_gpio4_hwmod, |
| 672 | .clk = "gpios_ick", |
| 673 | .addr = omap2420_gpio4_addr_space, |
| 674 | .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), |
| 675 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 676 | }; |
| 677 | |
| 678 | /* gpio dev_attr */ |
| 679 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 680 | .bank_width = 32, |
| 681 | .dbck_flag = false, |
| 682 | }; |
| 683 | |
| 684 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { |
| 685 | .rev_offs = 0x0000, |
| 686 | .sysc_offs = 0x0010, |
| 687 | .syss_offs = 0x0014, |
| 688 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 689 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 690 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 691 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 692 | }; |
| 693 | |
| 694 | /* |
| 695 | * 'gpio' class |
| 696 | * general purpose io module |
| 697 | */ |
| 698 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { |
| 699 | .name = "gpio", |
| 700 | .sysc = &omap242x_gpio_sysc, |
| 701 | .rev = 0, |
| 702 | }; |
| 703 | |
| 704 | /* gpio1 */ |
| 705 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { |
| 706 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ |
| 707 | }; |
| 708 | |
| 709 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
| 710 | &omap2420_l4_wkup__gpio1, |
| 711 | }; |
| 712 | |
| 713 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 714 | .name = "gpio1", |
| 715 | .mpu_irqs = omap242x_gpio1_irqs, |
| 716 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), |
| 717 | .main_clk = "gpios_fck", |
| 718 | .prcm = { |
| 719 | .omap2 = { |
| 720 | .prcm_reg_id = 1, |
| 721 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 722 | .module_offs = WKUP_MOD, |
| 723 | .idlest_reg_id = 1, |
| 724 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 725 | }, |
| 726 | }, |
| 727 | .slaves = omap2420_gpio1_slaves, |
| 728 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), |
| 729 | .class = &omap242x_gpio_hwmod_class, |
| 730 | .dev_attr = &gpio_dev_attr, |
| 731 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 732 | }; |
| 733 | |
| 734 | /* gpio2 */ |
| 735 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { |
| 736 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ |
| 737 | }; |
| 738 | |
| 739 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
| 740 | &omap2420_l4_wkup__gpio2, |
| 741 | }; |
| 742 | |
| 743 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 744 | .name = "gpio2", |
| 745 | .mpu_irqs = omap242x_gpio2_irqs, |
| 746 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), |
| 747 | .main_clk = "gpios_fck", |
| 748 | .prcm = { |
| 749 | .omap2 = { |
| 750 | .prcm_reg_id = 1, |
| 751 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 752 | .module_offs = WKUP_MOD, |
| 753 | .idlest_reg_id = 1, |
| 754 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 755 | }, |
| 756 | }, |
| 757 | .slaves = omap2420_gpio2_slaves, |
| 758 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), |
| 759 | .class = &omap242x_gpio_hwmod_class, |
| 760 | .dev_attr = &gpio_dev_attr, |
| 761 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 762 | }; |
| 763 | |
| 764 | /* gpio3 */ |
| 765 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { |
| 766 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ |
| 767 | }; |
| 768 | |
| 769 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
| 770 | &omap2420_l4_wkup__gpio3, |
| 771 | }; |
| 772 | |
| 773 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 774 | .name = "gpio3", |
| 775 | .mpu_irqs = omap242x_gpio3_irqs, |
| 776 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), |
| 777 | .main_clk = "gpios_fck", |
| 778 | .prcm = { |
| 779 | .omap2 = { |
| 780 | .prcm_reg_id = 1, |
| 781 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 782 | .module_offs = WKUP_MOD, |
| 783 | .idlest_reg_id = 1, |
| 784 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 785 | }, |
| 786 | }, |
| 787 | .slaves = omap2420_gpio3_slaves, |
| 788 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), |
| 789 | .class = &omap242x_gpio_hwmod_class, |
| 790 | .dev_attr = &gpio_dev_attr, |
| 791 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 792 | }; |
| 793 | |
| 794 | /* gpio4 */ |
| 795 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { |
| 796 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ |
| 797 | }; |
| 798 | |
| 799 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
| 800 | &omap2420_l4_wkup__gpio4, |
| 801 | }; |
| 802 | |
| 803 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 804 | .name = "gpio4", |
| 805 | .mpu_irqs = omap242x_gpio4_irqs, |
| 806 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), |
| 807 | .main_clk = "gpios_fck", |
| 808 | .prcm = { |
| 809 | .omap2 = { |
| 810 | .prcm_reg_id = 1, |
| 811 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 812 | .module_offs = WKUP_MOD, |
| 813 | .idlest_reg_id = 1, |
| 814 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 815 | }, |
| 816 | }, |
| 817 | .slaves = omap2420_gpio4_slaves, |
| 818 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), |
| 819 | .class = &omap242x_gpio_hwmod_class, |
| 820 | .dev_attr = &gpio_dev_attr, |
| 821 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 822 | }; |
| 823 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 824 | /* system dma */ |
| 825 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { |
| 826 | .rev_offs = 0x0000, |
| 827 | .sysc_offs = 0x002c, |
| 828 | .syss_offs = 0x0028, |
| 829 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 830 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
| 831 | SYSC_HAS_AUTOIDLE), |
| 832 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 833 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 834 | }; |
| 835 | |
| 836 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { |
| 837 | .name = "dma", |
| 838 | .sysc = &omap2420_dma_sysc, |
| 839 | }; |
| 840 | |
| 841 | /* dma attributes */ |
| 842 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 843 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 844 | IS_CSSA_32 | IS_CDSA_32, |
| 845 | .lch_count = 32, |
| 846 | }; |
| 847 | |
| 848 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { |
| 849 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ |
| 850 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ |
| 851 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ |
| 852 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ |
| 853 | }; |
| 854 | |
| 855 | static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { |
| 856 | { |
| 857 | .pa_start = 0x48056000, |
| 858 | .pa_end = 0x4a0560ff, |
| 859 | .flags = ADDR_TYPE_RT |
| 860 | }, |
| 861 | }; |
| 862 | |
| 863 | /* dma_system -> L3 */ |
| 864 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 865 | .master = &omap2420_dma_system_hwmod, |
| 866 | .slave = &omap2420_l3_main_hwmod, |
| 867 | .clk = "core_l3_ck", |
| 868 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 869 | }; |
| 870 | |
| 871 | /* dma_system master ports */ |
| 872 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { |
| 873 | &omap2420_dma_system__l3, |
| 874 | }; |
| 875 | |
| 876 | /* l4_core -> dma_system */ |
| 877 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
| 878 | .master = &omap2420_l4_core_hwmod, |
| 879 | .slave = &omap2420_dma_system_hwmod, |
| 880 | .clk = "sdma_ick", |
| 881 | .addr = omap2420_dma_system_addrs, |
| 882 | .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), |
| 883 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 884 | }; |
| 885 | |
| 886 | /* dma_system slave ports */ |
| 887 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { |
| 888 | &omap2420_l4_core__dma_system, |
| 889 | }; |
| 890 | |
| 891 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 892 | .name = "dma", |
| 893 | .class = &omap2420_dma_hwmod_class, |
| 894 | .mpu_irqs = omap2420_dma_system_irqs, |
| 895 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), |
| 896 | .main_clk = "core_l3_ck", |
| 897 | .slaves = omap2420_dma_system_slaves, |
| 898 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), |
| 899 | .masters = omap2420_dma_system_masters, |
| 900 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), |
| 901 | .dev_attr = &dma_dev_attr, |
| 902 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 903 | .flags = HWMOD_NO_IDLEST, |
| 904 | }; |
| 905 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 906 | /* |
| 907 | * 'mcspi' class |
| 908 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 909 | * bus |
| 910 | */ |
| 911 | |
| 912 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { |
| 913 | .rev_offs = 0x0000, |
| 914 | .sysc_offs = 0x0010, |
| 915 | .syss_offs = 0x0014, |
| 916 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 917 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 918 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 919 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 920 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 921 | }; |
| 922 | |
| 923 | static struct omap_hwmod_class omap2420_mcspi_class = { |
| 924 | .name = "mcspi", |
| 925 | .sysc = &omap2420_mcspi_sysc, |
| 926 | .rev = OMAP2_MCSPI_REV, |
| 927 | }; |
| 928 | |
| 929 | /* mcspi1 */ |
| 930 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { |
| 931 | { .irq = 65 }, |
| 932 | }; |
| 933 | |
| 934 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { |
| 935 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 936 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 937 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 938 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 939 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 940 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 941 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 942 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 943 | }; |
| 944 | |
| 945 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { |
| 946 | &omap2420_l4_core__mcspi1, |
| 947 | }; |
| 948 | |
| 949 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 950 | .num_chipselect = 4, |
| 951 | }; |
| 952 | |
| 953 | static struct omap_hwmod omap2420_mcspi1_hwmod = { |
| 954 | .name = "mcspi1_hwmod", |
| 955 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, |
| 956 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), |
| 957 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, |
| 958 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), |
| 959 | .main_clk = "mcspi1_fck", |
| 960 | .prcm = { |
| 961 | .omap2 = { |
| 962 | .module_offs = CORE_MOD, |
| 963 | .prcm_reg_id = 1, |
| 964 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 965 | .idlest_reg_id = 1, |
| 966 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 967 | }, |
| 968 | }, |
| 969 | .slaves = omap2420_mcspi1_slaves, |
| 970 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), |
| 971 | .class = &omap2420_mcspi_class, |
| 972 | .dev_attr = &omap_mcspi1_dev_attr, |
| 973 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 974 | }; |
| 975 | |
| 976 | /* mcspi2 */ |
| 977 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { |
| 978 | { .irq = 66 }, |
| 979 | }; |
| 980 | |
| 981 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { |
| 982 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 983 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 984 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 985 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 986 | }; |
| 987 | |
| 988 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { |
| 989 | &omap2420_l4_core__mcspi2, |
| 990 | }; |
| 991 | |
| 992 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 993 | .num_chipselect = 2, |
| 994 | }; |
| 995 | |
| 996 | static struct omap_hwmod omap2420_mcspi2_hwmod = { |
| 997 | .name = "mcspi2_hwmod", |
| 998 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, |
| 999 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), |
| 1000 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, |
| 1001 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), |
| 1002 | .main_clk = "mcspi2_fck", |
| 1003 | .prcm = { |
| 1004 | .omap2 = { |
| 1005 | .module_offs = CORE_MOD, |
| 1006 | .prcm_reg_id = 1, |
| 1007 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1008 | .idlest_reg_id = 1, |
| 1009 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 1010 | }, |
| 1011 | }, |
| 1012 | .slaves = omap2420_mcspi2_slaves, |
| 1013 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), |
| 1014 | .class = &omap2420_mcspi_class, |
| 1015 | .dev_attr = &omap_mcspi2_dev_attr, |
| 1016 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1017 | }; |
| 1018 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1019 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1020 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1021 | &omap2420_l4_core_hwmod, |
| 1022 | &omap2420_l4_wkup_hwmod, |
| 1023 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 1024 | &omap2420_iva_hwmod, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 1025 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1026 | &omap2420_uart1_hwmod, |
| 1027 | &omap2420_uart2_hwmod, |
| 1028 | &omap2420_uart3_hwmod, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1029 | &omap2420_i2c1_hwmod, |
| 1030 | &omap2420_i2c2_hwmod, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1031 | |
| 1032 | /* gpio class */ |
| 1033 | &omap2420_gpio1_hwmod, |
| 1034 | &omap2420_gpio2_hwmod, |
| 1035 | &omap2420_gpio3_hwmod, |
| 1036 | &omap2420_gpio4_hwmod, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1037 | |
| 1038 | /* dma_system class*/ |
| 1039 | &omap2420_dma_system_hwmod, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1040 | |
| 1041 | /* mcspi class */ |
| 1042 | &omap2420_mcspi1_hwmod, |
| 1043 | &omap2420_mcspi2_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1044 | NULL, |
| 1045 | }; |
| 1046 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1047 | int __init omap2420_hwmod_init(void) |
| 1048 | { |
| 1049 | return omap_hwmod_init(omap2420_hwmods); |
| 1050 | } |