blob: 682b1e7383704d81ecd4608fa8142b67529bc5df [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000028#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000029#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090030#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090031#include <linux/of.h>
32#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000033
34#include <mach/dma.h>
Arnd Bergmann436d42c2012-08-24 15:22:12 +020035#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000036
Thomas Abrahama5238e32012-07-13 07:15:14 +090037#define MAX_SPI_PORTS 3
38
Jassi Brar230d42d2009-11-30 07:39:42 +000039/* Registers and bit-fields */
40
41#define S3C64XX_SPI_CH_CFG 0x00
42#define S3C64XX_SPI_CLK_CFG 0x04
43#define S3C64XX_SPI_MODE_CFG 0x08
44#define S3C64XX_SPI_SLAVE_SEL 0x0C
45#define S3C64XX_SPI_INT_EN 0x10
46#define S3C64XX_SPI_STATUS 0x14
47#define S3C64XX_SPI_TX_DATA 0x18
48#define S3C64XX_SPI_RX_DATA 0x1C
49#define S3C64XX_SPI_PACKET_CNT 0x20
50#define S3C64XX_SPI_PENDING_CLR 0x24
51#define S3C64XX_SPI_SWAP_CFG 0x28
52#define S3C64XX_SPI_FB_CLK 0x2C
53
54#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
55#define S3C64XX_SPI_CH_SW_RST (1<<5)
56#define S3C64XX_SPI_CH_SLAVE (1<<4)
57#define S3C64XX_SPI_CPOL_L (1<<3)
58#define S3C64XX_SPI_CPHA_B (1<<2)
59#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
60#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
61
62#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
63#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
64#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090065#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000066
67#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
68#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
69#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
70#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
71#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
72#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
73#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
74#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
75#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
76#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
77#define S3C64XX_SPI_MODE_4BURST (1<<0)
78
79#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
80#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
81
Jassi Brar230d42d2009-11-30 07:39:42 +000082#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
83#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
84#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
85#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
86#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
87#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
88#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
89
90#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
91#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
92#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
93#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
94#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
95#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
96
97#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
98
99#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
100#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
101#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
102#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
103#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
104
105#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
106#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
107#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
108#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
109#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
110#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
111#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
112#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
113
114#define S3C64XX_SPI_FBCLK_MSK (3<<0)
115
Thomas Abrahama5238e32012-07-13 07:15:14 +0900116#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
117#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
118 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
119#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
120#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
121 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000122
123#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
124#define S3C64XX_SPI_TRAILCNT_OFF 19
125
126#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
127
128#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
129
Jassi Brar230d42d2009-11-30 07:39:42 +0000130#define RXBUSY (1<<2)
131#define TXBUSY (1<<3)
132
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900133struct s3c64xx_spi_dma_data {
134 unsigned ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000135 enum dma_transfer_direction direction;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900136 enum dma_ch dmach;
137};
138
Jassi Brar230d42d2009-11-30 07:39:42 +0000139/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900140 * struct s3c64xx_spi_info - SPI Controller hardware info
141 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
142 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
143 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
144 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
145 * @clk_from_cmu: True, if the controller does not include a clock mux and
146 * prescaler unit.
147 *
148 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
149 * differ in some aspects such as the size of the fifo and spi bus clock
150 * setup. Such differences are specified to the driver using this structure
151 * which is provided as driver data to the driver.
152 */
153struct s3c64xx_spi_port_config {
154 int fifo_lvl_mask[MAX_SPI_PORTS];
155 int rx_lvl_offset;
156 int tx_st_done;
157 bool high_speed;
158 bool clk_from_cmu;
159};
160
161/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000162 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
163 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700164 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000165 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000166 * @cntrlr_info: Platform specific data for the controller this driver manages.
167 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000168 * @queue: To log SPI xfer requests.
169 * @lock: Controller specific lock.
170 * @state: Set of FLAGS to indicate status.
171 * @rx_dmach: Controller's DMA channel for Rx.
172 * @tx_dmach: Controller's DMA channel for Tx.
173 * @sfr_start: BUS address of SPI controller regs.
174 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000175 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000176 * @xfer_completion: To indicate completion of xfer task.
177 * @cur_mode: Stores the active configuration of the controller.
178 * @cur_bpw: Stores the active bits per word settings.
179 * @cur_speed: Stores the active xfer clock speed.
180 */
181struct s3c64xx_spi_driver_data {
182 void __iomem *regs;
183 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700184 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000185 struct platform_device *pdev;
186 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700187 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000188 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000189 struct list_head queue;
190 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000191 unsigned long sfr_start;
192 struct completion xfer_completion;
193 unsigned state;
194 unsigned cur_mode, cur_bpw;
195 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900196 struct s3c64xx_spi_dma_data rx_dma;
197 struct s3c64xx_spi_dma_data tx_dma;
Boojin Kim39d3e802011-09-02 09:44:41 +0900198 struct samsung_dma_ops *ops;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900199 struct s3c64xx_spi_port_config *port_conf;
200 unsigned int port_id;
Thomas Abraham2b908072012-07-13 07:15:15 +0900201 unsigned long gpios[4];
Jassi Brar230d42d2009-11-30 07:39:42 +0000202};
203
204static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
205 .name = "samsung-spi-dma",
206};
207
208static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
209{
Jassi Brar230d42d2009-11-30 07:39:42 +0000210 void __iomem *regs = sdd->regs;
211 unsigned long loops;
212 u32 val;
213
214 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
215
216 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900217 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
218 writel(val, regs + S3C64XX_SPI_CH_CFG);
219
220 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000221 val |= S3C64XX_SPI_CH_SW_RST;
222 val &= ~S3C64XX_SPI_CH_HS_EN;
223 writel(val, regs + S3C64XX_SPI_CH_CFG);
224
225 /* Flush TxFIFO*/
226 loops = msecs_to_loops(1);
227 do {
228 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900229 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000230
Mark Brownbe7852a2010-08-23 17:40:56 +0100231 if (loops == 0)
232 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
233
Jassi Brar230d42d2009-11-30 07:39:42 +0000234 /* Flush RxFIFO*/
235 loops = msecs_to_loops(1);
236 do {
237 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900238 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000239 readl(regs + S3C64XX_SPI_RX_DATA);
240 else
241 break;
242 } while (loops--);
243
Mark Brownbe7852a2010-08-23 17:40:56 +0100244 if (loops == 0)
245 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
246
Jassi Brar230d42d2009-11-30 07:39:42 +0000247 val = readl(regs + S3C64XX_SPI_CH_CFG);
248 val &= ~S3C64XX_SPI_CH_SW_RST;
249 writel(val, regs + S3C64XX_SPI_CH_CFG);
250
251 val = readl(regs + S3C64XX_SPI_MODE_CFG);
252 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
253 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000254}
255
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900256static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900257{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900258 struct s3c64xx_spi_driver_data *sdd;
259 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900260 unsigned long flags;
261
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900262 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900263 sdd = container_of(data,
264 struct s3c64xx_spi_driver_data, rx_dma);
265 else
266 sdd = container_of(data,
267 struct s3c64xx_spi_driver_data, tx_dma);
268
Boojin Kim39d3e802011-09-02 09:44:41 +0900269 spin_lock_irqsave(&sdd->lock, flags);
270
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900271 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900272 sdd->state &= ~RXBUSY;
273 if (!(sdd->state & TXBUSY))
274 complete(&sdd->xfer_completion);
275 } else {
276 sdd->state &= ~TXBUSY;
277 if (!(sdd->state & RXBUSY))
278 complete(&sdd->xfer_completion);
279 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900280
281 spin_unlock_irqrestore(&sdd->lock, flags);
282}
283
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900284static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
285 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900286{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900287 struct s3c64xx_spi_driver_data *sdd;
Boojin Kim4969c322012-06-19 13:27:03 +0900288 struct samsung_dma_prep info;
289 struct samsung_dma_config config;
Boojin Kim39d3e802011-09-02 09:44:41 +0900290
Boojin Kim4969c322012-06-19 13:27:03 +0900291 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900292 sdd = container_of((void *)dma,
293 struct s3c64xx_spi_driver_data, rx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900294 config.direction = sdd->rx_dma.direction;
295 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
296 config.width = sdd->cur_bpw / 8;
297 sdd->ops->config(sdd->rx_dma.ch, &config);
298 } else {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900299 sdd = container_of((void *)dma,
300 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900301 config.direction = sdd->tx_dma.direction;
302 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
303 config.width = sdd->cur_bpw / 8;
304 sdd->ops->config(sdd->tx_dma.ch, &config);
305 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900306
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900307 info.cap = DMA_SLAVE;
308 info.len = len;
309 info.fp = s3c64xx_spi_dmacb;
310 info.fp_param = dma;
311 info.direction = dma->direction;
312 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900313
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900314 sdd->ops->prepare(dma->ch, &info);
315 sdd->ops->trigger(dma->ch);
316}
317
318static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
319{
Boojin Kim4969c322012-06-19 13:27:03 +0900320 struct samsung_dma_req req;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530321 struct device *dev = &sdd->pdev->dev;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900322
323 sdd->ops = samsung_dma_get_ops();
324
Boojin Kim4969c322012-06-19 13:27:03 +0900325 req.cap = DMA_SLAVE;
326 req.client = &s3c64xx_spi_dma_client;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900327
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530328 sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
329 sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900330
331 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900332}
333
Jassi Brar230d42d2009-11-30 07:39:42 +0000334static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
335 struct spi_device *spi,
336 struct spi_transfer *xfer, int dma_mode)
337{
Jassi Brar230d42d2009-11-30 07:39:42 +0000338 void __iomem *regs = sdd->regs;
339 u32 modecfg, chcfg;
340
341 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
342 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
343
344 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
345 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
346
347 if (dma_mode) {
348 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
349 } else {
350 /* Always shift in data in FIFO, even if xfer is Tx only,
351 * this helps setting PCKT_CNT value for generating clocks
352 * as exactly needed.
353 */
354 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
355 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
356 | S3C64XX_SPI_PACKET_CNT_EN,
357 regs + S3C64XX_SPI_PACKET_CNT);
358 }
359
360 if (xfer->tx_buf != NULL) {
361 sdd->state |= TXBUSY;
362 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
363 if (dma_mode) {
364 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900365 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000366 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900367 switch (sdd->cur_bpw) {
368 case 32:
369 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
370 xfer->tx_buf, xfer->len / 4);
371 break;
372 case 16:
373 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
374 xfer->tx_buf, xfer->len / 2);
375 break;
376 default:
377 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
378 xfer->tx_buf, xfer->len);
379 break;
380 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000381 }
382 }
383
384 if (xfer->rx_buf != NULL) {
385 sdd->state |= RXBUSY;
386
Thomas Abrahama5238e32012-07-13 07:15:14 +0900387 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000388 && !(sdd->cur_mode & SPI_CPHA))
389 chcfg |= S3C64XX_SPI_CH_HS_EN;
390
391 if (dma_mode) {
392 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
393 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
394 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
395 | S3C64XX_SPI_PACKET_CNT_EN,
396 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900397 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000398 }
399 }
400
401 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
402 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
403}
404
405static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
406 struct spi_device *spi)
407{
408 struct s3c64xx_spi_csinfo *cs;
409
410 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
411 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
412 /* Deselect the last toggled device */
413 cs = sdd->tgl_spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900414 gpio_set_value(cs->line,
415 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000416 }
417 sdd->tgl_spi = NULL;
418 }
419
420 cs = spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900421 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Jassi Brar230d42d2009-11-30 07:39:42 +0000422}
423
424static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
425 struct spi_transfer *xfer, int dma_mode)
426{
Jassi Brar230d42d2009-11-30 07:39:42 +0000427 void __iomem *regs = sdd->regs;
428 unsigned long val;
429 int ms;
430
431 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
432 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100433 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000434
435 if (dma_mode) {
436 val = msecs_to_jiffies(ms) + 10;
437 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
438 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900439 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000440 val = msecs_to_loops(ms);
441 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900442 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900443 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000444 }
445
446 if (!val)
447 return -EIO;
448
449 if (dma_mode) {
450 u32 status;
451
452 /*
453 * DmaTx returns after simply writing data in the FIFO,
454 * w/o waiting for real transmission on the bus to finish.
455 * DmaRx returns only after Dma read data from FIFO which
456 * needs bus transmission to finish, so we don't worry if
457 * Xfer involved Rx(with or without Tx).
458 */
459 if (xfer->rx_buf == NULL) {
460 val = msecs_to_loops(10);
461 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900462 while ((TX_FIFO_LVL(status, sdd)
463 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000464 && --val) {
465 cpu_relax();
466 status = readl(regs + S3C64XX_SPI_STATUS);
467 }
468
469 if (!val)
470 return -EIO;
471 }
472 } else {
Jassi Brar230d42d2009-11-30 07:39:42 +0000473 /* If it was only Tx */
474 if (xfer->rx_buf == NULL) {
475 sdd->state &= ~TXBUSY;
476 return 0;
477 }
478
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900479 switch (sdd->cur_bpw) {
480 case 32:
481 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
482 xfer->rx_buf, xfer->len / 4);
483 break;
484 case 16:
485 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
486 xfer->rx_buf, xfer->len / 2);
487 break;
488 default:
489 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
490 xfer->rx_buf, xfer->len);
491 break;
492 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000493 sdd->state &= ~RXBUSY;
494 }
495
496 return 0;
497}
498
499static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
500 struct spi_device *spi)
501{
502 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
503
504 if (sdd->tgl_spi == spi)
505 sdd->tgl_spi = NULL;
506
Thomas Abraham1c20c202012-07-13 07:15:14 +0900507 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000508}
509
510static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
511{
Jassi Brar230d42d2009-11-30 07:39:42 +0000512 void __iomem *regs = sdd->regs;
513 u32 val;
514
515 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900516 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900517 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900518 } else {
519 val = readl(regs + S3C64XX_SPI_CLK_CFG);
520 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
521 writel(val, regs + S3C64XX_SPI_CLK_CFG);
522 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000523
524 /* Set Polarity and Phase */
525 val = readl(regs + S3C64XX_SPI_CH_CFG);
526 val &= ~(S3C64XX_SPI_CH_SLAVE |
527 S3C64XX_SPI_CPOL_L |
528 S3C64XX_SPI_CPHA_B);
529
530 if (sdd->cur_mode & SPI_CPOL)
531 val |= S3C64XX_SPI_CPOL_L;
532
533 if (sdd->cur_mode & SPI_CPHA)
534 val |= S3C64XX_SPI_CPHA_B;
535
536 writel(val, regs + S3C64XX_SPI_CH_CFG);
537
538 /* Set Channel & DMA Mode */
539 val = readl(regs + S3C64XX_SPI_MODE_CFG);
540 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
541 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
542
543 switch (sdd->cur_bpw) {
544 case 32:
545 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900546 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000547 break;
548 case 16:
549 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900550 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000551 break;
552 default:
553 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900554 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000555 break;
556 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000557
558 writel(val, regs + S3C64XX_SPI_MODE_CFG);
559
Thomas Abrahama5238e32012-07-13 07:15:14 +0900560 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900561 /* Configure Clock */
562 /* There is half-multiplier before the SPI */
563 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
564 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900565 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900566 } else {
567 /* Configure Clock */
568 val = readl(regs + S3C64XX_SPI_CLK_CFG);
569 val &= ~S3C64XX_SPI_PSR_MASK;
570 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
571 & S3C64XX_SPI_PSR_MASK);
572 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000573
Jassi Brarb42a81c2010-09-29 17:31:33 +0900574 /* Enable Clock */
575 val = readl(regs + S3C64XX_SPI_CLK_CFG);
576 val |= S3C64XX_SPI_ENCLK_ENABLE;
577 writel(val, regs + S3C64XX_SPI_CLK_CFG);
578 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000579}
580
Jassi Brar230d42d2009-11-30 07:39:42 +0000581#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
582
583static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
584 struct spi_message *msg)
585{
586 struct device *dev = &sdd->pdev->dev;
587 struct spi_transfer *xfer;
588
589 if (msg->is_dma_mapped)
590 return 0;
591
592 /* First mark all xfer unmapped */
593 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
594 xfer->rx_dma = XFER_DMAADDR_INVALID;
595 xfer->tx_dma = XFER_DMAADDR_INVALID;
596 }
597
598 /* Map until end or first fail */
599 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
600
Thomas Abrahama5238e32012-07-13 07:15:14 +0900601 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900602 continue;
603
Jassi Brar230d42d2009-11-30 07:39:42 +0000604 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900605 xfer->tx_dma = dma_map_single(dev,
606 (void *)xfer->tx_buf, xfer->len,
607 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000608 if (dma_mapping_error(dev, xfer->tx_dma)) {
609 dev_err(dev, "dma_map_single Tx failed\n");
610 xfer->tx_dma = XFER_DMAADDR_INVALID;
611 return -ENOMEM;
612 }
613 }
614
615 if (xfer->rx_buf != NULL) {
616 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
617 xfer->len, DMA_FROM_DEVICE);
618 if (dma_mapping_error(dev, xfer->rx_dma)) {
619 dev_err(dev, "dma_map_single Rx failed\n");
620 dma_unmap_single(dev, xfer->tx_dma,
621 xfer->len, DMA_TO_DEVICE);
622 xfer->tx_dma = XFER_DMAADDR_INVALID;
623 xfer->rx_dma = XFER_DMAADDR_INVALID;
624 return -ENOMEM;
625 }
626 }
627 }
628
629 return 0;
630}
631
632static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
633 struct spi_message *msg)
634{
635 struct device *dev = &sdd->pdev->dev;
636 struct spi_transfer *xfer;
637
638 if (msg->is_dma_mapped)
639 return;
640
641 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
642
Thomas Abrahama5238e32012-07-13 07:15:14 +0900643 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900644 continue;
645
Jassi Brar230d42d2009-11-30 07:39:42 +0000646 if (xfer->rx_buf != NULL
647 && xfer->rx_dma != XFER_DMAADDR_INVALID)
648 dma_unmap_single(dev, xfer->rx_dma,
649 xfer->len, DMA_FROM_DEVICE);
650
651 if (xfer->tx_buf != NULL
652 && xfer->tx_dma != XFER_DMAADDR_INVALID)
653 dma_unmap_single(dev, xfer->tx_dma,
654 xfer->len, DMA_TO_DEVICE);
655 }
656}
657
Mark Brownad2a99a2012-02-15 14:48:32 -0800658static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
659 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000660{
Mark Brownad2a99a2012-02-15 14:48:32 -0800661 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000662 struct spi_device *spi = msg->spi;
663 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
664 struct spi_transfer *xfer;
665 int status = 0, cs_toggle = 0;
666 u32 speed;
667 u8 bpw;
668
669 /* If Master's(controller) state differs from that needed by Slave */
670 if (sdd->cur_speed != spi->max_speed_hz
671 || sdd->cur_mode != spi->mode
672 || sdd->cur_bpw != spi->bits_per_word) {
673 sdd->cur_bpw = spi->bits_per_word;
674 sdd->cur_speed = spi->max_speed_hz;
675 sdd->cur_mode = spi->mode;
676 s3c64xx_spi_config(sdd);
677 }
678
679 /* Map all the transfers if needed */
680 if (s3c64xx_spi_map_mssg(sdd, msg)) {
681 dev_err(&spi->dev,
682 "Xfer: Unable to map message buffers!\n");
683 status = -ENOMEM;
684 goto out;
685 }
686
687 /* Configure feedback delay */
688 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
689
690 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
691
692 unsigned long flags;
693 int use_dma;
694
695 INIT_COMPLETION(sdd->xfer_completion);
696
697 /* Only BPW and Speed may change across transfers */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530698 bpw = xfer->bits_per_word;
Jassi Brar230d42d2009-11-30 07:39:42 +0000699 speed = xfer->speed_hz ? : spi->max_speed_hz;
700
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900701 if (xfer->len % (bpw / 8)) {
702 dev_err(&spi->dev,
703 "Xfer length(%u) not a multiple of word size(%u)\n",
704 xfer->len, bpw / 8);
705 status = -EIO;
706 goto out;
707 }
708
Jassi Brar230d42d2009-11-30 07:39:42 +0000709 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
710 sdd->cur_bpw = bpw;
711 sdd->cur_speed = speed;
712 s3c64xx_spi_config(sdd);
713 }
714
715 /* Polling method for xfers not bigger than FIFO capacity */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900716 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brar230d42d2009-11-30 07:39:42 +0000717 use_dma = 0;
718 else
719 use_dma = 1;
720
721 spin_lock_irqsave(&sdd->lock, flags);
722
723 /* Pending only which is to be done */
724 sdd->state &= ~RXBUSY;
725 sdd->state &= ~TXBUSY;
726
727 enable_datapath(sdd, spi, xfer, use_dma);
728
729 /* Slave Select */
730 enable_cs(sdd, spi);
731
732 /* Start the signals */
Mark Brown5fc3e832012-07-19 14:36:23 +0900733 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000734
735 spin_unlock_irqrestore(&sdd->lock, flags);
736
737 status = wait_for_xfer(sdd, xfer, use_dma);
738
739 /* Quiese the signals */
Mark Brown5fc3e832012-07-19 14:36:23 +0900740 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
741 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000742
743 if (status) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900744 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000745 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
746 (sdd->state & RXBUSY) ? 'f' : 'p',
747 (sdd->state & TXBUSY) ? 'f' : 'p',
748 xfer->len);
749
750 if (use_dma) {
751 if (xfer->tx_buf != NULL
752 && (sdd->state & TXBUSY))
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900753 sdd->ops->stop(sdd->tx_dma.ch);
Jassi Brar230d42d2009-11-30 07:39:42 +0000754 if (xfer->rx_buf != NULL
755 && (sdd->state & RXBUSY))
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900756 sdd->ops->stop(sdd->rx_dma.ch);
Jassi Brar230d42d2009-11-30 07:39:42 +0000757 }
758
759 goto out;
760 }
761
762 if (xfer->delay_usecs)
763 udelay(xfer->delay_usecs);
764
765 if (xfer->cs_change) {
766 /* Hint that the next mssg is gonna be
767 for the same device */
768 if (list_is_last(&xfer->transfer_list,
769 &msg->transfers))
770 cs_toggle = 1;
Jassi Brar230d42d2009-11-30 07:39:42 +0000771 }
772
773 msg->actual_length += xfer->len;
774
775 flush_fifo(sdd);
776 }
777
778out:
779 if (!cs_toggle || status)
780 disable_cs(sdd, spi);
781 else
782 sdd->tgl_spi = spi;
783
784 s3c64xx_spi_unmap_mssg(sdd, msg);
785
786 msg->status = status;
787
Mark Brownad2a99a2012-02-15 14:48:32 -0800788 spi_finalize_current_message(master);
789
790 return 0;
Jassi Brar230d42d2009-11-30 07:39:42 +0000791}
792
Mark Brownad2a99a2012-02-15 14:48:32 -0800793static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
Jassi Brar230d42d2009-11-30 07:39:42 +0000794{
Mark Brownad2a99a2012-02-15 14:48:32 -0800795 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
Jassi Brar230d42d2009-11-30 07:39:42 +0000796
797 /* Acquire DMA channels */
798 while (!acquire_dma(sdd))
Jingoo Han75bf3362013-01-31 15:25:01 +0900799 usleep_range(10000, 11000);
Jassi Brar230d42d2009-11-30 07:39:42 +0000800
Mark Brownb97b6622011-12-04 00:58:06 +0000801 pm_runtime_get_sync(&sdd->pdev->dev);
802
Mark Brownad2a99a2012-02-15 14:48:32 -0800803 return 0;
804}
Jassi Brar230d42d2009-11-30 07:39:42 +0000805
Mark Brownad2a99a2012-02-15 14:48:32 -0800806static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
807{
808 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
Jassi Brar230d42d2009-11-30 07:39:42 +0000809
810 /* Free DMA channels */
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900811 sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
812 sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
Mark Brownb97b6622011-12-04 00:58:06 +0000813
814 pm_runtime_put(&sdd->pdev->dev);
Jassi Brar230d42d2009-11-30 07:39:42 +0000815
816 return 0;
817}
818
Thomas Abraham2b908072012-07-13 07:15:15 +0900819static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +0900820 struct spi_device *spi)
821{
822 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +0000823 struct device_node *slave_np, *data_np = NULL;
Thomas Abraham2b908072012-07-13 07:15:15 +0900824 u32 fb_delay = 0;
825
826 slave_np = spi->dev.of_node;
827 if (!slave_np) {
828 dev_err(&spi->dev, "device node not found\n");
829 return ERR_PTR(-EINVAL);
830 }
831
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100832 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +0900833 if (!data_np) {
834 dev_err(&spi->dev, "child node 'controller-data' not found\n");
835 return ERR_PTR(-EINVAL);
836 }
837
838 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
839 if (!cs) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900840 dev_err(&spi->dev, "could not allocate memory for controller data\n");
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100841 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900842 return ERR_PTR(-ENOMEM);
843 }
844
845 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
846 if (!gpio_is_valid(cs->line)) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900847 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
Thomas Abraham2b908072012-07-13 07:15:15 +0900848 kfree(cs);
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100849 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900850 return ERR_PTR(-EINVAL);
851 }
852
853 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
854 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100855 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900856 return cs;
857}
858
Jassi Brar230d42d2009-11-30 07:39:42 +0000859/*
860 * Here we only check the validity of requested configuration
861 * and save the configuration in a local data-structure.
862 * The controller is actually configured only just before we
863 * get a message to transfer.
864 */
865static int s3c64xx_spi_setup(struct spi_device *spi)
866{
867 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
868 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -0700869 struct s3c64xx_spi_info *sci;
Jassi Brar230d42d2009-11-30 07:39:42 +0000870 struct spi_message *msg;
Jassi Brar230d42d2009-11-30 07:39:42 +0000871 unsigned long flags;
Thomas Abraham2b908072012-07-13 07:15:15 +0900872 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +0000873
Thomas Abraham2b908072012-07-13 07:15:15 +0900874 sdd = spi_master_get_devdata(spi->master);
875 if (!cs && spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +0100876 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +0900877 spi->controller_data = cs;
878 }
879
880 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000881 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
882 return -ENODEV;
883 }
884
Thomas Abraham1c20c202012-07-13 07:15:14 +0900885 if (!spi_get_ctldata(spi)) {
Mark Brown707214d2012-07-19 14:36:16 +0900886 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
887 dev_name(&spi->dev));
Thomas Abraham1c20c202012-07-13 07:15:14 +0900888 if (err) {
Mark Brown49f3eac2012-07-19 14:36:13 +0900889 dev_err(&spi->dev,
890 "Failed to get /CS gpio [%d]: %d\n",
891 cs->line, err);
Thomas Abraham2b908072012-07-13 07:15:15 +0900892 goto err_gpio_req;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900893 }
894 spi_set_ctldata(spi, cs);
895 }
896
Jassi Brar230d42d2009-11-30 07:39:42 +0000897 sci = sdd->cntrlr_info;
898
899 spin_lock_irqsave(&sdd->lock, flags);
900
901 list_for_each_entry(msg, &sdd->queue, queue) {
902 /* Is some mssg is already queued for this device */
903 if (msg->spi == spi) {
904 dev_err(&spi->dev,
905 "setup: attempt while mssg in queue!\n");
906 spin_unlock_irqrestore(&sdd->lock, flags);
Thomas Abraham2b908072012-07-13 07:15:15 +0900907 err = -EBUSY;
908 goto err_msgq;
Jassi Brar230d42d2009-11-30 07:39:42 +0000909 }
910 }
911
Jassi Brar230d42d2009-11-30 07:39:42 +0000912 spin_unlock_irqrestore(&sdd->lock, flags);
913
Mark Brownb97b6622011-12-04 00:58:06 +0000914 pm_runtime_get_sync(&sdd->pdev->dev);
915
Jassi Brar230d42d2009-11-30 07:39:42 +0000916 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900917 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900918 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000919
Jassi Brarb42a81c2010-09-29 17:31:33 +0900920 /* Max possible */
921 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000922
Jassi Brarb42a81c2010-09-29 17:31:33 +0900923 if (spi->max_speed_hz > speed)
924 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000925
Jassi Brarb42a81c2010-09-29 17:31:33 +0900926 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
927 psr &= S3C64XX_SPI_PSR_MASK;
928 if (psr == S3C64XX_SPI_PSR_MASK)
929 psr--;
930
931 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
932 if (spi->max_speed_hz < speed) {
933 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
934 psr++;
935 } else {
936 err = -EINVAL;
937 goto setup_exit;
938 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000939 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000940
Jassi Brarb42a81c2010-09-29 17:31:33 +0900941 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +0900942 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900943 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +0900944 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +0000945 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
946 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900947 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +0900948 goto setup_exit;
949 }
Jassi Brarb42a81c2010-09-29 17:31:33 +0900950 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000951
Mark Brownb97b6622011-12-04 00:58:06 +0000952 pm_runtime_put(&sdd->pdev->dev);
Thomas Abraham2b908072012-07-13 07:15:15 +0900953 disable_cs(sdd, spi);
954 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +0000955
Jassi Brar230d42d2009-11-30 07:39:42 +0000956setup_exit:
Jassi Brar230d42d2009-11-30 07:39:42 +0000957 /* setup() returns with device de-selected */
958 disable_cs(sdd, spi);
959
Thomas Abraham2b908072012-07-13 07:15:15 +0900960err_msgq:
961 gpio_free(cs->line);
962 spi_set_ctldata(spi, NULL);
963
964err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +0200965 if (spi->dev.of_node)
966 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +0900967
Jassi Brar230d42d2009-11-30 07:39:42 +0000968 return err;
969}
970
Thomas Abraham1c20c202012-07-13 07:15:14 +0900971static void s3c64xx_spi_cleanup(struct spi_device *spi)
972{
973 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
974
Thomas Abraham2b908072012-07-13 07:15:15 +0900975 if (cs) {
Thomas Abraham1c20c202012-07-13 07:15:14 +0900976 gpio_free(cs->line);
Thomas Abraham2b908072012-07-13 07:15:15 +0900977 if (spi->dev.of_node)
978 kfree(cs);
979 }
Thomas Abraham1c20c202012-07-13 07:15:14 +0900980 spi_set_ctldata(spi, NULL);
981}
982
Mark Brownc2573122011-11-10 10:57:32 +0000983static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
984{
985 struct s3c64xx_spi_driver_data *sdd = data;
986 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +0530987 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +0000988
Girish K S375981f2013-03-13 12:13:30 +0530989 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +0000990
Girish K S375981f2013-03-13 12:13:30 +0530991 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
992 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000993 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530994 }
995 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
996 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000997 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530998 }
999 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1000 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001001 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301002 }
1003 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1004 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001005 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301006 }
1007
1008 /* Clear the pending irq by setting and then clearing it */
1009 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1010 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +00001011
1012 return IRQ_HANDLED;
1013}
1014
Jassi Brar230d42d2009-11-30 07:39:42 +00001015static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1016{
Jassi Brarad7de722010-01-20 13:49:44 -07001017 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001018 void __iomem *regs = sdd->regs;
1019 unsigned int val;
1020
1021 sdd->cur_speed = 0;
1022
Mark Brown5fc3e832012-07-19 14:36:23 +09001023 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +00001024
1025 /* Disable Interrupts - we use Polling if not DMA mode */
1026 writel(0, regs + S3C64XX_SPI_INT_EN);
1027
Thomas Abrahama5238e32012-07-13 07:15:14 +09001028 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +09001029 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +00001030 regs + S3C64XX_SPI_CLK_CFG);
1031 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1032 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1033
Girish K S375981f2013-03-13 12:13:30 +05301034 /* Clear any irq pending bits, should set and clear the bits */
1035 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1036 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1037 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1038 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1039 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1040 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +00001041
1042 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1043
1044 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1045 val &= ~S3C64XX_SPI_MODE_4BURST;
1046 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1047 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1048 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1049
1050 flush_fifo(sdd);
1051}
1052
Thomas Abraham2b908072012-07-13 07:15:15 +09001053#ifdef CONFIG_OF
1054static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1055{
1056 struct device *dev = &sdd->pdev->dev;
1057 int idx, gpio, ret;
1058
1059 /* find gpios for mosi, miso and clock lines */
1060 for (idx = 0; idx < 3; idx++) {
1061 gpio = of_get_gpio(dev->of_node, idx);
1062 if (!gpio_is_valid(gpio)) {
1063 dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1064 goto free_gpio;
1065 }
Abhilash Kesavan45e50332012-11-07 11:40:12 +05301066 sdd->gpios[idx] = gpio;
Thomas Abraham2b908072012-07-13 07:15:15 +09001067 ret = gpio_request(gpio, "spi-bus");
1068 if (ret) {
Mark Brown49f3eac2012-07-19 14:36:13 +09001069 dev_err(dev, "gpio [%d] request failed: %d\n",
1070 gpio, ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001071 goto free_gpio;
1072 }
1073 }
1074 return 0;
1075
1076free_gpio:
1077 while (--idx >= 0)
1078 gpio_free(sdd->gpios[idx]);
1079 return -EINVAL;
1080}
1081
1082static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1083{
1084 unsigned int idx;
1085 for (idx = 0; idx < 3; idx++)
1086 gpio_free(sdd->gpios[idx]);
1087}
1088
Jingoo Han75bf3362013-01-31 15:25:01 +09001089static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +09001090{
1091 struct s3c64xx_spi_info *sci;
1092 u32 temp;
1093
1094 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1095 if (!sci) {
1096 dev_err(dev, "memory allocation for spi_info failed\n");
1097 return ERR_PTR(-ENOMEM);
1098 }
1099
1100 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001101 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001102 sci->src_clk_nr = 0;
1103 } else {
1104 sci->src_clk_nr = temp;
1105 }
1106
1107 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001108 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001109 sci->num_cs = 1;
1110 } else {
1111 sci->num_cs = temp;
1112 }
1113
1114 return sci;
1115}
1116#else
1117static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1118{
1119 return dev->platform_data;
1120}
1121
1122static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1123{
1124 return -EINVAL;
1125}
1126
1127static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1128{
1129}
1130#endif
1131
1132static const struct of_device_id s3c64xx_spi_dt_match[];
1133
Thomas Abrahama5238e32012-07-13 07:15:14 +09001134static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1135 struct platform_device *pdev)
1136{
Thomas Abraham2b908072012-07-13 07:15:15 +09001137#ifdef CONFIG_OF
1138 if (pdev->dev.of_node) {
1139 const struct of_device_id *match;
1140 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1141 return (struct s3c64xx_spi_port_config *)match->data;
1142 }
1143#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001144 return (struct s3c64xx_spi_port_config *)
1145 platform_get_device_id(pdev)->driver_data;
1146}
1147
Grant Likely2deff8d2013-02-05 13:27:35 +00001148static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001149{
Thomas Abraham2b908072012-07-13 07:15:15 +09001150 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301151 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001152 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001153 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
Jassi Brar230d42d2009-11-30 07:39:42 +00001154 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001155 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001156 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001157
Thomas Abraham2b908072012-07-13 07:15:15 +09001158 if (!sci && pdev->dev.of_node) {
1159 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1160 if (IS_ERR(sci))
1161 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001162 }
1163
Thomas Abraham2b908072012-07-13 07:15:15 +09001164 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001165 dev_err(&pdev->dev, "platform_data missing!\n");
1166 return -ENODEV;
1167 }
1168
Jassi Brar230d42d2009-11-30 07:39:42 +00001169 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1170 if (mem_res == NULL) {
1171 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1172 return -ENXIO;
1173 }
1174
Mark Brownc2573122011-11-10 10:57:32 +00001175 irq = platform_get_irq(pdev, 0);
1176 if (irq < 0) {
1177 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1178 return irq;
1179 }
1180
Jassi Brar230d42d2009-11-30 07:39:42 +00001181 master = spi_alloc_master(&pdev->dev,
1182 sizeof(struct s3c64xx_spi_driver_data));
1183 if (master == NULL) {
1184 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1185 return -ENOMEM;
1186 }
1187
Jassi Brar230d42d2009-11-30 07:39:42 +00001188 platform_set_drvdata(pdev, master);
1189
1190 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001191 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001192 sdd->master = master;
1193 sdd->cntrlr_info = sci;
1194 sdd->pdev = pdev;
1195 sdd->sfr_start = mem_res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001196 if (pdev->dev.of_node) {
1197 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1198 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001199 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1200 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001201 goto err0;
1202 }
1203 sdd->port_id = ret;
1204 } else {
1205 sdd->port_id = pdev->id;
1206 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001207
1208 sdd->cur_bpw = 8;
1209
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301210 if (!sdd->pdev->dev.of_node) {
1211 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1212 if (!res) {
1213 dev_err(&pdev->dev, "Unable to get SPI tx dma "
1214 "resource\n");
1215 return -ENXIO;
1216 }
1217 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001218
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301219 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1220 if (!res) {
1221 dev_err(&pdev->dev, "Unable to get SPI rx dma "
1222 "resource\n");
1223 return -ENXIO;
1224 }
1225 sdd->rx_dma.dmach = res->start;
1226 }
1227
1228 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1229 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001230
1231 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001232 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001233 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001234 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001235 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1236 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1237 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001238 master->num_chipselect = sci->num_cs;
1239 master->dma_alignment = 8;
Mark Browne761f422013-04-01 14:17:37 +01001240 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001241 /* the spi->mode bits understood by this driver: */
1242 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1243
Thierry Redingb0ee5602013-01-21 11:09:18 +01001244 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1245 if (IS_ERR(sdd->regs)) {
1246 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001247 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001248 }
1249
Thomas Abraham2b908072012-07-13 07:15:15 +09001250 if (!sci->cfg_gpio && pdev->dev.of_node) {
1251 if (s3c64xx_spi_parse_dt_gpio(sdd))
1252 return -EBUSY;
1253 } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001254 dev_err(&pdev->dev, "Unable to config gpio\n");
1255 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001256 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001257 }
1258
1259 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001260 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001261 if (IS_ERR(sdd->clk)) {
1262 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1263 ret = PTR_ERR(sdd->clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001264 goto err1;
Jassi Brar230d42d2009-11-30 07:39:42 +00001265 }
1266
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001267 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001268 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1269 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001270 goto err1;
Jassi Brar230d42d2009-11-30 07:39:42 +00001271 }
1272
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001273 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001274 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001275 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001276 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001277 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001278 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001279 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001280 }
1281
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001282 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001283 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001284 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001285 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001286 }
1287
Jassi Brar230d42d2009-11-30 07:39:42 +00001288 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001289 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001290
1291 spin_lock_init(&sdd->lock);
1292 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001293 INIT_LIST_HEAD(&sdd->queue);
1294
Jingoo Han4eb77002013-01-10 11:04:21 +09001295 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1296 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001297 if (ret != 0) {
1298 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1299 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001300 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001301 }
1302
1303 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1304 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1305 sdd->regs + S3C64XX_SPI_INT_EN);
1306
Jassi Brar230d42d2009-11-30 07:39:42 +00001307 if (spi_register_master(master)) {
1308 dev_err(&pdev->dev, "cannot register SPI master\n");
1309 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001310 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001311 }
1312
Jingoo Han75bf3362013-01-31 15:25:01 +09001313 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001314 sdd->port_id, master->num_chipselect);
Joe Perches8a349d42010-02-02 07:22:13 +00001315 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
Jassi Brar230d42d2009-11-30 07:39:42 +00001316 mem_res->end, mem_res->start,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001317 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001318
Mark Brownb97b6622011-12-04 00:58:06 +00001319 pm_runtime_enable(&pdev->dev);
1320
Jassi Brar230d42d2009-11-30 07:39:42 +00001321 return 0;
1322
Jassi Brar230d42d2009-11-30 07:39:42 +00001323err3:
Jingoo Han4eb77002013-01-10 11:04:21 +09001324 clk_disable_unprepare(sdd->src_clk);
1325err2:
1326 clk_disable_unprepare(sdd->clk);
1327err1:
Thomas Abraham2b908072012-07-13 07:15:15 +09001328 if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1329 s3c64xx_spi_dt_gpio_free(sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +00001330err0:
1331 platform_set_drvdata(pdev, NULL);
1332 spi_master_put(master);
1333
1334 return ret;
1335}
1336
1337static int s3c64xx_spi_remove(struct platform_device *pdev)
1338{
1339 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1340 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001341
Mark Brownb97b6622011-12-04 00:58:06 +00001342 pm_runtime_disable(&pdev->dev);
1343
Jassi Brar230d42d2009-11-30 07:39:42 +00001344 spi_unregister_master(master);
1345
Mark Brownc2573122011-11-10 10:57:32 +00001346 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1347
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001348 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001349
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001350 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001351
Thomas Abraham2b908072012-07-13 07:15:15 +09001352 if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1353 s3c64xx_spi_dt_gpio_free(sdd);
1354
Jassi Brar230d42d2009-11-30 07:39:42 +00001355 platform_set_drvdata(pdev, NULL);
1356 spi_master_put(master);
1357
1358 return 0;
1359}
1360
Jingoo Han997230d2013-03-22 02:09:08 +00001361#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001362static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001363{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001364 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001365 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001366
Mark Brownad2a99a2012-02-15 14:48:32 -08001367 spi_master_suspend(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001368
1369 /* Disable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001370 clk_disable_unprepare(sdd->src_clk);
1371 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001372
Thomas Abraham2b908072012-07-13 07:15:15 +09001373 if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1374 s3c64xx_spi_dt_gpio_free(sdd);
1375
Jassi Brar230d42d2009-11-30 07:39:42 +00001376 sdd->cur_speed = 0; /* Output Clock is stopped */
1377
1378 return 0;
1379}
1380
Mark Browne25d0bf2011-12-04 00:36:18 +00001381static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001382{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001383 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001384 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001385 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001386
Thomas Abraham2b908072012-07-13 07:15:15 +09001387 if (!sci->cfg_gpio && dev->of_node)
1388 s3c64xx_spi_parse_dt_gpio(sdd);
1389 else
1390 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001391
1392 /* Enable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001393 clk_prepare_enable(sdd->src_clk);
1394 clk_prepare_enable(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001395
Thomas Abrahama5238e32012-07-13 07:15:14 +09001396 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001397
Mark Brownad2a99a2012-02-15 14:48:32 -08001398 spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001399
1400 return 0;
1401}
Jingoo Han997230d2013-03-22 02:09:08 +00001402#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001403
Mark Brownb97b6622011-12-04 00:58:06 +00001404#ifdef CONFIG_PM_RUNTIME
1405static int s3c64xx_spi_runtime_suspend(struct device *dev)
1406{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001407 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001408 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1409
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001410 clk_disable_unprepare(sdd->clk);
1411 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001412
1413 return 0;
1414}
1415
1416static int s3c64xx_spi_runtime_resume(struct device *dev)
1417{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001418 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001419 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1420
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001421 clk_prepare_enable(sdd->src_clk);
1422 clk_prepare_enable(sdd->clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001423
1424 return 0;
1425}
1426#endif /* CONFIG_PM_RUNTIME */
1427
Mark Browne25d0bf2011-12-04 00:36:18 +00001428static const struct dev_pm_ops s3c64xx_spi_pm = {
1429 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001430 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1431 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001432};
1433
Sachin Kamat10ce0472012-08-03 10:08:12 +05301434static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001435 .fifo_lvl_mask = { 0x7f },
1436 .rx_lvl_offset = 13,
1437 .tx_st_done = 21,
1438 .high_speed = true,
1439};
1440
Sachin Kamat10ce0472012-08-03 10:08:12 +05301441static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001442 .fifo_lvl_mask = { 0x7f, 0x7F },
1443 .rx_lvl_offset = 13,
1444 .tx_st_done = 21,
1445};
1446
Sachin Kamat10ce0472012-08-03 10:08:12 +05301447static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001448 .fifo_lvl_mask = { 0x1ff, 0x7F },
1449 .rx_lvl_offset = 15,
1450 .tx_st_done = 25,
1451};
1452
Sachin Kamat10ce0472012-08-03 10:08:12 +05301453static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001454 .fifo_lvl_mask = { 0x7f, 0x7F },
1455 .rx_lvl_offset = 13,
1456 .tx_st_done = 21,
1457 .high_speed = true,
1458};
1459
Sachin Kamat10ce0472012-08-03 10:08:12 +05301460static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001461 .fifo_lvl_mask = { 0x1ff, 0x7F },
1462 .rx_lvl_offset = 15,
1463 .tx_st_done = 25,
1464 .high_speed = true,
1465};
1466
Sachin Kamat10ce0472012-08-03 10:08:12 +05301467static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001468 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1469 .rx_lvl_offset = 15,
1470 .tx_st_done = 25,
1471 .high_speed = true,
1472 .clk_from_cmu = true,
1473};
1474
1475static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1476 {
1477 .name = "s3c2443-spi",
1478 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1479 }, {
1480 .name = "s3c6410-spi",
1481 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1482 }, {
1483 .name = "s5p64x0-spi",
1484 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1485 }, {
1486 .name = "s5pc100-spi",
1487 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1488 }, {
1489 .name = "s5pv210-spi",
1490 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1491 }, {
1492 .name = "exynos4210-spi",
1493 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1494 },
1495 { },
1496};
1497
Thomas Abraham2b908072012-07-13 07:15:15 +09001498#ifdef CONFIG_OF
1499static const struct of_device_id s3c64xx_spi_dt_match[] = {
1500 { .compatible = "samsung,exynos4210-spi",
1501 .data = (void *)&exynos4_spi_port_config,
1502 },
1503 { },
1504};
1505MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1506#endif /* CONFIG_OF */
1507
Jassi Brar230d42d2009-11-30 07:39:42 +00001508static struct platform_driver s3c64xx_spi_driver = {
1509 .driver = {
1510 .name = "s3c64xx-spi",
1511 .owner = THIS_MODULE,
Mark Browne25d0bf2011-12-04 00:36:18 +00001512 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001513 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001514 },
1515 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001516 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001517};
1518MODULE_ALIAS("platform:s3c64xx-spi");
1519
1520static int __init s3c64xx_spi_init(void)
1521{
1522 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1523}
Mark Brownd2a787f2010-09-07 11:29:17 +01001524subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001525
1526static void __exit s3c64xx_spi_exit(void)
1527{
1528 platform_driver_unregister(&s3c64xx_spi_driver);
1529}
1530module_exit(s3c64xx_spi_exit);
1531
1532MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1533MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1534MODULE_LICENSE("GPL");