Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge |
| 3 | * |
| 4 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file COPYING in the main directory of this archive for |
| 8 | * more details. |
| 9 | * |
| 10 | * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) |
| 11 | * which is based on the code of neofb. |
| 12 | */ |
| 13 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/string.h> |
| 18 | #include <linux/mm.h> |
| 19 | #include <linux/tty.h> |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/fb.h> |
| 22 | #include <linux/svga.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/pci.h> |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 25 | #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 26 | #include <video/vga.h> |
| 27 | |
| 28 | #ifdef CONFIG_MTRR |
| 29 | #include <asm/mtrr.h> |
| 30 | #endif |
| 31 | |
| 32 | struct s3fb_info { |
| 33 | int chip, rev, mclk_freq; |
| 34 | int mtrr_reg; |
| 35 | struct vgastate state; |
| 36 | struct mutex open_lock; |
| 37 | unsigned int ref_count; |
| 38 | u32 pseudo_palette[16]; |
| 39 | }; |
| 40 | |
| 41 | |
| 42 | /* ------------------------------------------------------------------------- */ |
| 43 | |
| 44 | static const struct svga_fb_format s3fb_formats[] = { |
| 45 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, |
| 46 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 47 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 48 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 49 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 50 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 51 | { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 52 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, |
| 53 | {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, |
| 54 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, |
| 55 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, |
| 56 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, |
| 57 | {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
| 58 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, |
| 59 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
| 60 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, |
| 61 | SVGA_FORMAT_END |
| 62 | }; |
| 63 | |
| 64 | |
| 65 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 66 | 35000, 240000, 14318}; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 67 | |
| 68 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; |
| 69 | |
| 70 | static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", |
| 71 | "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", |
| 72 | "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge", |
| 73 | "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 74 | "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P", |
| 75 | "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X"}; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 76 | |
| 77 | #define CHIP_UNKNOWN 0x00 |
| 78 | #define CHIP_732_TRIO32 0x01 |
| 79 | #define CHIP_764_TRIO64 0x02 |
| 80 | #define CHIP_765_TRIO64VP 0x03 |
| 81 | #define CHIP_767_TRIO64UVP 0x04 |
| 82 | #define CHIP_775_TRIO64V2_DX 0x05 |
| 83 | #define CHIP_785_TRIO64V2_GX 0x06 |
| 84 | #define CHIP_551_PLATO_PX 0x07 |
| 85 | #define CHIP_M65_AURORA64VP 0x08 |
| 86 | #define CHIP_325_VIRGE 0x09 |
| 87 | #define CHIP_988_VIRGE_VX 0x0A |
| 88 | #define CHIP_375_VIRGE_DX 0x0B |
| 89 | #define CHIP_385_VIRGE_GX 0x0C |
| 90 | #define CHIP_356_VIRGE_GX2 0x0D |
| 91 | #define CHIP_357_VIRGE_GX2P 0x0E |
| 92 | #define CHIP_359_VIRGE_GX2P 0x0F |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 93 | #define CHIP_360_TRIO3D_1X 0x10 |
| 94 | #define CHIP_362_TRIO3D_2X 0x11 |
| 95 | #define CHIP_368_TRIO3D_2X 0x12 |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 96 | |
| 97 | #define CHIP_XXX_TRIO 0x80 |
| 98 | #define CHIP_XXX_TRIO64V2_DXGX 0x81 |
| 99 | #define CHIP_XXX_VIRGE_DXGX 0x82 |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 100 | #define CHIP_36X_TRIO3D_1X_2X 0x83 |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 101 | |
| 102 | #define CHIP_UNDECIDED_FLAG 0x80 |
| 103 | #define CHIP_MASK 0xFF |
| 104 | |
| 105 | /* CRT timing register sets */ |
| 106 | |
| 107 | static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; |
| 108 | static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; |
| 109 | static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; |
| 110 | static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; |
| 111 | static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; |
| 112 | static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; |
| 113 | |
| 114 | static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; |
| 115 | static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; |
| 116 | static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; |
| 117 | static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; |
| 118 | static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; |
| 119 | static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; |
| 120 | |
| 121 | static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; |
| 122 | static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END}; |
| 123 | static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ |
| 124 | |
| 125 | static const struct svga_timing_regs s3_timing_regs = { |
| 126 | s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, |
| 127 | s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, |
| 128 | s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, |
| 129 | s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, |
| 130 | }; |
| 131 | |
| 132 | |
| 133 | /* ------------------------------------------------------------------------- */ |
| 134 | |
| 135 | /* Module parameters */ |
| 136 | |
| 137 | |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 138 | static char *mode_option __devinitdata = "640x480-8@60"; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 139 | |
| 140 | #ifdef CONFIG_MTRR |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 141 | static int mtrr __devinitdata = 1; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 142 | #endif |
| 143 | |
| 144 | static int fasttext = 1; |
| 145 | |
| 146 | |
| 147 | MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); |
| 148 | MODULE_LICENSE("GPL"); |
| 149 | MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); |
| 150 | |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 151 | module_param(mode_option, charp, 0444); |
| 152 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); |
| 153 | module_param_named(mode, mode_option, charp, 0444); |
| 154 | MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 155 | |
| 156 | #ifdef CONFIG_MTRR |
| 157 | module_param(mtrr, int, 0444); |
| 158 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); |
| 159 | #endif |
| 160 | |
| 161 | module_param(fasttext, int, 0644); |
| 162 | MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); |
| 163 | |
| 164 | |
| 165 | /* ------------------------------------------------------------------------- */ |
| 166 | |
| 167 | /* Set font in S3 fast text mode */ |
| 168 | |
| 169 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) |
| 170 | { |
| 171 | const u8 *font = map->data; |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 172 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 173 | int i, c; |
| 174 | |
| 175 | if ((map->width != 8) || (map->height != 16) || |
| 176 | (map->depth != 1) || (map->length != 256)) { |
| 177 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
| 178 | info->node, map->width, map->height, map->depth, map->length); |
| 179 | return; |
| 180 | } |
| 181 | |
| 182 | fb += 2; |
| 183 | for (i = 0; i < map->height; i++) { |
| 184 | for (c = 0; c < map->length; c++) { |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 185 | fb_writeb(font[c * map->height + i], fb + c * 4); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 186 | } |
| 187 | fb += 1024; |
| 188 | } |
| 189 | } |
| 190 | |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 191 | static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) |
| 192 | { |
| 193 | struct s3fb_info *par = info->par; |
| 194 | |
| 195 | svga_tilecursor(par->state.vgabase, info, cursor); |
| 196 | } |
| 197 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 198 | static struct fb_tile_ops s3fb_tile_ops = { |
| 199 | .fb_settile = svga_settile, |
| 200 | .fb_tilecopy = svga_tilecopy, |
| 201 | .fb_tilefill = svga_tilefill, |
| 202 | .fb_tileblit = svga_tileblit, |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 203 | .fb_tilecursor = s3fb_tilecursor, |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 204 | .fb_get_tilemax = svga_get_tilemax, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | static struct fb_tile_ops s3fb_fast_tile_ops = { |
| 208 | .fb_settile = s3fb_settile_fast, |
| 209 | .fb_tilecopy = svga_tilecopy, |
| 210 | .fb_tilefill = svga_tilefill, |
| 211 | .fb_tileblit = svga_tileblit, |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 212 | .fb_tilecursor = s3fb_tilecursor, |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 213 | .fb_get_tilemax = svga_get_tilemax, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | |
| 217 | /* ------------------------------------------------------------------------- */ |
| 218 | |
| 219 | /* image data is MSB-first, fb structure is MSB-first too */ |
| 220 | static inline u32 expand_color(u32 c) |
| 221 | { |
| 222 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; |
| 223 | } |
| 224 | |
| 225 | /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ |
| 226 | static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) |
| 227 | { |
| 228 | u32 fg = expand_color(image->fg_color); |
| 229 | u32 bg = expand_color(image->bg_color); |
| 230 | const u8 *src1, *src; |
| 231 | u8 __iomem *dst1; |
| 232 | u32 __iomem *dst; |
| 233 | u32 val; |
| 234 | int x, y; |
| 235 | |
| 236 | src1 = image->data; |
| 237 | dst1 = info->screen_base + (image->dy * info->fix.line_length) |
| 238 | + ((image->dx / 8) * 4); |
| 239 | |
| 240 | for (y = 0; y < image->height; y++) { |
| 241 | src = src1; |
| 242 | dst = (u32 __iomem *) dst1; |
| 243 | for (x = 0; x < image->width; x += 8) { |
| 244 | val = *(src++) * 0x01010101; |
| 245 | val = (val & fg) | (~val & bg); |
| 246 | fb_writel(val, dst++); |
| 247 | } |
| 248 | src1 += image->width / 8; |
| 249 | dst1 += info->fix.line_length; |
| 250 | } |
| 251 | |
| 252 | } |
| 253 | |
| 254 | /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ |
| 255 | static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 256 | { |
| 257 | u32 fg = expand_color(rect->color); |
| 258 | u8 __iomem *dst1; |
| 259 | u32 __iomem *dst; |
| 260 | int x, y; |
| 261 | |
| 262 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) |
| 263 | + ((rect->dx / 8) * 4); |
| 264 | |
| 265 | for (y = 0; y < rect->height; y++) { |
| 266 | dst = (u32 __iomem *) dst1; |
| 267 | for (x = 0; x < rect->width; x += 8) { |
| 268 | fb_writel(fg, dst++); |
| 269 | } |
| 270 | dst1 += info->fix.line_length; |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | |
| 275 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ |
| 276 | static inline u32 expand_pixel(u32 c) |
| 277 | { |
| 278 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | |
| 279 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; |
| 280 | } |
| 281 | |
| 282 | /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ |
| 283 | static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) |
| 284 | { |
| 285 | u32 fg = image->fg_color * 0x11111111; |
| 286 | u32 bg = image->bg_color * 0x11111111; |
| 287 | const u8 *src1, *src; |
| 288 | u8 __iomem *dst1; |
| 289 | u32 __iomem *dst; |
| 290 | u32 val; |
| 291 | int x, y; |
| 292 | |
| 293 | src1 = image->data; |
| 294 | dst1 = info->screen_base + (image->dy * info->fix.line_length) |
| 295 | + ((image->dx / 8) * 4); |
| 296 | |
| 297 | for (y = 0; y < image->height; y++) { |
| 298 | src = src1; |
| 299 | dst = (u32 __iomem *) dst1; |
| 300 | for (x = 0; x < image->width; x += 8) { |
| 301 | val = expand_pixel(*(src++)); |
| 302 | val = (val & fg) | (~val & bg); |
| 303 | fb_writel(val, dst++); |
| 304 | } |
| 305 | src1 += image->width / 8; |
| 306 | dst1 += info->fix.line_length; |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) |
| 311 | { |
| 312 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) |
| 313 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { |
| 314 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) |
| 315 | s3fb_iplan_imageblit(info, image); |
| 316 | else |
| 317 | s3fb_cfb4_imageblit(info, image); |
| 318 | } else |
| 319 | cfb_imageblit(info, image); |
| 320 | } |
| 321 | |
| 322 | static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 323 | { |
| 324 | if ((info->var.bits_per_pixel == 4) |
| 325 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) |
| 326 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) |
| 327 | s3fb_iplan_fillrect(info, rect); |
| 328 | else |
| 329 | cfb_fillrect(info, rect); |
| 330 | } |
| 331 | |
| 332 | |
| 333 | |
| 334 | /* ------------------------------------------------------------------------- */ |
| 335 | |
| 336 | |
| 337 | static void s3_set_pixclock(struct fb_info *info, u32 pixclock) |
| 338 | { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 339 | struct s3fb_info *par = info->par; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 340 | u16 m, n, r; |
| 341 | u8 regval; |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 342 | int rv; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 343 | |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 344 | rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node); |
| 345 | if (rv < 0) { |
| 346 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); |
| 347 | return; |
| 348 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 349 | |
| 350 | /* Set VGA misc register */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 351 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
| 352 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 353 | |
| 354 | /* Set S3 clock registers */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 355 | if (par->chip == CHIP_360_TRIO3D_1X || |
| 356 | par->chip == CHIP_362_TRIO3D_2X || |
| 357 | par->chip == CHIP_368_TRIO3D_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 358 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ |
| 359 | vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 360 | } else |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 361 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); |
| 362 | vga_wseq(par->state.vgabase, 0x13, m - 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 363 | |
| 364 | udelay(1000); |
| 365 | |
| 366 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 367 | regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ |
| 368 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
| 369 | vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); |
| 370 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | |
| 374 | /* Open framebuffer */ |
| 375 | |
| 376 | static int s3fb_open(struct fb_info *info, int user) |
| 377 | { |
| 378 | struct s3fb_info *par = info->par; |
| 379 | |
| 380 | mutex_lock(&(par->open_lock)); |
| 381 | if (par->ref_count == 0) { |
David Miller | 3ff259f | 2011-01-11 23:53:53 +0000 | [diff] [blame] | 382 | void __iomem *vgabase = par->state.vgabase; |
| 383 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 384 | memset(&(par->state), 0, sizeof(struct vgastate)); |
David Miller | 3ff259f | 2011-01-11 23:53:53 +0000 | [diff] [blame] | 385 | par->state.vgabase = vgabase; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 386 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; |
| 387 | par->state.num_crtc = 0x70; |
| 388 | par->state.num_seq = 0x20; |
| 389 | save_vga(&(par->state)); |
| 390 | } |
| 391 | |
| 392 | par->ref_count++; |
| 393 | mutex_unlock(&(par->open_lock)); |
| 394 | |
| 395 | return 0; |
| 396 | } |
| 397 | |
| 398 | /* Close framebuffer */ |
| 399 | |
| 400 | static int s3fb_release(struct fb_info *info, int user) |
| 401 | { |
| 402 | struct s3fb_info *par = info->par; |
| 403 | |
| 404 | mutex_lock(&(par->open_lock)); |
| 405 | if (par->ref_count == 0) { |
| 406 | mutex_unlock(&(par->open_lock)); |
| 407 | return -EINVAL; |
| 408 | } |
| 409 | |
| 410 | if (par->ref_count == 1) |
| 411 | restore_vga(&(par->state)); |
| 412 | |
| 413 | par->ref_count--; |
| 414 | mutex_unlock(&(par->open_lock)); |
| 415 | |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | /* Validate passed in var */ |
| 420 | |
| 421 | static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 422 | { |
| 423 | struct s3fb_info *par = info->par; |
| 424 | int rv, mem, step; |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 425 | u16 m, n, r; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 426 | |
| 427 | /* Find appropriate format */ |
| 428 | rv = svga_match_format (s3fb_formats, var, NULL); |
Ondrej Zajicek | d4b766a | 2007-10-16 01:29:52 -0700 | [diff] [blame] | 429 | |
| 430 | /* 32bpp mode is not supported on VIRGE VX, |
| 431 | 24bpp is not supported on others */ |
| 432 | if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) |
| 433 | rv = -EINVAL; |
| 434 | |
| 435 | if (rv < 0) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 436 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); |
| 437 | return rv; |
| 438 | } |
| 439 | |
| 440 | /* Do not allow to have real resoulution larger than virtual */ |
| 441 | if (var->xres > var->xres_virtual) |
| 442 | var->xres_virtual = var->xres; |
| 443 | |
| 444 | if (var->yres > var->yres_virtual) |
| 445 | var->yres_virtual = var->yres; |
| 446 | |
| 447 | /* Round up xres_virtual to have proper alignment of lines */ |
| 448 | step = s3fb_formats[rv].xresstep - 1; |
| 449 | var->xres_virtual = (var->xres_virtual+step) & ~step; |
| 450 | |
| 451 | /* Check whether have enough memory */ |
| 452 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 453 | if (mem > info->screen_size) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 454 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", |
| 455 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); |
| 456 | return -EINVAL; |
| 457 | } |
| 458 | |
| 459 | rv = svga_check_timings (&s3_timing_regs, var, info->node); |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 460 | if (rv < 0) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 461 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); |
| 462 | return rv; |
| 463 | } |
| 464 | |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 465 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
| 466 | info->node); |
| 467 | if (rv < 0) { |
| 468 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", |
| 469 | info->node); |
| 470 | return rv; |
| 471 | } |
| 472 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 473 | return 0; |
| 474 | } |
| 475 | |
| 476 | /* Set video mode from par */ |
| 477 | |
| 478 | static int s3fb_set_par(struct fb_info *info) |
| 479 | { |
| 480 | struct s3fb_info *par = info->par; |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 481 | u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 482 | u32 bpp = info->var.bits_per_pixel; |
| 483 | |
| 484 | if (bpp != 0) { |
| 485 | info->fix.ypanstep = 1; |
| 486 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; |
| 487 | |
| 488 | info->flags &= ~FBINFO_MISC_TILEBLITTING; |
| 489 | info->tileops = NULL; |
| 490 | |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 491 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ |
| 492 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); |
Antonino A. Daplas | 8db5166 | 2007-05-08 00:39:14 -0700 | [diff] [blame] | 493 | info->pixmap.blit_y = ~(u32)0; |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 494 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 495 | offset_value = (info->var.xres_virtual * bpp) / 64; |
| 496 | screen_size = info->var.yres_virtual * info->fix.line_length; |
| 497 | } else { |
| 498 | info->fix.ypanstep = 16; |
| 499 | info->fix.line_length = 0; |
| 500 | |
| 501 | info->flags |= FBINFO_MISC_TILEBLITTING; |
| 502 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 503 | |
Antonino A. Daplas | 8db5166 | 2007-05-08 00:39:14 -0700 | [diff] [blame] | 504 | /* supports 8x16 tiles only */ |
| 505 | info->pixmap.blit_x = 1 << (8 - 1); |
| 506 | info->pixmap.blit_y = 1 << (16 - 1); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 507 | |
| 508 | offset_value = info->var.xres_virtual / 16; |
| 509 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; |
| 510 | } |
| 511 | |
| 512 | info->var.xoffset = 0; |
| 513 | info->var.yoffset = 0; |
| 514 | info->var.activate = FB_ACTIVATE_NOW; |
| 515 | |
| 516 | /* Unlock registers */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 517 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
| 518 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
| 519 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 520 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 521 | |
| 522 | /* Blank screen and turn off sync */ |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 523 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 524 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 525 | |
| 526 | /* Set default values */ |
David Miller | e2fade2 | 2011-01-11 23:50:04 +0000 | [diff] [blame] | 527 | svga_set_default_gfx_regs(par->state.vgabase); |
David Miller | f51a14d | 2011-01-11 23:50:36 +0000 | [diff] [blame] | 528 | svga_set_default_atc_regs(par->state.vgabase); |
David Miller | a4ade839 | 2011-01-11 23:50:54 +0000 | [diff] [blame] | 529 | svga_set_default_seq_regs(par->state.vgabase); |
David Miller | 1d28fca | 2011-01-11 23:51:41 +0000 | [diff] [blame] | 530 | svga_set_default_crt_regs(par->state.vgabase); |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 531 | svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); |
| 532 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 533 | |
| 534 | /* S3 specific initialization */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 535 | svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ |
| 536 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 537 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 538 | /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ |
| 539 | /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ |
| 540 | svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ |
| 541 | svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 542 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 543 | svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 544 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 545 | /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 546 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 547 | /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ |
| 548 | /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 549 | |
| 550 | |
| 551 | /* Set the offset register */ |
| 552 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 553 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 554 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 555 | if (par->chip != CHIP_360_TRIO3D_1X && |
| 556 | par->chip != CHIP_362_TRIO3D_2X && |
| 557 | par->chip != CHIP_368_TRIO3D_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 558 | vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ |
| 559 | vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ |
| 560 | vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ |
| 561 | vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 562 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 563 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 564 | vga_wcrt(par->state.vgabase, 0x3A, 0x35); |
David Miller | f6b0cc4 | 2011-01-11 23:49:18 +0000 | [diff] [blame] | 565 | svga_wattr(par->state.vgabase, 0x33, 0x00); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 566 | |
| 567 | if (info->var.vmode & FB_VMODE_DOUBLE) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 568 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 569 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 570 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 571 | |
| 572 | if (info->var.vmode & FB_VMODE_INTERLACED) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 573 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 574 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 575 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 576 | |
| 577 | /* Disable hardware graphics cursor */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 578 | svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 579 | /* Disable Streams engine */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 580 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 581 | |
| 582 | mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); |
| 583 | |
| 584 | /* S3 virge DX hack */ |
| 585 | if (par->chip == CHIP_375_VIRGE_DX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 586 | vga_wcrt(par->state.vgabase, 0x86, 0x80); |
| 587 | vga_wcrt(par->state.vgabase, 0x90, 0x00); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 588 | } |
| 589 | |
| 590 | /* S3 virge VX hack */ |
| 591 | if (par->chip == CHIP_988_VIRGE_VX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 592 | vga_wcrt(par->state.vgabase, 0x50, 0x00); |
| 593 | vga_wcrt(par->state.vgabase, 0x67, 0x50); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 594 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 595 | vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); |
| 596 | vga_wcrt(par->state.vgabase, 0x66, 0x90); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 597 | } |
| 598 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 599 | if (par->chip == CHIP_360_TRIO3D_1X || |
| 600 | par->chip == CHIP_362_TRIO3D_2X || |
| 601 | par->chip == CHIP_368_TRIO3D_2X) { |
| 602 | dbytes = info->var.xres * ((bpp+7)/8); |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 603 | vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); |
| 604 | vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 605 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 606 | vga_wcrt(par->state.vgabase, 0x66, 0x81); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 607 | } |
| 608 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 609 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 610 | multiplex = 0; |
| 611 | hmul = 1; |
| 612 | |
| 613 | /* Set mode-specific register values */ |
| 614 | switch (mode) { |
| 615 | case 0: |
| 616 | pr_debug("fb%d: text mode\n", info->node); |
David Miller | 9c96394 | 2011-01-11 23:51:56 +0000 | [diff] [blame] | 617 | svga_set_textmode_vga_regs(par->state.vgabase); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 618 | |
| 619 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 620 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 621 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 622 | |
| 623 | /* Disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 624 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 625 | |
| 626 | if (fasttext) { |
| 627 | pr_debug("fb%d: high speed text mode set\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 628 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 629 | } |
| 630 | break; |
| 631 | case 1: |
| 632 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 633 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 634 | |
| 635 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 636 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 637 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 638 | |
| 639 | /* disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 640 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 641 | break; |
| 642 | case 2: |
| 643 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); |
| 644 | |
| 645 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 646 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 647 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 648 | |
| 649 | /* disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 650 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 651 | break; |
| 652 | case 3: |
| 653 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 654 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 655 | if (info->var.pixclock > 20000 || |
| 656 | par->chip == CHIP_360_TRIO3D_1X || |
| 657 | par->chip == CHIP_362_TRIO3D_2X || |
| 658 | par->chip == CHIP_368_TRIO3D_2X) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 659 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 660 | else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 661 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 662 | multiplex = 1; |
| 663 | } |
| 664 | break; |
| 665 | case 4: |
| 666 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); |
| 667 | if (par->chip == CHIP_988_VIRGE_VX) { |
| 668 | if (info->var.pixclock > 20000) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 669 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 670 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 671 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 672 | } else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 673 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 674 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 675 | if (par->chip != CHIP_360_TRIO3D_1X && |
| 676 | par->chip != CHIP_362_TRIO3D_2X && |
| 677 | par->chip != CHIP_368_TRIO3D_2X) |
| 678 | hmul = 2; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 679 | } |
| 680 | break; |
| 681 | case 5: |
| 682 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); |
| 683 | if (par->chip == CHIP_988_VIRGE_VX) { |
| 684 | if (info->var.pixclock > 20000) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 685 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 686 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 687 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 688 | } else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 689 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 690 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 691 | if (par->chip != CHIP_360_TRIO3D_1X && |
| 692 | par->chip != CHIP_362_TRIO3D_2X && |
| 693 | par->chip != CHIP_368_TRIO3D_2X) |
| 694 | hmul = 2; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 695 | } |
| 696 | break; |
| 697 | case 6: |
| 698 | /* VIRGE VX case */ |
| 699 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 700 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 701 | break; |
| 702 | case 7: |
| 703 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 704 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); |
| 705 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 706 | break; |
| 707 | default: |
| 708 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); |
| 709 | return -EINVAL; |
| 710 | } |
| 711 | |
| 712 | if (par->chip != CHIP_988_VIRGE_VX) { |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 713 | svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); |
| 714 | svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | s3_set_pixclock(info, info->var.pixclock); |
David Miller | 38d2620 | 2011-01-11 23:52:25 +0000 | [diff] [blame] | 718 | svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 719 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, |
| 720 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, |
| 721 | hmul, info->node); |
| 722 | |
| 723 | /* Set interlaced mode start/end register */ |
| 724 | value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; |
| 725 | value = ((value * hmul) / 8) - 5; |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 726 | vga_wcrt(par->state.vgabase, 0x3C, (value + 1) / 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 727 | |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 728 | memset_io(info->screen_base, 0x00, screen_size); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 729 | /* Device and screen back on */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 730 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 731 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 732 | |
| 733 | return 0; |
| 734 | } |
| 735 | |
| 736 | /* Set a colour register */ |
| 737 | |
| 738 | static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
| 739 | u_int transp, struct fb_info *fb) |
| 740 | { |
| 741 | switch (fb->var.bits_per_pixel) { |
| 742 | case 0: |
| 743 | case 4: |
| 744 | if (regno >= 16) |
| 745 | return -EINVAL; |
| 746 | |
| 747 | if ((fb->var.bits_per_pixel == 4) && |
| 748 | (fb->var.nonstd == 0)) { |
| 749 | outb(0xF0, VGA_PEL_MSK); |
| 750 | outb(regno*16, VGA_PEL_IW); |
| 751 | } else { |
| 752 | outb(0x0F, VGA_PEL_MSK); |
| 753 | outb(regno, VGA_PEL_IW); |
| 754 | } |
| 755 | outb(red >> 10, VGA_PEL_D); |
| 756 | outb(green >> 10, VGA_PEL_D); |
| 757 | outb(blue >> 10, VGA_PEL_D); |
| 758 | break; |
| 759 | case 8: |
| 760 | if (regno >= 256) |
| 761 | return -EINVAL; |
| 762 | |
| 763 | outb(0xFF, VGA_PEL_MSK); |
| 764 | outb(regno, VGA_PEL_IW); |
| 765 | outb(red >> 10, VGA_PEL_D); |
| 766 | outb(green >> 10, VGA_PEL_D); |
| 767 | outb(blue >> 10, VGA_PEL_D); |
| 768 | break; |
| 769 | case 16: |
| 770 | if (regno >= 16) |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 771 | return 0; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 772 | |
| 773 | if (fb->var.green.length == 5) |
| 774 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | |
| 775 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); |
| 776 | else if (fb->var.green.length == 6) |
| 777 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | |
| 778 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); |
| 779 | else return -EINVAL; |
| 780 | break; |
| 781 | case 24: |
| 782 | case 32: |
| 783 | if (regno >= 16) |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 784 | return 0; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 785 | |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 786 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 787 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
| 788 | break; |
| 789 | default: |
| 790 | return -EINVAL; |
| 791 | } |
| 792 | |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | |
| 797 | /* Set the display blanking state */ |
| 798 | |
| 799 | static int s3fb_blank(int blank_mode, struct fb_info *info) |
| 800 | { |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 801 | struct s3fb_info *par = info->par; |
| 802 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 803 | switch (blank_mode) { |
| 804 | case FB_BLANK_UNBLANK: |
| 805 | pr_debug("fb%d: unblank\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 806 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 807 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 808 | break; |
| 809 | case FB_BLANK_NORMAL: |
| 810 | pr_debug("fb%d: blank\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 811 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 812 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 813 | break; |
| 814 | case FB_BLANK_HSYNC_SUSPEND: |
| 815 | pr_debug("fb%d: hsync\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 816 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 817 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 818 | break; |
| 819 | case FB_BLANK_VSYNC_SUSPEND: |
| 820 | pr_debug("fb%d: vsync\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 821 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 822 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 823 | break; |
| 824 | case FB_BLANK_POWERDOWN: |
| 825 | pr_debug("fb%d: sync down\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 826 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 827 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 828 | break; |
| 829 | } |
| 830 | |
| 831 | return 0; |
| 832 | } |
| 833 | |
| 834 | |
| 835 | /* Pan the display */ |
| 836 | |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 837 | static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
| 838 | { |
| 839 | struct s3fb_info *par = info->par; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 840 | unsigned int offset; |
| 841 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 842 | /* Calculate the offset */ |
| 843 | if (var->bits_per_pixel == 0) { |
| 844 | offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2); |
| 845 | offset = offset >> 2; |
| 846 | } else { |
| 847 | offset = (var->yoffset * info->fix.line_length) + |
| 848 | (var->xoffset * var->bits_per_pixel / 8); |
| 849 | offset = offset >> 2; |
| 850 | } |
| 851 | |
| 852 | /* Set the offset */ |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 853 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
| 858 | /* ------------------------------------------------------------------------- */ |
| 859 | |
| 860 | /* Frame buffer operations */ |
| 861 | |
| 862 | static struct fb_ops s3fb_ops = { |
| 863 | .owner = THIS_MODULE, |
| 864 | .fb_open = s3fb_open, |
| 865 | .fb_release = s3fb_release, |
| 866 | .fb_check_var = s3fb_check_var, |
| 867 | .fb_set_par = s3fb_set_par, |
| 868 | .fb_setcolreg = s3fb_setcolreg, |
| 869 | .fb_blank = s3fb_blank, |
| 870 | .fb_pan_display = s3fb_pan_display, |
| 871 | .fb_fillrect = s3fb_fillrect, |
| 872 | .fb_copyarea = cfb_copyarea, |
| 873 | .fb_imageblit = s3fb_imageblit, |
Antonino A. Daplas | 5a87ede | 2007-05-09 02:35:32 -0700 | [diff] [blame] | 874 | .fb_get_caps = svga_get_caps, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 875 | }; |
| 876 | |
| 877 | /* ------------------------------------------------------------------------- */ |
| 878 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 879 | static int __devinit s3_identification(struct s3fb_info *par) |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 880 | { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 881 | int chip = par->chip; |
| 882 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 883 | if (chip == CHIP_XXX_TRIO) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 884 | u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); |
| 885 | u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); |
| 886 | u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 887 | |
| 888 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { |
| 889 | if (cr2e == 0x10) |
| 890 | return CHIP_732_TRIO32; |
| 891 | if (cr2e == 0x11) { |
| 892 | if (! (cr2f & 0x40)) |
| 893 | return CHIP_764_TRIO64; |
| 894 | else |
| 895 | return CHIP_765_TRIO64VP; |
| 896 | } |
| 897 | } |
| 898 | } |
| 899 | |
| 900 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 901 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 902 | |
| 903 | if (! (cr6f & 0x01)) |
| 904 | return CHIP_775_TRIO64V2_DX; |
| 905 | else |
| 906 | return CHIP_785_TRIO64V2_GX; |
| 907 | } |
| 908 | |
| 909 | if (chip == CHIP_XXX_VIRGE_DXGX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 910 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 911 | |
| 912 | if (! (cr6f & 0x01)) |
| 913 | return CHIP_375_VIRGE_DX; |
| 914 | else |
| 915 | return CHIP_385_VIRGE_GX; |
| 916 | } |
| 917 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 918 | if (chip == CHIP_36X_TRIO3D_1X_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 919 | switch (vga_rcrt(par->state.vgabase, 0x2f)) { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 920 | case 0x00: |
| 921 | return CHIP_360_TRIO3D_1X; |
| 922 | case 0x01: |
| 923 | return CHIP_362_TRIO3D_2X; |
| 924 | case 0x02: |
| 925 | return CHIP_368_TRIO3D_2X; |
| 926 | } |
| 927 | } |
| 928 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 929 | return CHIP_UNKNOWN; |
| 930 | } |
| 931 | |
| 932 | |
| 933 | /* PCI probe */ |
| 934 | |
| 935 | static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
| 936 | { |
David Miller | 94c322c | 2011-01-11 23:54:21 +0000 | [diff] [blame] | 937 | struct pci_bus_region bus_reg; |
| 938 | struct resource vga_res; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 939 | struct fb_info *info; |
| 940 | struct s3fb_info *par; |
| 941 | int rc; |
| 942 | u8 regval, cr38, cr39; |
| 943 | |
| 944 | /* Ignore secondary VGA device because there is no VGA arbitration */ |
| 945 | if (! svga_primary_device(dev)) { |
| 946 | dev_info(&(dev->dev), "ignoring secondary device\n"); |
| 947 | return -ENODEV; |
| 948 | } |
| 949 | |
| 950 | /* Allocate and fill driver data structure */ |
Ondrej Zajicek | 20e061f | 2008-04-28 02:15:18 -0700 | [diff] [blame] | 951 | info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 952 | if (!info) { |
| 953 | dev_err(&(dev->dev), "cannot allocate memory\n"); |
| 954 | return -ENOMEM; |
| 955 | } |
| 956 | |
| 957 | par = info->par; |
| 958 | mutex_init(&par->open_lock); |
| 959 | |
| 960 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; |
| 961 | info->fbops = &s3fb_ops; |
| 962 | |
| 963 | /* Prepare PCI device */ |
| 964 | rc = pci_enable_device(dev); |
| 965 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 966 | dev_err(info->device, "cannot enable PCI device\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 967 | goto err_enable_device; |
| 968 | } |
| 969 | |
| 970 | rc = pci_request_regions(dev, "s3fb"); |
| 971 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 972 | dev_err(info->device, "cannot reserve framebuffer region\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 973 | goto err_request_regions; |
| 974 | } |
| 975 | |
| 976 | |
| 977 | info->fix.smem_start = pci_resource_start(dev, 0); |
| 978 | info->fix.smem_len = pci_resource_len(dev, 0); |
| 979 | |
| 980 | /* Map physical IO memory address into kernel space */ |
| 981 | info->screen_base = pci_iomap(dev, 0, 0); |
| 982 | if (! info->screen_base) { |
| 983 | rc = -ENOMEM; |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 984 | dev_err(info->device, "iomap for framebuffer failed\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 985 | goto err_iomap; |
| 986 | } |
| 987 | |
David Miller | 94c322c | 2011-01-11 23:54:21 +0000 | [diff] [blame] | 988 | bus_reg.start = 0; |
| 989 | bus_reg.end = 64 * 1024; |
| 990 | |
| 991 | vga_res.flags = IORESOURCE_IO; |
| 992 | |
| 993 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); |
| 994 | |
| 995 | par->state.vgabase = (void __iomem *) vga_res.start; |
| 996 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 997 | /* Unlock regs */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 998 | cr38 = vga_rcrt(par->state.vgabase, 0x38); |
| 999 | cr39 = vga_rcrt(par->state.vgabase, 0x39); |
| 1000 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
| 1001 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
| 1002 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1003 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1004 | /* Identify chip type */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1005 | par->chip = id->driver_data & CHIP_MASK; |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1006 | par->rev = vga_rcrt(par->state.vgabase, 0x2f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1007 | if (par->chip & CHIP_UNDECIDED_FLAG) |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1008 | par->chip = s3_identification(par); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1009 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1010 | /* Find how many physical memory there is on card */ |
| 1011 | /* 0x36 register is accessible even if other registers are locked */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1012 | regval = vga_rcrt(par->state.vgabase, 0x36); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1013 | if (par->chip == CHIP_360_TRIO3D_1X || |
| 1014 | par->chip == CHIP_362_TRIO3D_2X || |
| 1015 | par->chip == CHIP_368_TRIO3D_2X) { |
| 1016 | switch ((regval & 0xE0) >> 5) { |
| 1017 | case 0: /* 8MB -- only 4MB usable for display */ |
| 1018 | case 1: /* 4MB with 32-bit bus */ |
| 1019 | case 2: /* 4MB */ |
| 1020 | info->screen_size = 4 << 20; |
| 1021 | break; |
| 1022 | case 6: /* 2MB */ |
| 1023 | info->screen_size = 2 << 20; |
| 1024 | break; |
| 1025 | } |
| 1026 | } else |
| 1027 | info->screen_size = s3_memsizes[regval >> 5] << 10; |
| 1028 | info->fix.smem_len = info->screen_size; |
| 1029 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1030 | /* Find MCLK frequency */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1031 | regval = vga_rseq(par->state.vgabase, 0x10); |
| 1032 | par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1033 | par->mclk_freq = par->mclk_freq >> (regval >> 5); |
| 1034 | |
| 1035 | /* Restore locks */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1036 | vga_wcrt(par->state.vgabase, 0x38, cr38); |
| 1037 | vga_wcrt(par->state.vgabase, 0x39, cr39); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1038 | |
| 1039 | strcpy(info->fix.id, s3_names [par->chip]); |
| 1040 | info->fix.mmio_start = 0; |
| 1041 | info->fix.mmio_len = 0; |
| 1042 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
| 1043 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
| 1044 | info->fix.ypanstep = 0; |
| 1045 | info->fix.accel = FB_ACCEL_NONE; |
| 1046 | info->pseudo_palette = (void*) (par->pseudo_palette); |
| 1047 | |
| 1048 | /* Prepare startup mode */ |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 1049 | rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1050 | if (! ((rc == 1) || (rc == 2))) { |
| 1051 | rc = -EINVAL; |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1052 | dev_err(info->device, "mode %s not found\n", mode_option); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1053 | goto err_find_mode; |
| 1054 | } |
| 1055 | |
| 1056 | rc = fb_alloc_cmap(&info->cmap, 256, 0); |
| 1057 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1058 | dev_err(info->device, "cannot allocate colormap\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1059 | goto err_alloc_cmap; |
| 1060 | } |
| 1061 | |
| 1062 | rc = register_framebuffer(info); |
| 1063 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1064 | dev_err(info->device, "cannot register framebuffer\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1065 | goto err_reg_fb; |
| 1066 | } |
| 1067 | |
| 1068 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, |
| 1069 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); |
| 1070 | |
| 1071 | if (par->chip == CHIP_UNKNOWN) |
| 1072 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1073 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), |
| 1074 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1075 | |
| 1076 | /* Record a reference to the driver data */ |
| 1077 | pci_set_drvdata(dev, info); |
| 1078 | |
| 1079 | #ifdef CONFIG_MTRR |
| 1080 | if (mtrr) { |
| 1081 | par->mtrr_reg = -1; |
| 1082 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); |
| 1083 | } |
| 1084 | #endif |
| 1085 | |
| 1086 | return 0; |
| 1087 | |
| 1088 | /* Error handling */ |
| 1089 | err_reg_fb: |
| 1090 | fb_dealloc_cmap(&info->cmap); |
| 1091 | err_alloc_cmap: |
| 1092 | err_find_mode: |
| 1093 | pci_iounmap(dev, info->screen_base); |
| 1094 | err_iomap: |
| 1095 | pci_release_regions(dev); |
| 1096 | err_request_regions: |
| 1097 | /* pci_disable_device(dev); */ |
| 1098 | err_enable_device: |
| 1099 | framebuffer_release(info); |
| 1100 | return rc; |
| 1101 | } |
| 1102 | |
| 1103 | |
| 1104 | /* PCI remove */ |
| 1105 | |
| 1106 | static void __devexit s3_pci_remove(struct pci_dev *dev) |
| 1107 | { |
| 1108 | struct fb_info *info = pci_get_drvdata(dev); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1109 | |
| 1110 | if (info) { |
| 1111 | |
| 1112 | #ifdef CONFIG_MTRR |
Adrian Bunk | 47ebea8 | 2007-03-22 00:11:16 -0800 | [diff] [blame] | 1113 | struct s3fb_info *par = info->par; |
| 1114 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1115 | if (par->mtrr_reg >= 0) { |
| 1116 | mtrr_del(par->mtrr_reg, 0, 0); |
| 1117 | par->mtrr_reg = -1; |
| 1118 | } |
| 1119 | #endif |
| 1120 | |
| 1121 | unregister_framebuffer(info); |
| 1122 | fb_dealloc_cmap(&info->cmap); |
| 1123 | |
| 1124 | pci_iounmap(dev, info->screen_base); |
| 1125 | pci_release_regions(dev); |
| 1126 | /* pci_disable_device(dev); */ |
| 1127 | |
| 1128 | pci_set_drvdata(dev, NULL); |
| 1129 | framebuffer_release(info); |
| 1130 | } |
| 1131 | } |
| 1132 | |
| 1133 | /* PCI suspend */ |
| 1134 | |
| 1135 | static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) |
| 1136 | { |
| 1137 | struct fb_info *info = pci_get_drvdata(dev); |
| 1138 | struct s3fb_info *par = info->par; |
| 1139 | |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1140 | dev_info(info->device, "suspend\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1141 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1142 | console_lock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1143 | mutex_lock(&(par->open_lock)); |
| 1144 | |
| 1145 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { |
| 1146 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1147 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1148 | return 0; |
| 1149 | } |
| 1150 | |
| 1151 | fb_set_suspend(info, 1); |
| 1152 | |
| 1153 | pci_save_state(dev); |
| 1154 | pci_disable_device(dev); |
| 1155 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
| 1156 | |
| 1157 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1158 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1159 | |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | |
| 1164 | /* PCI resume */ |
| 1165 | |
| 1166 | static int s3_pci_resume(struct pci_dev* dev) |
| 1167 | { |
| 1168 | struct fb_info *info = pci_get_drvdata(dev); |
| 1169 | struct s3fb_info *par = info->par; |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1170 | int err; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1171 | |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1172 | dev_info(info->device, "resume\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1173 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1174 | console_lock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1175 | mutex_lock(&(par->open_lock)); |
| 1176 | |
| 1177 | if (par->ref_count == 0) { |
| 1178 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1179 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1180 | return 0; |
| 1181 | } |
| 1182 | |
| 1183 | pci_set_power_state(dev, PCI_D0); |
| 1184 | pci_restore_state(dev); |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1185 | err = pci_enable_device(dev); |
| 1186 | if (err) { |
| 1187 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1188 | console_unlock(); |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1189 | dev_err(info->device, "error %d enabling device for resume\n", err); |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1190 | return err; |
| 1191 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1192 | pci_set_master(dev); |
| 1193 | |
| 1194 | s3fb_set_par(info); |
| 1195 | fb_set_suspend(info, 0); |
| 1196 | |
| 1197 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1198 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1199 | |
| 1200 | return 0; |
| 1201 | } |
| 1202 | |
| 1203 | |
| 1204 | /* List of boards that we are trying to support */ |
| 1205 | |
| 1206 | static struct pci_device_id s3_devices[] __devinitdata = { |
| 1207 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, |
| 1208 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, |
| 1209 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, |
| 1210 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, |
| 1211 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, |
| 1212 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, |
| 1213 | |
| 1214 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, |
| 1215 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, |
| 1216 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, |
| 1217 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2}, |
| 1218 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P}, |
| 1219 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1220 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1221 | |
| 1222 | {0, 0, 0, 0, 0, 0, 0} |
| 1223 | }; |
| 1224 | |
| 1225 | |
| 1226 | MODULE_DEVICE_TABLE(pci, s3_devices); |
| 1227 | |
| 1228 | static struct pci_driver s3fb_pci_driver = { |
| 1229 | .name = "s3fb", |
| 1230 | .id_table = s3_devices, |
| 1231 | .probe = s3_pci_probe, |
| 1232 | .remove = __devexit_p(s3_pci_remove), |
| 1233 | .suspend = s3_pci_suspend, |
| 1234 | .resume = s3_pci_resume, |
| 1235 | }; |
| 1236 | |
| 1237 | /* Parse user speficied options */ |
| 1238 | |
| 1239 | #ifndef MODULE |
| 1240 | static int __init s3fb_setup(char *options) |
| 1241 | { |
| 1242 | char *opt; |
| 1243 | |
| 1244 | if (!options || !*options) |
| 1245 | return 0; |
| 1246 | |
| 1247 | while ((opt = strsep(&options, ",")) != NULL) { |
| 1248 | |
| 1249 | if (!*opt) |
| 1250 | continue; |
| 1251 | #ifdef CONFIG_MTRR |
Ondrej Zajicek | 62fa4dc | 2007-02-22 17:00:41 +0100 | [diff] [blame] | 1252 | else if (!strncmp(opt, "mtrr:", 5)) |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1253 | mtrr = simple_strtoul(opt + 5, NULL, 0); |
| 1254 | #endif |
Ondrej Zajicek | 62fa4dc | 2007-02-22 17:00:41 +0100 | [diff] [blame] | 1255 | else if (!strncmp(opt, "fasttext:", 9)) |
| 1256 | fasttext = simple_strtoul(opt + 9, NULL, 0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1257 | else |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 1258 | mode_option = opt; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1259 | } |
| 1260 | |
| 1261 | return 0; |
| 1262 | } |
| 1263 | #endif |
| 1264 | |
| 1265 | /* Cleanup */ |
| 1266 | |
| 1267 | static void __exit s3fb_cleanup(void) |
| 1268 | { |
| 1269 | pr_debug("s3fb: cleaning up\n"); |
| 1270 | pci_unregister_driver(&s3fb_pci_driver); |
| 1271 | } |
| 1272 | |
| 1273 | /* Driver Initialisation */ |
| 1274 | |
| 1275 | static int __init s3fb_init(void) |
| 1276 | { |
| 1277 | |
| 1278 | #ifndef MODULE |
| 1279 | char *option = NULL; |
| 1280 | |
| 1281 | if (fb_get_options("s3fb", &option)) |
| 1282 | return -ENODEV; |
| 1283 | s3fb_setup(option); |
| 1284 | #endif |
| 1285 | |
| 1286 | pr_debug("s3fb: initializing\n"); |
| 1287 | return pci_register_driver(&s3fb_pci_driver); |
| 1288 | } |
| 1289 | |
| 1290 | /* ------------------------------------------------------------------------- */ |
| 1291 | |
| 1292 | /* Modularization */ |
| 1293 | |
| 1294 | module_init(s3fb_init); |
| 1295 | module_exit(s3fb_cleanup); |