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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 *
7 * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
8 * and can only be used for expansion cards. Onboard DMA controllers, such
9 * as the R4030 on Jazz boards behave totally different!
10 */
11
12#ifndef _ASM_DMA_H
13#define _ASM_DMA_H
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <asm/io.h> /* need byte IO */
16#include <linux/spinlock.h> /* And spinlocks */
17#include <linux/delay.h>
18#include <asm/system.h>
19
20
21#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
22#define dma_outb outb_p
23#else
24#define dma_outb outb
25#endif
26
27#define dma_inb inb
28
29/*
30 * NOTES about DMA transfers:
31 *
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
34 *
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
38 * - channels 5-7 are word - addresses/counts are for physical words
39 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
40 * - transfer count loaded to registers is 1 less than actual count
41 * - controller 2 offsets are all even (2x offsets for controller 1)
42 * - page registers for 5-7 don't use data bit 0, represent 128K pages
43 * - page registers for 0-3 use bit 0, represent 64K pages
44 *
45 * DMA transfers are limited to the lower 16MB of _physical_ memory.
46 * Note that addresses loaded into registers must be _physical_ addresses,
47 * not logical addresses (which may differ if paging is active).
48 *
49 * Address mapping for channels 0-3:
50 *
51 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
52 * | ... | | ... | | ... |
53 * | ... | | ... | | ... |
54 * | ... | | ... | | ... |
55 * P7 ... P0 A7 ... A0 A7 ... A0
56 * | Page | Addr MSB | Addr LSB | (DMA registers)
57 *
58 * Address mapping for channels 5-7:
59 *
60 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
61 * | ... | \ \ ... \ \ \ ... \ \
62 * | ... | \ \ ... \ \ \ ... \ (not used)
63 * | ... | \ \ ... \ \ \ ... \
64 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
65 * | Page | Addr MSB | Addr LSB | (DMA registers)
66 *
67 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
68 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
69 * the hardware level, so odd-byte transfers aren't possible).
70 *
71 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
72 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
73 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
74 *
75 */
76
77#define MAX_DMA_CHANNELS 8
78
79/*
80 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
81 * platform. This describes only the PC style part of the DMA logic like on
82 * Deskstations or Acer PICA but not the much more versatile DMA logic used
83 * for the local devices on Acer PICA or Magnums.
84 */
85#ifdef CONFIG_SGI_IP22
86/* Horrible hack to have a correct DMA window on IP22 */
87#include <asm/sgi/mc.h>
88#define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
89#else
90#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
91#endif
92
93/* 8237 DMA controllers */
94#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
95#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
96
97/* DMA controller registers */
98#define DMA1_CMD_REG 0x08 /* command register (w) */
99#define DMA1_STAT_REG 0x08 /* status register (r) */
100#define DMA1_REQ_REG 0x09 /* request register (w) */
101#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
102#define DMA1_MODE_REG 0x0B /* mode register (w) */
103#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
104#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
105#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
106#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
107#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
108
109#define DMA2_CMD_REG 0xD0 /* command register (w) */
110#define DMA2_STAT_REG 0xD0 /* status register (r) */
111#define DMA2_REQ_REG 0xD2 /* request register (w) */
112#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
113#define DMA2_MODE_REG 0xD6 /* mode register (w) */
114#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
115#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
116#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
117#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
118#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
119
120#define DMA_ADDR_0 0x00 /* DMA address registers */
121#define DMA_ADDR_1 0x02
122#define DMA_ADDR_2 0x04
123#define DMA_ADDR_3 0x06
124#define DMA_ADDR_4 0xC0
125#define DMA_ADDR_5 0xC4
126#define DMA_ADDR_6 0xC8
127#define DMA_ADDR_7 0xCC
128
129#define DMA_CNT_0 0x01 /* DMA count registers */
130#define DMA_CNT_1 0x03
131#define DMA_CNT_2 0x05
132#define DMA_CNT_3 0x07
133#define DMA_CNT_4 0xC2
134#define DMA_CNT_5 0xC6
135#define DMA_CNT_6 0xCA
136#define DMA_CNT_7 0xCE
137
138#define DMA_PAGE_0 0x87 /* DMA page registers */
139#define DMA_PAGE_1 0x83
140#define DMA_PAGE_2 0x81
141#define DMA_PAGE_3 0x82
142#define DMA_PAGE_5 0x8B
143#define DMA_PAGE_6 0x89
144#define DMA_PAGE_7 0x8A
145
146#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
147#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
148#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
149
150#define DMA_AUTOINIT 0x10
151
152extern spinlock_t dma_spin_lock;
153
154static __inline__ unsigned long claim_dma_lock(void)
155{
156 unsigned long flags;
157 spin_lock_irqsave(&dma_spin_lock, flags);
158 return flags;
159}
160
161static __inline__ void release_dma_lock(unsigned long flags)
162{
163 spin_unlock_irqrestore(&dma_spin_lock, flags);
164}
165
166/* enable/disable a specific DMA channel */
167static __inline__ void enable_dma(unsigned int dmanr)
168{
169 if (dmanr<=3)
170 dma_outb(dmanr, DMA1_MASK_REG);
171 else
172 dma_outb(dmanr & 3, DMA2_MASK_REG);
173}
174
175static __inline__ void disable_dma(unsigned int dmanr)
176{
177 if (dmanr<=3)
178 dma_outb(dmanr | 4, DMA1_MASK_REG);
179 else
180 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
181}
182
183/* Clear the 'DMA Pointer Flip Flop'.
184 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
185 * Use this once to initialize the FF to a known state.
186 * After that, keep track of it. :-)
187 * --- In order to do that, the DMA routines below should ---
188 * --- only be used while holding the DMA lock ! ---
189 */
190static __inline__ void clear_dma_ff(unsigned int dmanr)
191{
192 if (dmanr<=3)
193 dma_outb(0, DMA1_CLEAR_FF_REG);
194 else
195 dma_outb(0, DMA2_CLEAR_FF_REG);
196}
197
198/* set mode (above) for a specific DMA channel */
199static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
200{
201 if (dmanr<=3)
202 dma_outb(mode | dmanr, DMA1_MODE_REG);
203 else
204 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
205}
206
207/* Set only the page register bits of the transfer address.
208 * This is used for successive transfers when we know the contents of
209 * the lower 16 bits of the DMA current address register, but a 64k boundary
210 * may have been crossed.
211 */
212static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
213{
214 switch(dmanr) {
215 case 0:
216 dma_outb(pagenr, DMA_PAGE_0);
217 break;
218 case 1:
219 dma_outb(pagenr, DMA_PAGE_1);
220 break;
221 case 2:
222 dma_outb(pagenr, DMA_PAGE_2);
223 break;
224 case 3:
225 dma_outb(pagenr, DMA_PAGE_3);
226 break;
227 case 5:
228 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
229 break;
230 case 6:
231 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
232 break;
233 case 7:
234 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
235 break;
236 }
237}
238
239
240/* Set transfer address & page bits for specific DMA channel.
241 * Assumes dma flipflop is clear.
242 */
243static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
244{
245 set_dma_page(dmanr, a>>16);
246 if (dmanr <= 3) {
247 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
248 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
249 } else {
250 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
251 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
252 }
253}
254
255
256/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
257 * a specific DMA channel.
258 * You must ensure the parameters are valid.
259 * NOTE: from a manual: "the number of transfers is one more
260 * than the initial word count"! This is taken into account.
261 * Assumes dma flip-flop is clear.
262 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
263 */
264static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
265{
266 count--;
267 if (dmanr <= 3) {
268 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
269 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
270 } else {
271 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
272 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
273 }
274}
275
276
277/* Get DMA residue count. After a DMA transfer, this
278 * should return zero. Reading this while a DMA transfer is
279 * still in progress will return unpredictable results.
280 * If called before the channel has been used, it may return 1.
281 * Otherwise, it returns the number of _bytes_ left to transfer.
282 *
283 * Assumes DMA flip-flop is clear.
284 */
285static __inline__ int get_dma_residue(unsigned int dmanr)
286{
287 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
288 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
289
290 /* using short to get 16-bit wrap around */
291 unsigned short count;
292
293 count = 1 + dma_inb(io_port);
294 count += dma_inb(io_port) << 8;
295
296 return (dmanr<=3)? count : (count<<1);
297}
298
299
300/* These are in kernel/dma.c: */
301extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
302extern void free_dma(unsigned int dmanr); /* release it again */
303
304/* From PCI */
305
306#ifdef CONFIG_PCI
307extern int isa_dma_bridge_buggy;
308#else
309#define isa_dma_bridge_buggy (0)
310#endif
311
312#endif /* _ASM_DMA_H */