Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC |
| 3 | * |
| 4 | * Copyright (C) 2011 Atmel, |
| 5 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, |
| 6 | * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
| 7 | * |
| 8 | * Licensed under GPLv2 or later. |
| 9 | */ |
| 10 | |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 11 | #include "skeleton.dtsi" |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 12 | #include <dt-bindings/pinctrl/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 14 | #include <dt-bindings/gpio/gpio.h> |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 15 | #include <dt-bindings/clock/at91.h> |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 16 | |
| 17 | / { |
| 18 | model = "Atmel AT91SAM9260 family SoC"; |
| 19 | compatible = "atmel,at91sam9260"; |
| 20 | interrupt-parent = <&aic>; |
| 21 | |
| 22 | aliases { |
| 23 | serial0 = &dbgu; |
| 24 | serial1 = &usart0; |
| 25 | serial2 = &usart1; |
| 26 | serial3 = &usart2; |
| 27 | serial4 = &usart3; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 28 | serial5 = &uart0; |
| 29 | serial6 = &uart1; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 30 | gpio0 = &pioA; |
| 31 | gpio1 = &pioB; |
| 32 | gpio2 = &pioC; |
| 33 | tcb0 = &tcb0; |
| 34 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 35 | i2c0 = &i2c0; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 36 | ssc0 = &ssc0; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 37 | }; |
| 38 | cpus { |
Lorenzo Pieralisi | e757a6e | 2013-04-18 18:31:35 +0100 | [diff] [blame] | 39 | #address-cells = <0>; |
| 40 | #size-cells = <0>; |
| 41 | |
| 42 | cpu { |
| 43 | compatible = "arm,arm926ej-s"; |
| 44 | device_type = "cpu"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 45 | }; |
| 46 | }; |
| 47 | |
| 48 | memory { |
| 49 | reg = <0x20000000 0x04000000>; |
| 50 | }; |
| 51 | |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 52 | clocks { |
| 53 | slow_xtal: slow_xtal { |
| 54 | compatible = "fixed-clock"; |
| 55 | #clock-cells = <0>; |
| 56 | clock-frequency = <0>; |
| 57 | }; |
| 58 | |
| 59 | main_xtal: main_xtal { |
| 60 | compatible = "fixed-clock"; |
| 61 | #clock-cells = <0>; |
| 62 | clock-frequency = <0>; |
| 63 | }; |
| 64 | |
| 65 | adc_op_clk: adc_op_clk{ |
| 66 | compatible = "fixed-clock"; |
| 67 | #clock-cells = <0>; |
| 68 | clock-frequency = <5000000>; |
| 69 | }; |
| 70 | }; |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 72 | ahb { |
| 73 | compatible = "simple-bus"; |
| 74 | #address-cells = <1>; |
| 75 | #size-cells = <1>; |
| 76 | ranges; |
| 77 | |
| 78 | apb { |
| 79 | compatible = "simple-bus"; |
| 80 | #address-cells = <1>; |
| 81 | #size-cells = <1>; |
| 82 | ranges; |
| 83 | |
| 84 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 85 | #interrupt-cells = <3>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 86 | compatible = "atmel,at91rm9200-aic"; |
| 87 | interrupt-controller; |
| 88 | reg = <0xfffff000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | c657394 | 2012-04-09 19:36:36 +0800 | [diff] [blame] | 89 | atmel,external-irqs = <29 30 31>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | ramc0: ramc@ffffea00 { |
| 93 | compatible = "atmel,at91sam9260-sdramc"; |
| 94 | reg = <0xffffea00 0x200>; |
| 95 | }; |
| 96 | |
| 97 | pmc: pmc@fffffc00 { |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 98 | compatible = "atmel,at91sam9260-pmc"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 99 | reg = <0xfffffc00 0x100>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 100 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 101 | interrupt-controller; |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <0>; |
| 104 | #interrupt-cells = <1>; |
| 105 | |
| 106 | main_osc: main_osc { |
| 107 | compatible = "atmel,at91rm9200-clk-main-osc"; |
| 108 | #clock-cells = <0>; |
| 109 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; |
| 110 | clocks = <&main_xtal>; |
| 111 | }; |
| 112 | |
| 113 | main: mainck { |
| 114 | compatible = "atmel,at91rm9200-clk-main"; |
| 115 | #clock-cells = <0>; |
| 116 | clocks = <&main_osc>; |
| 117 | }; |
| 118 | |
| 119 | slow_rc_osc: slow_rc_osc { |
| 120 | compatible = "fixed-clock"; |
| 121 | #clock-cells = <0>; |
| 122 | clock-frequency = <32768>; |
| 123 | clock-accuracy = <50000000>; |
| 124 | }; |
| 125 | |
| 126 | clk32k: slck { |
| 127 | compatible = "atmel,at91sam9260-clk-slow"; |
| 128 | #clock-cells = <0>; |
| 129 | clocks = <&slow_rc_osc>, <&slow_xtal>; |
| 130 | }; |
| 131 | |
| 132 | plla: pllack { |
| 133 | compatible = "atmel,at91rm9200-clk-pll"; |
| 134 | #clock-cells = <0>; |
| 135 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; |
| 136 | clocks = <&main>; |
| 137 | reg = <0>; |
| 138 | atmel,clk-input-range = <1000000 32000000>; |
| 139 | #atmel,pll-clk-output-range-cells = <4>; |
| 140 | atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, |
| 141 | <150000000 240000000 2 1>; |
| 142 | }; |
| 143 | |
| 144 | pllb: pllbck { |
| 145 | compatible = "atmel,at91rm9200-clk-pll"; |
| 146 | #clock-cells = <0>; |
| 147 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; |
| 148 | clocks = <&main>; |
| 149 | reg = <1>; |
| 150 | atmel,clk-input-range = <1000000 5000000>; |
| 151 | #atmel,pll-clk-output-range-cells = <4>; |
| 152 | atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; |
| 153 | }; |
| 154 | |
| 155 | mck: masterck { |
| 156 | compatible = "atmel,at91rm9200-clk-master"; |
| 157 | #clock-cells = <0>; |
| 158 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; |
| 159 | clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; |
| 160 | atmel,clk-output-range = <0 105000000>; |
| 161 | atmel,clk-divisors = <1 2 4 0>; |
| 162 | }; |
| 163 | |
| 164 | usb: usbck { |
| 165 | compatible = "atmel,at91rm9200-clk-usb"; |
| 166 | #clock-cells = <0>; |
| 167 | atmel,clk-divisors = <1 2 4 0>; |
| 168 | clocks = <&pllb>; |
| 169 | }; |
| 170 | |
| 171 | prog: progck { |
| 172 | compatible = "atmel,at91rm9200-clk-programmable"; |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; |
| 175 | interrupt-parent = <&pmc>; |
| 176 | clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; |
| 177 | |
| 178 | prog0: prog0 { |
| 179 | #clock-cells = <0>; |
| 180 | reg = <0>; |
| 181 | interrupts = <AT91_PMC_PCKRDY(0)>; |
| 182 | }; |
| 183 | |
| 184 | prog1: prog1 { |
| 185 | #clock-cells = <0>; |
| 186 | reg = <1>; |
| 187 | interrupts = <AT91_PMC_PCKRDY(1)>; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | systemck { |
| 192 | compatible = "atmel,at91rm9200-clk-system"; |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; |
| 195 | |
| 196 | uhpck: uhpck { |
| 197 | #clock-cells = <0>; |
| 198 | reg = <6>; |
| 199 | clocks = <&usb>; |
| 200 | }; |
| 201 | |
| 202 | udpck: udpck { |
| 203 | #clock-cells = <0>; |
| 204 | reg = <7>; |
| 205 | clocks = <&usb>; |
| 206 | }; |
| 207 | |
| 208 | pck0: pck0 { |
| 209 | #clock-cells = <0>; |
| 210 | reg = <8>; |
| 211 | clocks = <&prog0>; |
| 212 | }; |
| 213 | |
| 214 | pck1: pck1 { |
| 215 | #clock-cells = <0>; |
| 216 | reg = <9>; |
| 217 | clocks = <&prog1>; |
| 218 | }; |
| 219 | }; |
| 220 | |
| 221 | periphck { |
| 222 | compatible = "atmel,at91rm9200-clk-peripheral"; |
| 223 | #address-cells = <1>; |
| 224 | #size-cells = <0>; |
| 225 | clocks = <&mck>; |
| 226 | |
| 227 | pioA_clk: pioA_clk { |
| 228 | #clock-cells = <0>; |
| 229 | reg = <2>; |
| 230 | }; |
| 231 | |
| 232 | pioB_clk: pioB_clk { |
| 233 | #clock-cells = <0>; |
| 234 | reg = <3>; |
| 235 | }; |
| 236 | |
| 237 | pioC_clk: pioC_clk { |
| 238 | #clock-cells = <0>; |
| 239 | reg = <4>; |
| 240 | }; |
| 241 | |
| 242 | adc_clk: adc_clk { |
| 243 | #clock-cells = <0>; |
| 244 | reg = <5>; |
| 245 | }; |
| 246 | |
| 247 | usart0_clk: usart0_clk { |
| 248 | #clock-cells = <0>; |
| 249 | reg = <6>; |
| 250 | }; |
| 251 | |
| 252 | usart1_clk: usart1_clk { |
| 253 | #clock-cells = <0>; |
| 254 | reg = <7>; |
| 255 | }; |
| 256 | |
| 257 | usart2_clk: usart2_clk { |
| 258 | #clock-cells = <0>; |
| 259 | reg = <8>; |
| 260 | }; |
| 261 | |
| 262 | mci0_clk: mci0_clk { |
| 263 | #clock-cells = <0>; |
| 264 | reg = <9>; |
| 265 | }; |
| 266 | |
| 267 | udc_clk: udc_clk { |
| 268 | #clock-cells = <0>; |
| 269 | reg = <10>; |
| 270 | }; |
| 271 | |
| 272 | twi0_clk: twi0_clk { |
| 273 | reg = <11>; |
| 274 | #clock-cells = <0>; |
| 275 | }; |
| 276 | |
| 277 | spi0_clk: spi0_clk { |
| 278 | #clock-cells = <0>; |
| 279 | reg = <12>; |
| 280 | }; |
| 281 | |
| 282 | spi1_clk: spi1_clk { |
| 283 | #clock-cells = <0>; |
| 284 | reg = <13>; |
| 285 | }; |
| 286 | |
| 287 | ssc0_clk: ssc0_clk { |
| 288 | #clock-cells = <0>; |
| 289 | reg = <14>; |
| 290 | }; |
| 291 | |
| 292 | tc0_clk: tc0_clk { |
| 293 | #clock-cells = <0>; |
| 294 | reg = <17>; |
| 295 | }; |
| 296 | |
| 297 | tc1_clk: tc1_clk { |
| 298 | #clock-cells = <0>; |
| 299 | reg = <18>; |
| 300 | }; |
| 301 | |
| 302 | tc2_clk: tc2_clk { |
| 303 | #clock-cells = <0>; |
| 304 | reg = <19>; |
| 305 | }; |
| 306 | |
| 307 | ohci_clk: ohci_clk { |
| 308 | #clock-cells = <0>; |
| 309 | reg = <20>; |
| 310 | }; |
| 311 | |
| 312 | macb0_clk: macb0_clk { |
| 313 | #clock-cells = <0>; |
| 314 | reg = <21>; |
| 315 | }; |
| 316 | |
| 317 | isi_clk: isi_clk { |
| 318 | #clock-cells = <0>; |
| 319 | reg = <22>; |
| 320 | }; |
| 321 | |
| 322 | usart3_clk: usart3_clk { |
| 323 | #clock-cells = <0>; |
| 324 | reg = <23>; |
| 325 | }; |
| 326 | |
| 327 | uart0_clk: uart0_clk { |
| 328 | #clock-cells = <0>; |
| 329 | reg = <24>; |
| 330 | }; |
| 331 | |
| 332 | uart1_clk: uart1_clk { |
| 333 | #clock-cells = <0>; |
| 334 | reg = <25>; |
| 335 | }; |
| 336 | |
| 337 | tc3_clk: tc3_clk { |
| 338 | #clock-cells = <0>; |
| 339 | reg = <26>; |
| 340 | }; |
| 341 | |
| 342 | tc4_clk: tc4_clk { |
| 343 | #clock-cells = <0>; |
| 344 | reg = <27>; |
| 345 | }; |
| 346 | |
| 347 | tc5_clk: tc5_clk { |
| 348 | #clock-cells = <0>; |
| 349 | reg = <28>; |
| 350 | }; |
| 351 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | rstc@fffffd00 { |
| 355 | compatible = "atmel,at91sam9260-rstc"; |
| 356 | reg = <0xfffffd00 0x10>; |
| 357 | }; |
| 358 | |
| 359 | shdwc@fffffd10 { |
| 360 | compatible = "atmel,at91sam9260-shdwc"; |
| 361 | reg = <0xfffffd10 0x10>; |
| 362 | }; |
| 363 | |
| 364 | pit: timer@fffffd30 { |
| 365 | compatible = "atmel,at91sam9260-pit"; |
| 366 | reg = <0xfffffd30 0xf>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 367 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 368 | clocks = <&mck>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | tcb0: timer@fffa0000 { |
| 372 | compatible = "atmel,at91rm9200-tcb"; |
| 373 | reg = <0xfffa0000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 374 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 |
| 375 | 18 IRQ_TYPE_LEVEL_HIGH 0 |
| 376 | 19 IRQ_TYPE_LEVEL_HIGH 0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 377 | clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; |
| 378 | clock-names = "t0_clk", "t1_clk", "t2_clk"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | tcb1: timer@fffdc000 { |
| 382 | compatible = "atmel,at91rm9200-tcb"; |
| 383 | reg = <0xfffdc000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 384 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 |
| 385 | 27 IRQ_TYPE_LEVEL_HIGH 0 |
| 386 | 28 IRQ_TYPE_LEVEL_HIGH 0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 387 | clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; |
| 388 | clock-names = "t0_clk", "t1_clk", "t2_clk"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 389 | }; |
| 390 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 391 | pinctrl@fffff400 { |
| 392 | #address-cells = <1>; |
| 393 | #size-cells = <1>; |
| 394 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; |
| 395 | ranges = <0xfffff400 0xfffff400 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 396 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 397 | atmel,mux-mask = < |
| 398 | /* A B */ |
| 399 | 0xffffffff 0xffc00c3b /* pioA */ |
| 400 | 0xffffffff 0x7fff3ccf /* pioB */ |
| 401 | 0xffffffff 0x007fffff /* pioC */ |
| 402 | >; |
| 403 | |
| 404 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 405 | dbgu { |
| 406 | pinctrl_dbgu: dbgu-0 { |
| 407 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 408 | <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ |
| 409 | AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 410 | }; |
| 411 | }; |
| 412 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 413 | usart0 { |
| 414 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 415 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 416 | <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| 417 | AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 418 | }; |
| 419 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 420 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 421 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 422 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 423 | }; |
| 424 | |
| 425 | pinctrl_usart0_cts: usart0_cts-0 { |
| 426 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 427 | <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 428 | }; |
| 429 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 430 | pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 431 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 432 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ |
| 433 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 434 | }; |
| 435 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 436 | pinctrl_usart0_dcd: usart0_dcd-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 437 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 438 | <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 439 | }; |
| 440 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 441 | pinctrl_usart0_ri: usart0_ri-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 442 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 443 | <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 444 | }; |
| 445 | }; |
| 446 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 447 | usart1 { |
| 448 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 449 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 450 | <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ |
| 451 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 452 | }; |
| 453 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 454 | pinctrl_usart1_rts: usart1_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 455 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 456 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | pinctrl_usart1_cts: usart1_cts-0 { |
| 460 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 461 | <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 462 | }; |
| 463 | }; |
| 464 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 465 | usart2 { |
| 466 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 467 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 468 | <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ |
| 469 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 470 | }; |
| 471 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 472 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 473 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 474 | <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 475 | }; |
| 476 | |
| 477 | pinctrl_usart2_cts: usart2_cts-0 { |
| 478 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 479 | <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 480 | }; |
| 481 | }; |
| 482 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 483 | usart3 { |
| 484 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 485 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 486 | <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ |
| 487 | AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 488 | }; |
| 489 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 490 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 491 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 492 | <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 493 | }; |
| 494 | |
| 495 | pinctrl_usart3_cts: usart3_cts-0 { |
| 496 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 497 | <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 498 | }; |
| 499 | }; |
| 500 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 501 | uart0 { |
| 502 | pinctrl_uart0: uart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 503 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 504 | <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ |
| 505 | AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 506 | }; |
| 507 | }; |
| 508 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 509 | uart1 { |
| 510 | pinctrl_uart1: uart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 511 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 512 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ |
| 513 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 514 | }; |
| 515 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 516 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 517 | nand { |
| 518 | pinctrl_nand: nand-0 { |
| 519 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 520 | <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ |
| 521 | AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 522 | }; |
| 523 | }; |
| 524 | |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 525 | macb { |
| 526 | pinctrl_macb_rmii: macb_rmii-0 { |
| 527 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 528 | <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ |
| 529 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ |
| 530 | AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ |
| 531 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ |
| 532 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ |
| 533 | AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 534 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ |
| 535 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ |
| 536 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ |
| 537 | AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | pinctrl_macb_rmii_mii: macb_rmii_mii-0 { |
| 541 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 542 | <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ |
| 543 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ |
| 544 | AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 545 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 546 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ |
| 547 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 548 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 549 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 550 | }; |
| 551 | |
| 552 | pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { |
| 553 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 554 | <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ |
| 555 | AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ |
Olof Johansson | fc20c6f | 2013-06-01 00:38:04 -0700 | [diff] [blame] | 556 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 557 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 558 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ |
| 559 | AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 560 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 561 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 562 | }; |
| 563 | }; |
| 564 | |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 565 | mmc0 { |
| 566 | pinctrl_mmc0_clk: mmc0_clk-0 { |
| 567 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 568 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 569 | }; |
| 570 | |
| 571 | pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { |
| 572 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 573 | <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ |
| 574 | AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 575 | }; |
| 576 | |
| 577 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 578 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 579 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ |
| 580 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ |
| 581 | AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { |
| 585 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 586 | <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ |
| 587 | AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 588 | }; |
| 589 | |
| 590 | pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { |
| 591 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 592 | <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ |
| 593 | AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ |
| 594 | AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ |
Jean-Christophe PLAGNIOL-VILLARD | d4fe9ac | 2012-11-16 08:24:17 +0800 | [diff] [blame] | 595 | }; |
| 596 | }; |
| 597 | |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 598 | ssc0 { |
| 599 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 600 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 601 | <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ |
| 602 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ |
| 603 | AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 604 | }; |
| 605 | |
| 606 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 607 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 608 | <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ |
| 609 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ |
| 610 | AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 611 | }; |
| 612 | }; |
| 613 | |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 614 | spi0 { |
| 615 | pinctrl_spi0: spi0-0 { |
| 616 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 617 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ |
| 618 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ |
| 619 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 620 | }; |
| 621 | }; |
| 622 | |
| 623 | spi1 { |
| 624 | pinctrl_spi1: spi1-0 { |
| 625 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 626 | <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ |
| 627 | AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ |
| 628 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 629 | }; |
| 630 | }; |
| 631 | |
Jean-Christophe PLAGNIOL-VILLARD | f89ae61 | 2013-05-26 16:55:59 +0800 | [diff] [blame] | 632 | i2c_gpio0 { |
| 633 | pinctrl_i2c_gpio0: i2c_gpio0-0 { |
| 634 | atmel,pins = |
| 635 | <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE |
| 636 | AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; |
| 637 | }; |
| 638 | }; |
| 639 | |
Boris BREZILLON | 028633c | 2013-05-24 10:05:56 +0000 | [diff] [blame] | 640 | tcb0 { |
| 641 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { |
| 642 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 643 | }; |
| 644 | |
| 645 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { |
| 646 | atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 647 | }; |
| 648 | |
| 649 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { |
| 650 | atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 651 | }; |
| 652 | |
| 653 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { |
| 654 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 655 | }; |
| 656 | |
| 657 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { |
| 658 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 659 | }; |
| 660 | |
| 661 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { |
| 662 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 663 | }; |
| 664 | |
| 665 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { |
| 666 | atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 667 | }; |
| 668 | |
| 669 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { |
| 670 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 671 | }; |
| 672 | |
| 673 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { |
| 674 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 675 | }; |
| 676 | }; |
| 677 | |
| 678 | tcb1 { |
| 679 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { |
| 680 | atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 681 | }; |
| 682 | |
| 683 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { |
| 684 | atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 685 | }; |
| 686 | |
| 687 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { |
| 688 | atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 689 | }; |
| 690 | |
| 691 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { |
| 692 | atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 693 | }; |
| 694 | |
| 695 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { |
| 696 | atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 697 | }; |
| 698 | |
| 699 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { |
| 700 | atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 701 | }; |
| 702 | |
| 703 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { |
| 704 | atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 705 | }; |
| 706 | |
| 707 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { |
| 708 | atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 709 | }; |
| 710 | |
| 711 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { |
| 712 | atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 713 | }; |
| 714 | }; |
| 715 | |
| 716 | pioA: gpio@fffff400 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 717 | compatible = "atmel,at91rm9200-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 718 | reg = <0xfffff400 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 719 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 720 | #gpio-cells = <2>; |
| 721 | gpio-controller; |
| 722 | interrupt-controller; |
| 723 | #interrupt-cells = <2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 724 | clocks = <&pioA_clk>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 725 | }; |
| 726 | |
| 727 | pioB: gpio@fffff600 { |
| 728 | compatible = "atmel,at91rm9200-gpio"; |
| 729 | reg = <0xfffff600 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 730 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 731 | #gpio-cells = <2>; |
| 732 | gpio-controller; |
| 733 | interrupt-controller; |
| 734 | #interrupt-cells = <2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 735 | clocks = <&pioB_clk>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 736 | }; |
| 737 | |
| 738 | pioC: gpio@fffff800 { |
| 739 | compatible = "atmel,at91rm9200-gpio"; |
| 740 | reg = <0xfffff800 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 741 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 742 | #gpio-cells = <2>; |
| 743 | gpio-controller; |
| 744 | interrupt-controller; |
| 745 | #interrupt-cells = <2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 746 | clocks = <&pioC_clk>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 747 | }; |
| 748 | }; |
| 749 | |
| 750 | dbgu: serial@fffff200 { |
| 751 | compatible = "atmel,at91sam9260-usart"; |
| 752 | reg = <0xfffff200 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 753 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 754 | pinctrl-names = "default"; |
| 755 | pinctrl-0 = <&pinctrl_dbgu>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 756 | clocks = <&mck>; |
| 757 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 758 | status = "disabled"; |
| 759 | }; |
| 760 | |
| 761 | usart0: serial@fffb0000 { |
| 762 | compatible = "atmel,at91sam9260-usart"; |
| 763 | reg = <0xfffb0000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 764 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 765 | atmel,use-dma-rx; |
| 766 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 767 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 768 | pinctrl-0 = <&pinctrl_usart0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 769 | clocks = <&usart0_clk>; |
| 770 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 771 | status = "disabled"; |
| 772 | }; |
| 773 | |
| 774 | usart1: serial@fffb4000 { |
| 775 | compatible = "atmel,at91sam9260-usart"; |
| 776 | reg = <0xfffb4000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 777 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 778 | atmel,use-dma-rx; |
| 779 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 780 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 781 | pinctrl-0 = <&pinctrl_usart1>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 782 | clocks = <&usart1_clk>; |
| 783 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | usart2: serial@fffb8000 { |
| 788 | compatible = "atmel,at91sam9260-usart"; |
| 789 | reg = <0xfffb8000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 790 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 791 | atmel,use-dma-rx; |
| 792 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 793 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 794 | pinctrl-0 = <&pinctrl_usart2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 795 | clocks = <&usart2_clk>; |
| 796 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 797 | status = "disabled"; |
| 798 | }; |
| 799 | |
| 800 | usart3: serial@fffd0000 { |
| 801 | compatible = "atmel,at91sam9260-usart"; |
| 802 | reg = <0xfffd0000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 803 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 804 | atmel,use-dma-rx; |
| 805 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 806 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 807 | pinctrl-0 = <&pinctrl_usart3>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 808 | clocks = <&usart3_clk>; |
| 809 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 810 | status = "disabled"; |
| 811 | }; |
| 812 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 813 | uart0: serial@fffd4000 { |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 814 | compatible = "atmel,at91sam9260-usart"; |
| 815 | reg = <0xfffd4000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 816 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 817 | atmel,use-dma-rx; |
| 818 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 819 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 820 | pinctrl-0 = <&pinctrl_uart0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 821 | clocks = <&uart0_clk>; |
| 822 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 823 | status = "disabled"; |
| 824 | }; |
| 825 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 826 | uart1: serial@fffd8000 { |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 827 | compatible = "atmel,at91sam9260-usart"; |
| 828 | reg = <0xfffd8000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 829 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 830 | atmel,use-dma-rx; |
| 831 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 832 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 833 | pinctrl-0 = <&pinctrl_uart1>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 834 | clocks = <&uart1_clk>; |
| 835 | clock-names = "usart"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 836 | status = "disabled"; |
| 837 | }; |
| 838 | |
| 839 | macb0: ethernet@fffc4000 { |
| 840 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 841 | reg = <0xfffc4000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 842 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; |
Jean-Christophe PLAGNIOL-VILLARD | d9b4fe8 | 2012-10-23 10:19:11 +0800 | [diff] [blame] | 843 | pinctrl-names = "default"; |
| 844 | pinctrl-0 = <&pinctrl_macb_rmii>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 845 | clocks = <&macb0_clk>, <&macb0_clk>; |
| 846 | clock-names = "hclk", "pclk"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 847 | status = "disabled"; |
| 848 | }; |
| 849 | |
| 850 | usb1: gadget@fffa4000 { |
| 851 | compatible = "atmel,at91rm9200-udc"; |
| 852 | reg = <0xfffa4000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 853 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 854 | clocks = <&udc_clk>, <&udpck>; |
| 855 | clock-names = "pclk", "hclk"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 856 | status = "disabled"; |
| 857 | }; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 858 | |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 859 | i2c0: i2c@fffac000 { |
| 860 | compatible = "atmel,at91sam9260-i2c"; |
| 861 | reg = <0xfffac000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 862 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 863 | #address-cells = <1>; |
| 864 | #size-cells = <0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 865 | clocks = <&twi0_clk>; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 866 | status = "disabled"; |
| 867 | }; |
| 868 | |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 869 | mmc0: mmc@fffa8000 { |
| 870 | compatible = "atmel,hsmci"; |
| 871 | reg = <0xfffa8000 0x600>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 872 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 873 | #address-cells = <1>; |
| 874 | #size-cells = <0>; |
Jean-Christophe PLAGNIOL-VILLARD | 6e19c94 | 2013-07-15 12:05:19 +0200 | [diff] [blame] | 875 | pinctrl-names = "default"; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 876 | clocks = <&mci0_clk>; |
| 877 | clock-names = "mci_clk"; |
Ludovic Desroches | 9873137 | 2012-11-19 12:23:36 +0100 | [diff] [blame] | 878 | status = "disabled"; |
| 879 | }; |
| 880 | |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 881 | ssc0: ssc@fffbc000 { |
| 882 | compatible = "atmel,at91rm9200-ssc"; |
| 883 | reg = <0xfffbc000 0x4000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 884 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
Bo Shen | 544ae6b | 2013-01-11 15:08:30 +0100 | [diff] [blame] | 885 | pinctrl-names = "default"; |
| 886 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 887 | clocks = <&ssc0_clk>; |
| 888 | clock-names = "pclk"; |
Linus Torvalds | 046e7d6 | 2012-12-13 11:51:23 -0800 | [diff] [blame] | 889 | status = "disabled"; |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 890 | }; |
| 891 | |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 892 | spi0: spi@fffc8000 { |
| 893 | #address-cells = <1>; |
| 894 | #size-cells = <0>; |
| 895 | compatible = "atmel,at91rm9200-spi"; |
| 896 | reg = <0xfffc8000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 897 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 898 | pinctrl-names = "default"; |
| 899 | pinctrl-0 = <&pinctrl_spi0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 900 | clocks = <&spi0_clk>; |
| 901 | clock-names = "spi_clk"; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 902 | status = "disabled"; |
| 903 | }; |
| 904 | |
| 905 | spi1: spi@fffcc000 { |
| 906 | #address-cells = <1>; |
| 907 | #size-cells = <0>; |
| 908 | compatible = "atmel,at91rm9200-spi"; |
| 909 | reg = <0xfffcc000 0x200>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 910 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
Wenyou Yang | a68b728 | 2013-04-03 14:03:52 +0800 | [diff] [blame] | 911 | pinctrl-names = "default"; |
| 912 | pinctrl-0 = <&pinctrl_spi1>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 913 | clocks = <&spi1_clk>; |
| 914 | clock-names = "spi_clk"; |
Richard Genoud | d50f88a | 2013-04-03 14:02:18 +0800 | [diff] [blame] | 915 | status = "disabled"; |
| 916 | }; |
| 917 | |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 918 | adc0: adc@fffe0000 { |
Alexandre Belloni | e568d69 | 2014-03-10 20:17:21 +0100 | [diff] [blame] | 919 | #address-cells = <1>; |
| 920 | #size-cells = <0>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 921 | compatible = "atmel,at91sam9260-adc"; |
| 922 | reg = <0xfffe0000 0x100>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 923 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 924 | clocks = <&adc_clk>, <&adc_op_clk>; |
| 925 | clock-names = "adc_clk", "adc_op_clk"; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 926 | atmel,adc-use-external-triggers; |
| 927 | atmel,adc-channels-used = <0xf>; |
| 928 | atmel,adc-vref = <3300>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 929 | atmel,adc-startup-time = <15>; |
Ludovic Desroches | 4b50da6 | 2013-03-29 10:13:19 +0100 | [diff] [blame] | 930 | atmel,adc-res = <8 10>; |
| 931 | atmel,adc-res-names = "lowres", "highres"; |
| 932 | atmel,adc-use-res = "highres"; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 933 | |
| 934 | trigger@0 { |
Alexandre Belloni | e568d69 | 2014-03-10 20:17:21 +0100 | [diff] [blame] | 935 | reg = <0>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 936 | trigger-name = "timer-counter-0"; |
| 937 | trigger-value = <0x1>; |
| 938 | }; |
| 939 | trigger@1 { |
Alexandre Belloni | e568d69 | 2014-03-10 20:17:21 +0100 | [diff] [blame] | 940 | reg = <1>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 941 | trigger-name = "timer-counter-1"; |
| 942 | trigger-value = <0x3>; |
| 943 | }; |
| 944 | |
| 945 | trigger@2 { |
Alexandre Belloni | e568d69 | 2014-03-10 20:17:21 +0100 | [diff] [blame] | 946 | reg = <2>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 947 | trigger-name = "timer-counter-2"; |
| 948 | trigger-value = <0x5>; |
| 949 | }; |
| 950 | |
| 951 | trigger@3 { |
Alexandre Belloni | e568d69 | 2014-03-10 20:17:21 +0100 | [diff] [blame] | 952 | reg = <3>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 953 | trigger-name = "external"; |
Alexandre Belloni | c1ff0b4 | 2014-05-12 18:32:55 +0200 | [diff] [blame] | 954 | trigger-value = <0xd>; |
Nicolas Ferre | 73d68d9 | 2012-05-16 17:37:06 +0200 | [diff] [blame] | 955 | trigger-external; |
| 956 | }; |
| 957 | }; |
Fabio Porcedda | 7492e7c | 2012-11-12 09:37:26 +0100 | [diff] [blame] | 958 | |
| 959 | watchdog@fffffd40 { |
| 960 | compatible = "atmel,at91sam9260-wdt"; |
| 961 | reg = <0xfffffd40 0x10>; |
Boris BREZILLON | fe46aa6 | 2013-10-04 09:24:14 +0200 | [diff] [blame] | 962 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 963 | atmel,watchdog-type = "hardware"; |
| 964 | atmel,reset-type = "all"; |
| 965 | atmel,dbg-halt; |
| 966 | atmel,idle-halt; |
Fabio Porcedda | 7492e7c | 2012-11-12 09:37:26 +0100 | [diff] [blame] | 967 | status = "disabled"; |
| 968 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 969 | }; |
| 970 | |
| 971 | nand0: nand@40000000 { |
| 972 | compatible = "atmel,at91rm9200-nand"; |
| 973 | #address-cells = <1>; |
| 974 | #size-cells = <1>; |
| 975 | reg = <0x40000000 0x10000000 |
| 976 | 0xffffe800 0x200 |
| 977 | >; |
| 978 | atmel,nand-addr-offset = <21>; |
| 979 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 980 | pinctrl-names = "default"; |
| 981 | pinctrl-0 = <&pinctrl_nand>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 982 | gpios = <&pioC 13 GPIO_ACTIVE_HIGH |
| 983 | &pioC 14 GPIO_ACTIVE_HIGH |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 984 | 0 |
| 985 | >; |
| 986 | status = "disabled"; |
| 987 | }; |
| 988 | |
| 989 | usb0: ohci@00500000 { |
| 990 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 991 | reg = <0x00500000 0x100000>; |
Jean-Christophe PLAGNIOL-VILLARD | 5e8b3bc | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 992 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; |
Alexandre Belloni | 684b8fb | 2014-04-18 12:44:20 +0200 | [diff] [blame] | 993 | clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; |
| 994 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 995 | status = "disabled"; |
| 996 | }; |
| 997 | }; |
| 998 | |
| 999 | i2c@0 { |
| 1000 | compatible = "i2c-gpio"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 1001 | gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ |
| 1002 | &pioA 24 GPIO_ACTIVE_HIGH /* scl */ |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 1003 | >; |
| 1004 | i2c-gpio,sda-open-drain; |
| 1005 | i2c-gpio,scl-open-drain; |
| 1006 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 1007 | #address-cells = <1>; |
| 1008 | #size-cells = <0>; |
Jean-Christophe PLAGNIOL-VILLARD | f89ae61 | 2013-05-26 16:55:59 +0800 | [diff] [blame] | 1009 | pinctrl-names = "default"; |
| 1010 | pinctrl-0 = <&pinctrl_i2c_gpio0>; |
Jean-Christophe PLAGNIOL-VILLARD | 5b6089c | 2012-04-09 19:26:33 +0800 | [diff] [blame] | 1011 | status = "disabled"; |
| 1012 | }; |
| 1013 | }; |