Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 9 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 11 | #include <dt-bindings/pinctrl/omap.h> |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 12 | |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 13 | / { |
| 14 | compatible = "ti,omap4430", "ti,omap4"; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 15 | interrupt-parent = <&wakeupgen>; |
Javier Martinez Canillas | da6269e | 2016-08-31 12:35:19 +0200 | [diff] [blame] | 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
Javier Martinez Canillas | 835bf87 | 2016-12-19 11:44:35 -0300 | [diff] [blame] | 18 | chosen { }; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 19 | |
| 20 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 21 | i2c0 = &i2c1; |
| 22 | i2c1 = &i2c2; |
| 23 | i2c2 = &i2c3; |
| 24 | i2c3 = &i2c4; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 25 | serial0 = &uart1; |
| 26 | serial1 = &uart2; |
| 27 | serial2 = &uart3; |
| 28 | serial3 = &uart4; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 29 | }; |
| 30 | |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 31 | cpus { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 35 | cpu@0 { |
| 36 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 37 | device_type = "cpu"; |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 38 | next-level-cache = <&L2>; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 39 | reg = <0x0>; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 40 | |
| 41 | clocks = <&dpll_mpu_ck>; |
| 42 | clock-names = "cpu"; |
| 43 | |
| 44 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 45 | }; |
| 46 | cpu@1 { |
| 47 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 48 | device_type = "cpu"; |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 49 | next-level-cache = <&L2>; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 50 | reg = <0x1>; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 51 | }; |
| 52 | }; |
| 53 | |
Benoit Cousson | 5635121 | 2012-09-03 17:56:32 +0200 | [diff] [blame] | 54 | gic: interrupt-controller@48241000 { |
| 55 | compatible = "arm,cortex-a9-gic"; |
| 56 | interrupt-controller; |
| 57 | #interrupt-cells = <3>; |
| 58 | reg = <0x48241000 0x1000>, |
| 59 | <0x48240100 0x0100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 60 | interrupt-parent = <&gic>; |
Benoit Cousson | 5635121 | 2012-09-03 17:56:32 +0200 | [diff] [blame] | 61 | }; |
| 62 | |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 63 | L2: l2-cache-controller@48242000 { |
| 64 | compatible = "arm,pl310-cache"; |
| 65 | reg = <0x48242000 0x1000>; |
| 66 | cache-unified; |
| 67 | cache-level = <2>; |
| 68 | }; |
| 69 | |
Lee Jones | 75d71d4 | 2013-07-22 11:52:36 +0100 | [diff] [blame] | 70 | local-timer@48240600 { |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 71 | compatible = "arm,cortex-a9-twd-timer"; |
Gilles Chanteperdrix | 23c4737 | 2014-04-07 22:05:39 +0200 | [diff] [blame] | 72 | clocks = <&mpu_periphclk>; |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 73 | reg = <0x48240600 0x20>; |
Jon Hunter | 6b47257 | 2016-03-17 14:19:06 +0000 | [diff] [blame] | 74 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 75 | interrupt-parent = <&gic>; |
| 76 | }; |
| 77 | |
| 78 | wakeupgen: interrupt-controller@48281000 { |
| 79 | compatible = "ti,omap4-wugen-mpu"; |
| 80 | interrupt-controller; |
| 81 | #interrupt-cells = <3>; |
| 82 | reg = <0x48281000 0x1000>; |
| 83 | interrupt-parent = <&gic>; |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 84 | }; |
| 85 | |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 86 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 87 | * The soc node represents the soc top level view. It is used for IPs |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 88 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 89 | */ |
| 90 | soc { |
| 91 | compatible = "ti,omap-infra"; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 92 | mpu { |
| 93 | compatible = "ti,omap4-mpu"; |
| 94 | ti,hwmods = "mpu"; |
Rajendra Nayak | 1306c08 | 2014-09-10 11:04:04 -0500 | [diff] [blame] | 95 | sram = <&ocmcram>; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | dsp { |
| 99 | compatible = "ti,omap3-c64"; |
| 100 | ti,hwmods = "dsp"; |
| 101 | }; |
| 102 | |
| 103 | iva { |
| 104 | compatible = "ti,ivahd"; |
| 105 | ti,hwmods = "iva"; |
| 106 | }; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | /* |
| 110 | * XXX: Use a flat representation of the OMAP4 interconnect. |
| 111 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 112 | * Since it will not bring real advantage to represent that in DT for |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 113 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 114 | * hierarchy. |
| 115 | */ |
| 116 | ocp { |
Benoit Cousson | ad8dfac | 2011-08-12 13:48:47 +0200 | [diff] [blame] | 117 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 118 | #address-cells = <1>; |
| 119 | #size-cells = <1>; |
| 120 | ranges; |
Benoit Cousson | ad8dfac | 2011-08-12 13:48:47 +0200 | [diff] [blame] | 121 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Santosh Shilimkar | 20a60ea | 2013-02-26 17:36:14 +0530 | [diff] [blame] | 122 | reg = <0x44000000 0x1000>, |
| 123 | <0x44800000 0x2000>, |
| 124 | <0x45000000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 125 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 126 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 127 | |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 128 | l4_cfg: l4@4a000000 { |
| 129 | compatible = "ti,omap4-l4-cfg", "simple-bus"; |
Tony Lindgren | 679e331 | 2012-09-10 10:34:51 -0700 | [diff] [blame] | 130 | #address-cells = <1>; |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 131 | #size-cells = <1>; |
| 132 | ranges = <0 0x4a000000 0x1000000>; |
Tony Lindgren | 679e331 | 2012-09-10 10:34:51 -0700 | [diff] [blame] | 133 | |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 134 | cm1: cm1@4000 { |
| 135 | compatible = "ti,omap4-cm1"; |
| 136 | reg = <0x4000 0x2000>; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 137 | |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 138 | cm1_clocks: clocks { |
| 139 | #address-cells = <1>; |
| 140 | #size-cells = <0>; |
| 141 | }; |
| 142 | |
| 143 | cm1_clockdomains: clockdomains { |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | cm2: cm2@8000 { |
| 148 | compatible = "ti,omap4-cm2"; |
| 149 | reg = <0x8000 0x3000>; |
| 150 | |
| 151 | cm2_clocks: clocks { |
| 152 | #address-cells = <1>; |
| 153 | #size-cells = <0>; |
| 154 | }; |
| 155 | |
| 156 | cm2_clockdomains: clockdomains { |
| 157 | }; |
| 158 | }; |
| 159 | |
| 160 | omap4_scm_core: scm@2000 { |
| 161 | compatible = "ti,omap4-scm-core", "simple-bus"; |
| 162 | reg = <0x2000 0x1000>; |
| 163 | #address-cells = <1>; |
| 164 | #size-cells = <1>; |
| 165 | ranges = <0 0x2000 0x1000>; |
| 166 | |
| 167 | scm_conf: scm_conf@0 { |
| 168 | compatible = "syscon"; |
| 169 | reg = <0x0 0x800>; |
| 170 | #address-cells = <1>; |
| 171 | #size-cells = <1>; |
| 172 | }; |
| 173 | }; |
| 174 | |
| 175 | omap4_padconf_core: scm@100000 { |
| 176 | compatible = "ti,omap4-scm-padconf-core", |
| 177 | "simple-bus"; |
| 178 | #address-cells = <1>; |
| 179 | #size-cells = <1>; |
| 180 | ranges = <0 0x100000 0x1000>; |
| 181 | |
| 182 | omap4_pmx_core: pinmux@40 { |
| 183 | compatible = "ti,omap4-padconf", |
| 184 | "pinctrl-single"; |
| 185 | reg = <0x40 0x0196>; |
| 186 | #address-cells = <1>; |
| 187 | #size-cells = <0>; |
| 188 | #interrupt-cells = <1>; |
| 189 | interrupt-controller; |
| 190 | pinctrl-single,register-width = <16>; |
| 191 | pinctrl-single,function-mask = <0x7fff>; |
| 192 | }; |
| 193 | |
| 194 | omap4_padconf_global: omap4_padconf_global@5a0 { |
Kishon Vijay Abraham I | 89a898d | 2015-07-27 17:46:39 +0530 | [diff] [blame] | 195 | compatible = "syscon", |
| 196 | "simple-bus"; |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 197 | reg = <0x5a0 0x170>; |
| 198 | #address-cells = <1>; |
| 199 | #size-cells = <1>; |
Kishon Vijay Abraham I | 9a5e3f2 | 2015-09-04 17:38:24 +0530 | [diff] [blame] | 200 | ranges = <0 0x5a0 0x170>; |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 201 | |
Javier Martinez Canillas | 308cfda | 2016-04-01 16:20:18 -0400 | [diff] [blame] | 202 | pbias_regulator: pbias_regulator@60 { |
Kishon Vijay Abraham I | 737f146 | 2015-09-04 17:30:25 +0530 | [diff] [blame] | 203 | compatible = "ti,pbias-omap4", "ti,pbias-omap"; |
Tero Kristo | 7415b0b | 2015-02-12 11:32:14 +0200 | [diff] [blame] | 204 | reg = <0x60 0x4>; |
| 205 | syscon = <&omap4_padconf_global>; |
| 206 | pbias_mmc_reg: pbias_mmc_omap4 { |
| 207 | regulator-name = "pbias_mmc_omap4"; |
| 208 | regulator-min-microvolt = <1800000>; |
| 209 | regulator-max-microvolt = <3000000>; |
| 210 | }; |
| 211 | }; |
| 212 | }; |
| 213 | }; |
| 214 | |
| 215 | l4_wkup: l4@300000 { |
| 216 | compatible = "ti,omap4-l4-wkup", "simple-bus"; |
| 217 | #address-cells = <1>; |
| 218 | #size-cells = <1>; |
| 219 | ranges = <0 0x300000 0x40000>; |
| 220 | |
| 221 | counter32k: counter@4000 { |
| 222 | compatible = "ti,omap-counter32k"; |
| 223 | reg = <0x4000 0x20>; |
| 224 | ti,hwmods = "counter_32k"; |
| 225 | }; |
| 226 | |
| 227 | prm: prm@6000 { |
| 228 | compatible = "ti,omap4-prm"; |
| 229 | reg = <0x6000 0x3000>; |
| 230 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 231 | |
| 232 | prm_clocks: clocks { |
| 233 | #address-cells = <1>; |
| 234 | #size-cells = <0>; |
| 235 | }; |
| 236 | |
| 237 | prm_clockdomains: clockdomains { |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | scrm: scrm@a000 { |
| 242 | compatible = "ti,omap4-scrm"; |
| 243 | reg = <0xa000 0x2000>; |
| 244 | |
| 245 | scrm_clocks: clocks { |
| 246 | #address-cells = <1>; |
| 247 | #size-cells = <0>; |
| 248 | }; |
| 249 | |
| 250 | scrm_clockdomains: clockdomains { |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | omap4_pmx_wkup: pinmux@1e040 { |
| 255 | compatible = "ti,omap4-padconf", |
| 256 | "pinctrl-single"; |
| 257 | reg = <0x1e040 0x0038>; |
| 258 | #address-cells = <1>; |
| 259 | #size-cells = <0>; |
| 260 | #interrupt-cells = <1>; |
| 261 | interrupt-controller; |
| 262 | pinctrl-single,register-width = <16>; |
| 263 | pinctrl-single,function-mask = <0x7fff>; |
| 264 | }; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 265 | }; |
| 266 | }; |
| 267 | |
Rajendra Nayak | 8b9a281 | 2014-09-10 11:04:03 -0500 | [diff] [blame] | 268 | ocmcram: ocmcram@40304000 { |
| 269 | compatible = "mmio-sram"; |
| 270 | reg = <0x40304000 0xa000>; /* 40k */ |
| 271 | }; |
| 272 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 273 | sdma: dma-controller@4a056000 { |
| 274 | compatible = "ti,omap4430-sdma"; |
| 275 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 276 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 277 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 278 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 279 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 280 | #dma-cells = <1>; |
Peter Ujfalusi | 24ac177 | 2015-02-20 15:42:04 +0200 | [diff] [blame] | 281 | dma-channels = <32>; |
| 282 | dma-requests = <127>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 283 | }; |
| 284 | |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 285 | gpio1: gpio@4a310000 { |
| 286 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 287 | reg = <0x4a310000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 288 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 289 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 290 | ti,gpio-always-on; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 291 | gpio-controller; |
| 292 | #gpio-cells = <2>; |
| 293 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 294 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 295 | }; |
| 296 | |
| 297 | gpio2: gpio@48055000 { |
| 298 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 299 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 300 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 301 | ti,hwmods = "gpio2"; |
| 302 | gpio-controller; |
| 303 | #gpio-cells = <2>; |
| 304 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 305 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 306 | }; |
| 307 | |
| 308 | gpio3: gpio@48057000 { |
| 309 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 310 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 311 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 312 | ti,hwmods = "gpio3"; |
| 313 | gpio-controller; |
| 314 | #gpio-cells = <2>; |
| 315 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 316 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | gpio4: gpio@48059000 { |
| 320 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 321 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 322 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 323 | ti,hwmods = "gpio4"; |
| 324 | gpio-controller; |
| 325 | #gpio-cells = <2>; |
| 326 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 327 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | gpio5: gpio@4805b000 { |
| 331 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 332 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 333 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 334 | ti,hwmods = "gpio5"; |
| 335 | gpio-controller; |
| 336 | #gpio-cells = <2>; |
| 337 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 338 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 339 | }; |
| 340 | |
| 341 | gpio6: gpio@4805d000 { |
| 342 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 343 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 344 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 345 | ti,hwmods = "gpio6"; |
| 346 | gpio-controller; |
| 347 | #gpio-cells = <2>; |
| 348 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 349 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 350 | }; |
| 351 | |
Franklin S Cooper Jr | 258511e | 2015-10-28 16:02:16 -0500 | [diff] [blame] | 352 | elm: elm@48078000 { |
| 353 | compatible = "ti,am3352-elm"; |
| 354 | reg = <0x48078000 0x2000>; |
| 355 | interrupts = <4>; |
| 356 | ti,hwmods = "elm"; |
| 357 | status = "disabled"; |
| 358 | }; |
| 359 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 360 | gpmc: gpmc@50000000 { |
| 361 | compatible = "ti,omap4430-gpmc"; |
| 362 | reg = <0x50000000 0x1000>; |
| 363 | #address-cells = <2>; |
| 364 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 365 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Franklin S Cooper Jr | 201c7e3 | 2015-10-15 12:37:27 -0500 | [diff] [blame] | 366 | dmas = <&sdma 4>; |
| 367 | dma-names = "rxtx"; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 368 | gpmc,num-cs = <8>; |
| 369 | gpmc,num-waitpins = <4>; |
| 370 | ti,hwmods = "gpmc"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 371 | ti,no-idle-on-init; |
Florian Vaussard | 7b8b6af | 2014-02-26 11:38:09 +0100 | [diff] [blame] | 372 | clocks = <&l3_div_ck>; |
| 373 | clock-names = "fck"; |
Roger Quadros | 8c75b76 | 2016-04-07 13:25:29 +0300 | [diff] [blame] | 374 | interrupt-controller; |
| 375 | #interrupt-cells = <2>; |
| 376 | gpio-controller; |
| 377 | #gpio-cells = <2>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 378 | }; |
| 379 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 380 | uart1: serial@4806a000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 381 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 382 | reg = <0x4806a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 383 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 384 | ti,hwmods = "uart1"; |
| 385 | clock-frequency = <48000000>; |
| 386 | }; |
| 387 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 388 | uart2: serial@4806c000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 389 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 390 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 391 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 392 | ti,hwmods = "uart2"; |
| 393 | clock-frequency = <48000000>; |
| 394 | }; |
| 395 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 396 | uart3: serial@48020000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 397 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 398 | reg = <0x48020000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 399 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 400 | ti,hwmods = "uart3"; |
| 401 | clock-frequency = <48000000>; |
| 402 | }; |
| 403 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 404 | uart4: serial@4806e000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 405 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 406 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 407 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 408 | ti,hwmods = "uart4"; |
| 409 | clock-frequency = <48000000>; |
| 410 | }; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 411 | |
Suman Anna | 04c7d92 | 2013-10-10 16:15:33 -0500 | [diff] [blame] | 412 | hwspinlock: spinlock@4a0f6000 { |
| 413 | compatible = "ti,omap4-hwspinlock"; |
| 414 | reg = <0x4a0f6000 0x1000>; |
| 415 | ti,hwmods = "spinlock"; |
Suman Anna | 3405421 | 2014-01-13 18:26:45 -0600 | [diff] [blame] | 416 | #hwlock-cells = <1>; |
Suman Anna | 04c7d92 | 2013-10-10 16:15:33 -0500 | [diff] [blame] | 417 | }; |
| 418 | |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 419 | i2c1: i2c@48070000 { |
| 420 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 421 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 422 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 423 | #address-cells = <1>; |
| 424 | #size-cells = <0>; |
| 425 | ti,hwmods = "i2c1"; |
| 426 | }; |
| 427 | |
| 428 | i2c2: i2c@48072000 { |
| 429 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 430 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 431 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 432 | #address-cells = <1>; |
| 433 | #size-cells = <0>; |
| 434 | ti,hwmods = "i2c2"; |
| 435 | }; |
| 436 | |
| 437 | i2c3: i2c@48060000 { |
| 438 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 439 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 440 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 441 | #address-cells = <1>; |
| 442 | #size-cells = <0>; |
| 443 | ti,hwmods = "i2c3"; |
| 444 | }; |
| 445 | |
| 446 | i2c4: i2c@48350000 { |
| 447 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 448 | reg = <0x48350000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 449 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 450 | #address-cells = <1>; |
| 451 | #size-cells = <0>; |
| 452 | ti,hwmods = "i2c4"; |
| 453 | }; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 454 | |
| 455 | mcspi1: spi@48098000 { |
| 456 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 457 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 458 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 459 | #address-cells = <1>; |
| 460 | #size-cells = <0>; |
| 461 | ti,hwmods = "mcspi1"; |
| 462 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 463 | dmas = <&sdma 35>, |
| 464 | <&sdma 36>, |
| 465 | <&sdma 37>, |
| 466 | <&sdma 38>, |
| 467 | <&sdma 39>, |
| 468 | <&sdma 40>, |
| 469 | <&sdma 41>, |
| 470 | <&sdma 42>; |
| 471 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 472 | "tx2", "rx2", "tx3", "rx3"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 473 | }; |
| 474 | |
| 475 | mcspi2: spi@4809a000 { |
| 476 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 477 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 478 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 479 | #address-cells = <1>; |
| 480 | #size-cells = <0>; |
| 481 | ti,hwmods = "mcspi2"; |
| 482 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 483 | dmas = <&sdma 43>, |
| 484 | <&sdma 44>, |
| 485 | <&sdma 45>, |
| 486 | <&sdma 46>; |
| 487 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 488 | }; |
| 489 | |
| 490 | mcspi3: spi@480b8000 { |
| 491 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 492 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 493 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 494 | #address-cells = <1>; |
| 495 | #size-cells = <0>; |
| 496 | ti,hwmods = "mcspi3"; |
| 497 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 498 | dmas = <&sdma 15>, <&sdma 16>; |
| 499 | dma-names = "tx0", "rx0"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 500 | }; |
| 501 | |
| 502 | mcspi4: spi@480ba000 { |
| 503 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 504 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 505 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 506 | #address-cells = <1>; |
| 507 | #size-cells = <0>; |
| 508 | ti,hwmods = "mcspi4"; |
| 509 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 510 | dmas = <&sdma 70>, <&sdma 71>; |
| 511 | dma-names = "tx0", "rx0"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 512 | }; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 513 | |
| 514 | mmc1: mmc@4809c000 { |
| 515 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 516 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 517 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 518 | ti,hwmods = "mmc1"; |
| 519 | ti,dual-volt; |
| 520 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 521 | dmas = <&sdma 61>, <&sdma 62>; |
| 522 | dma-names = "tx", "rx"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 523 | pbias-supply = <&pbias_mmc_reg>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 524 | }; |
| 525 | |
| 526 | mmc2: mmc@480b4000 { |
| 527 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 528 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 529 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 530 | ti,hwmods = "mmc2"; |
| 531 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 532 | dmas = <&sdma 47>, <&sdma 48>; |
| 533 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | mmc3: mmc@480ad000 { |
| 537 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 538 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 539 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 540 | ti,hwmods = "mmc3"; |
| 541 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 542 | dmas = <&sdma 77>, <&sdma 78>; |
| 543 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 544 | }; |
| 545 | |
| 546 | mmc4: mmc@480d1000 { |
| 547 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 548 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 549 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 550 | ti,hwmods = "mmc4"; |
| 551 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 552 | dmas = <&sdma 57>, <&sdma 58>; |
| 553 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 554 | }; |
| 555 | |
| 556 | mmc5: mmc@480d5000 { |
| 557 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 558 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 559 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 560 | ti,hwmods = "mmc5"; |
| 561 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 562 | dmas = <&sdma 59>, <&sdma 60>; |
| 563 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 564 | }; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 565 | |
Florian Vaussard | 21bd85a | 2014-03-05 18:24:18 -0600 | [diff] [blame] | 566 | mmu_dsp: mmu@4a066000 { |
| 567 | compatible = "ti,omap4-iommu"; |
| 568 | reg = <0x4a066000 0x100>; |
| 569 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 570 | ti,hwmods = "mmu_dsp"; |
Suman Anna | 22e3bcc | 2015-07-10 12:28:55 -0500 | [diff] [blame] | 571 | #iommu-cells = <0>; |
Florian Vaussard | 21bd85a | 2014-03-05 18:24:18 -0600 | [diff] [blame] | 572 | }; |
| 573 | |
| 574 | mmu_ipu: mmu@55082000 { |
| 575 | compatible = "ti,omap4-iommu"; |
| 576 | reg = <0x55082000 0x100>; |
| 577 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 578 | ti,hwmods = "mmu_ipu"; |
Suman Anna | 22e3bcc | 2015-07-10 12:28:55 -0500 | [diff] [blame] | 579 | #iommu-cells = <0>; |
Florian Vaussard | 21bd85a | 2014-03-05 18:24:18 -0600 | [diff] [blame] | 580 | ti,iommu-bus-err-back; |
| 581 | }; |
| 582 | |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 583 | wdt2: wdt@4a314000 { |
| 584 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 585 | reg = <0x4a314000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 586 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 587 | ti,hwmods = "wd_timer2"; |
| 588 | }; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 589 | |
| 590 | mcpdm: mcpdm@40132000 { |
| 591 | compatible = "ti,omap4-mcpdm"; |
| 592 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 593 | <0x49032000 0x7f>; /* L3 Interconnect */ |
Peter Ujfalusi | 63467cf | 2012-08-29 16:31:06 +0300 | [diff] [blame] | 594 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 595 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 596 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 597 | dmas = <&sdma 65>, |
| 598 | <&sdma 66>; |
| 599 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 600 | status = "disabled"; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 601 | }; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 602 | |
| 603 | dmic: dmic@4012e000 { |
| 604 | compatible = "ti,omap4-dmic"; |
| 605 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 606 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
Peter Ujfalusi | 63467cf | 2012-08-29 16:31:06 +0300 | [diff] [blame] | 607 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 608 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 609 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 610 | dmas = <&sdma 67>; |
| 611 | dma-names = "up_link"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 612 | status = "disabled"; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 613 | }; |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 614 | |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 615 | mcbsp1: mcbsp@40122000 { |
| 616 | compatible = "ti,omap4-mcbsp"; |
| 617 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 618 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 619 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 620 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 621 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 622 | ti,buffer-size = <128>; |
| 623 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 624 | dmas = <&sdma 33>, |
| 625 | <&sdma 34>; |
| 626 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 627 | status = "disabled"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 628 | }; |
| 629 | |
| 630 | mcbsp2: mcbsp@40124000 { |
| 631 | compatible = "ti,omap4-mcbsp"; |
| 632 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 633 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 634 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 635 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 636 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 637 | ti,buffer-size = <128>; |
| 638 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 639 | dmas = <&sdma 17>, |
| 640 | <&sdma 18>; |
| 641 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 642 | status = "disabled"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | mcbsp3: mcbsp@40126000 { |
| 646 | compatible = "ti,omap4-mcbsp"; |
| 647 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 648 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 649 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 650 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 651 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 652 | ti,buffer-size = <128>; |
| 653 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 654 | dmas = <&sdma 19>, |
| 655 | <&sdma 20>; |
| 656 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 657 | status = "disabled"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 658 | }; |
| 659 | |
| 660 | mcbsp4: mcbsp@48096000 { |
| 661 | compatible = "ti,omap4-mcbsp"; |
| 662 | reg = <0x48096000 0xff>; /* L4 Interconnect */ |
| 663 | reg-names = "mpu"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 664 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 665 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 666 | ti,buffer-size = <128>; |
| 667 | ti,hwmods = "mcbsp4"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 668 | dmas = <&sdma 31>, |
| 669 | <&sdma 32>; |
| 670 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 7adb093 | 2014-01-24 10:19:01 +0200 | [diff] [blame] | 671 | status = "disabled"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 672 | }; |
| 673 | |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 674 | keypad: keypad@4a31c000 { |
| 675 | compatible = "ti,omap4-keypad"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 676 | reg = <0x4a31c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 677 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 678 | reg-names = "mpu"; |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 679 | ti,hwmods = "kbd"; |
| 680 | }; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 681 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 682 | dmm@4e000000 { |
| 683 | compatible = "ti,omap4-dmm"; |
| 684 | reg = <0x4e000000 0x800>; |
| 685 | interrupts = <0 113 0x4>; |
| 686 | ti,hwmods = "dmm"; |
| 687 | }; |
| 688 | |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 689 | emif1: emif@4c000000 { |
| 690 | compatible = "ti,emif-4d"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 691 | reg = <0x4c000000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 692 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 693 | ti,hwmods = "emif1"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 694 | ti,no-idle-on-init; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 695 | phy-type = <1>; |
| 696 | hw-caps-read-idle-ctrl; |
| 697 | hw-caps-ll-interface; |
| 698 | hw-caps-temp-alert; |
| 699 | }; |
| 700 | |
| 701 | emif2: emif@4d000000 { |
| 702 | compatible = "ti,emif-4d"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 703 | reg = <0x4d000000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 704 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 705 | ti,hwmods = "emif2"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 706 | ti,no-idle-on-init; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 707 | phy-type = <1>; |
| 708 | hw-caps-read-idle-ctrl; |
| 709 | hw-caps-ll-interface; |
| 710 | hw-caps-temp-alert; |
| 711 | }; |
Linus Torvalds | 8f446a7 | 2012-10-01 18:46:13 -0700 | [diff] [blame] | 712 | |
Kishon Vijay Abraham I | 3ce0a99 | 2012-09-19 16:02:51 +0530 | [diff] [blame] | 713 | ocp2scp@4a0ad000 { |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 714 | compatible = "ti,omap-ocp2scp"; |
Kishon Vijay Abraham I | 3ce0a99 | 2012-09-19 16:02:51 +0530 | [diff] [blame] | 715 | reg = <0x4a0ad000 0x1f>; |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 716 | #address-cells = <1>; |
| 717 | #size-cells = <1>; |
| 718 | ranges; |
| 719 | ti,hwmods = "ocp2scp_usb_phy"; |
Kishon Vijay Abraham I | cf0d869 | 2013-03-07 19:05:15 +0530 | [diff] [blame] | 720 | usb2_phy: usb2phy@4a0ad080 { |
| 721 | compatible = "ti,omap-usb2"; |
| 722 | reg = <0x4a0ad080 0x58>; |
Roger Quadros | 470019a | 2013-10-03 18:12:36 +0300 | [diff] [blame] | 723 | ctrl-module = <&omap_control_usb2phy>; |
Roger Quadros | c65d0ad | 2014-05-05 12:54:42 +0300 | [diff] [blame] | 724 | clocks = <&usb_phy_cm_clk32k>; |
| 725 | clock-names = "wkupclk"; |
Kishon Vijay Abraham I | 975d963 | 2013-09-27 11:53:29 +0530 | [diff] [blame] | 726 | #phy-cells = <0>; |
Kishon Vijay Abraham I | cf0d869 | 2013-03-07 19:05:15 +0530 | [diff] [blame] | 727 | }; |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 728 | }; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 729 | |
Suman Anna | 8ebc30d | 2014-07-11 16:44:35 -0500 | [diff] [blame] | 730 | mailbox: mailbox@4a0f4000 { |
| 731 | compatible = "ti,omap4-mailbox"; |
| 732 | reg = <0x4a0f4000 0x200>; |
| 733 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 734 | ti,hwmods = "mailbox"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 735 | #mbox-cells = <1>; |
Suman Anna | 8ebc30d | 2014-07-11 16:44:35 -0500 | [diff] [blame] | 736 | ti,mbox-num-users = <3>; |
| 737 | ti,mbox-num-fifos = <8>; |
Suman Anna | d27704d | 2014-09-10 14:27:23 -0500 | [diff] [blame] | 738 | mbox_ipu: mbox_ipu { |
| 739 | ti,mbox-tx = <0 0 0>; |
| 740 | ti,mbox-rx = <1 0 0>; |
| 741 | }; |
| 742 | mbox_dsp: mbox_dsp { |
| 743 | ti,mbox-tx = <3 0 0>; |
| 744 | ti,mbox-rx = <2 0 0>; |
| 745 | }; |
Suman Anna | 8ebc30d | 2014-07-11 16:44:35 -0500 | [diff] [blame] | 746 | }; |
| 747 | |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 748 | timer1: timer@4a318000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 749 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 750 | reg = <0x4a318000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 751 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 752 | ti,hwmods = "timer1"; |
| 753 | ti,timer-alwon; |
| 754 | }; |
| 755 | |
| 756 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 757 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 758 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 759 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 760 | ti,hwmods = "timer2"; |
| 761 | }; |
| 762 | |
| 763 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 764 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 765 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 766 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 767 | ti,hwmods = "timer3"; |
| 768 | }; |
| 769 | |
| 770 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 771 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 772 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 773 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 774 | ti,hwmods = "timer4"; |
| 775 | }; |
| 776 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 777 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 778 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 779 | reg = <0x40138000 0x80>, |
| 780 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 781 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 782 | ti,hwmods = "timer5"; |
| 783 | ti,timer-dsp; |
| 784 | }; |
| 785 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 786 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 787 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 788 | reg = <0x4013a000 0x80>, |
| 789 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 790 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 791 | ti,hwmods = "timer6"; |
| 792 | ti,timer-dsp; |
| 793 | }; |
| 794 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 795 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 796 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 797 | reg = <0x4013c000 0x80>, |
| 798 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 799 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 800 | ti,hwmods = "timer7"; |
| 801 | ti,timer-dsp; |
| 802 | }; |
| 803 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 804 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 805 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 806 | reg = <0x4013e000 0x80>, |
| 807 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 808 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 809 | ti,hwmods = "timer8"; |
| 810 | ti,timer-pwm; |
| 811 | ti,timer-dsp; |
| 812 | }; |
| 813 | |
| 814 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 815 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 816 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 817 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 818 | ti,hwmods = "timer9"; |
| 819 | ti,timer-pwm; |
| 820 | }; |
| 821 | |
| 822 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 823 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 824 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 825 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 826 | ti,hwmods = "timer10"; |
| 827 | ti,timer-pwm; |
| 828 | }; |
| 829 | |
| 830 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 831 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 832 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 833 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 834 | ti,hwmods = "timer11"; |
| 835 | ti,timer-pwm; |
| 836 | }; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 837 | |
| 838 | usbhstll: usbhstll@4a062000 { |
| 839 | compatible = "ti,usbhs-tll"; |
| 840 | reg = <0x4a062000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 841 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 842 | ti,hwmods = "usb_tll_hs"; |
| 843 | }; |
| 844 | |
| 845 | usbhshost: usbhshost@4a064000 { |
| 846 | compatible = "ti,usbhs-host"; |
| 847 | reg = <0x4a064000 0x800>; |
| 848 | ti,hwmods = "usb_host_hs"; |
| 849 | #address-cells = <1>; |
| 850 | #size-cells = <1>; |
| 851 | ranges; |
Roger Quadros | 051fc06 | 2014-02-27 16:18:26 +0200 | [diff] [blame] | 852 | clocks = <&init_60m_fclk>, |
| 853 | <&xclk60mhsp1_ck>, |
| 854 | <&xclk60mhsp2_ck>; |
| 855 | clock-names = "refclk_60m_int", |
| 856 | "refclk_60m_ext_p1", |
| 857 | "refclk_60m_ext_p2"; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 858 | |
| 859 | usbhsohci: ohci@4a064800 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 860 | compatible = "ti,ohci-omap3"; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 861 | reg = <0x4a064800 0x400>; |
| 862 | interrupt-parent = <&gic>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 863 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 864 | }; |
| 865 | |
| 866 | usbhsehci: ehci@4a064c00 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 867 | compatible = "ti,ehci-omap"; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 868 | reg = <0x4a064c00 0x400>; |
| 869 | interrupt-parent = <&gic>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 870 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 871 | }; |
| 872 | }; |
Kishon Vijay Abraham I | 840e5fd | 2013-03-07 19:05:14 +0530 | [diff] [blame] | 873 | |
Roger Quadros | 470019a | 2013-10-03 18:12:36 +0300 | [diff] [blame] | 874 | omap_control_usb2phy: control-phy@4a002300 { |
| 875 | compatible = "ti,control-phy-usb2"; |
| 876 | reg = <0x4a002300 0x4>; |
| 877 | reg-names = "power"; |
| 878 | }; |
| 879 | |
| 880 | omap_control_usbotg: control-phy@4a00233c { |
| 881 | compatible = "ti,control-phy-otghs"; |
| 882 | reg = <0x4a00233c 0x4>; |
| 883 | reg-names = "otghs_control"; |
Kishon Vijay Abraham I | 840e5fd | 2013-03-07 19:05:14 +0530 | [diff] [blame] | 884 | }; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 885 | |
| 886 | usb_otg_hs: usb_otg_hs@4a0ab000 { |
| 887 | compatible = "ti,omap4-musb"; |
| 888 | reg = <0x4a0ab000 0x7ff>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 889 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 890 | interrupt-names = "mc", "dma"; |
| 891 | ti,hwmods = "usb_otg_hs"; |
| 892 | usb-phy = <&usb2_phy>; |
Kishon Vijay Abraham I | 975d963 | 2013-09-27 11:53:29 +0530 | [diff] [blame] | 893 | phys = <&usb2_phy>; |
| 894 | phy-names = "usb2-phy"; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 895 | multipoint = <1>; |
| 896 | num-eps = <16>; |
| 897 | ram-bits = <12>; |
Roger Quadros | 470019a | 2013-10-03 18:12:36 +0300 | [diff] [blame] | 898 | ctrl-module = <&omap_control_usbotg>; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 899 | }; |
Joel Fernandes | dd6317d | 2013-07-11 18:20:05 -0500 | [diff] [blame] | 900 | |
| 901 | aes: aes@4b501000 { |
| 902 | compatible = "ti,omap4-aes"; |
| 903 | ti,hwmods = "aes"; |
| 904 | reg = <0x4b501000 0xa0>; |
| 905 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 906 | dmas = <&sdma 111>, <&sdma 110>; |
| 907 | dma-names = "tx", "rx"; |
| 908 | }; |
Joel Fernandes | 806e943 | 2013-09-24 15:23:33 -0500 | [diff] [blame] | 909 | |
| 910 | des: des@480a5000 { |
| 911 | compatible = "ti,omap4-des"; |
| 912 | ti,hwmods = "des"; |
| 913 | reg = <0x480a5000 0xa0>; |
| 914 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 915 | dmas = <&sdma 117>, <&sdma 116>; |
| 916 | dma-names = "tx", "rx"; |
| 917 | }; |
Andrii.Tseglytskyi | e12c773 | 2014-03-03 20:20:22 +0530 | [diff] [blame] | 918 | |
| 919 | abb_mpu: regulator-abb-mpu { |
| 920 | compatible = "ti,abb-v2"; |
| 921 | regulator-name = "abb_mpu"; |
| 922 | #address-cells = <0>; |
| 923 | #size-cells = <0>; |
| 924 | ti,tranxdone-status-mask = <0x80>; |
| 925 | clocks = <&sys_clkin_ck>; |
| 926 | ti,settling-time = <50>; |
| 927 | ti,clock-cycles = <16>; |
| 928 | |
| 929 | status = "disabled"; |
| 930 | }; |
| 931 | |
| 932 | abb_iva: regulator-abb-iva { |
| 933 | compatible = "ti,abb-v2"; |
| 934 | regulator-name = "abb_iva"; |
| 935 | #address-cells = <0>; |
| 936 | #size-cells = <0>; |
| 937 | ti,tranxdone-status-mask = <0x80000000>; |
| 938 | clocks = <&sys_clkin_ck>; |
| 939 | ti,settling-time = <50>; |
| 940 | ti,clock-cycles = <16>; |
| 941 | |
| 942 | status = "disabled"; |
| 943 | }; |
Tomi Valkeinen | cfe86fc | 2012-08-21 15:34:50 +0300 | [diff] [blame] | 944 | |
| 945 | dss: dss@58000000 { |
| 946 | compatible = "ti,omap4-dss"; |
| 947 | reg = <0x58000000 0x80>; |
| 948 | status = "disabled"; |
| 949 | ti,hwmods = "dss_core"; |
| 950 | clocks = <&dss_dss_clk>; |
| 951 | clock-names = "fck"; |
| 952 | #address-cells = <1>; |
| 953 | #size-cells = <1>; |
| 954 | ranges; |
| 955 | |
| 956 | dispc@58001000 { |
| 957 | compatible = "ti,omap4-dispc"; |
| 958 | reg = <0x58001000 0x1000>; |
| 959 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 960 | ti,hwmods = "dss_dispc"; |
| 961 | clocks = <&dss_dss_clk>; |
| 962 | clock-names = "fck"; |
| 963 | }; |
| 964 | |
| 965 | rfbi: encoder@58002000 { |
| 966 | compatible = "ti,omap4-rfbi"; |
| 967 | reg = <0x58002000 0x1000>; |
| 968 | status = "disabled"; |
| 969 | ti,hwmods = "dss_rfbi"; |
Tomi Valkeinen | 2cc84f4 | 2014-10-09 17:03:18 +0300 | [diff] [blame] | 970 | clocks = <&dss_dss_clk>, <&l3_div_ck>; |
Tomi Valkeinen | cfe86fc | 2012-08-21 15:34:50 +0300 | [diff] [blame] | 971 | clock-names = "fck", "ick"; |
| 972 | }; |
| 973 | |
| 974 | venc: encoder@58003000 { |
| 975 | compatible = "ti,omap4-venc"; |
| 976 | reg = <0x58003000 0x1000>; |
| 977 | status = "disabled"; |
| 978 | ti,hwmods = "dss_venc"; |
| 979 | clocks = <&dss_tv_clk>; |
| 980 | clock-names = "fck"; |
| 981 | }; |
| 982 | |
| 983 | dsi1: encoder@58004000 { |
| 984 | compatible = "ti,omap4-dsi"; |
| 985 | reg = <0x58004000 0x200>, |
| 986 | <0x58004200 0x40>, |
| 987 | <0x58004300 0x20>; |
| 988 | reg-names = "proto", "phy", "pll"; |
| 989 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 990 | status = "disabled"; |
| 991 | ti,hwmods = "dss_dsi1"; |
| 992 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 993 | clock-names = "fck", "sys_clk"; |
| 994 | }; |
| 995 | |
| 996 | dsi2: encoder@58005000 { |
| 997 | compatible = "ti,omap4-dsi"; |
| 998 | reg = <0x58005000 0x200>, |
| 999 | <0x58005200 0x40>, |
| 1000 | <0x58005300 0x20>; |
| 1001 | reg-names = "proto", "phy", "pll"; |
| 1002 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 1003 | status = "disabled"; |
| 1004 | ti,hwmods = "dss_dsi2"; |
| 1005 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 1006 | clock-names = "fck", "sys_clk"; |
| 1007 | }; |
| 1008 | |
| 1009 | hdmi: encoder@58006000 { |
| 1010 | compatible = "ti,omap4-hdmi"; |
| 1011 | reg = <0x58006000 0x200>, |
| 1012 | <0x58006200 0x100>, |
| 1013 | <0x58006300 0x100>, |
| 1014 | <0x58006400 0x1000>; |
| 1015 | reg-names = "wp", "pll", "phy", "core"; |
| 1016 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 1017 | status = "disabled"; |
| 1018 | ti,hwmods = "dss_hdmi"; |
| 1019 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; |
| 1020 | clock-names = "fck", "sys_clk"; |
Jyri Sarha | 53855b3 | 2014-05-12 12:12:24 +0300 | [diff] [blame] | 1021 | dmas = <&sdma 76>; |
| 1022 | dma-names = "audio_tx"; |
Tomi Valkeinen | cfe86fc | 2012-08-21 15:34:50 +0300 | [diff] [blame] | 1023 | }; |
| 1024 | }; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 1025 | }; |
| 1026 | }; |
Tero Kristo | 2488ff6 | 2013-07-18 12:42:02 +0300 | [diff] [blame] | 1027 | |
| 1028 | /include/ "omap44xx-clocks.dtsi" |