R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 10 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 12 | #include <dt-bindings/pinctrl/omap.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 14 | / { |
Tony Lindgren | 98cc454 | 2016-09-13 16:10:56 -0700 | [diff] [blame] | 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 17 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 18 | compatible = "ti,omap5"; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 19 | interrupt-parent = <&wakeupgen>; |
Javier Martinez Canillas | c3f7ca4 | 2016-12-19 11:44:36 -0300 | [diff] [blame] | 20 | chosen { }; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 21 | |
| 22 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 23 | i2c0 = &i2c1; |
| 24 | i2c1 = &i2c2; |
| 25 | i2c2 = &i2c3; |
| 26 | i2c3 = &i2c4; |
| 27 | i2c4 = &i2c5; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 28 | serial0 = &uart1; |
| 29 | serial1 = &uart2; |
| 30 | serial2 = &uart3; |
| 31 | serial3 = &uart4; |
| 32 | serial4 = &uart5; |
| 33 | serial5 = &uart6; |
| 34 | }; |
| 35 | |
| 36 | cpus { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | |
Nishanth Menon | b8981d7 | 2013-10-16 10:39:04 -0500 | [diff] [blame] | 40 | cpu0: cpu@0 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 41 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 42 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 43 | reg = <0x0>; |
J Keerthy | 6c24894 | 2013-10-16 10:39:06 -0500 | [diff] [blame] | 44 | |
| 45 | operating-points = < |
| 46 | /* kHz uV */ |
J Keerthy | 6c24894 | 2013-10-16 10:39:06 -0500 | [diff] [blame] | 47 | 1000000 1060000 |
| 48 | 1500000 1250000 |
| 49 | >; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 50 | |
| 51 | clocks = <&dpll_mpu_ck>; |
| 52 | clock-names = "cpu"; |
| 53 | |
| 54 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
| 55 | |
Eduardo Valentin | 2cd29f6 | 2013-08-16 11:30:47 -0400 | [diff] [blame] | 56 | /* cooling options */ |
| 57 | cooling-min-level = <0>; |
| 58 | cooling-max-level = <2>; |
| 59 | #cooling-cells = <2>; /* min followed by max */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 60 | }; |
| 61 | cpu@1 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 62 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 63 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 64 | reg = <0x1>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 65 | }; |
| 66 | }; |
| 67 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 68 | thermal-zones { |
| 69 | #include "omap4-cpu-thermal.dtsi" |
| 70 | #include "omap5-gpu-thermal.dtsi" |
| 71 | #include "omap5-core-thermal.dtsi" |
| 72 | }; |
| 73 | |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 74 | timer { |
| 75 | compatible = "arm,armv7-timer"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 76 | /* PPI secure/nonsecure IRQ */ |
| 77 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 78 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 79 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 80 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 81 | interrupt-parent = <&gic>; |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 82 | }; |
| 83 | |
Nathan Lynch | 69a126c | 2014-03-19 10:45:53 -0500 | [diff] [blame] | 84 | pmu { |
| 85 | compatible = "arm,cortex-a15-pmu"; |
| 86 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 87 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | }; |
| 89 | |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 90 | gic: interrupt-controller@48211000 { |
| 91 | compatible = "arm,cortex-a15-gic"; |
| 92 | interrupt-controller; |
| 93 | #interrupt-cells = <3>; |
Tony Lindgren | 98cc454 | 2016-09-13 16:10:56 -0700 | [diff] [blame] | 94 | reg = <0 0x48211000 0 0x1000>, |
| 95 | <0 0x48212000 0 0x1000>, |
| 96 | <0 0x48214000 0 0x2000>, |
| 97 | <0 0x48216000 0 0x2000>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 98 | interrupt-parent = <&gic>; |
| 99 | }; |
| 100 | |
| 101 | wakeupgen: interrupt-controller@48281000 { |
| 102 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| 103 | interrupt-controller; |
| 104 | #interrupt-cells = <3>; |
Tony Lindgren | 98cc454 | 2016-09-13 16:10:56 -0700 | [diff] [blame] | 105 | reg = <0 0x48281000 0 0x1000>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 106 | interrupt-parent = <&gic>; |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 107 | }; |
| 108 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 109 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 110 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 111 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 112 | */ |
| 113 | soc { |
| 114 | compatible = "ti,omap-infra"; |
| 115 | mpu { |
Rajendra Nayak | 1306c08 | 2014-09-10 11:04:04 -0500 | [diff] [blame] | 116 | compatible = "ti,omap4-mpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 117 | ti,hwmods = "mpu"; |
Rajendra Nayak | 1306c08 | 2014-09-10 11:04:04 -0500 | [diff] [blame] | 118 | sram = <&ocmcram>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 119 | }; |
| 120 | }; |
| 121 | |
| 122 | /* |
| 123 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 124 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 125 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 126 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 127 | * hierarchy. |
| 128 | */ |
| 129 | ocp { |
Suman Anna | e7309c2 | 2015-04-24 12:54:20 -0500 | [diff] [blame] | 130 | compatible = "ti,omap5-l3-noc", "simple-bus"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 131 | #address-cells = <1>; |
| 132 | #size-cells = <1>; |
Tony Lindgren | 98cc454 | 2016-09-13 16:10:56 -0700 | [diff] [blame] | 133 | ranges = <0 0 0 0xc0000000>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 134 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Tony Lindgren | 98cc454 | 2016-09-13 16:10:56 -0700 | [diff] [blame] | 135 | reg = <0 0x44000000 0 0x2000>, |
| 136 | <0 0x44800000 0 0x3000>, |
| 137 | <0 0x45000000 0 0x4000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 138 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 139 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 140 | |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 141 | l4_cfg: l4@4a000000 { |
| 142 | compatible = "ti,omap5-l4-cfg", "simple-bus"; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 143 | #address-cells = <1>; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 144 | #size-cells = <1>; |
| 145 | ranges = <0 0x4a000000 0x22a000>; |
| 146 | |
| 147 | scm_core: scm@2000 { |
| 148 | compatible = "ti,omap5-scm-core", "simple-bus"; |
| 149 | reg = <0x2000 0x1000>; |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <1>; |
| 152 | ranges = <0 0x2000 0x800>; |
| 153 | |
| 154 | scm_conf: scm_conf@0 { |
| 155 | compatible = "syscon"; |
| 156 | reg = <0x0 0x800>; |
| 157 | #address-cells = <1>; |
| 158 | #size-cells = <1>; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | scm_padconf_core: scm@2800 { |
| 163 | compatible = "ti,omap5-scm-padconf-core", |
| 164 | "simple-bus"; |
| 165 | #address-cells = <1>; |
| 166 | #size-cells = <1>; |
| 167 | ranges = <0 0x2800 0x800>; |
| 168 | |
| 169 | omap5_pmx_core: pinmux@40 { |
| 170 | compatible = "ti,omap5-padconf", |
| 171 | "pinctrl-single"; |
| 172 | reg = <0x40 0x01b6>; |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; |
| 175 | #interrupt-cells = <1>; |
| 176 | interrupt-controller; |
| 177 | pinctrl-single,register-width = <16>; |
| 178 | pinctrl-single,function-mask = <0x7fff>; |
| 179 | }; |
| 180 | |
| 181 | omap5_padconf_global: omap5_padconf_global@5a0 { |
Kishon Vijay Abraham I | 70caac3 | 2015-07-27 17:46:40 +0530 | [diff] [blame] | 182 | compatible = "syscon", |
| 183 | "simple-bus"; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 184 | reg = <0x5a0 0xec>; |
| 185 | #address-cells = <1>; |
| 186 | #size-cells = <1>; |
Kishon Vijay Abraham I | 9a5e3f2 | 2015-09-04 17:38:24 +0530 | [diff] [blame] | 187 | ranges = <0 0x5a0 0xec>; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 188 | |
Javier Martinez Canillas | 308cfda | 2016-04-01 16:20:18 -0400 | [diff] [blame] | 189 | pbias_regulator: pbias_regulator@60 { |
Kishon Vijay Abraham I | 737f146 | 2015-09-04 17:30:25 +0530 | [diff] [blame] | 190 | compatible = "ti,pbias-omap5", "ti,pbias-omap"; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 191 | reg = <0x60 0x4>; |
| 192 | syscon = <&omap5_padconf_global>; |
| 193 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 194 | regulator-name = "pbias_mmc_omap5"; |
| 195 | regulator-min-microvolt = <1800000>; |
| 196 | regulator-max-microvolt = <3000000>; |
| 197 | }; |
| 198 | }; |
| 199 | }; |
| 200 | }; |
| 201 | |
| 202 | cm_core_aon: cm_core_aon@4000 { |
| 203 | compatible = "ti,omap5-cm-core-aon"; |
| 204 | reg = <0x4000 0x2000>; |
| 205 | |
| 206 | cm_core_aon_clocks: clocks { |
| 207 | #address-cells = <1>; |
| 208 | #size-cells = <0>; |
| 209 | }; |
| 210 | |
| 211 | cm_core_aon_clockdomains: clockdomains { |
| 212 | }; |
| 213 | }; |
| 214 | |
| 215 | cm_core: cm_core@8000 { |
| 216 | compatible = "ti,omap5-cm-core"; |
| 217 | reg = <0x8000 0x3000>; |
| 218 | |
| 219 | cm_core_clocks: clocks { |
| 220 | #address-cells = <1>; |
| 221 | #size-cells = <0>; |
| 222 | }; |
| 223 | |
| 224 | cm_core_clockdomains: clockdomains { |
| 225 | }; |
| 226 | }; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 227 | }; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 228 | |
| 229 | l4_wkup: l4@4ae00000 { |
| 230 | compatible = "ti,omap5-l4-wkup", "simple-bus"; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 231 | #address-cells = <1>; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 232 | #size-cells = <1>; |
| 233 | ranges = <0 0x4ae00000 0x2b000>; |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 234 | |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 235 | counter32k: counter@4000 { |
| 236 | compatible = "ti,omap-counter32k"; |
| 237 | reg = <0x4000 0x40>; |
| 238 | ti,hwmods = "counter_32k"; |
| 239 | }; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 240 | |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 241 | prm: prm@6000 { |
| 242 | compatible = "ti,omap5-prm"; |
| 243 | reg = <0x6000 0x3000>; |
| 244 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 245 | |
| 246 | prm_clocks: clocks { |
| 247 | #address-cells = <1>; |
| 248 | #size-cells = <0>; |
| 249 | }; |
| 250 | |
| 251 | prm_clockdomains: clockdomains { |
| 252 | }; |
| 253 | }; |
| 254 | |
| 255 | scrm: scrm@a000 { |
| 256 | compatible = "ti,omap5-scrm"; |
| 257 | reg = <0xa000 0x2000>; |
| 258 | |
| 259 | scrm_clocks: clocks { |
| 260 | #address-cells = <1>; |
| 261 | #size-cells = <0>; |
| 262 | }; |
| 263 | |
| 264 | scrm_clockdomains: clockdomains { |
| 265 | }; |
| 266 | }; |
| 267 | |
| 268 | omap5_pmx_wkup: pinmux@c840 { |
| 269 | compatible = "ti,omap5-padconf", |
| 270 | "pinctrl-single"; |
H. Nikolaus Schaller | 7472931 | 2016-04-18 20:20:59 +0200 | [diff] [blame] | 271 | reg = <0xc840 0x003c>; |
Tero Kristo | ed8509e | 2015-02-12 11:35:29 +0200 | [diff] [blame] | 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
| 274 | #interrupt-cells = <1>; |
| 275 | interrupt-controller; |
| 276 | pinctrl-single,register-width = <16>; |
| 277 | pinctrl-single,function-mask = <0x7fff>; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 278 | }; |
| 279 | }; |
| 280 | |
Rajendra Nayak | 8b9a281 | 2014-09-10 11:04:03 -0500 | [diff] [blame] | 281 | ocmcram: ocmcram@40300000 { |
| 282 | compatible = "mmio-sram"; |
| 283 | reg = <0x40300000 0x20000>; /* 128k */ |
| 284 | }; |
| 285 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 286 | sdma: dma-controller@4a056000 { |
| 287 | compatible = "ti,omap4430-sdma"; |
| 288 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 289 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 290 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 291 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 292 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 293 | #dma-cells = <1>; |
Peter Ujfalusi | 951c1c0 | 2015-02-20 15:42:05 +0200 | [diff] [blame] | 294 | dma-channels = <32>; |
| 295 | dma-requests = <127>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 296 | }; |
| 297 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 298 | gpio1: gpio@4ae10000 { |
| 299 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 300 | reg = <0x4ae10000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 301 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 302 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 303 | ti,gpio-always-on; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 304 | gpio-controller; |
| 305 | #gpio-cells = <2>; |
| 306 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 307 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | gpio2: gpio@48055000 { |
| 311 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 312 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 313 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 314 | ti,hwmods = "gpio2"; |
| 315 | gpio-controller; |
| 316 | #gpio-cells = <2>; |
| 317 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 318 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 319 | }; |
| 320 | |
| 321 | gpio3: gpio@48057000 { |
| 322 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 323 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 324 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 325 | ti,hwmods = "gpio3"; |
| 326 | gpio-controller; |
| 327 | #gpio-cells = <2>; |
| 328 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 329 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | gpio4: gpio@48059000 { |
| 333 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 334 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 335 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 336 | ti,hwmods = "gpio4"; |
| 337 | gpio-controller; |
| 338 | #gpio-cells = <2>; |
| 339 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 340 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | gpio5: gpio@4805b000 { |
| 344 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 345 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 346 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 347 | ti,hwmods = "gpio5"; |
| 348 | gpio-controller; |
| 349 | #gpio-cells = <2>; |
| 350 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 351 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | gpio6: gpio@4805d000 { |
| 355 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 356 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 357 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 358 | ti,hwmods = "gpio6"; |
| 359 | gpio-controller; |
| 360 | #gpio-cells = <2>; |
| 361 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 362 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 363 | }; |
| 364 | |
| 365 | gpio7: gpio@48051000 { |
| 366 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 367 | reg = <0x48051000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 368 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 369 | ti,hwmods = "gpio7"; |
| 370 | gpio-controller; |
| 371 | #gpio-cells = <2>; |
| 372 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 373 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 374 | }; |
| 375 | |
| 376 | gpio8: gpio@48053000 { |
| 377 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 378 | reg = <0x48053000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 379 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 380 | ti,hwmods = "gpio8"; |
| 381 | gpio-controller; |
| 382 | #gpio-cells = <2>; |
| 383 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 384 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 385 | }; |
| 386 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 387 | gpmc: gpmc@50000000 { |
| 388 | compatible = "ti,omap4430-gpmc"; |
| 389 | reg = <0x50000000 0x1000>; |
| 390 | #address-cells = <2>; |
| 391 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 392 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Franklin S Cooper Jr | 201c7e3 | 2015-10-15 12:37:27 -0500 | [diff] [blame] | 393 | dmas = <&sdma 4>; |
| 394 | dma-names = "rxtx"; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 395 | gpmc,num-cs = <8>; |
| 396 | gpmc,num-waitpins = <4>; |
| 397 | ti,hwmods = "gpmc"; |
Florian Vaussard | 7b8b6af | 2014-02-26 11:38:09 +0100 | [diff] [blame] | 398 | clocks = <&l3_iclk_div>; |
| 399 | clock-names = "fck"; |
Roger Quadros | e99d413 | 2016-04-07 13:25:30 +0300 | [diff] [blame] | 400 | interrupt-controller; |
| 401 | #interrupt-cells = <2>; |
| 402 | gpio-controller; |
| 403 | #gpio-cells = <2>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 404 | }; |
| 405 | |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 406 | i2c1: i2c@48070000 { |
| 407 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 408 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 409 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 410 | #address-cells = <1>; |
| 411 | #size-cells = <0>; |
| 412 | ti,hwmods = "i2c1"; |
| 413 | }; |
| 414 | |
| 415 | i2c2: i2c@48072000 { |
| 416 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 417 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 418 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 419 | #address-cells = <1>; |
| 420 | #size-cells = <0>; |
| 421 | ti,hwmods = "i2c2"; |
| 422 | }; |
| 423 | |
| 424 | i2c3: i2c@48060000 { |
| 425 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 426 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 427 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 428 | #address-cells = <1>; |
| 429 | #size-cells = <0>; |
| 430 | ti,hwmods = "i2c3"; |
| 431 | }; |
| 432 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 433 | i2c4: i2c@4807a000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 434 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 435 | reg = <0x4807a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 436 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 437 | #address-cells = <1>; |
| 438 | #size-cells = <0>; |
| 439 | ti,hwmods = "i2c4"; |
| 440 | }; |
| 441 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 442 | i2c5: i2c@4807c000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 443 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 444 | reg = <0x4807c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 445 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 446 | #address-cells = <1>; |
| 447 | #size-cells = <0>; |
| 448 | ti,hwmods = "i2c5"; |
| 449 | }; |
| 450 | |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 451 | hwspinlock: spinlock@4a0f6000 { |
| 452 | compatible = "ti,omap4-hwspinlock"; |
| 453 | reg = <0x4a0f6000 0x1000>; |
| 454 | ti,hwmods = "spinlock"; |
Suman Anna | 3405421 | 2014-01-13 18:26:45 -0600 | [diff] [blame] | 455 | #hwlock-cells = <1>; |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 456 | }; |
| 457 | |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 458 | mcspi1: spi@48098000 { |
| 459 | compatible = "ti,omap4-mcspi"; |
| 460 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 461 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 462 | #address-cells = <1>; |
| 463 | #size-cells = <0>; |
| 464 | ti,hwmods = "mcspi1"; |
| 465 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 466 | dmas = <&sdma 35>, |
| 467 | <&sdma 36>, |
| 468 | <&sdma 37>, |
| 469 | <&sdma 38>, |
| 470 | <&sdma 39>, |
| 471 | <&sdma 40>, |
| 472 | <&sdma 41>, |
| 473 | <&sdma 42>; |
| 474 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 475 | "tx2", "rx2", "tx3", "rx3"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 476 | }; |
| 477 | |
| 478 | mcspi2: spi@4809a000 { |
| 479 | compatible = "ti,omap4-mcspi"; |
| 480 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 481 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 482 | #address-cells = <1>; |
| 483 | #size-cells = <0>; |
| 484 | ti,hwmods = "mcspi2"; |
| 485 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 486 | dmas = <&sdma 43>, |
| 487 | <&sdma 44>, |
| 488 | <&sdma 45>, |
| 489 | <&sdma 46>; |
| 490 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 491 | }; |
| 492 | |
| 493 | mcspi3: spi@480b8000 { |
| 494 | compatible = "ti,omap4-mcspi"; |
| 495 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 496 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 497 | #address-cells = <1>; |
| 498 | #size-cells = <0>; |
| 499 | ti,hwmods = "mcspi3"; |
| 500 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 501 | dmas = <&sdma 15>, <&sdma 16>; |
| 502 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | mcspi4: spi@480ba000 { |
| 506 | compatible = "ti,omap4-mcspi"; |
| 507 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 508 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
| 511 | ti,hwmods = "mcspi4"; |
| 512 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 513 | dmas = <&sdma 70>, <&sdma 71>; |
| 514 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 515 | }; |
| 516 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 517 | uart1: serial@4806a000 { |
| 518 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 519 | reg = <0x4806a000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 520 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 521 | ti,hwmods = "uart1"; |
| 522 | clock-frequency = <48000000>; |
| 523 | }; |
| 524 | |
| 525 | uart2: serial@4806c000 { |
| 526 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 527 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 528 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 529 | ti,hwmods = "uart2"; |
| 530 | clock-frequency = <48000000>; |
| 531 | }; |
| 532 | |
| 533 | uart3: serial@48020000 { |
| 534 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 535 | reg = <0x48020000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 536 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 537 | ti,hwmods = "uart3"; |
| 538 | clock-frequency = <48000000>; |
| 539 | }; |
| 540 | |
| 541 | uart4: serial@4806e000 { |
| 542 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 543 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 544 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 545 | ti,hwmods = "uart4"; |
| 546 | clock-frequency = <48000000>; |
| 547 | }; |
| 548 | |
| 549 | uart5: serial@48066000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 550 | compatible = "ti,omap4-uart"; |
| 551 | reg = <0x48066000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 552 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 553 | ti,hwmods = "uart5"; |
| 554 | clock-frequency = <48000000>; |
| 555 | }; |
| 556 | |
| 557 | uart6: serial@48068000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 558 | compatible = "ti,omap4-uart"; |
| 559 | reg = <0x48068000 0x100>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 560 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 561 | ti,hwmods = "uart6"; |
| 562 | clock-frequency = <48000000>; |
| 563 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 564 | |
| 565 | mmc1: mmc@4809c000 { |
| 566 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 567 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 568 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 569 | ti,hwmods = "mmc1"; |
| 570 | ti,dual-volt; |
| 571 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 572 | dmas = <&sdma 61>, <&sdma 62>; |
| 573 | dma-names = "tx", "rx"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 574 | pbias-supply = <&pbias_mmc_reg>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 575 | }; |
| 576 | |
| 577 | mmc2: mmc@480b4000 { |
| 578 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 579 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 580 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 581 | ti,hwmods = "mmc2"; |
| 582 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 583 | dmas = <&sdma 47>, <&sdma 48>; |
| 584 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 585 | }; |
| 586 | |
| 587 | mmc3: mmc@480ad000 { |
| 588 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 589 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 590 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 591 | ti,hwmods = "mmc3"; |
| 592 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 593 | dmas = <&sdma 77>, <&sdma 78>; |
| 594 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 595 | }; |
| 596 | |
| 597 | mmc4: mmc@480d1000 { |
| 598 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 599 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 600 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 601 | ti,hwmods = "mmc4"; |
| 602 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 603 | dmas = <&sdma 57>, <&sdma 58>; |
| 604 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 605 | }; |
| 606 | |
| 607 | mmc5: mmc@480d5000 { |
| 608 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 609 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 610 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 611 | ti,hwmods = "mmc5"; |
| 612 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 613 | dmas = <&sdma 59>, <&sdma 60>; |
| 614 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 615 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 616 | |
Suman Anna | 2dcfa56 | 2014-03-05 18:24:19 -0600 | [diff] [blame] | 617 | mmu_dsp: mmu@4a066000 { |
| 618 | compatible = "ti,omap4-iommu"; |
| 619 | reg = <0x4a066000 0x100>; |
| 620 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 621 | ti,hwmods = "mmu_dsp"; |
Suman Anna | c1b5d0f | 2015-07-10 12:28:56 -0500 | [diff] [blame] | 622 | #iommu-cells = <0>; |
Suman Anna | 2dcfa56 | 2014-03-05 18:24:19 -0600 | [diff] [blame] | 623 | }; |
| 624 | |
| 625 | mmu_ipu: mmu@55082000 { |
| 626 | compatible = "ti,omap4-iommu"; |
| 627 | reg = <0x55082000 0x100>; |
| 628 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 629 | ti,hwmods = "mmu_ipu"; |
Suman Anna | c1b5d0f | 2015-07-10 12:28:56 -0500 | [diff] [blame] | 630 | #iommu-cells = <0>; |
Suman Anna | 2dcfa56 | 2014-03-05 18:24:19 -0600 | [diff] [blame] | 631 | ti,iommu-bus-err-back; |
| 632 | }; |
| 633 | |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 634 | keypad: keypad@4ae1c000 { |
| 635 | compatible = "ti,omap4-keypad"; |
Santosh Shilimkar | 8cc8b89 | 2013-01-23 19:53:30 +0530 | [diff] [blame] | 636 | reg = <0x4ae1c000 0x400>; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 637 | ti,hwmods = "kbd"; |
| 638 | }; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 639 | |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 640 | mcpdm: mcpdm@40132000 { |
| 641 | compatible = "ti,omap4-mcpdm"; |
| 642 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 643 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 644 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 645 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 646 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 647 | dmas = <&sdma 65>, |
| 648 | <&sdma 66>; |
| 649 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 650 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 651 | }; |
| 652 | |
| 653 | dmic: dmic@4012e000 { |
| 654 | compatible = "ti,omap4-dmic"; |
| 655 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 656 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 657 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 658 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 659 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 660 | dmas = <&sdma 67>; |
| 661 | dma-names = "up_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 662 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 663 | }; |
| 664 | |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 665 | mcbsp1: mcbsp@40122000 { |
| 666 | compatible = "ti,omap4-mcbsp"; |
| 667 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 668 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 669 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 670 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 671 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 672 | ti,buffer-size = <128>; |
| 673 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 674 | dmas = <&sdma 33>, |
| 675 | <&sdma 34>; |
| 676 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 677 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 678 | }; |
| 679 | |
| 680 | mcbsp2: mcbsp@40124000 { |
| 681 | compatible = "ti,omap4-mcbsp"; |
| 682 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 683 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 684 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 685 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 686 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 687 | ti,buffer-size = <128>; |
| 688 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 689 | dmas = <&sdma 17>, |
| 690 | <&sdma 18>; |
| 691 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 692 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 693 | }; |
| 694 | |
| 695 | mcbsp3: mcbsp@40126000 { |
| 696 | compatible = "ti,omap4-mcbsp"; |
| 697 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 698 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 699 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 700 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 701 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 702 | ti,buffer-size = <128>; |
| 703 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 704 | dmas = <&sdma 19>, |
| 705 | <&sdma 20>; |
| 706 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 707 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 708 | }; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 709 | |
Suman Anna | 84d89c3 | 2014-04-22 17:23:35 -0500 | [diff] [blame] | 710 | mailbox: mailbox@4a0f4000 { |
| 711 | compatible = "ti,omap4-mailbox"; |
| 712 | reg = <0x4a0f4000 0x200>; |
| 713 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 714 | ti,hwmods = "mailbox"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 715 | #mbox-cells = <1>; |
Suman Anna | 41ffada | 2014-07-11 16:44:34 -0500 | [diff] [blame] | 716 | ti,mbox-num-users = <3>; |
| 717 | ti,mbox-num-fifos = <8>; |
Suman Anna | d27704d | 2014-09-10 14:27:23 -0500 | [diff] [blame] | 718 | mbox_ipu: mbox_ipu { |
| 719 | ti,mbox-tx = <0 0 0>; |
| 720 | ti,mbox-rx = <1 0 0>; |
| 721 | }; |
| 722 | mbox_dsp: mbox_dsp { |
| 723 | ti,mbox-tx = <3 0 0>; |
| 724 | ti,mbox-rx = <2 0 0>; |
| 725 | }; |
Suman Anna | 84d89c3 | 2014-04-22 17:23:35 -0500 | [diff] [blame] | 726 | }; |
| 727 | |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 728 | timer1: timer@4ae18000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 729 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 730 | reg = <0x4ae18000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 731 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 732 | ti,hwmods = "timer1"; |
| 733 | ti,timer-alwon; |
| 734 | }; |
| 735 | |
| 736 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 737 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 738 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 739 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 740 | ti,hwmods = "timer2"; |
| 741 | }; |
| 742 | |
| 743 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 744 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 745 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 746 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 747 | ti,hwmods = "timer3"; |
| 748 | }; |
| 749 | |
| 750 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 751 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 752 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 753 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 754 | ti,hwmods = "timer4"; |
| 755 | }; |
| 756 | |
| 757 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 758 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 759 | reg = <0x40138000 0x80>, |
| 760 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 761 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 762 | ti,hwmods = "timer5"; |
| 763 | ti,timer-dsp; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 764 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 768 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 769 | reg = <0x4013a000 0x80>, |
| 770 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 771 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 772 | ti,hwmods = "timer6"; |
| 773 | ti,timer-dsp; |
| 774 | ti,timer-pwm; |
| 775 | }; |
| 776 | |
| 777 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 778 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 779 | reg = <0x4013c000 0x80>, |
| 780 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 781 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 782 | ti,hwmods = "timer7"; |
| 783 | ti,timer-dsp; |
| 784 | }; |
| 785 | |
| 786 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 787 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 788 | reg = <0x4013e000 0x80>, |
| 789 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 790 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 791 | ti,hwmods = "timer8"; |
| 792 | ti,timer-dsp; |
| 793 | ti,timer-pwm; |
| 794 | }; |
| 795 | |
| 796 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 797 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 798 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 799 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 800 | ti,hwmods = "timer9"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 801 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 802 | }; |
| 803 | |
| 804 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 805 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 806 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 807 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 808 | ti,hwmods = "timer10"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 809 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 810 | }; |
| 811 | |
| 812 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 813 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 814 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 815 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 816 | ti,hwmods = "timer11"; |
| 817 | ti,timer-pwm; |
| 818 | }; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 819 | |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 820 | wdt2: wdt@4ae14000 { |
| 821 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
| 822 | reg = <0x4ae14000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 823 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 824 | ti,hwmods = "wd_timer2"; |
| 825 | }; |
| 826 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 827 | dmm@4e000000 { |
| 828 | compatible = "ti,omap5-dmm"; |
| 829 | reg = <0x4e000000 0x800>; |
| 830 | interrupts = <0 113 0x4>; |
| 831 | ti,hwmods = "dmm"; |
| 832 | }; |
| 833 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 834 | emif1: emif@4c000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 835 | compatible = "ti,emif-4d5"; |
| 836 | ti,hwmods = "emif1"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 837 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 838 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 839 | reg = <0x4c000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 840 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 841 | hw-caps-read-idle-ctrl; |
| 842 | hw-caps-ll-interface; |
| 843 | hw-caps-temp-alert; |
| 844 | }; |
| 845 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 846 | emif2: emif@4d000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 847 | compatible = "ti,emif-4d5"; |
| 848 | ti,hwmods = "emif2"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 849 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 850 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 851 | reg = <0x4d000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 852 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 853 | hw-caps-read-idle-ctrl; |
| 854 | hw-caps-ll-interface; |
| 855 | hw-caps-temp-alert; |
| 856 | }; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 857 | |
Felipe Balbi | e3a412c | 2013-08-21 20:01:32 +0530 | [diff] [blame] | 858 | usb3: omap_dwc3@4a020000 { |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 859 | compatible = "ti,dwc3"; |
| 860 | ti,hwmods = "usb_otg_ss"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 861 | reg = <0x4a020000 0x10000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 862 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 863 | #address-cells = <1>; |
| 864 | #size-cells = <1>; |
| 865 | utmi-mode = <2>; |
| 866 | ranges; |
Tony Lindgren | 952a5db | 2016-09-09 14:04:28 -0700 | [diff] [blame] | 867 | dwc3: dwc3@4a030000 { |
Felipe Balbi | 22a5aa1 | 2013-07-02 21:20:24 +0300 | [diff] [blame] | 868 | compatible = "snps,dwc3"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 869 | reg = <0x4a030000 0x10000>; |
Roger Quadros | 8d33c09 | 2015-07-08 13:42:31 +0300 | [diff] [blame] | 870 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
| 871 | <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
| 872 | <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 873 | interrupt-names = "peripheral", |
| 874 | "host", |
| 875 | "otg"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 876 | phys = <&usb2_phy>, <&usb3_phy>; |
| 877 | phy-names = "usb2-phy", "usb3-phy"; |
George Cherian | c47ee6e | 2013-10-10 16:19:54 +0530 | [diff] [blame] | 878 | dr_mode = "peripheral"; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 879 | }; |
| 880 | }; |
| 881 | |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 882 | ocp2scp@4a080000 { |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 883 | compatible = "ti,omap-ocp2scp"; |
| 884 | #address-cells = <1>; |
| 885 | #size-cells = <1>; |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 886 | reg = <0x4a080000 0x20>; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 887 | ranges; |
| 888 | ti,hwmods = "ocp2scp1"; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 889 | usb2_phy: usb2phy@4a084000 { |
| 890 | compatible = "ti,omap-usb2"; |
| 891 | reg = <0x4a084000 0x7c>; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 892 | syscon-phy-power = <&scm_conf 0x300>; |
Roger Quadros | c65d0ad | 2014-05-05 12:54:42 +0300 | [diff] [blame] | 893 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
| 894 | clock-names = "wkupclk", "refclk"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 895 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 896 | }; |
| 897 | |
| 898 | usb3_phy: usb3phy@4a084400 { |
| 899 | compatible = "ti,omap-usb3"; |
| 900 | reg = <0x4a084400 0x80>, |
| 901 | <0x4a084800 0x64>, |
| 902 | <0x4a084c00 0x40>; |
| 903 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 904 | syscon-phy-power = <&scm_conf 0x370>; |
Roger Quadros | ada7657 | 2014-04-01 13:37:27 +0300 | [diff] [blame] | 905 | clocks = <&usb_phy_cm_clk32k>, |
| 906 | <&sys_clkin>, |
| 907 | <&usb_otg_ss_refclk960m>; |
| 908 | clock-names = "wkupclk", |
| 909 | "sysclk", |
| 910 | "refclk"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 911 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 912 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 913 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 914 | |
| 915 | usbhstll: usbhstll@4a062000 { |
| 916 | compatible = "ti,usbhs-tll"; |
| 917 | reg = <0x4a062000 0x1000>; |
| 918 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 919 | ti,hwmods = "usb_tll_hs"; |
| 920 | }; |
| 921 | |
| 922 | usbhshost: usbhshost@4a064000 { |
| 923 | compatible = "ti,usbhs-host"; |
| 924 | reg = <0x4a064000 0x800>; |
| 925 | ti,hwmods = "usb_host_hs"; |
| 926 | #address-cells = <1>; |
| 927 | #size-cells = <1>; |
| 928 | ranges; |
Roger Quadros | 051fc06 | 2014-02-27 16:18:26 +0200 | [diff] [blame] | 929 | clocks = <&l3init_60m_fclk>, |
| 930 | <&xclk60mhsp1_ck>, |
| 931 | <&xclk60mhsp2_ck>; |
| 932 | clock-names = "refclk_60m_int", |
| 933 | "refclk_60m_ext_p1", |
| 934 | "refclk_60m_ext_p2"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 935 | |
| 936 | usbhsohci: ohci@4a064800 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 937 | compatible = "ti,ohci-omap3"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 938 | reg = <0x4a064800 0x400>; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 939 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 940 | }; |
| 941 | |
| 942 | usbhsehci: ehci@4a064c00 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 943 | compatible = "ti,ehci-omap"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 944 | reg = <0x4a064c00 0x400>; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 945 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 946 | }; |
| 947 | }; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 948 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 949 | bandgap: bandgap@4a0021e0 { |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 950 | reg = <0x4a0021e0 0xc |
| 951 | 0x4a00232c 0xc |
| 952 | 0x4a002380 0x2c |
| 953 | 0x4a0023C0 0x3c>; |
| 954 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 955 | compatible = "ti,omap5430-bandgap"; |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 956 | |
| 957 | #thermal-sensor-cells = <1>; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 958 | }; |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 959 | |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 960 | /* OCP2SCP3 */ |
| 961 | ocp2scp@4a090000 { |
| 962 | compatible = "ti,omap-ocp2scp"; |
| 963 | #address-cells = <1>; |
| 964 | #size-cells = <1>; |
| 965 | reg = <0x4a090000 0x20>; |
| 966 | ranges; |
| 967 | ti,hwmods = "ocp2scp3"; |
| 968 | sata_phy: phy@4a096000 { |
| 969 | compatible = "ti,phy-pipe3-sata"; |
| 970 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 971 | <0x4A096400 0x64>, /* phy_tx */ |
| 972 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 973 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 974 | syscon-phy-power = <&scm_conf 0x374>; |
Roger Quadros | a018272 | 2015-01-13 14:23:22 +0200 | [diff] [blame] | 975 | clocks = <&sys_clkin>, <&sata_ref_clk>; |
| 976 | clock-names = "sysclk", "refclk"; |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 977 | #phy-cells = <0>; |
| 978 | }; |
| 979 | }; |
| 980 | |
| 981 | sata: sata@4a141100 { |
| 982 | compatible = "snps,dwc-ahci"; |
| 983 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| 984 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 985 | phys = <&sata_phy>; |
| 986 | phy-names = "sata-phy"; |
| 987 | clocks = <&sata_ref_clk>; |
| 988 | ti,hwmods = "sata"; |
Jean-Jacques Hiblot | 5b66186 | 2017-01-09 13:22:15 +0100 | [diff] [blame] | 989 | ports-implemented = <0x1>; |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 990 | }; |
| 991 | |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 992 | dss: dss@58000000 { |
| 993 | compatible = "ti,omap5-dss"; |
| 994 | reg = <0x58000000 0x80>; |
| 995 | status = "disabled"; |
| 996 | ti,hwmods = "dss_core"; |
| 997 | clocks = <&dss_dss_clk>; |
| 998 | clock-names = "fck"; |
| 999 | #address-cells = <1>; |
| 1000 | #size-cells = <1>; |
| 1001 | ranges; |
| 1002 | |
| 1003 | dispc@58001000 { |
| 1004 | compatible = "ti,omap5-dispc"; |
| 1005 | reg = <0x58001000 0x1000>; |
| 1006 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 1007 | ti,hwmods = "dss_dispc"; |
| 1008 | clocks = <&dss_dss_clk>; |
| 1009 | clock-names = "fck"; |
| 1010 | }; |
| 1011 | |
Tomi Valkeinen | 84ace67 | 2014-09-04 09:28:32 +0300 | [diff] [blame] | 1012 | rfbi: encoder@58002000 { |
| 1013 | compatible = "ti,omap5-rfbi"; |
| 1014 | reg = <0x58002000 0x100>; |
| 1015 | status = "disabled"; |
| 1016 | ti,hwmods = "dss_rfbi"; |
| 1017 | clocks = <&dss_dss_clk>, <&l3_iclk_div>; |
| 1018 | clock-names = "fck", "ick"; |
| 1019 | }; |
| 1020 | |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 1021 | dsi1: encoder@58004000 { |
| 1022 | compatible = "ti,omap5-dsi"; |
| 1023 | reg = <0x58004000 0x200>, |
| 1024 | <0x58004200 0x40>, |
| 1025 | <0x58004300 0x40>; |
| 1026 | reg-names = "proto", "phy", "pll"; |
| 1027 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 1028 | status = "disabled"; |
| 1029 | ti,hwmods = "dss_dsi1"; |
| 1030 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 1031 | clock-names = "fck", "sys_clk"; |
| 1032 | }; |
| 1033 | |
| 1034 | dsi2: encoder@58005000 { |
| 1035 | compatible = "ti,omap5-dsi"; |
| 1036 | reg = <0x58009000 0x200>, |
| 1037 | <0x58009200 0x40>, |
| 1038 | <0x58009300 0x40>; |
| 1039 | reg-names = "proto", "phy", "pll"; |
| 1040 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 1041 | status = "disabled"; |
| 1042 | ti,hwmods = "dss_dsi2"; |
| 1043 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; |
| 1044 | clock-names = "fck", "sys_clk"; |
| 1045 | }; |
| 1046 | |
| 1047 | hdmi: encoder@58060000 { |
| 1048 | compatible = "ti,omap5-hdmi"; |
| 1049 | reg = <0x58040000 0x200>, |
| 1050 | <0x58040200 0x80>, |
| 1051 | <0x58040300 0x80>, |
| 1052 | <0x58060000 0x19000>; |
| 1053 | reg-names = "wp", "pll", "phy", "core"; |
| 1054 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 1055 | status = "disabled"; |
| 1056 | ti,hwmods = "dss_hdmi"; |
| 1057 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; |
| 1058 | clock-names = "fck", "sys_clk"; |
Jyri Sarha | 7d0fde3 | 2014-05-12 12:12:26 +0300 | [diff] [blame] | 1059 | dmas = <&sdma 76>; |
| 1060 | dma-names = "audio_tx"; |
Tomi Valkeinen | e7585c4 | 2014-03-07 12:45:54 +0200 | [diff] [blame] | 1061 | }; |
| 1062 | }; |
Andrii.Tseglytskyi | 07b9b3d | 2014-06-05 20:11:12 -0500 | [diff] [blame] | 1063 | |
| 1064 | abb_mpu: regulator-abb-mpu { |
| 1065 | compatible = "ti,abb-v2"; |
| 1066 | regulator-name = "abb_mpu"; |
| 1067 | #address-cells = <0>; |
| 1068 | #size-cells = <0>; |
| 1069 | clocks = <&sys_clkin>; |
| 1070 | ti,settling-time = <50>; |
| 1071 | ti,clock-cycles = <16>; |
| 1072 | |
| 1073 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, |
| 1074 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; |
| 1075 | reg-names = "base-address", "int-address", |
| 1076 | "efuse-address", "ldo-address"; |
| 1077 | ti,tranxdone-status-mask = <0x80>; |
| 1078 | /* LDOVBBMPU_MUX_CTRL */ |
| 1079 | ti,ldovbb-override-mask = <0x400>; |
| 1080 | /* LDOVBBMPU_VSET_OUT */ |
| 1081 | ti,ldovbb-vset-mask = <0x1F>; |
| 1082 | |
| 1083 | /* |
| 1084 | * NOTE: only FBB mode used but actual vset will |
| 1085 | * determine final biasing |
| 1086 | */ |
| 1087 | ti,abb_info = < |
| 1088 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1089 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 1090 | 1250000 0 0x4 0 0x02000000 0x01F00000 |
| 1091 | >; |
| 1092 | }; |
| 1093 | |
| 1094 | abb_mm: regulator-abb-mm { |
| 1095 | compatible = "ti,abb-v2"; |
| 1096 | regulator-name = "abb_mm"; |
| 1097 | #address-cells = <0>; |
| 1098 | #size-cells = <0>; |
| 1099 | clocks = <&sys_clkin>; |
| 1100 | ti,settling-time = <50>; |
| 1101 | ti,clock-cycles = <16>; |
| 1102 | |
| 1103 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, |
| 1104 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; |
| 1105 | reg-names = "base-address", "int-address", |
| 1106 | "efuse-address", "ldo-address"; |
| 1107 | ti,tranxdone-status-mask = <0x80000000>; |
| 1108 | /* LDOVBBMM_MUX_CTRL */ |
| 1109 | ti,ldovbb-override-mask = <0x400>; |
| 1110 | /* LDOVBBMM_VSET_OUT */ |
| 1111 | ti,ldovbb-vset-mask = <0x1F>; |
| 1112 | |
| 1113 | /* |
| 1114 | * NOTE: only FBB mode used but actual vset will |
| 1115 | * determine final biasing |
| 1116 | */ |
| 1117 | ti,abb_info = < |
| 1118 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1119 | 1025000 0 0x0 0 0x02000000 0x01F00000 |
| 1120 | 1120000 0 0x4 0 0x02000000 0x01F00000 |
| 1121 | >; |
| 1122 | }; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1123 | }; |
| 1124 | }; |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 1125 | |
Tero Kristo | 38f5c8b | 2015-02-27 15:59:03 +0200 | [diff] [blame] | 1126 | &cpu_thermal { |
| 1127 | polling-delay = <500>; /* milliseconds */ |
| 1128 | }; |
| 1129 | |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 1130 | /include/ "omap54xx-clocks.dtsi" |