Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 30 | #include <linux/device.h> |
Jesse Barnes | e5747e3 | 2014-06-12 08:35:47 -0700 | [diff] [blame] | 31 | #include <linux/acpi.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drmP.h> |
| 33 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include "i915_drv.h" |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 35 | #include "i915_trace.h" |
Kenneth Graunke | f49f058 | 2010-09-11 01:19:14 -0700 | [diff] [blame] | 36 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include <linux/console.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 39 | #include <linux/module.h> |
Imre Deak | d610297 | 2014-05-07 19:57:49 +0300 | [diff] [blame] | 40 | #include <linux/pm_runtime.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 41 | #include <drm/drm_crtc_helper.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 42 | |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 43 | static struct drm_driver driver; |
| 44 | |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
| 46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ |
| 47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ |
| 48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ |
| 49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
| 51 | |
Rafael Barbalho | 84fd4f4 | 2014-04-28 14:00:42 +0300 | [diff] [blame] | 52 | #define GEN_CHV_PIPEOFFSETS \ |
| 53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ |
| 54 | CHV_PIPE_C_OFFSET }, \ |
| 55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ |
| 56 | CHV_TRANSCODER_C_OFFSET, }, \ |
Rafael Barbalho | 84fd4f4 | 2014-04-28 14:00:42 +0300 | [diff] [blame] | 57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
| 58 | CHV_PALETTE_C_OFFSET } |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 59 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 60 | #define CURSOR_OFFSETS \ |
| 61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } |
| 62 | |
| 63 | #define IVB_CURSOR_OFFSETS \ |
| 64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } |
| 65 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 66 | static const struct intel_device_info intel_i830_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 69 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 70 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 71 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 72 | }; |
| 73 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 74 | static const struct intel_device_info intel_845g_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 75 | .gen = 2, .num_pipes = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 77 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 78 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 79 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 80 | }; |
| 81 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 82 | static const struct intel_device_info intel_i85x_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
Adam Jackson | 5ce8ba7 | 2010-04-15 14:03:30 -0400 | [diff] [blame] | 84 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ville Syrjälä | fd70d52 | 2013-11-28 17:30:02 +0200 | [diff] [blame] | 86 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 87 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 88 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 89 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 90 | }; |
| 91 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 92 | static const struct intel_device_info intel_i865g_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 93 | .gen = 2, .num_pipes = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 95 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 96 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 97 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 98 | }; |
| 99 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 100 | static const struct intel_device_info intel_i915g_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 103 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 104 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 105 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 106 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 107 | static const struct intel_device_info intel_i915gm_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 109 | .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 111 | .supports_tv = 1, |
Ville Syrjälä | fd70d52 | 2013-11-28 17:30:02 +0200 | [diff] [blame] | 112 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 113 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 114 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 115 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 116 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 117 | static const struct intel_device_info intel_i945g_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 120 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 121 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 122 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 123 | }; |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 124 | static const struct intel_device_info intel_i945gm_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 128 | .supports_tv = 1, |
Ville Syrjälä | fd70d52 | 2013-11-28 17:30:02 +0200 | [diff] [blame] | 129 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 130 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 131 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 132 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 133 | }; |
| 134 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 135 | static const struct intel_device_info intel_i965g_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 137 | .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 138 | .has_overlay = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 139 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 140 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 141 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 142 | }; |
| 143 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 144 | static const struct intel_device_info intel_i965gm_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 147 | .has_overlay = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 148 | .supports_tv = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 149 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 150 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 151 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 152 | }; |
| 153 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 154 | static const struct intel_device_info intel_g33_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 157 | .has_overlay = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 158 | .ring_mask = RENDER_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 159 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 160 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 161 | }; |
| 162 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 163 | static const struct intel_device_info intel_g45_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 166 | .ring_mask = RENDER_RING | BSD_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 167 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 168 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 169 | }; |
| 170 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 171 | static const struct intel_device_info intel_gm45_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 175 | .supports_tv = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 176 | .ring_mask = RENDER_RING | BSD_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 177 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 178 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 179 | }; |
| 180 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 181 | static const struct intel_device_info intel_pineview_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 184 | .has_overlay = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 185 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 186 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 187 | }; |
| 188 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 189 | static const struct intel_device_info intel_ironlake_d_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 190 | .gen = 5, .num_pipes = 2, |
Eugeni Dodonov | 5a117db | 2012-01-05 09:34:29 -0200 | [diff] [blame] | 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 192 | .ring_mask = RENDER_RING | BSD_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 193 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 194 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 195 | }; |
| 196 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 197 | static const struct intel_device_info intel_ironlake_m_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
Chris Wilson | e3c4e5d | 2010-12-05 16:49:51 +0000 | [diff] [blame] | 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 200 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 201 | .ring_mask = RENDER_RING | BSD_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 202 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 203 | CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 204 | }; |
| 205 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 207 | .gen = 6, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
Ville Syrjälä | cbaef0f | 2013-11-06 23:02:24 +0200 | [diff] [blame] | 209 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 211 | .has_llc = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 212 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 213 | CURSOR_OFFSETS, |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 214 | }; |
| 215 | |
Tobias Klauser | 9a7e849 | 2010-05-20 10:33:46 +0200 | [diff] [blame] | 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
Chris Wilson | c96c3a8c | 2010-08-11 09:59:24 +0100 | [diff] [blame] | 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 219 | .has_fbc = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 221 | .has_llc = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 222 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 223 | CURSOR_OFFSETS, |
Eric Anholt | a13e409 | 2010-01-07 15:08:18 -0800 | [diff] [blame] | 224 | }; |
| 225 | |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 226 | #define GEN7_FEATURES \ |
| 227 | .gen = 7, .num_pipes = 3, \ |
| 228 | .need_gfx_hws = 1, .has_hotplug = 1, \ |
Ville Syrjälä | cbaef0f | 2013-11-06 23:02:24 +0200 | [diff] [blame] | 229 | .has_fbc = 1, \ |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 231 | .has_llc = 1 |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 232 | |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 234 | GEN7_FEATURES, |
| 235 | .is_ivybridge = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 236 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 237 | IVB_CURSOR_OFFSETS, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 238 | }; |
| 239 | |
| 240 | static const struct intel_device_info intel_ivybridge_m_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 241 | GEN7_FEATURES, |
| 242 | .is_ivybridge = 1, |
| 243 | .is_mobile = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 244 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 245 | IVB_CURSOR_OFFSETS, |
Jesse Barnes | c76b615 | 2011-04-28 14:32:07 -0700 | [diff] [blame] | 246 | }; |
| 247 | |
Ben Widawsky | 999bcde | 2013-04-05 13:12:45 -0700 | [diff] [blame] | 248 | static const struct intel_device_info intel_ivybridge_q_info = { |
| 249 | GEN7_FEATURES, |
| 250 | .is_ivybridge = 1, |
| 251 | .num_pipes = 0, /* legal, last one wins */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 252 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 253 | IVB_CURSOR_OFFSETS, |
Ben Widawsky | 999bcde | 2013-04-05 13:12:45 -0700 | [diff] [blame] | 254 | }; |
| 255 | |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 256 | static const struct intel_device_info intel_valleyview_m_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 257 | GEN7_FEATURES, |
| 258 | .is_mobile = 1, |
| 259 | .num_pipes = 2, |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 260 | .is_valleyview = 1, |
Ville Syrjälä | fba5d53 | 2013-01-24 15:29:56 +0200 | [diff] [blame] | 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
Ville Syrjälä | cbaef0f | 2013-11-06 23:02:24 +0200 | [diff] [blame] | 262 | .has_fbc = 0, /* legal, last one wins */ |
Ben Widawsky | 30ccd96 | 2013-04-15 21:48:03 -0700 | [diff] [blame] | 263 | .has_llc = 0, /* legal, last one wins */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 264 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 265 | CURSOR_OFFSETS, |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | static const struct intel_device_info intel_valleyview_d_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 269 | GEN7_FEATURES, |
| 270 | .num_pipes = 2, |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 271 | .is_valleyview = 1, |
Ville Syrjälä | fba5d53 | 2013-01-24 15:29:56 +0200 | [diff] [blame] | 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
Ville Syrjälä | cbaef0f | 2013-11-06 23:02:24 +0200 | [diff] [blame] | 273 | .has_fbc = 0, /* legal, last one wins */ |
Ben Widawsky | 30ccd96 | 2013-04-15 21:48:03 -0700 | [diff] [blame] | 274 | .has_llc = 0, /* legal, last one wins */ |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 275 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 276 | CURSOR_OFFSETS, |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 277 | }; |
| 278 | |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 279 | static const struct intel_device_info intel_haswell_d_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 280 | GEN7_FEATURES, |
| 281 | .is_haswell = 1, |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 282 | .has_ddi = 1, |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 283 | .has_fpga_dbg = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 285 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 286 | IVB_CURSOR_OFFSETS, |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | static const struct intel_device_info intel_haswell_m_info = { |
Ben Widawsky | 219f4fd | 2013-03-15 11:17:54 -0700 | [diff] [blame] | 290 | GEN7_FEATURES, |
| 291 | .is_haswell = 1, |
| 292 | .is_mobile = 1, |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 293 | .has_ddi = 1, |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 294 | .has_fpga_dbg = 1, |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 296 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 297 | IVB_CURSOR_OFFSETS, |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 298 | }; |
| 299 | |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 300 | static const struct intel_device_info intel_broadwell_d_info = { |
Damien Lespiau | 4b30553 | 2013-11-02 21:07:32 -0700 | [diff] [blame] | 301 | .gen = 8, .num_pipes = 3, |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 302 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 304 | .has_llc = 1, |
| 305 | .has_ddi = 1, |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 306 | .has_fpga_dbg = 1, |
Ben Widawsky | 8f94d24 | 2014-02-20 16:01:20 -0800 | [diff] [blame] | 307 | .has_fbc = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 308 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 309 | IVB_CURSOR_OFFSETS, |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | static const struct intel_device_info intel_broadwell_m_info = { |
Damien Lespiau | 4b30553 | 2013-11-02 21:07:32 -0700 | [diff] [blame] | 313 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 314 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 315 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 316 | .has_llc = 1, |
| 317 | .has_ddi = 1, |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 318 | .has_fpga_dbg = 1, |
Ben Widawsky | 8f94d24 | 2014-02-20 16:01:20 -0800 | [diff] [blame] | 319 | .has_fbc = 1, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 320 | GEN_DEFAULT_PIPEOFFSETS, |
Rodrigo Vivi | 15d24aa | 2014-06-04 17:09:30 -0700 | [diff] [blame] | 321 | IVB_CURSOR_OFFSETS, |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 322 | }; |
| 323 | |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 324 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
| 325 | .gen = 8, .num_pipes = 3, |
| 326 | .need_gfx_hws = 1, .has_hotplug = 1, |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 328 | .has_llc = 1, |
| 329 | .has_ddi = 1, |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 330 | .has_fpga_dbg = 1, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 331 | .has_fbc = 1, |
| 332 | GEN_DEFAULT_PIPEOFFSETS, |
Rodrigo Vivi | 15d24aa | 2014-06-04 17:09:30 -0700 | [diff] [blame] | 333 | IVB_CURSOR_OFFSETS, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 334 | }; |
| 335 | |
| 336 | static const struct intel_device_info intel_broadwell_gt3m_info = { |
| 337 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
| 338 | .need_gfx_hws = 1, .has_hotplug = 1, |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 340 | .has_llc = 1, |
| 341 | .has_ddi = 1, |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 342 | .has_fpga_dbg = 1, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 343 | .has_fbc = 1, |
| 344 | GEN_DEFAULT_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 345 | IVB_CURSOR_OFFSETS, |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 346 | }; |
| 347 | |
Ville Syrjälä | 7d87a7f | 2014-04-09 18:19:04 +0300 | [diff] [blame] | 348 | static const struct intel_device_info intel_cherryview_info = { |
| 349 | .is_preliminary = 1, |
Ville Syrjälä | 07fddb1 | 2014-04-09 13:28:54 +0300 | [diff] [blame] | 350 | .gen = 8, .num_pipes = 3, |
Ville Syrjälä | 7d87a7f | 2014-04-09 18:19:04 +0300 | [diff] [blame] | 351 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 352 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 353 | .is_valleyview = 1, |
| 354 | .display_mmio_offset = VLV_DISPLAY_BASE, |
Rafael Barbalho | 84fd4f4 | 2014-04-28 14:00:42 +0300 | [diff] [blame] | 355 | GEN_CHV_PIPEOFFSETS, |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 356 | CURSOR_OFFSETS, |
Ville Syrjälä | 7d87a7f | 2014-04-09 18:19:04 +0300 | [diff] [blame] | 357 | }; |
| 358 | |
Damien Lespiau | 72bbf0a | 2013-02-13 15:27:37 +0000 | [diff] [blame] | 359 | static const struct intel_device_info intel_skylake_info = { |
| 360 | .is_preliminary = 1, |
Satheeshakrishna M | 7201c0b | 2014-04-02 11:24:50 +0530 | [diff] [blame] | 361 | .is_skylake = 1, |
Damien Lespiau | 72bbf0a | 2013-02-13 15:27:37 +0000 | [diff] [blame] | 362 | .gen = 9, .num_pipes = 3, |
| 363 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 364 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 365 | .has_llc = 1, |
| 366 | .has_ddi = 1, |
Daisy Sun | 043efb1 | 2014-04-23 17:13:09 -0700 | [diff] [blame] | 367 | .has_fbc = 1, |
Damien Lespiau | 72bbf0a | 2013-02-13 15:27:37 +0000 | [diff] [blame] | 368 | GEN_DEFAULT_PIPEOFFSETS, |
| 369 | IVB_CURSOR_OFFSETS, |
| 370 | }; |
| 371 | |
Jesse Barnes | a0a1807 | 2013-07-26 13:32:51 -0700 | [diff] [blame] | 372 | /* |
| 373 | * Make sure any device matches here are from most specific to most |
| 374 | * general. For example, since the Quanta match is based on the subsystem |
| 375 | * and subvendor IDs, we need it to come before the more general IVB |
| 376 | * PCI ID matches, otherwise we'll use the wrong info struct above. |
| 377 | */ |
| 378 | #define INTEL_PCI_IDS \ |
| 379 | INTEL_I830_IDS(&intel_i830_info), \ |
| 380 | INTEL_I845G_IDS(&intel_845g_info), \ |
| 381 | INTEL_I85X_IDS(&intel_i85x_info), \ |
| 382 | INTEL_I865G_IDS(&intel_i865g_info), \ |
| 383 | INTEL_I915G_IDS(&intel_i915g_info), \ |
| 384 | INTEL_I915GM_IDS(&intel_i915gm_info), \ |
| 385 | INTEL_I945G_IDS(&intel_i945g_info), \ |
| 386 | INTEL_I945GM_IDS(&intel_i945gm_info), \ |
| 387 | INTEL_I965G_IDS(&intel_i965g_info), \ |
| 388 | INTEL_G33_IDS(&intel_g33_info), \ |
| 389 | INTEL_I965GM_IDS(&intel_i965gm_info), \ |
| 390 | INTEL_GM45_IDS(&intel_gm45_info), \ |
| 391 | INTEL_G45_IDS(&intel_g45_info), \ |
| 392 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ |
| 393 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ |
| 394 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ |
| 395 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ |
| 396 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ |
| 397 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ |
| 398 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ |
| 399 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ |
| 400 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ |
| 401 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ |
| 402 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ |
Ben Widawsky | 4d4dead | 2013-11-03 16:47:33 -0800 | [diff] [blame] | 403 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
Zhao Yakui | fd3c269 | 2014-04-17 10:37:35 +0800 | [diff] [blame] | 404 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
| 405 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ |
| 406 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ |
Ville Syrjälä | 7d87a7f | 2014-04-09 18:19:04 +0300 | [diff] [blame] | 407 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ |
Damien Lespiau | 72bbf0a | 2013-02-13 15:27:37 +0000 | [diff] [blame] | 408 | INTEL_CHV_IDS(&intel_cherryview_info), \ |
| 409 | INTEL_SKL_IDS(&intel_skylake_info) |
Jesse Barnes | a0a1807 | 2013-07-26 13:32:51 -0700 | [diff] [blame] | 410 | |
Chris Wilson | 6103da0 | 2010-07-05 18:01:47 +0100 | [diff] [blame] | 411 | static const struct pci_device_id pciidlist[] = { /* aka */ |
Jesse Barnes | a0a1807 | 2013-07-26 13:32:51 -0700 | [diff] [blame] | 412 | INTEL_PCI_IDS, |
Kristian Høgsberg | 49ae35f | 2009-12-16 15:16:15 -0500 | [diff] [blame] | 413 | {0, 0, 0} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | }; |
| 415 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 416 | #if defined(CONFIG_DRM_I915_KMS) |
| 417 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 418 | #endif |
| 419 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 420 | void intel_detect_pch(struct drm_device *dev) |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 421 | { |
| 422 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | bcdb72a | 2014-02-14 20:23:54 +0200 | [diff] [blame] | 423 | struct pci_dev *pch = NULL; |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 424 | |
Ben Widawsky | ce1bb32 | 2013-04-05 13:12:44 -0700 | [diff] [blame] | 425 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
| 426 | * (which really amounts to a PCH but no South Display). |
| 427 | */ |
| 428 | if (INTEL_INFO(dev)->num_pipes == 0) { |
| 429 | dev_priv->pch_type = PCH_NOP; |
Ben Widawsky | ce1bb32 | 2013-04-05 13:12:44 -0700 | [diff] [blame] | 430 | return; |
| 431 | } |
| 432 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 433 | /* |
| 434 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 435 | * make graphics device passthrough work easy for VMM, that only |
| 436 | * need to expose ISA bridge to let driver know the real hardware |
| 437 | * underneath. This is a requirement from virtualization team. |
Rui Guo | 6a9c4b3 | 2013-06-19 21:10:23 +0800 | [diff] [blame] | 438 | * |
| 439 | * In some virtualized environments (e.g. XEN), there is irrelevant |
| 440 | * ISA bridge in the system. To work reliably, we should scan trhough |
| 441 | * all the ISA bridge devices and check for the first match, instead |
| 442 | * of only checking the first one. |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 443 | */ |
Imre Deak | bcdb72a | 2014-02-14 20:23:54 +0200 | [diff] [blame] | 444 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 445 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
Imre Deak | bcdb72a | 2014-02-14 20:23:54 +0200 | [diff] [blame] | 446 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 447 | dev_priv->pch_id = id; |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 448 | |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 449 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 450 | dev_priv->pch_type = PCH_IBX; |
| 451 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 452 | WARN_ON(!IS_GEN5(dev)); |
Jesse Barnes | 90711d5 | 2011-04-28 14:48:02 -0700 | [diff] [blame] | 453 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 454 | dev_priv->pch_type = PCH_CPT; |
| 455 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 456 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
Jesse Barnes | c792513 | 2011-04-07 12:33:56 -0700 | [diff] [blame] | 457 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 458 | /* PantherPoint is CPT compatible */ |
| 459 | dev_priv->pch_type = PCH_CPT; |
Jani Nikula | 492ab66 | 2013-10-01 12:12:33 +0300 | [diff] [blame] | 460 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
Daniel Vetter | 7fcb83c | 2012-10-31 22:52:27 +0100 | [diff] [blame] | 461 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 462 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 463 | dev_priv->pch_type = PCH_LPT; |
| 464 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
Rodrigo Vivi | a35cc9d0 | 2015-01-21 10:33:53 -0800 | [diff] [blame] | 465 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
| 466 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); |
Ben Widawsky | e76e063 | 2013-11-07 21:40:41 -0800 | [diff] [blame] | 467 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 468 | dev_priv->pch_type = PCH_LPT; |
| 469 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
Rodrigo Vivi | a35cc9d0 | 2015-01-21 10:33:53 -0800 | [diff] [blame] | 470 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
| 471 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); |
Satheeshakrishna M | e7e7ea2 | 2014-04-09 11:08:57 +0530 | [diff] [blame] | 472 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
| 473 | dev_priv->pch_type = PCH_SPT; |
| 474 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); |
| 475 | WARN_ON(!IS_SKYLAKE(dev)); |
Satheeshakrishna M | e7e7ea2 | 2014-04-09 11:08:57 +0530 | [diff] [blame] | 476 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
| 477 | dev_priv->pch_type = PCH_SPT; |
| 478 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); |
| 479 | WARN_ON(!IS_SKYLAKE(dev)); |
Imre Deak | bcdb72a | 2014-02-14 20:23:54 +0200 | [diff] [blame] | 480 | } else |
| 481 | continue; |
| 482 | |
Rui Guo | 6a9c4b3 | 2013-06-19 21:10:23 +0800 | [diff] [blame] | 483 | break; |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 484 | } |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 485 | } |
Rui Guo | 6a9c4b3 | 2013-06-19 21:10:23 +0800 | [diff] [blame] | 486 | if (!pch) |
Imre Deak | bcdb72a | 2014-02-14 20:23:54 +0200 | [diff] [blame] | 487 | DRM_DEBUG_KMS("No PCH found.\n"); |
| 488 | |
| 489 | pci_dev_put(pch); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 490 | } |
| 491 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 492 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
| 493 | { |
| 494 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | a08acaf | 2013-12-17 09:56:53 +0100 | [diff] [blame] | 495 | return false; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 496 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 497 | if (i915.semaphores >= 0) |
| 498 | return i915.semaphores; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 499 | |
Oscar Mateo | 71386ef | 2014-07-24 17:04:44 +0100 | [diff] [blame] | 500 | /* TODO: make semaphores and Execlists play nicely together */ |
| 501 | if (i915.enable_execlists) |
| 502 | return false; |
| 503 | |
Rodrigo Vivi | be71eab | 2014-08-04 11:15:19 -0700 | [diff] [blame] | 504 | /* Until we get further testing... */ |
| 505 | if (IS_GEN8(dev)) |
| 506 | return false; |
| 507 | |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 508 | #ifdef CONFIG_INTEL_IOMMU |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 509 | /* Enable semaphores on SNB when IO remapping is off */ |
Daniel Vetter | 59de329 | 2012-04-02 20:48:43 +0200 | [diff] [blame] | 510 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 511 | return false; |
| 512 | #endif |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 513 | |
Daniel Vetter | a08acaf | 2013-12-17 09:56:53 +0100 | [diff] [blame] | 514 | return true; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 515 | } |
| 516 | |
Imre Deak | 1d0d343 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 517 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) |
| 518 | { |
| 519 | spin_lock_irq(&dev_priv->irq_lock); |
| 520 | |
| 521 | dev_priv->long_hpd_port_mask = 0; |
| 522 | dev_priv->short_hpd_port_mask = 0; |
| 523 | dev_priv->hpd_event_bits = 0; |
| 524 | |
| 525 | spin_unlock_irq(&dev_priv->irq_lock); |
| 526 | |
| 527 | cancel_work_sync(&dev_priv->dig_port_work); |
| 528 | cancel_work_sync(&dev_priv->hotplug_work); |
| 529 | cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); |
| 530 | } |
| 531 | |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 532 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
| 533 | { |
| 534 | struct drm_device *dev = dev_priv->dev; |
| 535 | struct drm_encoder *encoder; |
| 536 | |
| 537 | drm_modeset_lock_all(dev); |
| 538 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 539 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 540 | |
| 541 | if (intel_encoder->suspend) |
| 542 | intel_encoder->suspend(intel_encoder); |
| 543 | } |
| 544 | drm_modeset_unlock_all(dev); |
| 545 | } |
| 546 | |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 547 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
Paulo Zanoni | 1a5df18 | 2014-10-27 17:54:32 -0200 | [diff] [blame] | 548 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
| 549 | bool rpm_resume); |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 550 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 551 | static int i915_drm_suspend(struct drm_device *dev) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 552 | { |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 553 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 24576d2 | 2013-03-26 09:25:45 -0700 | [diff] [blame] | 554 | struct drm_crtc *crtc; |
Jesse Barnes | e5747e3 | 2014-06-12 08:35:47 -0700 | [diff] [blame] | 555 | pci_power_t opregion_target_state; |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 556 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 557 | /* ignore lid events during suspend */ |
| 558 | mutex_lock(&dev_priv->modeset_restore_lock); |
| 559 | dev_priv->modeset_restore = MODESET_SUSPENDED; |
| 560 | mutex_unlock(&dev_priv->modeset_restore_lock); |
| 561 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 562 | /* We do a lot of poking in a lot of registers, make sure they work |
| 563 | * properly. */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 564 | intel_display_set_init_power(dev_priv, true); |
Paulo Zanoni | cb10799 | 2013-01-25 16:59:15 -0200 | [diff] [blame] | 565 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 566 | drm_kms_helper_poll_disable(dev); |
| 567 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 568 | pci_save_state(dev->pdev); |
| 569 | |
| 570 | /* If KMS is active, we do the leavevt stuff here */ |
| 571 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 572 | int error; |
| 573 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 574 | error = i915_gem_suspend(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 575 | if (error) { |
| 576 | dev_err(&dev->pdev->dev, |
| 577 | "GEM idle failed, resume might fail\n"); |
| 578 | return error; |
| 579 | } |
Daniel Vetter | a261b24 | 2012-07-26 19:21:47 +0200 | [diff] [blame] | 580 | |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 581 | intel_suspend_gt_powersave(dev); |
| 582 | |
Jesse Barnes | 24576d2 | 2013-03-26 09:25:45 -0700 | [diff] [blame] | 583 | /* |
| 584 | * Disable CRTCs directly since we want to preserve sw state |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 585 | * for _thaw. Also, power gate the CRTC power wells. |
Jesse Barnes | 24576d2 | 2013-03-26 09:25:45 -0700 | [diff] [blame] | 586 | */ |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 587 | drm_modeset_lock_all(dev); |
Borun Fu | b04c5bd | 2014-07-12 10:02:27 +0530 | [diff] [blame] | 588 | for_each_crtc(dev, crtc) |
| 589 | intel_crtc_control(crtc, false); |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 590 | drm_modeset_unlock_all(dev); |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 591 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 592 | intel_dp_mst_suspend(dev); |
Dave Airlie | 09b6426 | 2014-07-23 14:25:24 +1000 | [diff] [blame] | 593 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 594 | intel_runtime_pm_disable_interrupts(dev_priv); |
Imre Deak | 1d0d343 | 2014-08-18 14:42:44 +0300 | [diff] [blame] | 595 | intel_hpd_cancel_work(dev_priv); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 596 | |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 597 | intel_suspend_encoders(dev_priv); |
| 598 | |
Daniel Vetter | 970104f | 2014-09-30 10:56:37 +0200 | [diff] [blame] | 599 | intel_suspend_hw(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 600 | } |
| 601 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 602 | i915_gem_suspend_gtt_mappings(dev); |
| 603 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 604 | i915_save_state(dev); |
| 605 | |
Imre Deak | 95fa2ee | 2014-06-23 15:46:02 +0300 | [diff] [blame] | 606 | opregion_target_state = PCI_D3cold; |
| 607 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) |
| 608 | if (acpi_target_system_state() < ACPI_STATE_S3) |
Jesse Barnes | e5747e3 | 2014-06-12 08:35:47 -0700 | [diff] [blame] | 609 | opregion_target_state = PCI_D1; |
Imre Deak | 95fa2ee | 2014-06-23 15:46:02 +0300 | [diff] [blame] | 610 | #endif |
Jesse Barnes | e5747e3 | 2014-06-12 08:35:47 -0700 | [diff] [blame] | 611 | intel_opregion_notify_adapter(dev, opregion_target_state); |
| 612 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 613 | intel_uncore_forcewake_reset(dev, false); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 614 | intel_opregion_fini(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 615 | |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 616 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
Dave Airlie | 3fa016a | 2012-03-28 10:48:49 +0100 | [diff] [blame] | 617 | |
Mika Kuoppala | 62d5d69 | 2014-02-25 17:11:28 +0200 | [diff] [blame] | 618 | dev_priv->suspend_count++; |
| 619 | |
Kristen Carlson Accardi | 85e9067 | 2014-06-12 08:35:44 -0700 | [diff] [blame] | 620 | intel_display_set_init_power(dev_priv, false); |
| 621 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 622 | return 0; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 623 | } |
| 624 | |
Imre Deak | ab3be73 | 2015-03-02 13:04:41 +0200 | [diff] [blame] | 625 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
Imre Deak | c3c09c9 | 2014-10-23 19:23:15 +0300 | [diff] [blame] | 626 | { |
| 627 | struct drm_i915_private *dev_priv = drm_dev->dev_private; |
| 628 | int ret; |
| 629 | |
| 630 | ret = intel_suspend_complete(dev_priv); |
| 631 | |
| 632 | if (ret) { |
| 633 | DRM_ERROR("Suspend complete failed: %d\n", ret); |
| 634 | |
| 635 | return ret; |
| 636 | } |
| 637 | |
| 638 | pci_disable_device(drm_dev->pdev); |
Imre Deak | ab3be73 | 2015-03-02 13:04:41 +0200 | [diff] [blame] | 639 | /* |
| 640 | * During hibernation on some GEN4 platforms the BIOS may try to access |
| 641 | * the device even though it's already in D3 and hang the machine. So |
| 642 | * leave the device in D0 on those platforms and hope the BIOS will |
| 643 | * power down the device properly. Platforms where this was seen: |
| 644 | * Lenovo Thinkpad X301, X61s |
| 645 | */ |
| 646 | if (!(hibernation && |
| 647 | drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && |
| 648 | INTEL_INFO(dev_priv)->gen == 4)) |
| 649 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
Imre Deak | c3c09c9 | 2014-10-23 19:23:15 +0300 | [diff] [blame] | 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
Imre Deak | fc49b3d | 2014-10-23 19:23:27 +0300 | [diff] [blame] | 654 | int i915_suspend_legacy(struct drm_device *dev, pm_message_t state) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 655 | { |
| 656 | int error; |
| 657 | |
| 658 | if (!dev || !dev->dev_private) { |
| 659 | DRM_ERROR("dev: %p\n", dev); |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 660 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 661 | return -ENODEV; |
| 662 | } |
| 663 | |
Imre Deak | 0b14cbd | 2014-09-10 18:16:55 +0300 | [diff] [blame] | 664 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
| 665 | state.event != PM_EVENT_FREEZE)) |
| 666 | return -EINVAL; |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 667 | |
| 668 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 669 | return 0; |
Chris Wilson | 6eecba3 | 2010-09-08 09:45:11 +0100 | [diff] [blame] | 670 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 671 | error = i915_drm_suspend(dev); |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 672 | if (error) |
| 673 | return error; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 674 | |
Imre Deak | ab3be73 | 2015-03-02 13:04:41 +0200 | [diff] [blame] | 675 | return i915_drm_suspend_late(dev, false); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 676 | } |
| 677 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 678 | static int i915_drm_resume(struct drm_device *dev) |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 679 | { |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 680 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 681 | |
Imre Deak | f4a12ea | 2014-10-23 19:23:20 +0300 | [diff] [blame] | 682 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Paulo Zanoni | 9d49c0e | 2013-09-12 18:06:43 -0300 | [diff] [blame] | 683 | mutex_lock(&dev->struct_mutex); |
| 684 | i915_gem_restore_gtt_mappings(dev); |
| 685 | mutex_unlock(&dev->struct_mutex); |
| 686 | } |
| 687 | |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 688 | i915_restore_state(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 689 | intel_opregion_setup(dev); |
Rafael J. Wysocki | 61caf87 | 2010-02-18 23:06:27 +0100 | [diff] [blame] | 690 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 691 | /* KMS EnterVT equivalent */ |
| 692 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 693 | intel_init_pch_refclk(dev); |
Daniel Vetter | 754970ee | 2014-01-16 22:28:44 +0100 | [diff] [blame] | 694 | drm_mode_config_reset(dev); |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 695 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 696 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 074c6ad | 2014-04-09 09:19:43 +0100 | [diff] [blame] | 697 | if (i915_gem_init_hw(dev)) { |
| 698 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); |
| 699 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 700 | } |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 701 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 226485e | 2009-02-23 15:41:09 -0800 | [diff] [blame] | 702 | |
Daniel Vetter | 2363d8c | 2014-09-08 18:28:20 +0200 | [diff] [blame] | 703 | /* We need working interrupts for modeset enabling ... */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 704 | intel_runtime_pm_enable_interrupts(dev_priv); |
Daniel Vetter | 1523909 | 2013-03-05 09:50:58 +0100 | [diff] [blame] | 705 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 706 | intel_modeset_init_hw(dev); |
Jesse Barnes | 24576d2 | 2013-03-26 09:25:45 -0700 | [diff] [blame] | 707 | |
Jani Nikula | 5ea13be | 2014-11-12 14:48:52 +0200 | [diff] [blame] | 708 | spin_lock_irq(&dev_priv->irq_lock); |
| 709 | if (dev_priv->display.hpd_irq_setup) |
| 710 | dev_priv->display.hpd_irq_setup(dev); |
| 711 | spin_unlock_irq(&dev_priv->irq_lock); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 712 | |
Jesse Barnes | 24576d2 | 2013-03-26 09:25:45 -0700 | [diff] [blame] | 713 | drm_modeset_lock_all(dev); |
| 714 | intel_modeset_setup_hw_state(dev, true); |
| 715 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 1523909 | 2013-03-05 09:50:58 +0100 | [diff] [blame] | 716 | |
Dave Airlie | e7d6f7d | 2014-12-08 13:23:37 +1000 | [diff] [blame] | 717 | intel_dp_mst_resume(dev); |
| 718 | |
Daniel Vetter | 1523909 | 2013-03-05 09:50:58 +0100 | [diff] [blame] | 719 | /* |
| 720 | * ... but also need to make sure that hotplug processing |
| 721 | * doesn't cause havoc. Like in the driver load code we don't |
| 722 | * bother with the tiny race here where we might loose hotplug |
| 723 | * notifications. |
| 724 | * */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 725 | intel_hpd_init(dev_priv); |
Jesse Barnes | bb60b96 | 2013-03-26 09:25:46 -0700 | [diff] [blame] | 726 | /* Config may have changed between suspend and resume */ |
Jesse Barnes | 1ff74cf | 2014-05-20 15:25:33 -0700 | [diff] [blame] | 727 | drm_helper_hpd_irq_event(dev); |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 728 | } |
Jesse Barnes | 1daed3f | 2011-01-05 12:01:25 -0800 | [diff] [blame] | 729 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 730 | intel_opregion_init(dev); |
| 731 | |
Chris Wilson | 82e3b8c | 2014-08-13 13:09:46 +0100 | [diff] [blame] | 732 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 733 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 734 | mutex_lock(&dev_priv->modeset_restore_lock); |
| 735 | dev_priv->modeset_restore = MODESET_DONE; |
| 736 | mutex_unlock(&dev_priv->modeset_restore_lock); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 737 | |
Jesse Barnes | e5747e3 | 2014-06-12 08:35:47 -0700 | [diff] [blame] | 738 | intel_opregion_notify_adapter(dev, PCI_D0); |
| 739 | |
Imre Deak | ee6f280 | 2014-10-23 19:23:22 +0300 | [diff] [blame] | 740 | drm_kms_helper_poll_enable(dev); |
| 741 | |
Chris Wilson | 074c6ad | 2014-04-09 09:19:43 +0100 | [diff] [blame] | 742 | return 0; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 743 | } |
| 744 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 745 | static int i915_drm_resume_early(struct drm_device *dev) |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 746 | { |
Imre Deak | 36d61e6 | 2014-10-23 19:23:24 +0300 | [diff] [blame] | 747 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1a5df18 | 2014-10-27 17:54:32 -0200 | [diff] [blame] | 748 | int ret = 0; |
Imre Deak | 36d61e6 | 2014-10-23 19:23:24 +0300 | [diff] [blame] | 749 | |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 750 | /* |
| 751 | * We have a resume ordering issue with the snd-hda driver also |
| 752 | * requiring our device to be power up. Due to the lack of a |
| 753 | * parent/child relationship we currently solve this with an early |
| 754 | * resume hook. |
| 755 | * |
| 756 | * FIXME: This should be solved with a special hdmi sink device or |
| 757 | * similar so that power domains can be employed. |
| 758 | */ |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 759 | if (pci_enable_device(dev->pdev)) |
| 760 | return -EIO; |
| 761 | |
| 762 | pci_set_master(dev->pdev); |
| 763 | |
Paulo Zanoni | efee833 | 2014-10-27 17:54:33 -0200 | [diff] [blame] | 764 | if (IS_VALLEYVIEW(dev_priv)) |
Paulo Zanoni | 1a5df18 | 2014-10-27 17:54:32 -0200 | [diff] [blame] | 765 | ret = vlv_resume_prepare(dev_priv, false); |
Imre Deak | 36d61e6 | 2014-10-23 19:23:24 +0300 | [diff] [blame] | 766 | if (ret) |
| 767 | DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret); |
| 768 | |
| 769 | intel_uncore_early_sanitize(dev, true); |
Paulo Zanoni | efee833 | 2014-10-27 17:54:33 -0200 | [diff] [blame] | 770 | |
| 771 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 772 | hsw_disable_pc8(dev_priv); |
| 773 | |
Imre Deak | 36d61e6 | 2014-10-23 19:23:24 +0300 | [diff] [blame] | 774 | intel_uncore_sanitize(dev); |
| 775 | intel_power_domains_init_hw(dev_priv); |
| 776 | |
| 777 | return ret; |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 778 | } |
| 779 | |
Imre Deak | fc49b3d | 2014-10-23 19:23:27 +0300 | [diff] [blame] | 780 | int i915_resume_legacy(struct drm_device *dev) |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 781 | { |
Imre Deak | 50a0072 | 2014-10-23 19:23:17 +0300 | [diff] [blame] | 782 | int ret; |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 783 | |
Imre Deak | 097dd83 | 2014-10-23 19:23:19 +0300 | [diff] [blame] | 784 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 785 | return 0; |
| 786 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 787 | ret = i915_drm_resume_early(dev); |
Imre Deak | 50a0072 | 2014-10-23 19:23:17 +0300 | [diff] [blame] | 788 | if (ret) |
| 789 | return ret; |
| 790 | |
Imre Deak | 5a17514 | 2014-10-23 19:23:18 +0300 | [diff] [blame] | 791 | return i915_drm_resume(dev); |
| 792 | } |
| 793 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 794 | /** |
Eugeni Dodonov | f3953dc | 2011-11-28 16:15:17 -0200 | [diff] [blame] | 795 | * i915_reset - reset chip after a hang |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 796 | * @dev: drm device to reset |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 797 | * |
| 798 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
| 799 | * reset or otherwise an error code. |
| 800 | * |
| 801 | * Procedure is fairly simple: |
| 802 | * - reset the chip using the reset reg |
| 803 | * - re-init context state |
| 804 | * - re-init hardware status page |
| 805 | * - re-init ring buffer |
| 806 | * - re-init interrupt state |
| 807 | * - re-init display |
| 808 | */ |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 809 | int i915_reset(struct drm_device *dev) |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 810 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 2e7c8ee | 2013-05-28 10:38:44 +0100 | [diff] [blame] | 812 | bool simulated; |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 813 | int ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 814 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 815 | if (!i915.reset) |
Chris Wilson | d78cb50 | 2010-12-23 13:33:15 +0000 | [diff] [blame] | 816 | return 0; |
| 817 | |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 818 | intel_reset_gt_powersave(dev); |
| 819 | |
Daniel Vetter | d54a02c | 2012-07-04 22:18:39 +0200 | [diff] [blame] | 820 | mutex_lock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 821 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 822 | i915_gem_reset(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 823 | |
Chris Wilson | 2e7c8ee | 2013-05-28 10:38:44 +0100 | [diff] [blame] | 824 | simulated = dev_priv->gpu_error.stop_rings != 0; |
| 825 | |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 826 | ret = intel_gpu_reset(dev); |
Daniel Vetter | 350d270 | 2012-04-27 15:17:42 +0200 | [diff] [blame] | 827 | |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 828 | /* Also reset the gpu hangman. */ |
| 829 | if (simulated) { |
| 830 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); |
| 831 | dev_priv->gpu_error.stop_rings = 0; |
| 832 | if (ret == -ENODEV) { |
Daniel Vetter | f2d91a2 | 2013-11-07 09:48:57 +0100 | [diff] [blame] | 833 | DRM_INFO("Reset not implemented, but ignoring " |
| 834 | "error for simulated gpu hangs\n"); |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 835 | ret = 0; |
| 836 | } |
Chris Wilson | 2e7c8ee | 2013-05-28 10:38:44 +0100 | [diff] [blame] | 837 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 838 | |
Daniel Vetter | d8f2716 | 2014-10-01 01:02:04 +0200 | [diff] [blame] | 839 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 840 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); |
| 841 | |
Kenneth Graunke | 0573ed4 | 2010-09-11 03:17:19 -0700 | [diff] [blame] | 842 | if (ret) { |
Daniel Vetter | f2d91a2 | 2013-11-07 09:48:57 +0100 | [diff] [blame] | 843 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
Daniel J Blueman | f953c93 | 2010-05-17 14:23:52 +0100 | [diff] [blame] | 844 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 845 | return ret; |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 846 | } |
| 847 | |
Ville Syrjälä | 1362b77 | 2014-11-26 17:07:29 +0200 | [diff] [blame] | 848 | intel_overlay_reset(dev_priv); |
| 849 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 850 | /* Ok, now get things going again... */ |
| 851 | |
| 852 | /* |
| 853 | * Everything depends on having the GTT running, so we need to start |
| 854 | * there. Fortunately we don't need to do this unless we reset the |
| 855 | * chip at a PCI level. |
| 856 | * |
| 857 | * Next we need to restore the context, but we don't use those |
| 858 | * yet either... |
| 859 | * |
| 860 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
| 861 | * was running at the time of the reset (i.e. we weren't VT |
| 862 | * switched away). |
| 863 | */ |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 864 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 865 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
| 866 | dev_priv->gpu_error.reload_in_reset = true; |
| 867 | |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 868 | ret = i915_gem_init_hw(dev); |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 869 | |
| 870 | dev_priv->gpu_error.reload_in_reset = false; |
| 871 | |
Daniel Vetter | 8e88a2b | 2012-06-19 18:40:00 +0200 | [diff] [blame] | 872 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 873 | if (ret) { |
| 874 | DRM_ERROR("Failed hw init on reset %d\n", ret); |
| 875 | return ret; |
| 876 | } |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 877 | |
Daniel Vetter | e090c53 | 2013-11-03 20:27:05 +0100 | [diff] [blame] | 878 | /* |
Daniel Vetter | 78ad455 | 2014-05-22 22:18:21 +0200 | [diff] [blame] | 879 | * FIXME: This races pretty badly against concurrent holders of |
| 880 | * ring interrupts. This is possible since we've started to drop |
| 881 | * dev->struct_mutex in select places when waiting for the gpu. |
Daniel Vetter | e090c53 | 2013-11-03 20:27:05 +0100 | [diff] [blame] | 882 | */ |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 883 | |
Daniel Vetter | 78ad455 | 2014-05-22 22:18:21 +0200 | [diff] [blame] | 884 | /* |
| 885 | * rps/rc6 re-init is necessary to restore state lost after the |
| 886 | * reset and the re-install of gt irqs. Skip for ironlake per |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 887 | * previous concerns that it doesn't respond well to some forms |
Daniel Vetter | 78ad455 | 2014-05-22 22:18:21 +0200 | [diff] [blame] | 888 | * of re-init after reset. |
| 889 | */ |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 890 | if (INTEL_INFO(dev)->gen > 5) |
Imre Deak | dbea3ce | 2014-12-15 18:59:28 +0200 | [diff] [blame] | 891 | intel_enable_gt_powersave(dev); |
Daniel Vetter | bcbc324 | 2012-04-27 15:17:41 +0200 | [diff] [blame] | 892 | } else { |
| 893 | mutex_unlock(&dev->struct_mutex); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 894 | } |
| 895 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 896 | return 0; |
| 897 | } |
| 898 | |
Greg Kroah-Hartman | 56550d9 | 2012-12-21 15:09:25 -0800 | [diff] [blame] | 899 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 900 | { |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 901 | struct intel_device_info *intel_info = |
| 902 | (struct intel_device_info *) ent->driver_data; |
| 903 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 904 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 905 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
| 906 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); |
| 907 | return -ENODEV; |
| 908 | } |
| 909 | |
Chris Wilson | 5fe49d8 | 2011-02-01 19:43:02 +0000 | [diff] [blame] | 910 | /* Only bind to function 0 of the device. Early generations |
| 911 | * used function 1 as a placeholder for multi-head. This causes |
| 912 | * us confusion instead, especially on the systems where both |
| 913 | * functions have the same PCI-ID! |
| 914 | */ |
| 915 | if (PCI_FUNC(pdev->devfn)) |
| 916 | return -ENODEV; |
| 917 | |
Daniel Vetter | 24986ee | 2013-12-11 11:34:33 +0100 | [diff] [blame] | 918 | driver.driver_features &= ~(DRIVER_USE_AGP); |
Daniel Vetter | 01a0685 | 2012-06-25 15:58:49 +0200 | [diff] [blame] | 919 | |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 920 | return drm_get_pci_dev(pdev, ent, &driver); |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static void |
| 924 | i915_pci_remove(struct pci_dev *pdev) |
| 925 | { |
| 926 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 927 | |
| 928 | drm_put_dev(dev); |
| 929 | } |
| 930 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 931 | static int i915_pm_suspend(struct device *dev) |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 932 | { |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 933 | struct pci_dev *pdev = to_pci_dev(dev); |
| 934 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 935 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 936 | if (!drm_dev || !drm_dev->dev_private) { |
| 937 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 938 | return -ENODEV; |
| 939 | } |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 940 | |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 941 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 942 | return 0; |
| 943 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 944 | return i915_drm_suspend(drm_dev); |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 945 | } |
| 946 | |
| 947 | static int i915_pm_suspend_late(struct device *dev) |
| 948 | { |
Imre Deak | 888d0d4 | 2015-01-08 17:54:13 +0200 | [diff] [blame] | 949 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 950 | |
| 951 | /* |
| 952 | * We have a suspedn ordering issue with the snd-hda driver also |
| 953 | * requiring our device to be power up. Due to the lack of a |
| 954 | * parent/child relationship we currently solve this with an late |
| 955 | * suspend hook. |
| 956 | * |
| 957 | * FIXME: This should be solved with a special hdmi sink device or |
| 958 | * similar so that power domains can be employed. |
| 959 | */ |
| 960 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 961 | return 0; |
Kristian Høgsberg | 112b715 | 2009-01-04 16:55:33 -0500 | [diff] [blame] | 962 | |
Imre Deak | ab3be73 | 2015-03-02 13:04:41 +0200 | [diff] [blame] | 963 | return i915_drm_suspend_late(drm_dev, false); |
| 964 | } |
| 965 | |
| 966 | static int i915_pm_poweroff_late(struct device *dev) |
| 967 | { |
| 968 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
| 969 | |
| 970 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 971 | return 0; |
| 972 | |
| 973 | return i915_drm_suspend_late(drm_dev, true); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 974 | } |
| 975 | |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 976 | static int i915_pm_resume_early(struct device *dev) |
| 977 | { |
Imre Deak | 888d0d4 | 2015-01-08 17:54:13 +0200 | [diff] [blame] | 978 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 979 | |
Imre Deak | 097dd83 | 2014-10-23 19:23:19 +0300 | [diff] [blame] | 980 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 981 | return 0; |
| 982 | |
Imre Deak | 5e365c3 | 2014-10-23 19:23:25 +0300 | [diff] [blame] | 983 | return i915_drm_resume_early(drm_dev); |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 984 | } |
| 985 | |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 986 | static int i915_pm_resume(struct device *dev) |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 987 | { |
Imre Deak | 888d0d4 | 2015-01-08 17:54:13 +0200 | [diff] [blame] | 988 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
Rafael J. Wysocki | 84b79f8 | 2010-02-07 21:48:24 +0100 | [diff] [blame] | 989 | |
Imre Deak | 097dd83 | 2014-10-23 19:23:19 +0300 | [diff] [blame] | 990 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 991 | return 0; |
| 992 | |
Imre Deak | 5a17514 | 2014-10-23 19:23:18 +0300 | [diff] [blame] | 993 | return i915_drm_resume(drm_dev); |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 994 | } |
| 995 | |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 996 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 97bea20 | 2014-03-07 20:12:33 -0300 | [diff] [blame] | 997 | { |
Paulo Zanoni | 414de7a | 2014-03-07 20:12:35 -0300 | [diff] [blame] | 998 | hsw_enable_pc8(dev_priv); |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 999 | |
| 1000 | return 0; |
Paulo Zanoni | 97bea20 | 2014-03-07 20:12:33 -0300 | [diff] [blame] | 1001 | } |
| 1002 | |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1003 | /* |
| 1004 | * Save all Gunit registers that may be lost after a D3 and a subsequent |
| 1005 | * S0i[R123] transition. The list of registers needing a save/restore is |
| 1006 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit |
| 1007 | * registers in the following way: |
| 1008 | * - Driver: saved/restored by the driver |
| 1009 | * - Punit : saved/restored by the Punit firmware |
| 1010 | * - No, w/o marking: no need to save/restore, since the register is R/O or |
| 1011 | * used internally by the HW in a way that doesn't depend |
| 1012 | * keeping the content across a suspend/resume. |
| 1013 | * - Debug : used for debugging |
| 1014 | * |
| 1015 | * We save/restore all registers marked with 'Driver', with the following |
| 1016 | * exceptions: |
| 1017 | * - Registers out of use, including also registers marked with 'Debug'. |
| 1018 | * These have no effect on the driver's operation, so we don't save/restore |
| 1019 | * them to reduce the overhead. |
| 1020 | * - Registers that are fully setup by an initialization function called from |
| 1021 | * the resume path. For example many clock gating and RPS/RC6 registers. |
| 1022 | * - Registers that provide the right functionality with their reset defaults. |
| 1023 | * |
| 1024 | * TODO: Except for registers that based on the above 3 criteria can be safely |
| 1025 | * ignored, we save/restore all others, practically treating the HW context as |
| 1026 | * a black-box for the driver. Further investigation is needed to reduce the |
| 1027 | * saved/restored registers even further, by following the same 3 criteria. |
| 1028 | */ |
| 1029 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) |
| 1030 | { |
| 1031 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; |
| 1032 | int i; |
| 1033 | |
| 1034 | /* GAM 0x4000-0x4770 */ |
| 1035 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); |
| 1036 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); |
| 1037 | s->arb_mode = I915_READ(ARB_MODE); |
| 1038 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); |
| 1039 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); |
| 1040 | |
| 1041 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) |
| 1042 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); |
| 1043 | |
| 1044 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); |
| 1045 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); |
| 1046 | |
| 1047 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); |
| 1048 | s->ecochk = I915_READ(GAM_ECOCHK); |
| 1049 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); |
| 1050 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); |
| 1051 | |
| 1052 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); |
| 1053 | |
| 1054 | /* MBC 0x9024-0x91D0, 0x8500 */ |
| 1055 | s->g3dctl = I915_READ(VLV_G3DCTL); |
| 1056 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); |
| 1057 | s->mbctl = I915_READ(GEN6_MBCTL); |
| 1058 | |
| 1059 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ |
| 1060 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); |
| 1061 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); |
| 1062 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); |
| 1063 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); |
| 1064 | s->rstctl = I915_READ(GEN6_RSTCTL); |
| 1065 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1066 | |
| 1067 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ |
| 1068 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); |
| 1069 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); |
| 1070 | s->rpdeuc = I915_READ(GEN6_RPDEUC); |
| 1071 | s->ecobus = I915_READ(ECOBUS); |
| 1072 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); |
| 1073 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); |
| 1074 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); |
| 1075 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); |
| 1076 | s->rcedata = I915_READ(VLV_RCEDATA); |
| 1077 | s->spare2gh = I915_READ(VLV_SPAREG2H); |
| 1078 | |
| 1079 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ |
| 1080 | s->gt_imr = I915_READ(GTIMR); |
| 1081 | s->gt_ier = I915_READ(GTIER); |
| 1082 | s->pm_imr = I915_READ(GEN6_PMIMR); |
| 1083 | s->pm_ier = I915_READ(GEN6_PMIER); |
| 1084 | |
| 1085 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) |
| 1086 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); |
| 1087 | |
| 1088 | /* GT SA CZ domain, 0x100000-0x138124 */ |
| 1089 | s->tilectl = I915_READ(TILECTL); |
| 1090 | s->gt_fifoctl = I915_READ(GTFIFOCTL); |
| 1091 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1092 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1093 | s->pmwgicz = I915_READ(VLV_PMWGICZ); |
| 1094 | |
| 1095 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ |
| 1096 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); |
| 1097 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); |
| 1098 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
| 1099 | |
| 1100 | /* |
| 1101 | * Not saving any of: |
| 1102 | * DFT, 0x9800-0x9EC0 |
| 1103 | * SARB, 0xB000-0xB1FC |
| 1104 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 |
| 1105 | * PCI CFG |
| 1106 | */ |
| 1107 | } |
| 1108 | |
| 1109 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) |
| 1110 | { |
| 1111 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; |
| 1112 | u32 val; |
| 1113 | int i; |
| 1114 | |
| 1115 | /* GAM 0x4000-0x4770 */ |
| 1116 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); |
| 1117 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); |
| 1118 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); |
| 1119 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); |
| 1120 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); |
| 1121 | |
| 1122 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) |
| 1123 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); |
| 1124 | |
| 1125 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); |
| 1126 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); |
| 1127 | |
| 1128 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); |
| 1129 | I915_WRITE(GAM_ECOCHK, s->ecochk); |
| 1130 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); |
| 1131 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); |
| 1132 | |
| 1133 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); |
| 1134 | |
| 1135 | /* MBC 0x9024-0x91D0, 0x8500 */ |
| 1136 | I915_WRITE(VLV_G3DCTL, s->g3dctl); |
| 1137 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); |
| 1138 | I915_WRITE(GEN6_MBCTL, s->mbctl); |
| 1139 | |
| 1140 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ |
| 1141 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); |
| 1142 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); |
| 1143 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); |
| 1144 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); |
| 1145 | I915_WRITE(GEN6_RSTCTL, s->rstctl); |
| 1146 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); |
| 1147 | |
| 1148 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ |
| 1149 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); |
| 1150 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); |
| 1151 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); |
| 1152 | I915_WRITE(ECOBUS, s->ecobus); |
| 1153 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); |
| 1154 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); |
| 1155 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); |
| 1156 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); |
| 1157 | I915_WRITE(VLV_RCEDATA, s->rcedata); |
| 1158 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); |
| 1159 | |
| 1160 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ |
| 1161 | I915_WRITE(GTIMR, s->gt_imr); |
| 1162 | I915_WRITE(GTIER, s->gt_ier); |
| 1163 | I915_WRITE(GEN6_PMIMR, s->pm_imr); |
| 1164 | I915_WRITE(GEN6_PMIER, s->pm_ier); |
| 1165 | |
| 1166 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) |
| 1167 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); |
| 1168 | |
| 1169 | /* GT SA CZ domain, 0x100000-0x138124 */ |
| 1170 | I915_WRITE(TILECTL, s->tilectl); |
| 1171 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); |
| 1172 | /* |
| 1173 | * Preserve the GT allow wake and GFX force clock bit, they are not |
| 1174 | * be restored, as they are used to control the s0ix suspend/resume |
| 1175 | * sequence by the caller. |
| 1176 | */ |
| 1177 | val = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1178 | val &= VLV_GTLC_ALLOWWAKEREQ; |
| 1179 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; |
| 1180 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); |
| 1181 | |
| 1182 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1183 | val &= VLV_GFX_CLK_FORCE_ON_BIT; |
| 1184 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; |
| 1185 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); |
| 1186 | |
| 1187 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); |
| 1188 | |
| 1189 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ |
| 1190 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); |
| 1191 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); |
| 1192 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
| 1193 | } |
| 1194 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 1195 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
| 1196 | { |
| 1197 | u32 val; |
| 1198 | int err; |
| 1199 | |
| 1200 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1201 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); |
| 1202 | |
| 1203 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
| 1204 | /* Wait for a previous force-off to settle */ |
| 1205 | if (force_on) { |
Imre Deak | 8d4eee9 | 2014-04-14 20:24:43 +0300 | [diff] [blame] | 1206 | err = wait_for(!COND, 20); |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 1207 | if (err) { |
| 1208 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", |
| 1209 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); |
| 1210 | return err; |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1215 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; |
| 1216 | if (force_on) |
| 1217 | val |= VLV_GFX_CLK_FORCE_ON_BIT; |
| 1218 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); |
| 1219 | |
| 1220 | if (!force_on) |
| 1221 | return 0; |
| 1222 | |
Imre Deak | 8d4eee9 | 2014-04-14 20:24:43 +0300 | [diff] [blame] | 1223 | err = wait_for(COND, 20); |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 1224 | if (err) |
| 1225 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", |
| 1226 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); |
| 1227 | |
| 1228 | return err; |
| 1229 | #undef COND |
| 1230 | } |
| 1231 | |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1232 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
| 1233 | { |
| 1234 | u32 val; |
| 1235 | int err = 0; |
| 1236 | |
| 1237 | val = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1238 | val &= ~VLV_GTLC_ALLOWWAKEREQ; |
| 1239 | if (allow) |
| 1240 | val |= VLV_GTLC_ALLOWWAKEREQ; |
| 1241 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); |
| 1242 | POSTING_READ(VLV_GTLC_WAKE_CTRL); |
| 1243 | |
| 1244 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ |
| 1245 | allow) |
| 1246 | err = wait_for(COND, 1); |
| 1247 | if (err) |
| 1248 | DRM_ERROR("timeout disabling GT waking\n"); |
| 1249 | return err; |
| 1250 | #undef COND |
| 1251 | } |
| 1252 | |
| 1253 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
| 1254 | bool wait_for_on) |
| 1255 | { |
| 1256 | u32 mask; |
| 1257 | u32 val; |
| 1258 | int err; |
| 1259 | |
| 1260 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; |
| 1261 | val = wait_for_on ? mask : 0; |
| 1262 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) |
| 1263 | if (COND) |
| 1264 | return 0; |
| 1265 | |
| 1266 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", |
| 1267 | wait_for_on ? "on" : "off", |
| 1268 | I915_READ(VLV_GTLC_PW_STATUS)); |
| 1269 | |
| 1270 | /* |
| 1271 | * RC6 transitioning can be delayed up to 2 msec (see |
| 1272 | * valleyview_enable_rps), use 3 msec for safety. |
| 1273 | */ |
| 1274 | err = wait_for(COND, 3); |
| 1275 | if (err) |
| 1276 | DRM_ERROR("timeout waiting for GT wells to go %s\n", |
| 1277 | wait_for_on ? "on" : "off"); |
| 1278 | |
| 1279 | return err; |
| 1280 | #undef COND |
| 1281 | } |
| 1282 | |
| 1283 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) |
| 1284 | { |
| 1285 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) |
| 1286 | return; |
| 1287 | |
| 1288 | DRM_ERROR("GT register access while GT waking disabled\n"); |
| 1289 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
| 1290 | } |
| 1291 | |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1292 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1293 | { |
| 1294 | u32 mask; |
| 1295 | int err; |
| 1296 | |
| 1297 | /* |
| 1298 | * Bspec defines the following GT well on flags as debug only, so |
| 1299 | * don't treat them as hard failures. |
| 1300 | */ |
| 1301 | (void)vlv_wait_for_gt_wells(dev_priv, false); |
| 1302 | |
| 1303 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; |
| 1304 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); |
| 1305 | |
| 1306 | vlv_check_no_gt_access(dev_priv); |
| 1307 | |
| 1308 | err = vlv_force_gfx_clock(dev_priv, true); |
| 1309 | if (err) |
| 1310 | goto err1; |
| 1311 | |
| 1312 | err = vlv_allow_gt_wake(dev_priv, false); |
| 1313 | if (err) |
| 1314 | goto err2; |
Deepak S | 9871116 | 2014-12-12 14:18:16 +0530 | [diff] [blame] | 1315 | |
| 1316 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 1317 | vlv_save_gunit_s0ix_state(dev_priv); |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1318 | |
| 1319 | err = vlv_force_gfx_clock(dev_priv, false); |
| 1320 | if (err) |
| 1321 | goto err2; |
| 1322 | |
| 1323 | return 0; |
| 1324 | |
| 1325 | err2: |
| 1326 | /* For safety always re-enable waking and disable gfx clock forcing */ |
| 1327 | vlv_allow_gt_wake(dev_priv, true); |
| 1328 | err1: |
| 1329 | vlv_force_gfx_clock(dev_priv, false); |
| 1330 | |
| 1331 | return err; |
| 1332 | } |
| 1333 | |
Sagar Kamble | 016970b | 2014-08-13 23:07:06 +0530 | [diff] [blame] | 1334 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
| 1335 | bool rpm_resume) |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1336 | { |
| 1337 | struct drm_device *dev = dev_priv->dev; |
| 1338 | int err; |
| 1339 | int ret; |
| 1340 | |
| 1341 | /* |
| 1342 | * If any of the steps fail just try to continue, that's the best we |
| 1343 | * can do at this point. Return the first error code (which will also |
| 1344 | * leave RPM permanently disabled). |
| 1345 | */ |
| 1346 | ret = vlv_force_gfx_clock(dev_priv, true); |
| 1347 | |
Deepak S | 9871116 | 2014-12-12 14:18:16 +0530 | [diff] [blame] | 1348 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 1349 | vlv_restore_gunit_s0ix_state(dev_priv); |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1350 | |
| 1351 | err = vlv_allow_gt_wake(dev_priv, true); |
| 1352 | if (!ret) |
| 1353 | ret = err; |
| 1354 | |
| 1355 | err = vlv_force_gfx_clock(dev_priv, false); |
| 1356 | if (!ret) |
| 1357 | ret = err; |
| 1358 | |
| 1359 | vlv_check_no_gt_access(dev_priv); |
| 1360 | |
Sagar Kamble | 016970b | 2014-08-13 23:07:06 +0530 | [diff] [blame] | 1361 | if (rpm_resume) { |
| 1362 | intel_init_clock_gating(dev); |
| 1363 | i915_gem_restore_fences(dev); |
| 1364 | } |
Imre Deak | ddeea5b | 2014-05-05 15:19:56 +0300 | [diff] [blame] | 1365 | |
| 1366 | return ret; |
| 1367 | } |
| 1368 | |
Paulo Zanoni | 97bea20 | 2014-03-07 20:12:33 -0300 | [diff] [blame] | 1369 | static int intel_runtime_suspend(struct device *device) |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1370 | { |
| 1371 | struct pci_dev *pdev = to_pci_dev(device); |
| 1372 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1373 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 1374 | int ret; |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1375 | |
Imre Deak | aeab0b5 | 2014-04-14 20:24:36 +0300 | [diff] [blame] | 1376 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 1377 | return -ENODEV; |
| 1378 | |
Imre Deak | 604effb | 2014-08-26 13:26:56 +0300 | [diff] [blame] | 1379 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
| 1380 | return -ENODEV; |
| 1381 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1382 | DRM_DEBUG_KMS("Suspending device\n"); |
| 1383 | |
Imre Deak | 9486db6 | 2014-04-22 20:21:07 +0300 | [diff] [blame] | 1384 | /* |
Imre Deak | d610297 | 2014-05-07 19:57:49 +0300 | [diff] [blame] | 1385 | * We could deadlock here in case another thread holding struct_mutex |
| 1386 | * calls RPM suspend concurrently, since the RPM suspend will wait |
| 1387 | * first for this RPM suspend to finish. In this case the concurrent |
| 1388 | * RPM resume will be followed by its RPM suspend counterpart. Still |
| 1389 | * for consistency return -EAGAIN, which will reschedule this suspend. |
| 1390 | */ |
| 1391 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1392 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); |
| 1393 | /* |
| 1394 | * Bump the expiration timestamp, otherwise the suspend won't |
| 1395 | * be rescheduled. |
| 1396 | */ |
| 1397 | pm_runtime_mark_last_busy(device); |
| 1398 | |
| 1399 | return -EAGAIN; |
| 1400 | } |
| 1401 | /* |
| 1402 | * We are safe here against re-faults, since the fault handler takes |
| 1403 | * an RPM reference. |
| 1404 | */ |
| 1405 | i915_gem_release_all_mmaps(dev_priv); |
| 1406 | mutex_unlock(&dev->struct_mutex); |
| 1407 | |
Paulo Zanoni | fac6adb | 2014-10-30 15:59:31 -0200 | [diff] [blame] | 1408 | intel_suspend_gt_powersave(dev); |
Imre Deak | 2eb5252 | 2014-11-19 15:30:05 +0200 | [diff] [blame] | 1409 | intel_runtime_pm_disable_interrupts(dev_priv); |
Imre Deak | b5478bc | 2014-04-14 20:24:37 +0300 | [diff] [blame] | 1410 | |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1411 | ret = intel_suspend_complete(dev_priv); |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 1412 | if (ret) { |
| 1413 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 1414 | intel_runtime_pm_enable_interrupts(dev_priv); |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 1415 | |
| 1416 | return ret; |
| 1417 | } |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 1418 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1419 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Chris Wilson | dc9fb09 | 2015-01-16 11:34:34 +0200 | [diff] [blame] | 1420 | intel_uncore_forcewake_reset(dev, false); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1421 | dev_priv->pm.suspended = true; |
Kristen Carlson Accardi | 1fb2362 | 2014-01-14 15:36:15 -0800 | [diff] [blame] | 1422 | |
| 1423 | /* |
Paulo Zanoni | c8a0bd4 | 2014-08-21 17:09:38 -0300 | [diff] [blame] | 1424 | * FIXME: We really should find a document that references the arguments |
| 1425 | * used below! |
Kristen Carlson Accardi | 1fb2362 | 2014-01-14 15:36:15 -0800 | [diff] [blame] | 1426 | */ |
Paulo Zanoni | c8a0bd4 | 2014-08-21 17:09:38 -0300 | [diff] [blame] | 1427 | if (IS_HASWELL(dev)) { |
| 1428 | /* |
| 1429 | * current versions of firmware which depend on this opregion |
| 1430 | * notification have repurposed the D1 definition to mean |
| 1431 | * "runtime suspended" vs. what you would normally expect (D3) |
| 1432 | * to distinguish it from notifications that might be sent via |
| 1433 | * the suspend path. |
| 1434 | */ |
| 1435 | intel_opregion_notify_adapter(dev, PCI_D1); |
| 1436 | } else { |
| 1437 | /* |
| 1438 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop |
| 1439 | * being detected, and the call we do at intel_runtime_resume() |
| 1440 | * won't be able to restore them. Since PCI_D3hot matches the |
| 1441 | * actual specification and appears to be working, use it. Let's |
| 1442 | * assume the other non-Haswell platforms will stay the same as |
| 1443 | * Broadwell. |
| 1444 | */ |
| 1445 | intel_opregion_notify_adapter(dev, PCI_D3hot); |
| 1446 | } |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1447 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 1448 | assert_forcewakes_inactive(dev_priv); |
Chris Wilson | dc9fb09 | 2015-01-16 11:34:34 +0200 | [diff] [blame] | 1449 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 1450 | DRM_DEBUG_KMS("Device suspended\n"); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1451 | return 0; |
| 1452 | } |
| 1453 | |
Paulo Zanoni | 97bea20 | 2014-03-07 20:12:33 -0300 | [diff] [blame] | 1454 | static int intel_runtime_resume(struct device *device) |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1455 | { |
| 1456 | struct pci_dev *pdev = to_pci_dev(device); |
| 1457 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1458 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1a5df18 | 2014-10-27 17:54:32 -0200 | [diff] [blame] | 1459 | int ret = 0; |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1460 | |
Imre Deak | 604effb | 2014-08-26 13:26:56 +0300 | [diff] [blame] | 1461 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
| 1462 | return -ENODEV; |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1463 | |
| 1464 | DRM_DEBUG_KMS("Resuming device\n"); |
| 1465 | |
Paulo Zanoni | cd2e9e9 | 2013-12-06 20:34:21 -0200 | [diff] [blame] | 1466 | intel_opregion_notify_adapter(dev, PCI_D0); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1467 | dev_priv->pm.suspended = false; |
| 1468 | |
Paulo Zanoni | 1a5df18 | 2014-10-27 17:54:32 -0200 | [diff] [blame] | 1469 | if (IS_GEN6(dev_priv)) |
| 1470 | intel_init_pch_refclk(dev); |
| 1471 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 1472 | hsw_disable_pc8(dev_priv); |
| 1473 | else if (IS_VALLEYVIEW(dev_priv)) |
| 1474 | ret = vlv_resume_prepare(dev_priv, true); |
| 1475 | |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 1476 | /* |
| 1477 | * No point of rolling back things in case of an error, as the best |
| 1478 | * we can do is to hope that things will still work (and disable RPM). |
| 1479 | */ |
Imre Deak | 92b806d | 2014-04-14 20:24:39 +0300 | [diff] [blame] | 1480 | i915_gem_init_swizzling(dev); |
| 1481 | gen6_update_ring_freq(dev); |
| 1482 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 1483 | intel_runtime_pm_enable_interrupts(dev_priv); |
Paulo Zanoni | fac6adb | 2014-10-30 15:59:31 -0200 | [diff] [blame] | 1484 | intel_enable_gt_powersave(dev); |
Imre Deak | b5478bc | 2014-04-14 20:24:37 +0300 | [diff] [blame] | 1485 | |
Imre Deak | 0ab9cfe | 2014-04-15 16:39:45 +0300 | [diff] [blame] | 1486 | if (ret) |
| 1487 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); |
| 1488 | else |
| 1489 | DRM_DEBUG_KMS("Device resumed\n"); |
| 1490 | |
| 1491 | return ret; |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1492 | } |
| 1493 | |
Sagar Kamble | 016970b | 2014-08-13 23:07:06 +0530 | [diff] [blame] | 1494 | /* |
| 1495 | * This function implements common functionality of runtime and system |
| 1496 | * suspend sequence. |
| 1497 | */ |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1498 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
| 1499 | { |
| 1500 | struct drm_device *dev = dev_priv->dev; |
| 1501 | int ret; |
| 1502 | |
Imre Deak | 604effb | 2014-08-26 13:26:56 +0300 | [diff] [blame] | 1503 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1504 | ret = hsw_suspend_complete(dev_priv); |
Imre Deak | 604effb | 2014-08-26 13:26:56 +0300 | [diff] [blame] | 1505 | else if (IS_VALLEYVIEW(dev)) |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1506 | ret = vlv_suspend_complete(dev_priv); |
Imre Deak | 604effb | 2014-08-26 13:26:56 +0300 | [diff] [blame] | 1507 | else |
| 1508 | ret = 0; |
Sagar Kamble | ebc3282 | 2014-08-13 23:07:05 +0530 | [diff] [blame] | 1509 | |
| 1510 | return ret; |
| 1511 | } |
| 1512 | |
Chris Wilson | b4b78d1 | 2010-06-06 15:40:20 +0100 | [diff] [blame] | 1513 | static const struct dev_pm_ops i915_pm_ops = { |
Imre Deak | 5545dbb | 2014-10-23 19:23:28 +0300 | [diff] [blame] | 1514 | /* |
| 1515 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, |
| 1516 | * PMSG_RESUME] |
| 1517 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1518 | .suspend = i915_pm_suspend, |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 1519 | .suspend_late = i915_pm_suspend_late, |
| 1520 | .resume_early = i915_pm_resume_early, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1521 | .resume = i915_pm_resume, |
Imre Deak | 5545dbb | 2014-10-23 19:23:28 +0300 | [diff] [blame] | 1522 | |
| 1523 | /* |
| 1524 | * S4 event handlers |
| 1525 | * @freeze, @freeze_late : called (1) before creating the |
| 1526 | * hibernation image [PMSG_FREEZE] and |
| 1527 | * (2) after rebooting, before restoring |
| 1528 | * the image [PMSG_QUIESCE] |
| 1529 | * @thaw, @thaw_early : called (1) after creating the hibernation |
| 1530 | * image, before writing it [PMSG_THAW] |
| 1531 | * and (2) after failing to create or |
| 1532 | * restore the image [PMSG_RECOVER] |
| 1533 | * @poweroff, @poweroff_late: called after writing the hibernation |
| 1534 | * image, before rebooting [PMSG_HIBERNATE] |
| 1535 | * @restore, @restore_early : called after rebooting and restoring the |
| 1536 | * hibernation image [PMSG_RESTORE] |
| 1537 | */ |
Imre Deak | 36d61e6 | 2014-10-23 19:23:24 +0300 | [diff] [blame] | 1538 | .freeze = i915_pm_suspend, |
| 1539 | .freeze_late = i915_pm_suspend_late, |
| 1540 | .thaw_early = i915_pm_resume_early, |
| 1541 | .thaw = i915_pm_resume, |
| 1542 | .poweroff = i915_pm_suspend, |
Imre Deak | ab3be73 | 2015-03-02 13:04:41 +0200 | [diff] [blame] | 1543 | .poweroff_late = i915_pm_poweroff_late, |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 1544 | .restore_early = i915_pm_resume_early, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1545 | .restore = i915_pm_resume, |
Imre Deak | 5545dbb | 2014-10-23 19:23:28 +0300 | [diff] [blame] | 1546 | |
| 1547 | /* S0ix (via runtime suspend) event handlers */ |
Paulo Zanoni | 97bea20 | 2014-03-07 20:12:33 -0300 | [diff] [blame] | 1548 | .runtime_suspend = intel_runtime_suspend, |
| 1549 | .runtime_resume = intel_runtime_resume, |
Zhenyu Wang | cbda12d | 2009-12-16 13:36:10 +0800 | [diff] [blame] | 1550 | }; |
| 1551 | |
Laurent Pinchart | 78b6855 | 2012-05-17 13:27:22 +0200 | [diff] [blame] | 1552 | static const struct vm_operations_struct i915_gem_vm_ops = { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1553 | .fault = i915_gem_fault, |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1554 | .open = drm_gem_vm_open, |
| 1555 | .close = drm_gem_vm_close, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1556 | }; |
| 1557 | |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 1558 | static const struct file_operations i915_driver_fops = { |
| 1559 | .owner = THIS_MODULE, |
| 1560 | .open = drm_open, |
| 1561 | .release = drm_release, |
| 1562 | .unlocked_ioctl = drm_ioctl, |
| 1563 | .mmap = drm_gem_mmap, |
| 1564 | .poll = drm_poll, |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 1565 | .read = drm_read, |
| 1566 | #ifdef CONFIG_COMPAT |
| 1567 | .compat_ioctl = i915_compat_ioctl, |
| 1568 | #endif |
| 1569 | .llseek = noop_llseek, |
| 1570 | }; |
| 1571 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | static struct drm_driver driver = { |
Michael Witten | 0c54781 | 2011-08-25 17:55:54 +0000 | [diff] [blame] | 1573 | /* Don't use MTRRs here; the Xserver or userspace app should |
| 1574 | * deal with them for Intel hardware. |
Dave Airlie | 792d2b9 | 2005-11-11 23:30:27 +1100 | [diff] [blame] | 1575 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1576 | .driver_features = |
Daniel Vetter | 24986ee | 2013-12-11 11:34:33 +0100 | [diff] [blame] | 1577 | DRIVER_USE_AGP | |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1578 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
| 1579 | DRIVER_RENDER, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1580 | .load = i915_driver_load, |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1581 | .unload = i915_driver_unload, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1582 | .open = i915_driver_open, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1583 | .lastclose = i915_driver_lastclose, |
| 1584 | .preclose = i915_driver_preclose, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1585 | .postclose = i915_driver_postclose, |
David Herrmann | 915b4d1 | 2014-08-29 12:12:43 +0200 | [diff] [blame] | 1586 | .set_busid = drm_pci_set_busid, |
Rafael J. Wysocki | d8e2920 | 2010-01-09 00:45:33 +0100 | [diff] [blame] | 1587 | |
| 1588 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ |
Imre Deak | fc49b3d | 2014-10-23 19:23:27 +0300 | [diff] [blame] | 1589 | .suspend = i915_suspend_legacy, |
Imre Deak | 76c4b25 | 2014-04-01 19:55:22 +0300 | [diff] [blame] | 1590 | .resume = i915_resume_legacy, |
Rafael J. Wysocki | d8e2920 | 2010-01-09 00:45:33 +0100 | [diff] [blame] | 1591 | |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1592 | .device_is_agp = i915_driver_device_is_agp, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 1593 | #if defined(CONFIG_DEBUG_FS) |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 1594 | .debugfs_init = i915_debugfs_init, |
| 1595 | .debugfs_cleanup = i915_debugfs_cleanup, |
Ben Gamari | 955b12d | 2009-02-17 20:08:49 -0500 | [diff] [blame] | 1596 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1597 | .gem_free_object = i915_gem_free_object, |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1598 | .gem_vm_ops = &i915_gem_vm_ops, |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1599 | |
| 1600 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1601 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1602 | .gem_prime_export = i915_gem_prime_export, |
| 1603 | .gem_prime_import = i915_gem_prime_import, |
| 1604 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1605 | .dumb_create = i915_gem_dumb_create, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 1606 | .dumb_map_offset = i915_gem_mmap_gtt, |
Daniel Vetter | 43387b3 | 2013-07-16 09:12:04 +0200 | [diff] [blame] | 1607 | .dumb_destroy = drm_gem_dumb_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1608 | .ioctls = i915_ioctls, |
Arjan van de Ven | e08e96d | 2011-10-31 07:28:57 -0700 | [diff] [blame] | 1609 | .fops = &i915_driver_fops, |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1610 | .name = DRIVER_NAME, |
| 1611 | .desc = DRIVER_DESC, |
| 1612 | .date = DRIVER_DATE, |
| 1613 | .major = DRIVER_MAJOR, |
| 1614 | .minor = DRIVER_MINOR, |
| 1615 | .patchlevel = DRIVER_PATCHLEVEL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1616 | }; |
| 1617 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1618 | static struct pci_driver i915_pci_driver = { |
| 1619 | .name = DRIVER_NAME, |
| 1620 | .id_table = pciidlist, |
| 1621 | .probe = i915_pci_probe, |
| 1622 | .remove = i915_pci_remove, |
| 1623 | .driver.pm = &i915_pm_ops, |
| 1624 | }; |
| 1625 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1626 | static int __init i915_init(void) |
| 1627 | { |
| 1628 | driver.num_ioctls = i915_max_ioctl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1629 | |
| 1630 | /* |
| 1631 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless |
| 1632 | * explicitly disabled with the module pararmeter. |
| 1633 | * |
| 1634 | * Otherwise, just follow the parameter (defaulting to off). |
| 1635 | * |
| 1636 | * Allow optional vga_text_mode_force boot option to override |
| 1637 | * the default behavior. |
| 1638 | */ |
| 1639 | #if defined(CONFIG_DRM_I915_KMS) |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1640 | if (i915.modeset != 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1641 | driver.driver_features |= DRIVER_MODESET; |
| 1642 | #endif |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1643 | if (i915.modeset == 1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1644 | driver.driver_features |= DRIVER_MODESET; |
| 1645 | |
| 1646 | #ifdef CONFIG_VGA_CONSOLE |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1647 | if (vgacon_text_force() && i915.modeset == -1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1648 | driver.driver_features &= ~DRIVER_MODESET; |
| 1649 | #endif |
| 1650 | |
Daniel Vetter | b30324a | 2013-11-13 22:11:25 +0100 | [diff] [blame] | 1651 | if (!(driver.driver_features & DRIVER_MODESET)) { |
Chris Wilson | 3885c6b | 2011-01-23 10:45:14 +0000 | [diff] [blame] | 1652 | driver.get_vblank_timestamp = NULL; |
Daniel Vetter | b30324a | 2013-11-13 22:11:25 +0100 | [diff] [blame] | 1653 | #ifndef CONFIG_DRM_I915_UMS |
| 1654 | /* Silently fail loading to not upset userspace. */ |
Jani Nikula | c9cd7b6 | 2014-06-02 16:58:30 +0300 | [diff] [blame] | 1655 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
Daniel Vetter | b30324a | 2013-11-13 22:11:25 +0100 | [diff] [blame] | 1656 | return 0; |
| 1657 | #endif |
| 1658 | } |
Chris Wilson | 3885c6b | 2011-01-23 10:45:14 +0000 | [diff] [blame] | 1659 | |
Matt Roper | b2e7723 | 2015-01-22 16:53:12 -0800 | [diff] [blame] | 1660 | /* |
| 1661 | * FIXME: Note that we're lying to the DRM core here so that we can get access |
| 1662 | * to the atomic ioctl and the atomic properties. Only plane operations on |
| 1663 | * a single CRTC will actually work. |
| 1664 | */ |
| 1665 | if (i915.nuclear_pageflip) |
| 1666 | driver.driver_features |= DRIVER_ATOMIC; |
| 1667 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1668 | return drm_pci_init(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | static void __exit i915_exit(void) |
| 1672 | { |
Daniel Vetter | b33ecdd | 2013-11-15 17:16:33 +0100 | [diff] [blame] | 1673 | #ifndef CONFIG_DRM_I915_UMS |
| 1674 | if (!(driver.driver_features & DRIVER_MODESET)) |
| 1675 | return; /* Never loaded a driver. */ |
| 1676 | #endif |
| 1677 | |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1678 | drm_pci_exit(&driver, &i915_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | } |
| 1680 | |
| 1681 | module_init(i915_init); |
| 1682 | module_exit(i915_exit); |
| 1683 | |
Damien Lespiau | 0a6d163 | 2014-08-27 11:30:20 +0100 | [diff] [blame] | 1684 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
Damien Lespiau | 1eab923 | 2014-08-27 11:30:21 +0100 | [diff] [blame] | 1685 | MODULE_AUTHOR("Intel Corporation"); |
Damien Lespiau | 0a6d163 | 2014-08-27 11:30:20 +0100 | [diff] [blame] | 1686 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1687 | MODULE_DESCRIPTION(DRIVER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1688 | MODULE_LICENSE("GPL and additional rights"); |