Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_FUTEX_H |
| 17 | #define __ASM_FUTEX_H |
| 18 | |
| 19 | #ifdef __KERNEL__ |
| 20 | |
| 21 | #include <linux/futex.h> |
| 22 | #include <linux/uaccess.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 23 | |
| 24 | #include <asm/alternative.h> |
| 25 | #include <asm/cpufeature.h> |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 26 | #include <asm/errno.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 27 | #include <asm/sysreg.h> |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 28 | |
| 29 | #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ |
| 30 | asm volatile( \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 31 | ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ |
| 32 | CONFIG_ARM64_PAN) \ |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 33 | " prfm pstl1strm, %2\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 34 | "1: ldxr %w1, %2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 35 | insn "\n" \ |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 36 | "2: stlxr %w0, %w3, %2\n" \ |
| 37 | " cbnz %w0, 1b\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 38 | " dmb ish\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 39 | "3:\n" \ |
| 40 | " .pushsection .fixup,\"ax\"\n" \ |
Will Deacon | 4da7a56 | 2013-11-06 19:31:24 +0000 | [diff] [blame] | 41 | " .align 2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 42 | "4: mov %w0, %w5\n" \ |
| 43 | " b 3b\n" \ |
| 44 | " .popsection\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 45 | _ASM_EXTABLE(1b, 4b) \ |
| 46 | _ASM_EXTABLE(2b, 4b) \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 47 | ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ |
| 48 | CONFIG_ARM64_PAN) \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 49 | : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ |
| 50 | : "r" (oparg), "Ir" (-EFAULT) \ |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 51 | : "memory") |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 52 | |
| 53 | static inline int |
Jiri Slaby | 81da9f8 | 2017-08-24 09:31:05 +0200 | [diff] [blame] | 54 | arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 55 | { |
Nathan Chancellor | 8e6a1ef | 2019-04-17 00:21:21 -0700 | [diff] [blame] | 56 | int oldval = 0, ret, tmp; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 57 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 58 | pagefault_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 59 | |
| 60 | switch (op) { |
| 61 | case FUTEX_OP_SET: |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 62 | __futex_atomic_op("mov %w3, %w4", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 63 | ret, oldval, uaddr, tmp, oparg); |
| 64 | break; |
| 65 | case FUTEX_OP_ADD: |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 66 | __futex_atomic_op("add %w3, %w1, %w4", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 67 | ret, oldval, uaddr, tmp, oparg); |
| 68 | break; |
| 69 | case FUTEX_OP_OR: |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 70 | __futex_atomic_op("orr %w3, %w1, %w4", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 71 | ret, oldval, uaddr, tmp, oparg); |
| 72 | break; |
| 73 | case FUTEX_OP_ANDN: |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 74 | __futex_atomic_op("and %w3, %w1, %w4", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 75 | ret, oldval, uaddr, tmp, ~oparg); |
| 76 | break; |
| 77 | case FUTEX_OP_XOR: |
Will Deacon | 32810f9 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 78 | __futex_atomic_op("eor %w3, %w1, %w4", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 79 | ret, oldval, uaddr, tmp, oparg); |
| 80 | break; |
| 81 | default: |
| 82 | ret = -ENOSYS; |
| 83 | } |
| 84 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 85 | pagefault_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 86 | |
Jiri Slaby | 81da9f8 | 2017-08-24 09:31:05 +0200 | [diff] [blame] | 87 | if (!ret) |
| 88 | *oval = oldval; |
| 89 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 90 | return ret; |
| 91 | } |
| 92 | |
| 93 | static inline int |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 94 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 95 | u32 oldval, u32 newval) |
| 96 | { |
| 97 | int ret = 0; |
| 98 | u32 val, tmp; |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 99 | u32 __user *uaddr; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 100 | |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 101 | if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32))) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 102 | return -EFAULT; |
| 103 | |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 104 | uaddr = __uaccess_mask_ptr(_uaddr); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 105 | asm volatile("// futex_atomic_cmpxchg_inatomic\n" |
James Morse | 811d61e | 2016-02-02 15:53:59 +0000 | [diff] [blame] | 106 | ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 107 | " prfm pstl1strm, %2\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 108 | "1: ldxr %w1, %2\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 109 | " sub %w3, %w1, %w4\n" |
| 110 | " cbnz %w3, 3f\n" |
| 111 | "2: stlxr %w3, %w5, %2\n" |
| 112 | " cbnz %w3, 1b\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 113 | " dmb ish\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 114 | "3:\n" |
| 115 | " .pushsection .fixup,\"ax\"\n" |
| 116 | "4: mov %w0, %w6\n" |
| 117 | " b 3b\n" |
| 118 | " .popsection\n" |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 119 | _ASM_EXTABLE(1b, 4b) |
| 120 | _ASM_EXTABLE(2b, 4b) |
James Morse | 811d61e | 2016-02-02 15:53:59 +0000 | [diff] [blame] | 121 | ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 122 | : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) |
| 123 | : "r" (oldval), "r" (newval), "Ir" (-EFAULT) |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 124 | : "memory"); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 125 | |
| 126 | *uval = val; |
| 127 | return ret; |
| 128 | } |
| 129 | |
| 130 | #endif /* __KERNEL__ */ |
| 131 | #endif /* __ASM_FUTEX_H */ |