blob: 394cbc5c93e3600a8c918bfb673756bdd279ce7b [file] [log] [blame]
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001/*
2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Saeed Bisharaff7b0472008-07-08 11:58:36 -070022#include <linux/delay.h>
23#include <linux/dma-mapping.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/memory.h>
Andrew Lunnc5101822012-02-19 13:30:26 +010028#include <linux/clk.h>
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +010029#include <linux/of.h>
30#include <linux/of_irq.h>
31#include <linux/irqdomain.h>
Arnd Bergmannc02cecb2012-08-24 15:21:54 +020032#include <linux/platform_data/dma-mv_xor.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000033
34#include "dmaengine.h"
Saeed Bisharaff7b0472008-07-08 11:58:36 -070035#include "mv_xor.h"
36
37static void mv_xor_issue_pending(struct dma_chan *chan);
38
39#define to_mv_xor_chan(chan) \
Thomas Petazzoni98817b92012-11-15 14:57:44 +010040 container_of(chan, struct mv_xor_chan, dmachan)
Saeed Bisharaff7b0472008-07-08 11:58:36 -070041
42#define to_mv_xor_slot(tx) \
43 container_of(tx, struct mv_xor_desc_slot, async_tx)
44
Thomas Petazzonic98c1782012-11-15 14:17:18 +010045#define mv_chan_to_devp(chan) \
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +010046 ((chan)->dmadev.dev)
Thomas Petazzonic98c1782012-11-15 14:17:18 +010047
Saeed Bisharaff7b0472008-07-08 11:58:36 -070048static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
49{
50 struct mv_xor_desc *hw_desc = desc->hw_desc;
51
52 hw_desc->status = (1 << 31);
53 hw_desc->phy_next_desc = 0;
54 hw_desc->desc_command = (1 << 31);
55}
56
Saeed Bisharaff7b0472008-07-08 11:58:36 -070057static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
58 u32 byte_count)
59{
60 struct mv_xor_desc *hw_desc = desc->hw_desc;
61 hw_desc->byte_count = byte_count;
62}
63
64static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
65 u32 next_desc_addr)
66{
67 struct mv_xor_desc *hw_desc = desc->hw_desc;
68 BUG_ON(hw_desc->phy_next_desc);
69 hw_desc->phy_next_desc = next_desc_addr;
70}
71
72static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
73{
74 struct mv_xor_desc *hw_desc = desc->hw_desc;
75 hw_desc->phy_next_desc = 0;
76}
77
Saeed Bisharaff7b0472008-07-08 11:58:36 -070078static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
79 dma_addr_t addr)
80{
81 struct mv_xor_desc *hw_desc = desc->hw_desc;
82 hw_desc->phy_dest_addr = addr;
83}
84
85static int mv_chan_memset_slot_count(size_t len)
86{
87 return 1;
88}
89
90#define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
91
92static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
93 int index, dma_addr_t addr)
94{
95 struct mv_xor_desc *hw_desc = desc->hw_desc;
Thomas Petazzonie03bc652013-07-29 17:42:14 +020096 hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
Saeed Bisharaff7b0472008-07-08 11:58:36 -070097 if (desc->type == DMA_XOR)
98 hw_desc->desc_command |= (1 << index);
99}
100
101static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
102{
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200103 return readl_relaxed(XOR_CURR_DESC(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700104}
105
106static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
107 u32 next_desc_addr)
108{
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200109 writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700110}
111
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700112static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
113{
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200114 u32 val = readl_relaxed(XOR_INTR_MASK(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700115 val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200116 writel_relaxed(val, XOR_INTR_MASK(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700117}
118
119static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
120{
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200121 u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700122 intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
123 return intr_cause;
124}
125
126static int mv_is_err_intr(u32 intr_cause)
127{
128 if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
129 return 1;
130
131 return 0;
132}
133
134static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
135{
Simon Guinot86363682010-09-17 23:33:51 +0200136 u32 val = ~(1 << (chan->idx * 16));
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100137 dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200138 writel_relaxed(val, XOR_INTR_CAUSE(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700139}
140
141static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
142{
143 u32 val = 0xFFFF0000 >> (chan->idx * 16);
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200144 writel_relaxed(val, XOR_INTR_CAUSE(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700145}
146
147static int mv_can_chain(struct mv_xor_desc_slot *desc)
148{
149 struct mv_xor_desc_slot *chain_old_tail = list_entry(
150 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
151
152 if (chain_old_tail->type != desc->type)
153 return 0;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700154
155 return 1;
156}
157
158static void mv_set_mode(struct mv_xor_chan *chan,
159 enum dma_transaction_type type)
160{
161 u32 op_mode;
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200162 u32 config = readl_relaxed(XOR_CONFIG(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700163
164 switch (type) {
165 case DMA_XOR:
166 op_mode = XOR_OPERATION_MODE_XOR;
167 break;
168 case DMA_MEMCPY:
169 op_mode = XOR_OPERATION_MODE_MEMCPY;
170 break;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700171 default:
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100172 dev_err(mv_chan_to_devp(chan),
Joe Perches1ba151c2012-10-28 01:05:44 -0700173 "error: unsupported operation %d\n",
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100174 type);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700175 BUG();
176 return;
177 }
178
179 config &= ~0x7;
180 config |= op_mode;
Thomas Petazzonie03bc652013-07-29 17:42:14 +0200181
182#if defined(__BIG_ENDIAN)
183 config |= XOR_DESCRIPTOR_SWAP;
184#else
185 config &= ~XOR_DESCRIPTOR_SWAP;
186#endif
187
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200188 writel_relaxed(config, XOR_CONFIG(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700189 chan->current_type = type;
190}
191
192static void mv_chan_activate(struct mv_xor_chan *chan)
193{
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100194 dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
Ezequiel Garcia5a9a55b2014-05-21 14:02:35 -0700195
196 /* writel ensures all descriptors are flushed before activation */
197 writel(BIT(0), XOR_ACTIVATION(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700198}
199
200static char mv_chan_is_busy(struct mv_xor_chan *chan)
201{
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200202 u32 state = readl_relaxed(XOR_ACTIVATION(chan));
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700203
204 state = (state >> 4) & 0x3;
205
206 return (state == 1) ? 1 : 0;
207}
208
209static int mv_chan_xor_slot_count(size_t len, int src_cnt)
210{
211 return 1;
212}
213
214/**
215 * mv_xor_free_slots - flags descriptor slots for reuse
216 * @slot: Slot to free
217 * Caller must hold &mv_chan->lock while calling this function
218 */
219static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
220 struct mv_xor_desc_slot *slot)
221{
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100222 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n",
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700223 __func__, __LINE__, slot);
224
225 slot->slots_per_op = 0;
226
227}
228
229/*
230 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
231 * sw_desc
232 * Caller must hold &mv_chan->lock while calling this function
233 */
234static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
235 struct mv_xor_desc_slot *sw_desc)
236{
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100237 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700238 __func__, __LINE__, sw_desc);
239 if (sw_desc->type != mv_chan->current_type)
240 mv_set_mode(mv_chan, sw_desc->type);
241
Bartlomiej Zolnierkiewicz48a9db42013-07-03 15:05:06 -0700242 /* set the hardware chain */
243 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
244
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700245 mv_chan->pending += sw_desc->slot_cnt;
Thomas Petazzoni98817b92012-11-15 14:57:44 +0100246 mv_xor_issue_pending(&mv_chan->dmachan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700247}
248
249static dma_cookie_t
250mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
251 struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
252{
253 BUG_ON(desc->async_tx.cookie < 0);
254
255 if (desc->async_tx.cookie > 0) {
256 cookie = desc->async_tx.cookie;
257
258 /* call the callback (must not sleep or submit new
259 * operations to this channel)
260 */
261 if (desc->async_tx.callback)
262 desc->async_tx.callback(
263 desc->async_tx.callback_param);
264
Dan Williamsd38a8c62013-10-18 19:35:23 +0200265 dma_descriptor_unmap(&desc->async_tx);
Bartlomiej Zolnierkiewicz54f8d502013-10-18 19:35:32 +0200266 if (desc->group_head)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700267 desc->group_head = NULL;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700268 }
269
270 /* run dependent operations */
Dan Williams07f22112009-01-05 17:14:31 -0700271 dma_run_dependencies(&desc->async_tx);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700272
273 return cookie;
274}
275
276static int
277mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
278{
279 struct mv_xor_desc_slot *iter, *_iter;
280
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100281 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700282 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
283 completed_node) {
284
285 if (async_tx_test_ack(&iter->async_tx)) {
286 list_del(&iter->completed_node);
287 mv_xor_free_slots(mv_chan, iter);
288 }
289 }
290 return 0;
291}
292
293static int
294mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
295 struct mv_xor_chan *mv_chan)
296{
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100297 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700298 __func__, __LINE__, desc, desc->async_tx.flags);
299 list_del(&desc->chain_node);
300 /* the client is allowed to attach dependent operations
301 * until 'ack' is set
302 */
303 if (!async_tx_test_ack(&desc->async_tx)) {
304 /* move this slot to the completed_slots */
305 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
306 return 0;
307 }
308
309 mv_xor_free_slots(mv_chan, desc);
310 return 0;
311}
312
313static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
314{
315 struct mv_xor_desc_slot *iter, *_iter;
316 dma_cookie_t cookie = 0;
317 int busy = mv_chan_is_busy(mv_chan);
318 u32 current_desc = mv_chan_get_current_desc(mv_chan);
319 int seen_current = 0;
320
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100321 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
322 dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700323 mv_xor_clean_completed_slots(mv_chan);
324
325 /* free completed slots from the chain starting with
326 * the oldest descriptor
327 */
328
329 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
330 chain_node) {
331 prefetch(_iter);
332 prefetch(&_iter->async_tx);
333
334 /* do not advance past the current descriptor loaded into the
335 * hardware channel, subsequent descriptors are either in
336 * process or have not been submitted
337 */
338 if (seen_current)
339 break;
340
341 /* stop the search if we reach the current descriptor and the
342 * channel is busy
343 */
344 if (iter->async_tx.phys == current_desc) {
345 seen_current = 1;
346 if (busy)
347 break;
348 }
349
350 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
351
352 if (mv_xor_clean_slot(iter, mv_chan))
353 break;
354 }
355
356 if ((busy == 0) && !list_empty(&mv_chan->chain)) {
357 struct mv_xor_desc_slot *chain_head;
358 chain_head = list_entry(mv_chan->chain.next,
359 struct mv_xor_desc_slot,
360 chain_node);
361
362 mv_xor_start_new_chain(mv_chan, chain_head);
363 }
364
365 if (cookie > 0)
Thomas Petazzoni98817b92012-11-15 14:57:44 +0100366 mv_chan->dmachan.completed_cookie = cookie;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700367}
368
369static void
370mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
371{
372 spin_lock_bh(&mv_chan->lock);
373 __mv_xor_slot_cleanup(mv_chan);
374 spin_unlock_bh(&mv_chan->lock);
375}
376
377static void mv_xor_tasklet(unsigned long data)
378{
379 struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
Saeed Bishara8333f652010-12-21 16:53:39 +0200380 mv_xor_slot_cleanup(chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700381}
382
383static struct mv_xor_desc_slot *
384mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
385 int slots_per_op)
386{
387 struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
388 LIST_HEAD(chain);
389 int slots_found, retry = 0;
390
391 /* start search from the last allocated descrtiptor
392 * if a contiguous allocation can not be found start searching
393 * from the beginning of the list
394 */
395retry:
396 slots_found = 0;
397 if (retry == 0)
398 iter = mv_chan->last_used;
399 else
400 iter = list_entry(&mv_chan->all_slots,
401 struct mv_xor_desc_slot,
402 slot_node);
403
404 list_for_each_entry_safe_continue(
405 iter, _iter, &mv_chan->all_slots, slot_node) {
406 prefetch(_iter);
407 prefetch(&_iter->async_tx);
408 if (iter->slots_per_op) {
409 /* give up after finding the first busy slot
410 * on the second pass through the list
411 */
412 if (retry)
413 break;
414
415 slots_found = 0;
416 continue;
417 }
418
419 /* start the allocation if the slot is correctly aligned */
420 if (!slots_found++)
421 alloc_start = iter;
422
423 if (slots_found == num_slots) {
424 struct mv_xor_desc_slot *alloc_tail = NULL;
425 struct mv_xor_desc_slot *last_used = NULL;
426 iter = alloc_start;
427 while (num_slots) {
428 int i;
429
430 /* pre-ack all but the last descriptor */
431 async_tx_ack(&iter->async_tx);
432
433 list_add_tail(&iter->chain_node, &chain);
434 alloc_tail = iter;
435 iter->async_tx.cookie = 0;
436 iter->slot_cnt = num_slots;
437 iter->xor_check_result = NULL;
438 for (i = 0; i < slots_per_op; i++) {
439 iter->slots_per_op = slots_per_op - i;
440 last_used = iter;
441 iter = list_entry(iter->slot_node.next,
442 struct mv_xor_desc_slot,
443 slot_node);
444 }
445 num_slots -= slots_per_op;
446 }
447 alloc_tail->group_head = alloc_start;
448 alloc_tail->async_tx.cookie = -EBUSY;
Dan Williams64203b62009-09-08 17:53:03 -0700449 list_splice(&chain, &alloc_tail->tx_list);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700450 mv_chan->last_used = last_used;
451 mv_desc_clear_next_desc(alloc_start);
452 mv_desc_clear_next_desc(alloc_tail);
453 return alloc_tail;
454 }
455 }
456 if (!retry++)
457 goto retry;
458
459 /* try to free some slots if the allocation fails */
460 tasklet_schedule(&mv_chan->irq_tasklet);
461
462 return NULL;
463}
464
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700465/************************ DMA engine API functions ****************************/
466static dma_cookie_t
467mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
468{
469 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
470 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
471 struct mv_xor_desc_slot *grp_start, *old_chain_tail;
472 dma_cookie_t cookie;
473 int new_hw_chain = 1;
474
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100475 dev_dbg(mv_chan_to_devp(mv_chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700476 "%s sw_desc %p: async_tx %p\n",
477 __func__, sw_desc, &sw_desc->async_tx);
478
479 grp_start = sw_desc->group_head;
480
481 spin_lock_bh(&mv_chan->lock);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000482 cookie = dma_cookie_assign(tx);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700483
484 if (list_empty(&mv_chan->chain))
Dan Williams64203b62009-09-08 17:53:03 -0700485 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700486 else {
487 new_hw_chain = 0;
488
489 old_chain_tail = list_entry(mv_chan->chain.prev,
490 struct mv_xor_desc_slot,
491 chain_node);
Dan Williams64203b62009-09-08 17:53:03 -0700492 list_splice_init(&grp_start->tx_list,
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700493 &old_chain_tail->chain_node);
494
495 if (!mv_can_chain(grp_start))
496 goto submit_done;
497
Olof Johansson31fd8f52014-02-03 17:13:23 -0800498 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
499 &old_chain_tail->async_tx.phys);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700500
501 /* fix up the hardware chain */
502 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
503
504 /* if the channel is not busy */
505 if (!mv_chan_is_busy(mv_chan)) {
506 u32 current_desc = mv_chan_get_current_desc(mv_chan);
507 /*
508 * and the curren desc is the end of the chain before
509 * the append, then we need to start the channel
510 */
511 if (current_desc == old_chain_tail->async_tx.phys)
512 new_hw_chain = 1;
513 }
514 }
515
516 if (new_hw_chain)
517 mv_xor_start_new_chain(mv_chan, grp_start);
518
519submit_done:
520 spin_unlock_bh(&mv_chan->lock);
521
522 return cookie;
523}
524
525/* returns the number of allocated descriptors */
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700526static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700527{
Olof Johansson31fd8f52014-02-03 17:13:23 -0800528 void *virt_desc;
529 dma_addr_t dma_desc;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700530 int idx;
531 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
532 struct mv_xor_desc_slot *slot = NULL;
Thomas Petazzonib503fa02012-11-15 15:55:30 +0100533 int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700534
535 /* Allocate descriptor slots */
536 idx = mv_chan->slots_allocated;
537 while (idx < num_descs_in_pool) {
538 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
539 if (!slot) {
540 printk(KERN_INFO "MV XOR Channel only initialized"
541 " %d descriptor slots", idx);
542 break;
543 }
Olof Johansson31fd8f52014-02-03 17:13:23 -0800544 virt_desc = mv_chan->dma_desc_pool_virt;
545 slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700546
547 dma_async_tx_descriptor_init(&slot->async_tx, chan);
548 slot->async_tx.tx_submit = mv_xor_tx_submit;
549 INIT_LIST_HEAD(&slot->chain_node);
550 INIT_LIST_HEAD(&slot->slot_node);
Dan Williams64203b62009-09-08 17:53:03 -0700551 INIT_LIST_HEAD(&slot->tx_list);
Olof Johansson31fd8f52014-02-03 17:13:23 -0800552 dma_desc = mv_chan->dma_desc_pool;
553 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700554 slot->idx = idx++;
555
556 spin_lock_bh(&mv_chan->lock);
557 mv_chan->slots_allocated = idx;
558 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
559 spin_unlock_bh(&mv_chan->lock);
560 }
561
562 if (mv_chan->slots_allocated && !mv_chan->last_used)
563 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
564 struct mv_xor_desc_slot,
565 slot_node);
566
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100567 dev_dbg(mv_chan_to_devp(mv_chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700568 "allocated %d descriptor slots last_used: %p\n",
569 mv_chan->slots_allocated, mv_chan->last_used);
570
571 return mv_chan->slots_allocated ? : -ENOMEM;
572}
573
574static struct dma_async_tx_descriptor *
575mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
576 size_t len, unsigned long flags)
577{
578 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
579 struct mv_xor_desc_slot *sw_desc, *grp_start;
580 int slot_cnt;
581
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100582 dev_dbg(mv_chan_to_devp(mv_chan),
Olof Johansson31fd8f52014-02-03 17:13:23 -0800583 "%s dest: %pad src %pad len: %u flags: %ld\n",
584 __func__, &dest, &src, len, flags);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700585 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
586 return NULL;
587
Coly Li7912d302011-03-27 01:26:53 +0800588 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700589
590 spin_lock_bh(&mv_chan->lock);
591 slot_cnt = mv_chan_memcpy_slot_count(len);
592 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
593 if (sw_desc) {
594 sw_desc->type = DMA_MEMCPY;
595 sw_desc->async_tx.flags = flags;
596 grp_start = sw_desc->group_head;
597 mv_desc_init(grp_start, flags);
598 mv_desc_set_byte_count(grp_start, len);
599 mv_desc_set_dest_addr(sw_desc->group_head, dest);
600 mv_desc_set_src_addr(grp_start, 0, src);
601 sw_desc->unmap_src_cnt = 1;
602 sw_desc->unmap_len = len;
603 }
604 spin_unlock_bh(&mv_chan->lock);
605
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100606 dev_dbg(mv_chan_to_devp(mv_chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700607 "%s sw_desc %p async_tx %p\n",
Jingoo Han4c143722013-08-06 19:37:08 +0900608 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700609
610 return sw_desc ? &sw_desc->async_tx : NULL;
611}
612
613static struct dma_async_tx_descriptor *
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700614mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
615 unsigned int src_cnt, size_t len, unsigned long flags)
616{
617 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
618 struct mv_xor_desc_slot *sw_desc, *grp_start;
619 int slot_cnt;
620
621 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
622 return NULL;
623
Coly Li7912d302011-03-27 01:26:53 +0800624 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700625
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100626 dev_dbg(mv_chan_to_devp(mv_chan),
Olof Johansson31fd8f52014-02-03 17:13:23 -0800627 "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
628 __func__, src_cnt, len, &dest, flags);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700629
630 spin_lock_bh(&mv_chan->lock);
631 slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
632 sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
633 if (sw_desc) {
634 sw_desc->type = DMA_XOR;
635 sw_desc->async_tx.flags = flags;
636 grp_start = sw_desc->group_head;
637 mv_desc_init(grp_start, flags);
638 /* the byte count field is the same as in memcpy desc*/
639 mv_desc_set_byte_count(grp_start, len);
640 mv_desc_set_dest_addr(sw_desc->group_head, dest);
641 sw_desc->unmap_src_cnt = src_cnt;
642 sw_desc->unmap_len = len;
643 while (src_cnt--)
644 mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
645 }
646 spin_unlock_bh(&mv_chan->lock);
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100647 dev_dbg(mv_chan_to_devp(mv_chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700648 "%s sw_desc %p async_tx %p \n",
649 __func__, sw_desc, &sw_desc->async_tx);
650 return sw_desc ? &sw_desc->async_tx : NULL;
651}
652
653static void mv_xor_free_chan_resources(struct dma_chan *chan)
654{
655 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
656 struct mv_xor_desc_slot *iter, *_iter;
657 int in_use_descs = 0;
658
659 mv_xor_slot_cleanup(mv_chan);
660
661 spin_lock_bh(&mv_chan->lock);
662 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
663 chain_node) {
664 in_use_descs++;
665 list_del(&iter->chain_node);
666 }
667 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
668 completed_node) {
669 in_use_descs++;
670 list_del(&iter->completed_node);
671 }
672 list_for_each_entry_safe_reverse(
673 iter, _iter, &mv_chan->all_slots, slot_node) {
674 list_del(&iter->slot_node);
675 kfree(iter);
676 mv_chan->slots_allocated--;
677 }
678 mv_chan->last_used = NULL;
679
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100680 dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700681 __func__, mv_chan->slots_allocated);
682 spin_unlock_bh(&mv_chan->lock);
683
684 if (in_use_descs)
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100685 dev_err(mv_chan_to_devp(mv_chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700686 "freeing %d in use descriptors!\n", in_use_descs);
687}
688
689/**
Linus Walleij07934482010-03-26 16:50:49 -0700690 * mv_xor_status - poll the status of an XOR transaction
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700691 * @chan: XOR channel handle
692 * @cookie: XOR transaction identifier
Linus Walleij07934482010-03-26 16:50:49 -0700693 * @txstate: XOR transactions state holder (or NULL)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700694 */
Linus Walleij07934482010-03-26 16:50:49 -0700695static enum dma_status mv_xor_status(struct dma_chan *chan,
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700696 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700697 struct dma_tx_state *txstate)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700698{
699 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700700 enum dma_status ret;
701
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000702 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koulb3efb8f2013-10-16 20:51:04 +0530703 if (ret == DMA_COMPLETE) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700704 mv_xor_clean_completed_slots(mv_chan);
705 return ret;
706 }
707 mv_xor_slot_cleanup(mv_chan);
708
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000709 return dma_cookie_status(chan, cookie, txstate);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700710}
711
712static void mv_dump_xor_regs(struct mv_xor_chan *chan)
713{
714 u32 val;
715
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200716 val = readl_relaxed(XOR_CONFIG(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700717 dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700718
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200719 val = readl_relaxed(XOR_ACTIVATION(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700720 dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700721
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200722 val = readl_relaxed(XOR_INTR_CAUSE(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700723 dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700724
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200725 val = readl_relaxed(XOR_INTR_MASK(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700726 dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700727
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200728 val = readl_relaxed(XOR_ERROR_CAUSE(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700729 dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700730
Thomas Petazzoni5733c382013-07-29 17:42:13 +0200731 val = readl_relaxed(XOR_ERROR_ADDR(chan));
Joe Perches1ba151c2012-10-28 01:05:44 -0700732 dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700733}
734
735static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
736 u32 intr_cause)
737{
738 if (intr_cause & (1 << 4)) {
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100739 dev_dbg(mv_chan_to_devp(chan),
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700740 "ignore this error\n");
741 return;
742 }
743
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100744 dev_err(mv_chan_to_devp(chan),
Joe Perches1ba151c2012-10-28 01:05:44 -0700745 "error on chan %d. intr cause 0x%08x\n",
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100746 chan->idx, intr_cause);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700747
748 mv_dump_xor_regs(chan);
749 BUG();
750}
751
752static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
753{
754 struct mv_xor_chan *chan = data;
755 u32 intr_cause = mv_chan_get_intr_cause(chan);
756
Thomas Petazzonic98c1782012-11-15 14:17:18 +0100757 dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700758
759 if (mv_is_err_intr(intr_cause))
760 mv_xor_err_interrupt_handler(chan, intr_cause);
761
762 tasklet_schedule(&chan->irq_tasklet);
763
764 mv_xor_device_clear_eoc_cause(chan);
765
766 return IRQ_HANDLED;
767}
768
769static void mv_xor_issue_pending(struct dma_chan *chan)
770{
771 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
772
773 if (mv_chan->pending >= MV_XOR_THRESHOLD) {
774 mv_chan->pending = 0;
775 mv_chan_activate(mv_chan);
776 }
777}
778
779/*
780 * Perform a transaction to verify the HW works.
781 */
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700782
Linus Torvaldsc2714332012-12-14 14:54:26 -0800783static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700784{
785 int i;
786 void *src, *dest;
787 dma_addr_t src_dma, dest_dma;
788 struct dma_chan *dma_chan;
789 dma_cookie_t cookie;
790 struct dma_async_tx_descriptor *tx;
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300791 struct dmaengine_unmap_data *unmap;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700792 int err = 0;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700793
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300794 src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700795 if (!src)
796 return -ENOMEM;
797
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300798 dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700799 if (!dest) {
800 kfree(src);
801 return -ENOMEM;
802 }
803
804 /* Fill in src buffer */
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300805 for (i = 0; i < PAGE_SIZE; i++)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700806 ((u8 *) src)[i] = (u8)i;
807
Thomas Petazzoni275cc0c2012-11-15 15:09:42 +0100808 dma_chan = &mv_chan->dmachan;
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700809 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700810 err = -ENODEV;
811 goto out;
812 }
813
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300814 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
815 if (!unmap) {
816 err = -ENOMEM;
817 goto free_resources;
818 }
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700819
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300820 src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
821 PAGE_SIZE, DMA_TO_DEVICE);
822 unmap->to_cnt = 1;
823 unmap->addr[0] = src_dma;
824
825 dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
826 PAGE_SIZE, DMA_FROM_DEVICE);
827 unmap->from_cnt = 1;
828 unmap->addr[1] = dest_dma;
829
830 unmap->len = PAGE_SIZE;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700831
832 tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300833 PAGE_SIZE, 0);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700834 cookie = mv_xor_tx_submit(tx);
835 mv_xor_issue_pending(dma_chan);
836 async_tx_ack(tx);
837 msleep(1);
838
Linus Walleij07934482010-03-26 16:50:49 -0700839 if (mv_xor_status(dma_chan, cookie, NULL) !=
Vinod Koulb3efb8f2013-10-16 20:51:04 +0530840 DMA_COMPLETE) {
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100841 dev_err(dma_chan->device->dev,
842 "Self-test copy timed out, disabling\n");
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700843 err = -ENODEV;
844 goto free_resources;
845 }
846
Thomas Petazzonic35064c2012-11-15 13:01:59 +0100847 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300848 PAGE_SIZE, DMA_FROM_DEVICE);
849 if (memcmp(src, dest, PAGE_SIZE)) {
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100850 dev_err(dma_chan->device->dev,
851 "Self-test copy failed compare, disabling\n");
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700852 err = -ENODEV;
853 goto free_resources;
854 }
855
856free_resources:
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300857 dmaengine_unmap_put(unmap);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700858 mv_xor_free_chan_resources(dma_chan);
859out:
860 kfree(src);
861 kfree(dest);
862 return err;
863}
864
865#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
Bill Pemberton463a1f82012-11-19 13:22:55 -0500866static int
Thomas Petazzoni275cc0c2012-11-15 15:09:42 +0100867mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700868{
869 int i, src_idx;
870 struct page *dest;
871 struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
872 dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
873 dma_addr_t dest_dma;
874 struct dma_async_tx_descriptor *tx;
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300875 struct dmaengine_unmap_data *unmap;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700876 struct dma_chan *dma_chan;
877 dma_cookie_t cookie;
878 u8 cmp_byte = 0;
879 u32 cmp_word;
880 int err = 0;
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300881 int src_count = MV_XOR_NUM_SRC_TEST;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700882
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300883 for (src_idx = 0; src_idx < src_count; src_idx++) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700884 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
Roel Kluina09b09a2009-02-25 13:56:21 +0100885 if (!xor_srcs[src_idx]) {
886 while (src_idx--)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700887 __free_page(xor_srcs[src_idx]);
Roel Kluina09b09a2009-02-25 13:56:21 +0100888 return -ENOMEM;
889 }
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700890 }
891
892 dest = alloc_page(GFP_KERNEL);
Roel Kluina09b09a2009-02-25 13:56:21 +0100893 if (!dest) {
894 while (src_idx--)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700895 __free_page(xor_srcs[src_idx]);
Roel Kluina09b09a2009-02-25 13:56:21 +0100896 return -ENOMEM;
897 }
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700898
899 /* Fill in src buffers */
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300900 for (src_idx = 0; src_idx < src_count; src_idx++) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700901 u8 *ptr = page_address(xor_srcs[src_idx]);
902 for (i = 0; i < PAGE_SIZE; i++)
903 ptr[i] = (1 << src_idx);
904 }
905
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300906 for (src_idx = 0; src_idx < src_count; src_idx++)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700907 cmp_byte ^= (u8) (1 << src_idx);
908
909 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
910 (cmp_byte << 8) | cmp_byte;
911
912 memset(page_address(dest), 0, PAGE_SIZE);
913
Thomas Petazzoni275cc0c2012-11-15 15:09:42 +0100914 dma_chan = &mv_chan->dmachan;
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700915 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700916 err = -ENODEV;
917 goto out;
918 }
919
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300920 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
921 GFP_KERNEL);
922 if (!unmap) {
923 err = -ENOMEM;
924 goto free_resources;
925 }
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700926
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300927 /* test xor */
928 for (i = 0; i < src_count; i++) {
929 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
930 0, PAGE_SIZE, DMA_TO_DEVICE);
931 dma_srcs[i] = unmap->addr[i];
932 unmap->to_cnt++;
933 }
934
935 unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
936 DMA_FROM_DEVICE);
937 dest_dma = unmap->addr[src_count];
938 unmap->from_cnt = 1;
939 unmap->len = PAGE_SIZE;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700940
941 tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300942 src_count, PAGE_SIZE, 0);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700943
944 cookie = mv_xor_tx_submit(tx);
945 mv_xor_issue_pending(dma_chan);
946 async_tx_ack(tx);
947 msleep(8);
948
Linus Walleij07934482010-03-26 16:50:49 -0700949 if (mv_xor_status(dma_chan, cookie, NULL) !=
Vinod Koulb3efb8f2013-10-16 20:51:04 +0530950 DMA_COMPLETE) {
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100951 dev_err(dma_chan->device->dev,
952 "Self-test xor timed out, disabling\n");
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700953 err = -ENODEV;
954 goto free_resources;
955 }
956
Thomas Petazzonic35064c2012-11-15 13:01:59 +0100957 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700958 PAGE_SIZE, DMA_FROM_DEVICE);
959 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
960 u32 *ptr = page_address(dest);
961 if (ptr[i] != cmp_word) {
Thomas Petazzonia3fc74b2012-11-15 12:50:27 +0100962 dev_err(dma_chan->device->dev,
Joe Perches1ba151c2012-10-28 01:05:44 -0700963 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
964 i, ptr[i], cmp_word);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700965 err = -ENODEV;
966 goto free_resources;
967 }
968 }
969
970free_resources:
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300971 dmaengine_unmap_put(unmap);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700972 mv_xor_free_chan_resources(dma_chan);
973out:
Ezequiel Garciad16695a2013-12-10 09:32:36 -0300974 src_idx = src_count;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700975 while (src_idx--)
976 __free_page(xor_srcs[src_idx]);
977 __free_page(dest);
978 return err;
979}
980
Andrew Lunn34c93c82012-11-18 11:44:56 +0100981/* This driver does not implement any of the optional DMA operations. */
982static int
983mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
984 unsigned long arg)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700985{
Andrew Lunn34c93c82012-11-18 11:44:56 +0100986 return -ENOSYS;
987}
988
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100989static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700990{
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700991 struct dma_chan *chan, *_chan;
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100992 struct device *dev = mv_chan->dmadev.dev;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700993
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100994 dma_async_device_unregister(&mv_chan->dmadev);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700995
Thomas Petazzonib503fa02012-11-15 15:55:30 +0100996 dma_free_coherent(dev, MV_XOR_POOL_SIZE,
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100997 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700998
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100999 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
Thomas Petazzonia6b4a9d2012-10-29 16:45:46 +01001000 device_node) {
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001001 list_del(&chan->device_node);
1002 }
1003
Thomas Petazzoni88eb92c2012-11-15 16:11:18 +01001004 free_irq(mv_chan->irq, mv_chan);
1005
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001006 return 0;
1007}
1008
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001009static struct mv_xor_chan *
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001010mv_xor_channel_add(struct mv_xor_device *xordev,
Thomas Petazzonia6b4a9d2012-10-29 16:45:46 +01001011 struct platform_device *pdev,
Thomas Petazzonib503fa02012-11-15 15:55:30 +01001012 int idx, dma_cap_mask_t cap_mask, int irq)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001013{
1014 int ret = 0;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001015 struct mv_xor_chan *mv_chan;
1016 struct dma_device *dma_dev;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001017
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001018 mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
Sachin Kamata5776592013-09-02 13:54:20 +05301019 if (!mv_chan)
1020 return ERR_PTR(-ENOMEM);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001021
Thomas Petazzoni9aedbdb2012-11-15 15:36:37 +01001022 mv_chan->idx = idx;
Thomas Petazzoni88eb92c2012-11-15 16:11:18 +01001023 mv_chan->irq = irq;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001024
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001025 dma_dev = &mv_chan->dmadev;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001026
1027 /* allocate coherent memory for hardware descriptors
1028 * note: writecombine gives slightly better performance, but
1029 * requires that we explicitly flush the writes
1030 */
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001031 mv_chan->dma_desc_pool_virt =
Thomas Petazzonib503fa02012-11-15 15:55:30 +01001032 dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE,
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001033 &mv_chan->dma_desc_pool, GFP_KERNEL);
1034 if (!mv_chan->dma_desc_pool_virt)
Thomas Petazzonia6b4a9d2012-10-29 16:45:46 +01001035 return ERR_PTR(-ENOMEM);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001036
1037 /* discover transaction capabilites from the platform data */
Thomas Petazzonia6b4a9d2012-10-29 16:45:46 +01001038 dma_dev->cap_mask = cap_mask;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001039
1040 INIT_LIST_HEAD(&dma_dev->channels);
1041
1042 /* set base routines */
1043 dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1044 dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07001045 dma_dev->device_tx_status = mv_xor_status;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001046 dma_dev->device_issue_pending = mv_xor_issue_pending;
Andrew Lunn34c93c82012-11-18 11:44:56 +01001047 dma_dev->device_control = mv_xor_control;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001048 dma_dev->dev = &pdev->dev;
1049
1050 /* set prep routines based on capability */
1051 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1052 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001053 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
Joe Perchesc0198942009-06-28 09:26:21 -07001054 dma_dev->max_xor = 8;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001055 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1056 }
1057
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001058 mv_chan->mmr_base = xordev->xor_base;
Ezequiel Garcia82a14022013-10-30 12:01:43 -03001059 mv_chan->mmr_high_base = xordev->xor_high_base;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001060 tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1061 mv_chan);
1062
1063 /* clear errors before enabling interrupts */
1064 mv_xor_device_clear_err_status(mv_chan);
1065
Thomas Petazzoni2d0a0742012-11-22 18:19:09 +01001066 ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1067 0, dev_name(&pdev->dev), mv_chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001068 if (ret)
1069 goto err_free_dma;
1070
1071 mv_chan_unmask_interrupts(mv_chan);
1072
1073 mv_set_mode(mv_chan, DMA_MEMCPY);
1074
1075 spin_lock_init(&mv_chan->lock);
1076 INIT_LIST_HEAD(&mv_chan->chain);
1077 INIT_LIST_HEAD(&mv_chan->completed_slots);
1078 INIT_LIST_HEAD(&mv_chan->all_slots);
Thomas Petazzoni98817b92012-11-15 14:57:44 +01001079 mv_chan->dmachan.device = dma_dev;
1080 dma_cookie_init(&mv_chan->dmachan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001081
Thomas Petazzoni98817b92012-11-15 14:57:44 +01001082 list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001083
1084 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
Thomas Petazzoni275cc0c2012-11-15 15:09:42 +01001085 ret = mv_xor_memcpy_self_test(mv_chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001086 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1087 if (ret)
Thomas Petazzoni2d0a0742012-11-22 18:19:09 +01001088 goto err_free_irq;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001089 }
1090
1091 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
Thomas Petazzoni275cc0c2012-11-15 15:09:42 +01001092 ret = mv_xor_xor_self_test(mv_chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001093 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1094 if (ret)
Thomas Petazzoni2d0a0742012-11-22 18:19:09 +01001095 goto err_free_irq;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001096 }
1097
Bartlomiej Zolnierkiewicz48a9db42013-07-03 15:05:06 -07001098 dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n",
Joe Perches1ba151c2012-10-28 01:05:44 -07001099 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
Joe Perches1ba151c2012-10-28 01:05:44 -07001100 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1101 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001102
1103 dma_async_device_register(dma_dev);
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001104 return mv_chan;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001105
Thomas Petazzoni2d0a0742012-11-22 18:19:09 +01001106err_free_irq:
1107 free_irq(mv_chan->irq, mv_chan);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001108 err_free_dma:
Thomas Petazzonib503fa02012-11-15 15:55:30 +01001109 dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +01001110 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
Thomas Petazzonia6b4a9d2012-10-29 16:45:46 +01001111 return ERR_PTR(ret);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001112}
1113
1114static void
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001115mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
Andrew Lunn63a93322011-12-07 21:48:07 +01001116 const struct mbus_dram_target_info *dram)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001117{
Ezequiel Garcia82a14022013-10-30 12:01:43 -03001118 void __iomem *base = xordev->xor_high_base;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001119 u32 win_enable = 0;
1120 int i;
1121
1122 for (i = 0; i < 8; i++) {
1123 writel(0, base + WINDOW_BASE(i));
1124 writel(0, base + WINDOW_SIZE(i));
1125 if (i < 4)
1126 writel(0, base + WINDOW_REMAP_HIGH(i));
1127 }
1128
1129 for (i = 0; i < dram->num_cs; i++) {
Andrew Lunn63a93322011-12-07 21:48:07 +01001130 const struct mbus_dram_window *cs = dram->cs + i;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001131
1132 writel((cs->base & 0xffff0000) |
1133 (cs->mbus_attr << 8) |
1134 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1135 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1136
1137 win_enable |= (1 << i);
1138 win_enable |= 3 << (16 + (2 * i));
1139 }
1140
1141 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1142 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
Thomas Petazzonic4b4b732012-11-22 18:16:37 +01001143 writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1144 writel(0, base + WINDOW_OVERRIDE_CTRL(1));
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001145}
1146
Linus Torvaldsc2714332012-12-14 14:54:26 -08001147static int mv_xor_probe(struct platform_device *pdev)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001148{
Andrew Lunn63a93322011-12-07 21:48:07 +01001149 const struct mbus_dram_target_info *dram;
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001150 struct mv_xor_device *xordev;
Jingoo Hand4adcc02013-07-30 17:09:11 +09001151 struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001152 struct resource *res;
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001153 int i, ret;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001154
Joe Perches1ba151c2012-10-28 01:05:44 -07001155 dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001156
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001157 xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1158 if (!xordev)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001159 return -ENOMEM;
1160
1161 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1162 if (!res)
1163 return -ENODEV;
1164
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001165 xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1166 resource_size(res));
1167 if (!xordev->xor_base)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001168 return -EBUSY;
1169
1170 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1171 if (!res)
1172 return -ENODEV;
1173
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001174 xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1175 resource_size(res));
1176 if (!xordev->xor_high_base)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001177 return -EBUSY;
1178
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001179 platform_set_drvdata(pdev, xordev);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001180
1181 /*
1182 * (Re-)program MBUS remapping windows if we are asked to.
1183 */
Andrew Lunn63a93322011-12-07 21:48:07 +01001184 dram = mv_mbus_dram_info();
1185 if (dram)
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001186 mv_xor_conf_mbus_windows(xordev, dram);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001187
Andrew Lunnc5101822012-02-19 13:30:26 +01001188 /* Not all platforms can gate the clock, so it is not
1189 * an error if the clock does not exists.
1190 */
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001191 xordev->clk = clk_get(&pdev->dev, NULL);
1192 if (!IS_ERR(xordev->clk))
1193 clk_prepare_enable(xordev->clk);
Andrew Lunnc5101822012-02-19 13:30:26 +01001194
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001195 if (pdev->dev.of_node) {
1196 struct device_node *np;
1197 int i = 0;
1198
1199 for_each_child_of_node(pdev->dev.of_node, np) {
Russell King0be82532013-12-12 23:59:08 +00001200 struct mv_xor_chan *chan;
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001201 dma_cap_mask_t cap_mask;
1202 int irq;
1203
1204 dma_cap_zero(cap_mask);
1205 if (of_property_read_bool(np, "dmacap,memcpy"))
1206 dma_cap_set(DMA_MEMCPY, cap_mask);
1207 if (of_property_read_bool(np, "dmacap,xor"))
1208 dma_cap_set(DMA_XOR, cap_mask);
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001209 if (of_property_read_bool(np, "dmacap,interrupt"))
1210 dma_cap_set(DMA_INTERRUPT, cap_mask);
1211
1212 irq = irq_of_parse_and_map(np, 0);
Thomas Petazzonif8eb9e72012-11-22 18:22:12 +01001213 if (!irq) {
1214 ret = -ENODEV;
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001215 goto err_channel_add;
1216 }
1217
Russell King0be82532013-12-12 23:59:08 +00001218 chan = mv_xor_channel_add(xordev, pdev, i,
1219 cap_mask, irq);
1220 if (IS_ERR(chan)) {
1221 ret = PTR_ERR(chan);
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001222 irq_dispose_mapping(irq);
1223 goto err_channel_add;
1224 }
1225
Russell King0be82532013-12-12 23:59:08 +00001226 xordev->channels[i] = chan;
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001227 i++;
1228 }
1229 } else if (pdata && pdata->channels) {
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001230 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
Thomas Petazzonie39f6ec2012-10-30 11:56:26 +01001231 struct mv_xor_channel_data *cd;
Russell King0be82532013-12-12 23:59:08 +00001232 struct mv_xor_chan *chan;
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001233 int irq;
1234
1235 cd = &pdata->channels[i];
1236 if (!cd) {
1237 ret = -ENODEV;
1238 goto err_channel_add;
1239 }
1240
1241 irq = platform_get_irq(pdev, i);
1242 if (irq < 0) {
1243 ret = irq;
1244 goto err_channel_add;
1245 }
1246
Russell King0be82532013-12-12 23:59:08 +00001247 chan = mv_xor_channel_add(xordev, pdev, i,
1248 cd->cap_mask, irq);
1249 if (IS_ERR(chan)) {
1250 ret = PTR_ERR(chan);
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001251 goto err_channel_add;
1252 }
Russell King0be82532013-12-12 23:59:08 +00001253
1254 xordev->channels[i] = chan;
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001255 }
1256 }
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001257
1258 return 0;
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001259
1260err_channel_add:
1261 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001262 if (xordev->channels[i]) {
Thomas Petazzoniab6e4392013-01-06 11:10:43 +01001263 mv_xor_channel_remove(xordev->channels[i]);
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001264 if (pdev->dev.of_node)
1265 irq_dispose_mapping(xordev->channels[i]->irq);
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001266 }
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001267
Thomas Petazzonidab92062013-01-06 11:10:44 +01001268 if (!IS_ERR(xordev->clk)) {
1269 clk_disable_unprepare(xordev->clk);
1270 clk_put(xordev->clk);
1271 }
1272
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001273 return ret;
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001274}
1275
Linus Torvaldsc2714332012-12-14 14:54:26 -08001276static int mv_xor_remove(struct platform_device *pdev)
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001277{
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001278 struct mv_xor_device *xordev = platform_get_drvdata(pdev);
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001279 int i;
Andrew Lunnc5101822012-02-19 13:30:26 +01001280
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001281 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001282 if (xordev->channels[i])
1283 mv_xor_channel_remove(xordev->channels[i]);
Thomas Petazzoni60d151f2012-10-29 16:54:49 +01001284 }
Andrew Lunnc5101822012-02-19 13:30:26 +01001285
Thomas Petazzoni297eedb2012-11-15 15:29:53 +01001286 if (!IS_ERR(xordev->clk)) {
1287 clk_disable_unprepare(xordev->clk);
1288 clk_put(xordev->clk);
Andrew Lunnc5101822012-02-19 13:30:26 +01001289 }
1290
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001291 return 0;
1292}
1293
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001294#ifdef CONFIG_OF
Linus Torvaldsc2714332012-12-14 14:54:26 -08001295static struct of_device_id mv_xor_dt_ids[] = {
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001296 { .compatible = "marvell,orion-xor", },
1297 {},
1298};
1299MODULE_DEVICE_TABLE(of, mv_xor_dt_ids);
1300#endif
1301
Thomas Petazzoni61971652012-10-30 12:05:40 +01001302static struct platform_driver mv_xor_driver = {
1303 .probe = mv_xor_probe,
Linus Torvaldsc2714332012-12-14 14:54:26 -08001304 .remove = mv_xor_remove,
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001305 .driver = {
Thomas Petazzonif7d12ef2012-11-15 16:47:58 +01001306 .owner = THIS_MODULE,
1307 .name = MV_XOR_NAME,
1308 .of_match_table = of_match_ptr(mv_xor_dt_ids),
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001309 },
1310};
1311
1312
1313static int __init mv_xor_init(void)
1314{
Thomas Petazzoni61971652012-10-30 12:05:40 +01001315 return platform_driver_register(&mv_xor_driver);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001316}
1317module_init(mv_xor_init);
1318
1319/* it's currently unsafe to unload this module */
1320#if 0
1321static void __exit mv_xor_exit(void)
1322{
1323 platform_driver_unregister(&mv_xor_driver);
Saeed Bisharaff7b0472008-07-08 11:58:36 -07001324 return;
1325}
1326
1327module_exit(mv_xor_exit);
1328#endif
1329
1330MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1331MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1332MODULE_LICENSE("GPL");