blob: 0f5a0aa3b871d3c725edc489a03e97d838b3d6a9 [file] [log] [blame]
David Brownellfdb3c182007-02-12 00:52:37 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * MicroWire interface driver for OMAP
David Brownellfdb3c182007-02-12 00:52:37 -08003 *
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
5 *
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
8 *
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
10 *
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
13 *
14 * Many updates by Imre Deak <imre.deak@nokia.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/platform_device.h>
David Brownellfdb3c182007-02-12 00:52:37 -080040#include <linux/interrupt.h>
41#include <linux/err.h>
42#include <linux/clk.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090043#include <linux/slab.h>
David Brownellfdb3c182007-02-12 00:52:37 -080044
45#include <linux/spi/spi.h>
46#include <linux/spi/spi_bitbang.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040047#include <linux/module.h>
David Brownellfdb3c182007-02-12 00:52:37 -080048
David Brownellfdb3c182007-02-12 00:52:37 -080049#include <asm/irq.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010050#include <mach/hardware.h>
David Brownellfdb3c182007-02-12 00:52:37 -080051#include <asm/io.h>
52#include <asm/mach-types.h>
53
Tony Lindgren70c494c2012-09-19 10:46:56 -070054#include <mach/mux.h>
Tony Lindgren68cb7002012-08-31 17:04:35 -070055
56#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
David Brownellfdb3c182007-02-12 00:52:37 -080057
58
59/* FIXME address is now a platform device resource,
60 * and irqs should show there too...
61 */
62#define UWIRE_BASE_PHYS 0xFFFB3000
David Brownellfdb3c182007-02-12 00:52:37 -080063
64/* uWire Registers: */
65#define UWIRE_IO_SIZE 0x20
66#define UWIRE_TDR 0x00
67#define UWIRE_RDR 0x00
68#define UWIRE_CSR 0x01
69#define UWIRE_SR1 0x02
70#define UWIRE_SR2 0x03
71#define UWIRE_SR3 0x04
72#define UWIRE_SR4 0x05
73#define UWIRE_SR5 0x06
74
75/* CSR bits */
76#define RDRB (1 << 15)
77#define CSRB (1 << 14)
78#define START (1 << 13)
79#define CS_CMD (1 << 12)
80
81/* SR1 or SR2 bits */
82#define UWIRE_READ_FALLING_EDGE 0x0001
83#define UWIRE_READ_RISING_EDGE 0x0000
84#define UWIRE_WRITE_FALLING_EDGE 0x0000
85#define UWIRE_WRITE_RISING_EDGE 0x0002
86#define UWIRE_CS_ACTIVE_LOW 0x0000
87#define UWIRE_CS_ACTIVE_HIGH 0x0004
88#define UWIRE_FREQ_DIV_2 0x0000
89#define UWIRE_FREQ_DIV_4 0x0008
90#define UWIRE_FREQ_DIV_8 0x0010
91#define UWIRE_CHK_READY 0x0020
92#define UWIRE_CLK_INVERTED 0x0040
93
94
95struct uwire_spi {
96 struct spi_bitbang bitbang;
97 struct clk *ck;
98};
99
100struct uwire_state {
David Brownellfdb3c182007-02-12 00:52:37 -0800101 unsigned div1_idx;
102};
103
104/* REVISIT compile time constant for idx_shift? */
Russell King55c381e2008-09-04 14:07:22 +0100105/*
106 * Or, put it in a structure which is used throughout the driver;
107 * that avoids having to issue two loads for each bit of static data.
108 */
David Brownellfdb3c182007-02-12 00:52:37 -0800109static unsigned int uwire_idx_shift;
Russell King55c381e2008-09-04 14:07:22 +0100110static void __iomem *uwire_base;
David Brownellfdb3c182007-02-12 00:52:37 -0800111
112static inline void uwire_write_reg(int idx, u16 val)
113{
Russell King55c381e2008-09-04 14:07:22 +0100114 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
David Brownellfdb3c182007-02-12 00:52:37 -0800115}
116
117static inline u16 uwire_read_reg(int idx)
118{
Russell King55c381e2008-09-04 14:07:22 +0100119 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
David Brownellfdb3c182007-02-12 00:52:37 -0800120}
121
122static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
123{
124 u16 w, val = 0;
125 int shift, reg;
126
127 if (flags & UWIRE_CLK_INVERTED)
128 val ^= 0x03;
129 val = flags & 0x3f;
130 if (cs & 1)
131 shift = 6;
132 else
133 shift = 0;
134 if (cs <= 1)
135 reg = UWIRE_SR1;
136 else
137 reg = UWIRE_SR2;
138
139 w = uwire_read_reg(reg);
140 w &= ~(0x3f << shift);
141 w |= val << shift;
142 uwire_write_reg(reg, w);
143}
144
145static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
146{
147 u16 w;
148 int c = 0;
149 unsigned long max_jiffies = jiffies + HZ;
150
151 for (;;) {
152 w = uwire_read_reg(UWIRE_CSR);
153 if ((w & mask) == val)
154 break;
155 if (time_after(jiffies, max_jiffies)) {
156 printk(KERN_ERR "%s: timeout. reg=%#06x "
157 "mask=%#06x val=%#06x\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700158 __func__, w, mask, val);
David Brownellfdb3c182007-02-12 00:52:37 -0800159 return -1;
160 }
161 c++;
162 if (might_not_catch && c > 64)
163 break;
164 }
165 return 0;
166}
167
168static void uwire_set_clk1_div(int div1_idx)
169{
170 u16 w;
171
172 w = uwire_read_reg(UWIRE_SR3);
173 w &= ~(0x03 << 1);
174 w |= div1_idx << 1;
175 uwire_write_reg(UWIRE_SR3, w);
176}
177
178static void uwire_chipselect(struct spi_device *spi, int value)
179{
180 struct uwire_state *ust = spi->controller_state;
181 u16 w;
182 int old_cs;
183
184
185 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
186
187 w = uwire_read_reg(UWIRE_CSR);
188 old_cs = (w >> 10) & 0x03;
189 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
190 /* Deselect this CS, or the previous CS */
191 w &= ~CS_CMD;
192 uwire_write_reg(UWIRE_CSR, w);
193 }
194 /* activate specfied chipselect */
195 if (value == BITBANG_CS_ACTIVE) {
196 uwire_set_clk1_div(ust->div1_idx);
197 /* invert clock? */
198 if (spi->mode & SPI_CPOL)
199 uwire_write_reg(UWIRE_SR4, 1);
200 else
201 uwire_write_reg(UWIRE_SR4, 0);
202
203 w = spi->chip_select << 10;
204 w |= CS_CMD;
205 uwire_write_reg(UWIRE_CSR, w);
206 }
207}
208
209static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
210{
David Brownellfdb3c182007-02-12 00:52:37 -0800211 unsigned len = t->len;
Axel Lin790fc552014-02-15 14:26:21 +0800212 unsigned bits = t->bits_per_word ? : spi->bits_per_word;
David Brownellfdb3c182007-02-12 00:52:37 -0800213 unsigned bytes;
214 u16 val, w;
Joe Perchesa419aef2009-08-18 11:18:35 -0700215 int status = 0;
David Brownellfdb3c182007-02-12 00:52:37 -0800216
217 if (!t->tx_buf && !t->rx_buf)
218 return 0;
219
David Brownellfdb3c182007-02-12 00:52:37 -0800220 w = spi->chip_select << 10;
221 w |= CS_CMD;
222
223 if (t->tx_buf) {
224 const u8 *buf = t->tx_buf;
225
226 /* NOTE: DMA could be used for TX transfers */
227
228 /* write one or two bytes at a time */
229 while (len >= 1) {
230 /* tx bit 15 is first sent; we byteswap multibyte words
231 * (msb-first) on the way out from memory.
232 */
233 val = *buf++;
234 if (bits > 8) {
235 bytes = 2;
236 val |= *buf++ << 8;
237 } else
238 bytes = 1;
239 val <<= 16 - bits;
240
241#ifdef VERBOSE
242 pr_debug("%s: write-%d =%04x\n",
Kay Sievers6c7377a2009-03-24 16:38:21 -0700243 dev_name(&spi->dev), bits, val);
David Brownellfdb3c182007-02-12 00:52:37 -0800244#endif
245 if (wait_uwire_csr_flag(CSRB, 0, 0))
246 goto eio;
247
248 uwire_write_reg(UWIRE_TDR, val);
249
250 /* start write */
251 val = START | w | (bits << 5);
252
253 uwire_write_reg(UWIRE_CSR, val);
254 len -= bytes;
255
256 /* Wait till write actually starts.
257 * This is needed with MPU clock 60+ MHz.
258 * REVISIT: we may not have time to catch it...
259 */
260 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
261 goto eio;
262
263 status += bytes;
264 }
265
266 /* REVISIT: save this for later to get more i/o overlap */
267 if (wait_uwire_csr_flag(CSRB, 0, 0))
268 goto eio;
269
270 } else if (t->rx_buf) {
271 u8 *buf = t->rx_buf;
272
273 /* read one or two bytes at a time */
274 while (len) {
275 if (bits > 8) {
276 bytes = 2;
277 } else
278 bytes = 1;
279
280 /* start read */
281 val = START | w | (bits << 0);
282 uwire_write_reg(UWIRE_CSR, val);
283 len -= bytes;
284
285 /* Wait till read actually starts */
286 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
287
288 if (wait_uwire_csr_flag(RDRB | CSRB,
289 RDRB, 0))
290 goto eio;
291
292 /* rx bit 0 is last received; multibyte words will
293 * be properly byteswapped on the way to memory.
294 */
295 val = uwire_read_reg(UWIRE_RDR);
296 val &= (1 << bits) - 1;
297 *buf++ = (u8) val;
298 if (bytes == 2)
299 *buf++ = val >> 8;
300 status += bytes;
301#ifdef VERBOSE
302 pr_debug("%s: read-%d =%04x\n",
Kay Sievers6c7377a2009-03-24 16:38:21 -0700303 dev_name(&spi->dev), bits, val);
David Brownellfdb3c182007-02-12 00:52:37 -0800304#endif
305
306 }
307 }
308 return status;
309eio:
310 return -EIO;
311}
312
313static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
314{
315 struct uwire_state *ust = spi->controller_state;
316 struct uwire_spi *uwire;
317 unsigned flags = 0;
David Brownellfdb3c182007-02-12 00:52:37 -0800318 unsigned hz;
319 unsigned long rate;
320 int div1_idx;
321 int div1;
322 int div2;
323 int status;
324
325 uwire = spi_master_get_devdata(spi->master);
326
David Brownellfdb3c182007-02-12 00:52:37 -0800327 /* mode 0..3, clock inverted separately;
328 * standard nCS signaling;
329 * don't treat DI=high as "not ready"
330 */
331 if (spi->mode & SPI_CS_HIGH)
332 flags |= UWIRE_CS_ACTIVE_HIGH;
333
334 if (spi->mode & SPI_CPOL)
335 flags |= UWIRE_CLK_INVERTED;
336
337 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
338 case SPI_MODE_0:
339 case SPI_MODE_3:
Imre Deake5f1b192007-05-23 13:58:20 -0700340 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
David Brownellfdb3c182007-02-12 00:52:37 -0800341 break;
342 case SPI_MODE_1:
343 case SPI_MODE_2:
Imre Deake5f1b192007-05-23 13:58:20 -0700344 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
David Brownellfdb3c182007-02-12 00:52:37 -0800345 break;
346 }
347
348 /* assume it's already enabled */
349 rate = clk_get_rate(uwire->ck);
350
351 hz = spi->max_speed_hz;
352 if (t != NULL && t->speed_hz)
353 hz = t->speed_hz;
354
355 if (!hz) {
Kay Sievers6c7377a2009-03-24 16:38:21 -0700356 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
David Brownellfdb3c182007-02-12 00:52:37 -0800357 status = -EINVAL;
358 goto done;
359 }
360
361 /* F_INT = mpu_xor_clk / DIV1 */
362 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
363 switch (div1_idx) {
364 case 0:
365 div1 = 2;
366 break;
367 case 1:
368 div1 = 4;
369 break;
370 case 2:
371 div1 = 7;
372 break;
373 default:
374 case 3:
375 div1 = 10;
376 break;
377 }
378 div2 = (rate / div1 + hz - 1) / hz;
379 if (div2 <= 8)
380 break;
381 }
382 if (div1_idx == 4) {
383 pr_debug("%s: lowest clock %ld, need %d\n",
Kay Sievers6c7377a2009-03-24 16:38:21 -0700384 dev_name(&spi->dev), rate / 10 / 8, hz);
David Brownellfdb3c182007-02-12 00:52:37 -0800385 status = -EDOM;
386 goto done;
387 }
388
389 /* we have to cache this and reset in uwire_chipselect as this is a
390 * global parameter and another uwire device can change it under
391 * us */
392 ust->div1_idx = div1_idx;
393 uwire_set_clk1_div(div1_idx);
394
395 rate /= div1;
396
397 switch (div2) {
398 case 0:
399 case 1:
400 case 2:
401 flags |= UWIRE_FREQ_DIV_2;
402 rate /= 2;
403 break;
404 case 3:
405 case 4:
406 flags |= UWIRE_FREQ_DIV_4;
407 rate /= 4;
408 break;
409 case 5:
410 case 6:
411 case 7:
412 case 8:
413 flags |= UWIRE_FREQ_DIV_8;
414 rate /= 8;
415 break;
416 }
417 omap_uwire_configure_mode(spi->chip_select, flags);
418 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700419 __func__, flags,
David Brownellfdb3c182007-02-12 00:52:37 -0800420 clk_get_rate(uwire->ck) / 1000,
421 rate / 1000);
422 status = 0;
423done:
424 return status;
425}
426
427static int uwire_setup(struct spi_device *spi)
428{
429 struct uwire_state *ust = spi->controller_state;
430
431 if (ust == NULL) {
432 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
433 if (ust == NULL)
434 return -ENOMEM;
435 spi->controller_state = ust;
436 }
437
438 return uwire_setup_transfer(spi, NULL);
439}
440
David Brownellbb2d1c32007-02-20 13:58:19 -0800441static void uwire_cleanup(struct spi_device *spi)
David Brownellfdb3c182007-02-12 00:52:37 -0800442{
443 kfree(spi->controller_state);
444}
445
446static void uwire_off(struct uwire_spi *uwire)
447{
448 uwire_write_reg(UWIRE_SR3, 0);
449 clk_disable(uwire->ck);
450 clk_put(uwire->ck);
451 spi_master_put(uwire->bitbang.master);
452}
453
Grant Likely2deff8d2013-02-05 13:27:35 +0000454static int uwire_probe(struct platform_device *pdev)
David Brownellfdb3c182007-02-12 00:52:37 -0800455{
456 struct spi_master *master;
457 struct uwire_spi *uwire;
458 int status;
459
460 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
461 if (!master)
462 return -ENODEV;
463
464 uwire = spi_master_get_devdata(master);
Russell King55c381e2008-09-04 14:07:22 +0100465
466 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
467 if (!uwire_base) {
468 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
469 spi_master_put(master);
470 return -ENOMEM;
471 }
472
Jingoo Han24b5a822013-05-23 19:20:40 +0900473 platform_set_drvdata(pdev, uwire);
David Brownellfdb3c182007-02-12 00:52:37 -0800474
Russell Kingb1ad3792009-01-22 19:41:20 +0000475 uwire->ck = clk_get(&pdev->dev, "fck");
476 if (IS_ERR(uwire->ck)) {
477 status = PTR_ERR(uwire->ck);
478 dev_dbg(&pdev->dev, "no functional clock?\n");
David Brownellfdb3c182007-02-12 00:52:37 -0800479 spi_master_put(master);
Nishanth Menoncbab8042014-03-27 11:07:59 -0500480 iounmap(uwire_base);
Russell Kingb1ad3792009-01-22 19:41:20 +0000481 return status;
David Brownellfdb3c182007-02-12 00:52:37 -0800482 }
483 clk_enable(uwire->ck);
484
Alistair Buxton7a8f48f2009-09-22 10:04:51 +0100485 if (cpu_is_omap7xx())
David Brownellfdb3c182007-02-12 00:52:37 -0800486 uwire_idx_shift = 1;
487 else
488 uwire_idx_shift = 2;
489
490 uwire_write_reg(UWIRE_SR3, 1);
491
David Brownelle7db06b2009-06-17 16:26:04 -0700492 /* the spi->mode bits understood by this driver: */
493 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Axel Lin790fc552014-02-15 14:26:21 +0800494 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
David Brownell70d60272009-06-30 11:41:27 -0700495 master->flags = SPI_MASTER_HALF_DUPLEX;
496
David Brownellfdb3c182007-02-12 00:52:37 -0800497 master->bus_num = 2; /* "official" */
498 master->num_chipselect = 4;
499 master->setup = uwire_setup;
500 master->cleanup = uwire_cleanup;
501
502 uwire->bitbang.master = master;
503 uwire->bitbang.chipselect = uwire_chipselect;
504 uwire->bitbang.setup_transfer = uwire_setup_transfer;
505 uwire->bitbang.txrx_bufs = uwire_txrx;
506
507 status = spi_bitbang_start(&uwire->bitbang);
Russell King55c381e2008-09-04 14:07:22 +0100508 if (status < 0) {
David Brownellfdb3c182007-02-12 00:52:37 -0800509 uwire_off(uwire);
Russell King55c381e2008-09-04 14:07:22 +0100510 iounmap(uwire_base);
511 }
David Brownellfdb3c182007-02-12 00:52:37 -0800512 return status;
513}
514
Grant Likely2deff8d2013-02-05 13:27:35 +0000515static int uwire_remove(struct platform_device *pdev)
David Brownellfdb3c182007-02-12 00:52:37 -0800516{
Jingoo Han24b5a822013-05-23 19:20:40 +0900517 struct uwire_spi *uwire = platform_get_drvdata(pdev);
David Brownellfdb3c182007-02-12 00:52:37 -0800518
519 // FIXME remove all child devices, somewhere ...
520
Axel Lind9721ae2014-03-29 18:50:12 +0800521 spi_bitbang_stop(&uwire->bitbang);
David Brownellfdb3c182007-02-12 00:52:37 -0800522 uwire_off(uwire);
Russell King55c381e2008-09-04 14:07:22 +0100523 iounmap(uwire_base);
Axel Lind9721ae2014-03-29 18:50:12 +0800524 return 0;
David Brownellfdb3c182007-02-12 00:52:37 -0800525}
526
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700527/* work with hotplug and coldplug */
528MODULE_ALIAS("platform:omap_uwire");
529
David Brownellfdb3c182007-02-12 00:52:37 -0800530static struct platform_driver uwire_driver = {
531 .driver = {
532 .name = "omap_uwire",
David Brownellfdb3c182007-02-12 00:52:37 -0800533 .owner = THIS_MODULE,
534 },
Wolfram Sang93e9c902013-10-08 22:35:39 +0200535 .probe = uwire_probe,
536 .remove = uwire_remove,
David Brownellfdb3c182007-02-12 00:52:37 -0800537 // suspend ... unuse ck
538 // resume ... use ck
539};
540
541static int __init omap_uwire_init(void)
542{
543 /* FIXME move these into the relevant board init code. also, include
544 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
545 */
546
547 if (machine_is_omap_h2()) {
548 /* defaults: W21 SDO, U18 SDI, V19 SCL */
549 omap_cfg_reg(N14_1610_UWIRE_CS0);
550 omap_cfg_reg(N15_1610_UWIRE_CS1);
551 }
552 if (machine_is_omap_perseus2()) {
553 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
Alistair Buxton7a8f48f2009-09-22 10:04:51 +0100554 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
555 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
David Brownellfdb3c182007-02-12 00:52:37 -0800556 }
557
Wolfram Sang93e9c902013-10-08 22:35:39 +0200558 return platform_driver_register(&uwire_driver);
David Brownellfdb3c182007-02-12 00:52:37 -0800559}
560
561static void __exit omap_uwire_exit(void)
562{
563 platform_driver_unregister(&uwire_driver);
564}
565
566subsys_initcall(omap_uwire_init);
567module_exit(omap_uwire_exit);
568
569MODULE_LICENSE("GPL");
570