| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
| Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 7 | depends on (PCI && X86) || ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX || PPC |
| Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 8 | depends on !HIGHMEM64G |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 9 | help |
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 10 | DMA engines can do asynchronous data transfers without |
| 11 | involving the host CPU. Currently, this framework can be |
| 12 | used to offload memory copies in the network stack and |
| 13 | RAID operations in the MD driver. |
| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 14 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 15 | if DMADEVICES |
| Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 16 | |
| Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 17 | comment "DMA Devices" |
| 18 | |
| 19 | config INTEL_IOATDMA |
| 20 | tristate "Intel I/OAT DMA support" |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 21 | depends on PCI && X86 |
| 22 | select DMA_ENGINE |
| 23 | select DCA |
| 24 | help |
| 25 | Enable support for the Intel(R) I/OAT DMA engine present |
| 26 | in recent Intel Xeon chipsets. |
| 27 | |
| 28 | Say Y here if you have such a chipset. |
| 29 | |
| 30 | If unsure, say N. |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 31 | |
| 32 | config INTEL_IOP_ADMA |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 33 | tristate "Intel IOP ADMA support" |
| 34 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 35 | select ASYNC_CORE |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 36 | select DMA_ENGINE |
| 37 | help |
| 38 | Enable support for the Intel(R) IOP Series RAID engines. |
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 39 | |
| Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 40 | config FSL_DMA |
| 41 | bool "Freescale MPC85xx/MPC83xx DMA support" |
| 42 | depends on PPC |
| 43 | select DMA_ENGINE |
| 44 | ---help--- |
| 45 | Enable support for the Freescale DMA engine. Now, it support |
| 46 | MPC8560/40, MPC8555, MPC8548 and MPC8641 processors. |
| 47 | The MPC8349, MPC8360 is also supported. |
| 48 | |
| 49 | config FSL_DMA_SELFTEST |
| 50 | bool "Enable the self test for each DMA channel" |
| 51 | depends on FSL_DMA |
| 52 | default y |
| 53 | ---help--- |
| 54 | Enable the self test for each DMA channel. A self test will be |
| 55 | performed after the channel probed to ensure the DMA works well. |
| 56 | |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 57 | config DMA_ENGINE |
| 58 | bool |
| 59 | |
| 60 | comment "DMA Clients" |
| 61 | depends on DMA_ENGINE |
| 62 | |
| 63 | config NET_DMA |
| 64 | bool "Network: TCP receive copy offload" |
| 65 | depends on DMA_ENGINE && NET |
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 66 | help |
| 67 | This enables the use of DMA engines in the network stack to |
| 68 | offload receive copy-to-user operations, freeing CPU cycles. |
| 69 | Since this is the main user of the DMA engine, it should be enabled; |
| 70 | say Y here. |
| 71 | |
| 72 | endif |