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Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Jon Hunter9c8eddd2016-06-07 16:12:34 +010011config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
Linus Walleija27d21e2015-12-18 10:44:53 +010017config ARM_GIC_MAX_NR
18 int
19 default 2 if ARCH_REALVIEW
20 default 1
21
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000022config ARM_GIC_V2M
23 bool
24 depends on ARM_GIC
25 depends on PCI && PCI_MSI
26 select PCI_MSI_IRQ_DOMAIN
27
Rob Herring81243e42012-11-20 21:21:40 -060028config GIC_NON_BANKED
29 bool
30
Marc Zyngier021f6532014-06-30 16:01:31 +010031config ARM_GIC_V3
32 bool
33 select IRQ_DOMAIN
34 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000035 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010036 select PARTITION_PERCPU
Marc Zyngier021f6532014-06-30 16:01:31 +010037
Marc Zyngier19812722014-11-24 14:35:19 +000038config ARM_GIC_V3_ITS
39 bool
40 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020041
Rob Herring44430ec2012-10-27 17:25:26 -050042config ARM_NVIC
43 bool
44 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020045 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050046 select GENERIC_IRQ_CHIP
47
48config ARM_VIC
49 bool
50 select IRQ_DOMAIN
51 select MULTI_IRQ_HANDLER
52
53config ARM_VIC_NR
54 int
55 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050056 default 2
57 depends on ARM_VIC
58 help
59 The maximum number of VICs available in the system, for
60 power management.
61
Thomas Petazzonifed6d332016-02-10 15:46:56 +010062config ARMADA_370_XP_IRQ
63 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010064 select GENERIC_IRQ_CHIP
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010065 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010066
Antoine Tenarte6b78f22016-02-19 16:22:44 +010067config ALPINE_MSI
68 bool
69 depends on PCI && PCI_MSI
70 select GENERIC_IRQ_CHIP
71 select PCI_MSI_IRQ_DOMAIN
72
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020073config ATMEL_AIC_IRQ
74 bool
75 select GENERIC_IRQ_CHIP
76 select IRQ_DOMAIN
77 select MULTI_IRQ_HANDLER
78 select SPARSE_IRQ
79
80config ATMEL_AIC5_IRQ
81 bool
82 select GENERIC_IRQ_CHIP
83 select IRQ_DOMAIN
84 select MULTI_IRQ_HANDLER
85 select SPARSE_IRQ
86
Ralf Baechle0509cfd2015-07-08 14:46:08 +020087config I8259
88 bool
89 select IRQ_DOMAIN
90
Simon Arlottc7c42ec2015-11-22 14:30:14 +000091config BCM6345_L1_IRQ
92 bool
93 select GENERIC_IRQ_CHIP
94 select IRQ_DOMAIN
95
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080096config BCM7038_L1_IRQ
97 bool
98 select GENERIC_IRQ_CHIP
99 select IRQ_DOMAIN
100
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800101config BCM7120_L2_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
105
Florian Fainelli7f646e92014-05-23 17:40:53 -0700106config BRCMSTB_L2_IRQ
107 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700108 select GENERIC_IRQ_CHIP
109 select IRQ_DOMAIN
110
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200111config DW_APB_ICTL
112 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800113 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200114 select IRQ_DOMAIN
115
MaJun9a7c4ab2016-03-23 17:06:33 +0800116config HISILICON_IRQ_MBIGEN
117 bool
118 select ARM_GIC_V3
119 select ARM_GIC_V3_ITS
120 select GENERIC_MSI_IRQ_DOMAIN
121
James Hoganb6ef9162013-04-22 15:43:50 +0100122config IMGPDC_IRQ
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200127config IRQ_MIPS_CPU
128 bool
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400132config CLPS711X_IRQCHIP
133 bool
134 depends on ARCH_CLPS711X
135 select IRQ_DOMAIN
136 select MULTI_IRQ_HANDLER
137 select SPARSE_IRQ
138 default y
139
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300140config OR1K_PIC
141 bool
142 select IRQ_DOMAIN
143
Felipe Balbi85980662014-09-15 16:15:02 -0500144config OMAP_IRQCHIP
145 bool
146 select GENERIC_IRQ_CHIP
147 select IRQ_DOMAIN
148
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200149config ORION_IRQCHIP
150 bool
151 select IRQ_DOMAIN
152 select MULTI_IRQ_HANDLER
153
Cristian Birsanaaa86662016-01-13 18:15:35 -0700154config PIC32_EVIC
155 bool
156 select GENERIC_IRQ_CHIP
157 select IRQ_DOMAIN
158
Magnus Damm44358042013-02-18 23:28:34 +0900159config RENESAS_INTC_IRQPIN
160 bool
161 select IRQ_DOMAIN
162
Magnus Dammfbc83b72013-02-27 17:15:01 +0900163config RENESAS_IRQC
164 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900165 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900166 select IRQ_DOMAIN
167
Lee Jones07088482015-02-18 15:13:58 +0000168config ST_IRQCHIP
169 bool
170 select REGMAP
171 select MFD_SYSCON
172 help
173 Enables SysCfg Controlled IRQs on STi based platforms.
174
Mans Rullgard4bba6682016-01-20 18:07:17 +0000175config TANGO_IRQ
176 bool
177 select IRQ_DOMAIN
178 select GENERIC_IRQ_CHIP
179
Christian Ruppertb06eb012013-06-25 18:29:57 +0200180config TB10X_IRQC
181 bool
182 select IRQ_DOMAIN
183 select GENERIC_IRQ_CHIP
184
Damien Riegeld01f8632015-12-21 15:11:23 -0500185config TS4800_IRQ
186 tristate "TS-4800 IRQ controller"
187 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100188 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100189 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500190 help
191 Support for the TS-4800 FPGA IRQ controller
192
Linus Walleij2389d502012-10-31 22:04:31 +0100193config VERSATILE_FPGA_IRQ
194 bool
195 select IRQ_DOMAIN
196
197config VERSATILE_FPGA_IRQ_NR
198 int
199 default 4
200 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400201
202config XTENSA_MX
203 bool
204 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530205
206config IRQ_CROSSBAR
207 bool
208 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900209 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530210 The primary irqchip invokes the crossbar's callback which inturn allocates
211 a free irq and configures the IP. Thus the peripheral interrupts are
212 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300213
214config KEYSTONE_IRQ
215 tristate "Keystone 2 IRQ controller IP"
216 depends on ARCH_KEYSTONE
217 help
218 Support for Texas Instruments Keystone 2 IRQ controller IP which
219 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700220
221config MIPS_GIC
222 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000223 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000224 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700225 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900226
Paul Burton44e08e72015-05-24 16:11:31 +0100227config INGENIC_IRQ
228 bool
229 depends on MACH_INGENIC
230 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700231
Yoshinori Sato8a764482015-05-10 02:30:47 +0900232config RENESAS_H8300H_INTC
233 bool
234 select IRQ_DOMAIN
235
236config RENESAS_H8S_INTC
237 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700238 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500239
240config IMX_GPCV2
241 bool
242 select IRQ_DOMAIN
243 help
244 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200245
246config IRQ_MXS
247 def_bool y if MACH_ASM9260 || ARCH_MXS
248 select IRQ_DOMAIN
249 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100250
251config MVEBU_ODMI
252 bool
253 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100254
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800255config LS_SCFG_MSI
256 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
257 depends on PCI && PCI_MSI
258 select PCI_MSI_IRQ_DOMAIN
259
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100260config PARTITION_PERCPU
261 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700262
Noam Camus44df427c2015-10-29 00:26:22 +0200263config EZNPS_GIC
264 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200265 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200266 select IRQ_DOMAIN
267 help
268 Support the EZchip NPS400 global interrupt controller