blob: b643991531359e6a4ed4eb842561f1ffaa11ceba [file] [log] [blame]
Andrew Vasquezfa90c542005-10-27 11:10:08 -07001/*
2 * QLogic Fibre Channel HBA Driver
Armen Baloyanbd21eaf2014-04-11 16:54:24 -04003 * Copyright (c) 2003-2014 QLogic Corporation
Andrew Vasquezfa90c542005-10-27 11:10:08 -07004 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
Andrew Vasquezabbd8872005-07-06 10:30:05 -070023#include <linux/interrupt.h>
James.Smart@Emulex.Com19a7b4a2005-10-18 12:03:35 -040024#include <linux/workqueue.h>
Andrew Vasquez54333832005-11-09 15:49:04 -080025#include <linux/firmware.h>
Seokmann Ju14e660e2007-09-20 14:07:36 -070026#include <linux/aer.h>
Harihara Kadayam4d4df192008-04-03 13:13:26 -070027#include <linux/mutex.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -080033#include <scsi/scsi_transport_fc.h>
Giridhar Malavali9a069e12010-01-12 13:02:47 -080034#include <scsi/scsi_bsg_fc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Giridhar Malavali6e980162010-03-19 17:03:58 -070036#include "qla_bsg.h"
Giridhar Malavalia9083012010-04-12 17:59:55 -070037#include "qla_nx.h"
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -040038#include "qla_nx2.h"
Harish Zunjarrao6a03b4c2010-05-04 15:01:24 -070039#define QLA2XXX_DRIVER_NAME "qla2xxx"
40#define QLA2XXX_APIDEV "ql2xapidev"
Paul Bollef24b6972013-02-08 01:57:55 -050041#define QLA2XXX_MANUFACTURER "QLogic Corporation"
Andrew Vasquezcb630672006-05-17 15:09:45 -070042
Linus Torvalds1da177e2005-04-16 15:20:36 -070043/*
44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
45 * but that's fine as we don't look at the last 24 ones for
46 * ISP2100 HBAs.
47 */
48#define MAILBOX_REGISTER_COUNT_2100 8
Andrew Vasquez67ddda32012-02-09 11:14:08 -080049#define MAILBOX_REGISTER_COUNT_2200 24
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#define MAILBOX_REGISTER_COUNT 32
51
52#define QLA2200A_RISC_ROM_VER 4
53#define FPM_2300 6
54#define FPM_2310 7
55
56#include "qla_settings.h"
57
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -070058/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 * Data bit definitions
60 */
61#define BIT_0 0x1
62#define BIT_1 0x2
63#define BIT_2 0x4
64#define BIT_3 0x8
65#define BIT_4 0x10
66#define BIT_5 0x20
67#define BIT_6 0x40
68#define BIT_7 0x80
69#define BIT_8 0x100
70#define BIT_9 0x200
71#define BIT_10 0x400
72#define BIT_11 0x800
73#define BIT_12 0x1000
74#define BIT_13 0x2000
75#define BIT_14 0x4000
76#define BIT_15 0x8000
77#define BIT_16 0x10000
78#define BIT_17 0x20000
79#define BIT_18 0x40000
80#define BIT_19 0x80000
81#define BIT_20 0x100000
82#define BIT_21 0x200000
83#define BIT_22 0x400000
84#define BIT_23 0x800000
85#define BIT_24 0x1000000
86#define BIT_25 0x2000000
87#define BIT_26 0x4000000
88#define BIT_27 0x8000000
89#define BIT_28 0x10000000
90#define BIT_29 0x20000000
91#define BIT_30 0x40000000
92#define BIT_31 0x80000000
93
94#define LSB(x) ((uint8_t)(x))
95#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
96
97#define LSW(x) ((uint16_t)(x))
98#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
99
100#define LSD(x) ((uint32_t)((uint64_t)(x)))
101#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
102
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -0700103#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105/*
106 * I/O register
107*/
108
109#define RD_REG_BYTE(addr) readb(addr)
110#define RD_REG_WORD(addr) readw(addr)
111#define RD_REG_DWORD(addr) readl(addr)
112#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
113#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
114#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
115#define WRT_REG_BYTE(addr, data) writeb(data,addr)
116#define WRT_REG_WORD(addr, data) writew(data,addr)
117#define WRT_REG_DWORD(addr, data) writel(data,addr)
118
119/*
Santosh Vernekar7d613ac2012-08-22 14:21:03 -0400120 * ISP83XX specific remote register addresses
121 */
122#define QLA83XX_LED_PORT0 0x00201320
123#define QLA83XX_LED_PORT1 0x00201328
124#define QLA83XX_IDC_DEV_STATE 0x22102384
125#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
126#define QLA83XX_IDC_MINOR_VERSION 0x22102398
127#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
128#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
129#define QLA83XX_IDC_CONTROL 0x22102390
130#define QLA83XX_IDC_AUDIT 0x22102394
131#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
132#define QLA83XX_DRIVER_LOCKID 0x22102104
133#define QLA83XX_DRIVER_LOCK 0x8111c028
134#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
135#define QLA83XX_FLASH_LOCKID 0x22102100
136#define QLA83XX_FLASH_LOCK 0x8111c010
137#define QLA83XX_FLASH_UNLOCK 0x8111c014
138#define QLA83XX_DEV_PARTINFO1 0x221023e0
139#define QLA83XX_DEV_PARTINFO2 0x221023e4
140#define QLA83XX_FW_HEARTBEAT 0x221020b0
141#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
142#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
143
144/* 83XX: Macros defining 8200 AEN Reason codes */
145#define IDC_DEVICE_STATE_CHANGE BIT_0
146#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
147#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
148#define IDC_HEARTBEAT_FAILURE BIT_3
149
150/* 83XX: Macros defining 8200 AEN Error-levels */
151#define ERR_LEVEL_NON_FATAL 0x1
152#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
153#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
154
155/* 83XX: Macros for IDC Version */
156#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
157#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
158
159/* 83XX: Macros for scheduling dpc tasks */
160#define QLA83XX_NIC_CORE_RESET 0x1
161#define QLA83XX_IDC_STATE_HANDLER 0x2
162#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
163
164/* 83XX: Macros for defining IDC-Control bits */
165#define QLA83XX_IDC_RESET_DISABLED BIT_0
166#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
167
168/* 83XX: Macros for different timeouts */
169#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
170#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
171#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
172
173/* 83XX: Macros for defining class in DEV-Partition Info register */
174#define QLA83XX_CLASS_TYPE_NONE 0x0
175#define QLA83XX_CLASS_TYPE_NIC 0x1
176#define QLA83XX_CLASS_TYPE_FCOE 0x2
177#define QLA83XX_CLASS_TYPE_ISCSI 0x3
178
179/* 83XX: Macros for IDC Lock-Recovery stages */
180#define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
181 * lock-recovery
182 */
183#define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
184
185/* 83XX: Macros for IDC Audit type */
186#define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
187 * dev-state change to NEED-RESET
188 * or NEED-QUIESCENT
189 */
190#define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
191 * reset-recovery completion is
192 * second
193 */
194
195/*
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800196 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
197 * 133Mhz slot.
198 */
199#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
200#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
201
202/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 * Fibre Channel device definitions.
204 */
205#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
Chad Dupuis642ef982012-02-09 11:15:57 -0800206#define MAX_FIBRE_DEVICES_2100 512
207#define MAX_FIBRE_DEVICES_2400 2048
208#define MAX_FIBRE_DEVICES_LOOP 128
209#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
Chad Dupuis5f16b332012-08-22 14:21:00 -0400210#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
Andrew Vasquezcc4731f2005-07-06 10:32:37 -0700211#define MAX_FIBRE_LUNS 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212#define MAX_HOST_COUNT 16
213
214/*
215 * Host adapter default definitions.
216 */
217#define MAX_BUSES 1 /* We only have one bus today */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218#define MIN_LUNS 8
219#define MAX_LUNS MAX_FIBRE_LUNS
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700220#define MAX_CMDS_PER_LUN 255
221
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222/*
223 * Fibre Channel device definitions.
224 */
225#define SNS_LAST_LOOP_ID_2100 0xfe
226#define SNS_LAST_LOOP_ID_2300 0x7ff
227
228#define LAST_LOCAL_LOOP_ID 0x7d
229#define SNS_FL_PORT 0x7e
230#define FABRIC_CONTROLLER 0x7f
231#define SIMPLE_NAME_SERVER 0x80
232#define SNS_FIRST_LOOP_ID 0x81
233#define MANAGEMENT_SERVER 0xfe
234#define BROADCAST 0xff
235
Andrew Vasquez3d716442005-07-06 10:30:26 -0700236/*
237 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
238 * valid range of an N-PORT id is 0 through 0x7ef.
239 */
240#define NPH_LAST_HANDLE 0x7ef
Andrew Vasquezcca53352005-08-26 19:08:30 -0700241#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700242#define NPH_SNS 0x7fc /* FFFFFC */
243#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
244#define NPH_F_PORT 0x7fe /* FFFFFE */
245#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
246
247#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
248#include "qla_fw.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249/*
250 * Timeout timer counts in seconds
251 */
8482e1182005-04-17 15:04:54 -0500252#define PORT_RETRY_TIME 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253#define LOOP_DOWN_TIMEOUT 60
254#define LOOP_DOWN_TIME 255 /* 240 */
255#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
256
Chad Dupuis8d93f552013-01-30 03:34:37 -0500257#define DEFAULT_OUTSTANDING_COMMANDS 1024
258#define MIN_OUTSTANDING_COMMANDS 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260/* ISP request and response entry counts (37-65535) */
261#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
262#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
Andrew Vasquezd743de62009-03-24 09:08:15 -0700263#define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
265#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -0700266#define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
Nicholas Bellinger2d70c102012-05-15 14:34:28 -0400267#define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400268#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Anirban Chakraborty17d98632008-12-18 10:06:15 -0800270struct req_que;
271
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272/*
Arun Easibad75002010-05-04 15:01:30 -0700273 * (sd.h is not exported, hence local inclusion)
274 * Data Integrity Field tuple.
275 */
276struct sd_dif_tuple {
277 __be16 guard_tag; /* Checksum */
278 __be16 app_tag; /* Opaque storage */
279 __be32 ref_tag; /* Target LBA or indirect LBA */
280};
281
282/*
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700283 * SCSI Request Block
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 */
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800285struct srb_cmd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 uint32_t request_sense_length;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400288 uint32_t fw_sense_length;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 uint8_t *request_sense_ptr;
Andrew Vasquezcf53b062009-08-20 11:06:04 -0700290 void *ctx;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800291};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
293/*
294 * SRB flag definitions
295 */
Arun Easibad75002010-05-04 15:01:30 -0700296#define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
297#define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
298#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
299#define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
300#define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
301
302/* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
303#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305/*
Andrew Vasquezac280b62009-08-20 11:06:05 -0700306 * SRB extensions.
307 */
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700308struct srb_iocb {
309 union {
310 struct {
311 uint16_t flags;
312#define SRB_LOGIN_RETRIED BIT_0
313#define SRB_LOGIN_COND_PLOGI BIT_1
314#define SRB_LOGIN_SKIP_PRLI BIT_2
315 uint16_t data[2];
316 } logio;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700317 struct {
318 /*
319 * Values for flags field below are as
320 * defined in tsk_mgmt_entry struct
321 * for control_flags field in qla_fw.h.
322 */
Hannes Reinecke9cb78c12014-06-25 15:27:36 +0200323 uint64_t lun;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700324 uint32_t flags;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700325 uint32_t data;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400326 struct completion comp;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400327 __le16 comp_status;
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700328 } tmf;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400329 struct {
330#define SRB_FXDISC_REQ_DMA_VALID BIT_0
331#define SRB_FXDISC_RESP_DMA_VALID BIT_1
332#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
333#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
334#define FXDISC_TIMEOUT 20
335 uint8_t flags;
336 uint32_t req_len;
337 uint32_t rsp_len;
338 void *req_addr;
339 void *rsp_addr;
340 dma_addr_t req_dma_handle;
341 dma_addr_t rsp_dma_handle;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400342 __le32 adapter_id;
343 __le32 adapter_id_hi;
344 __le16 req_func_type;
345 __le32 req_data;
346 __le32 req_data_extra;
347 __le32 result;
348 __le32 seq_number;
349 __le16 fw_flags;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400350 struct completion fxiocb_comp;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400351 __le32 reserved_0;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400352 uint8_t reserved_1;
353 } fxiocb;
354 struct {
355 uint32_t cmd_hndl;
Saurav Kashyap1f8deef2013-06-25 11:27:21 -0400356 __le16 comp_status;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400357 struct completion comp;
358 } abt;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700359 } u;
Andrew Vasquez99b0bec2010-05-04 15:01:25 -0700360
Andrew Vasquezac280b62009-08-20 11:06:05 -0700361 struct timer_list timer;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800362 void (*timeout)(void *);
Andrew Vasquezac280b62009-08-20 11:06:05 -0700363};
364
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700365/* Values for srb_ctx type */
366#define SRB_LOGIN_CMD 1
367#define SRB_LOGOUT_CMD 2
368#define SRB_ELS_CMD_RPT 3
369#define SRB_ELS_CMD_HST 4
370#define SRB_CT_CMD 5
371#define SRB_ADISC_CMD 6
Madhuranath Iyengar38222632010-05-04 15:01:29 -0700372#define SRB_TM_CMD 7
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800373#define SRB_SCSI_CMD 8
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -0400374#define SRB_BIDI_CMD 9
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400375#define SRB_FXIOCB_DCMD 10
376#define SRB_FXIOCB_BCMD 11
377#define SRB_ABT_CMD 12
378
Andrew Vasquezac280b62009-08-20 11:06:05 -0700379
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800380typedef struct srb {
381 atomic_t ref_count;
382 struct fc_port *fcport;
383 uint32_t handle;
384 uint16_t flags;
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800385 uint16_t type;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700386 char *name;
Andrew Vasquez57807902011-11-18 09:03:20 -0800387 int iocbs;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700388 union {
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800389 struct srb_iocb iocb_cmd;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700390 struct fc_bsg_job *bsg_job;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800391 struct srb_cmd scmd;
Madhuranath Iyengar49163922010-05-04 15:01:28 -0700392 } u;
Giridhar Malavali9ba56b92012-02-09 11:15:36 -0800393 void (*done)(void *, void *, int);
394 void (*free)(void *, void *);
395} srb_t;
396
397#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
398#define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
399#define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
400
401#define GET_CMD_SENSE_LEN(sp) \
402 (sp->u.scmd.request_sense_length)
403#define SET_CMD_SENSE_LEN(sp, len) \
404 (sp->u.scmd.request_sense_length = len)
405#define GET_CMD_SENSE_PTR(sp) \
406 (sp->u.scmd.request_sense_ptr)
407#define SET_CMD_SENSE_PTR(sp, ptr) \
408 (sp->u.scmd.request_sense_ptr = ptr)
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400409#define GET_FW_SENSE_LEN(sp) \
410 (sp->u.scmd.fw_sense_length)
411#define SET_FW_SENSE_LEN(sp, len) \
412 (sp->u.scmd.fw_sense_length = len)
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800413
414struct msg_echo_lb {
415 dma_addr_t send_dma;
416 dma_addr_t rcv_dma;
417 uint16_t req_sg_cnt;
418 uint16_t rsp_sg_cnt;
419 uint16_t options;
420 uint32_t transfer_size;
Joe Carnuccio1b98b422013-03-28 08:21:26 -0400421 uint32_t iteration_count;
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800422};
423
Andrew Vasquezac280b62009-08-20 11:06:05 -0700424/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 * ISP I/O Register Set structure definitions.
426 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700427struct device_reg_2xxx {
428 uint16_t flash_address; /* Flash BIOS address */
429 uint16_t flash_data; /* Flash BIOS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 uint16_t unused_1[1]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700431 uint16_t ctrl_status; /* Control/Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700432#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
434#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
435
Andrew Vasquez3d716442005-07-06 10:30:26 -0700436 uint16_t ictrl; /* Interrupt control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
438#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
439
Andrew Vasquez3d716442005-07-06 10:30:26 -0700440 uint16_t istatus; /* Interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441#define ISR_RISC_INT BIT_3 /* RISC interrupt */
442
Andrew Vasquez3d716442005-07-06 10:30:26 -0700443 uint16_t semaphore; /* Semaphore */
444 uint16_t nvram; /* NVRAM register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445#define NVR_DESELECT 0
446#define NVR_BUSY BIT_15
447#define NVR_WRT_ENABLE BIT_14 /* Write enable */
448#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
449#define NVR_DATA_IN BIT_3
450#define NVR_DATA_OUT BIT_2
451#define NVR_SELECT BIT_1
452#define NVR_CLOCK BIT_0
453
Ravi Anand45aeaf12006-05-17 15:08:49 -0700454#define NVR_WAIT_CNT 20000
455
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 union {
457 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700458 uint16_t mailbox0;
459 uint16_t mailbox1;
460 uint16_t mailbox2;
461 uint16_t mailbox3;
462 uint16_t mailbox4;
463 uint16_t mailbox5;
464 uint16_t mailbox6;
465 uint16_t mailbox7;
466 uint16_t unused_2[59]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 } __attribute__((packed)) isp2100;
468 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700469 /* Request Queue */
470 uint16_t req_q_in; /* In-Pointer */
471 uint16_t req_q_out; /* Out-Pointer */
472 /* Response Queue */
473 uint16_t rsp_q_in; /* In-Pointer */
474 uint16_t rsp_q_out; /* Out-Pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
476 /* RISC to Host Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700477 uint32_t host_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478#define HSR_RISC_INT BIT_15 /* RISC interrupt */
479#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
480
481 /* Host to Host Semaphore */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700482 uint16_t host_semaphore;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700483 uint16_t unused_3[17]; /* Gap */
484 uint16_t mailbox0;
485 uint16_t mailbox1;
486 uint16_t mailbox2;
487 uint16_t mailbox3;
488 uint16_t mailbox4;
489 uint16_t mailbox5;
490 uint16_t mailbox6;
491 uint16_t mailbox7;
492 uint16_t mailbox8;
493 uint16_t mailbox9;
494 uint16_t mailbox10;
495 uint16_t mailbox11;
496 uint16_t mailbox12;
497 uint16_t mailbox13;
498 uint16_t mailbox14;
499 uint16_t mailbox15;
500 uint16_t mailbox16;
501 uint16_t mailbox17;
502 uint16_t mailbox18;
503 uint16_t mailbox19;
504 uint16_t mailbox20;
505 uint16_t mailbox21;
506 uint16_t mailbox22;
507 uint16_t mailbox23;
508 uint16_t mailbox24;
509 uint16_t mailbox25;
510 uint16_t mailbox26;
511 uint16_t mailbox27;
512 uint16_t mailbox28;
513 uint16_t mailbox29;
514 uint16_t mailbox30;
515 uint16_t mailbox31;
516 uint16_t fb_cmd;
517 uint16_t unused_4[10]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 } __attribute__((packed)) isp2300;
519 } u;
520
Andrew Vasquez3d716442005-07-06 10:30:26 -0700521 uint16_t fpm_diag_config;
Andrew Vasquezc81d04c2007-07-26 11:41:13 -0700522 uint16_t unused_5[0x4]; /* Gap */
523 uint16_t risc_hw;
524 uint16_t unused_5_1; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700525 uint16_t pcr; /* Processor Control Register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 uint16_t unused_6[0x5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700527 uint16_t mctr; /* Memory Configuration and Timing. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 uint16_t unused_7[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700529 uint16_t fb_cmd_2100; /* Unused on 23XX */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 uint16_t unused_8[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700531 uint16_t hccr; /* Host command & control register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
533#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
534 /* HCCR commands */
535#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
536#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
537#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
538#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
539#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
540#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
541#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
542#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
543
544 uint16_t unused_9[5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700545 uint16_t gpiod; /* GPIO Data register. */
546 uint16_t gpioe; /* GPIO Enable register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547#define GPIO_LED_MASK 0x00C0
548#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
549#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
550#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
551#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800552#define GPIO_LED_ALL_OFF 0x0000
553#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
554#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
556 union {
557 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700558 uint16_t unused_10[8]; /* Gap */
559 uint16_t mailbox8;
560 uint16_t mailbox9;
561 uint16_t mailbox10;
562 uint16_t mailbox11;
563 uint16_t mailbox12;
564 uint16_t mailbox13;
565 uint16_t mailbox14;
566 uint16_t mailbox15;
567 uint16_t mailbox16;
568 uint16_t mailbox17;
569 uint16_t mailbox18;
570 uint16_t mailbox19;
571 uint16_t mailbox20;
572 uint16_t mailbox21;
573 uint16_t mailbox22;
574 uint16_t mailbox23; /* Also probe reg. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575 } __attribute__((packed)) isp2200;
576 } u_end;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700577};
578
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800579struct device_reg_25xxmq {
Andrew Vasquez08029992009-03-24 09:07:55 -0700580 uint32_t req_q_in;
581 uint32_t req_q_out;
582 uint32_t rsp_q_in;
583 uint32_t rsp_q_out;
Arun Easiaa230bc2013-01-30 03:34:39 -0500584 uint32_t atio_q_in;
585 uint32_t atio_q_out;
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800586};
587
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400588
589struct device_reg_fx00 {
590 uint32_t mailbox0; /* 00 */
591 uint32_t mailbox1; /* 04 */
592 uint32_t mailbox2; /* 08 */
593 uint32_t mailbox3; /* 0C */
594 uint32_t mailbox4; /* 10 */
595 uint32_t mailbox5; /* 14 */
596 uint32_t mailbox6; /* 18 */
597 uint32_t mailbox7; /* 1C */
598 uint32_t mailbox8; /* 20 */
599 uint32_t mailbox9; /* 24 */
600 uint32_t mailbox10; /* 28 */
601 uint32_t mailbox11;
602 uint32_t mailbox12;
603 uint32_t mailbox13;
604 uint32_t mailbox14;
605 uint32_t mailbox15;
606 uint32_t mailbox16;
607 uint32_t mailbox17;
608 uint32_t mailbox18;
609 uint32_t mailbox19;
610 uint32_t mailbox20;
611 uint32_t mailbox21;
612 uint32_t mailbox22;
613 uint32_t mailbox23;
614 uint32_t mailbox24;
615 uint32_t mailbox25;
616 uint32_t mailbox26;
617 uint32_t mailbox27;
618 uint32_t mailbox28;
619 uint32_t mailbox29;
620 uint32_t mailbox30;
621 uint32_t mailbox31;
622 uint32_t aenmailbox0;
623 uint32_t aenmailbox1;
624 uint32_t aenmailbox2;
625 uint32_t aenmailbox3;
626 uint32_t aenmailbox4;
627 uint32_t aenmailbox5;
628 uint32_t aenmailbox6;
629 uint32_t aenmailbox7;
630 /* Request Queue. */
631 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
632 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
633 /* Response Queue. */
634 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
635 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
636 /* Init values shadowed on FW Up Event */
637 uint32_t initval0; /* B0 */
638 uint32_t initval1; /* B4 */
639 uint32_t initval2; /* B8 */
640 uint32_t initval3; /* BC */
641 uint32_t initval4; /* C0 */
642 uint32_t initval5; /* C4 */
643 uint32_t initval6; /* C8 */
644 uint32_t initval7; /* CC */
645 uint32_t fwheartbeat; /* D0 */
Armen Baloyanf9a2a542013-08-27 01:37:42 -0400646 uint32_t pseudoaen; /* D4 */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400647};
648
649
650
Andrew Morton9a168bd2005-07-26 14:11:28 -0700651typedef union {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700652 struct device_reg_2xxx isp;
653 struct device_reg_24xx isp24;
Anirban Chakraborty73208df2008-12-09 16:45:39 -0800654 struct device_reg_25xxmq isp25mq;
Giridhar Malavalia9083012010-04-12 17:59:55 -0700655 struct device_reg_82xx isp82;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400656 struct device_reg_fx00 ispfx00;
Chad Dupuisf73cb692014-02-26 04:15:06 -0500657} __iomem device_reg_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658
659#define ISP_REQ_Q_IN(ha, reg) \
660 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
661 &(reg)->u.isp2100.mailbox4 : \
662 &(reg)->u.isp2300.req_q_in)
663#define ISP_REQ_Q_OUT(ha, reg) \
664 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
665 &(reg)->u.isp2100.mailbox4 : \
666 &(reg)->u.isp2300.req_q_out)
667#define ISP_RSP_Q_IN(ha, reg) \
668 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
669 &(reg)->u.isp2100.mailbox5 : \
670 &(reg)->u.isp2300.rsp_q_in)
671#define ISP_RSP_Q_OUT(ha, reg) \
672 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
673 &(reg)->u.isp2100.mailbox5 : \
674 &(reg)->u.isp2300.rsp_q_out)
675
Arun Easiaa230bc2013-01-30 03:34:39 -0500676#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
677#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
678
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679#define MAILBOX_REG(ha, reg, num) \
680 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
681 (num < 8 ? \
682 &(reg)->u.isp2100.mailbox0 + (num) : \
683 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
684 &(reg)->u.isp2300.mailbox0 + (num))
685#define RD_MAILBOX_REG(ha, reg, num) \
686 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
687#define WRT_MAILBOX_REG(ha, reg, num, data) \
688 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
689
690#define FB_CMD_REG(ha, reg) \
691 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
692 &(reg)->fb_cmd_2100 : \
693 &(reg)->u.isp2300.fb_cmd)
694#define RD_FB_CMD_REG(ha, reg) \
695 RD_REG_WORD(FB_CMD_REG(ha, reg))
696#define WRT_FB_CMD_REG(ha, reg, data) \
697 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
698
699typedef struct {
700 uint32_t out_mb; /* outbound from driver */
701 uint32_t in_mb; /* Incoming from RISC */
702 uint16_t mb[MAILBOX_REGISTER_COUNT];
703 long buf_size;
704 void *bufp;
705 uint32_t tov;
706 uint8_t flags;
707#define MBX_DMA_IN BIT_0
708#define MBX_DMA_OUT BIT_1
709#define IOCTL_CMD BIT_2
710} mbx_cmd_t;
711
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400712struct mbx_cmd_32 {
713 uint32_t out_mb; /* outbound from driver */
714 uint32_t in_mb; /* Incoming from RISC */
715 uint32_t mb[MAILBOX_REGISTER_COUNT];
716 long buf_size;
717 void *bufp;
718 uint32_t tov;
719 uint8_t flags;
720#define MBX_DMA_IN BIT_0
721#define MBX_DMA_OUT BIT_1
722#define IOCTL_CMD BIT_2
723};
724
725
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726#define MBX_TOV_SECONDS 30
727
728/*
729 * ISP product identification definitions in mailboxes after reset.
730 */
731#define PROD_ID_1 0x4953
732#define PROD_ID_2 0x0000
733#define PROD_ID_2a 0x5020
734#define PROD_ID_3 0x2020
735
736/*
737 * ISP mailbox Self-Test status codes
738 */
739#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
740#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
741#define MBS_BUSY 4 /* Busy. */
742
743/*
744 * ISP mailbox command complete status codes
745 */
746#define MBS_COMMAND_COMPLETE 0x4000
747#define MBS_INVALID_COMMAND 0x4001
748#define MBS_HOST_INTERFACE_ERROR 0x4002
749#define MBS_TEST_FAILED 0x4003
750#define MBS_COMMAND_ERROR 0x4005
751#define MBS_COMMAND_PARAMETER_ERROR 0x4006
752#define MBS_PORT_ID_USED 0x4007
753#define MBS_LOOP_ID_USED 0x4008
754#define MBS_ALL_IDS_IN_USE 0x4009
755#define MBS_NOT_LOGGED_IN 0x400A
Andrew Vasquez3d716442005-07-06 10:30:26 -0700756#define MBS_LINK_DOWN_ERROR 0x400B
757#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758
759/*
760 * ISP mailbox asynchronous event status codes
761 */
762#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
763#define MBA_RESET 0x8001 /* Reset Detected. */
764#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
765#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
766#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
767#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
768#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
769 /* occurred. */
770#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
771#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
772#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
773#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
774#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
775#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
776#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
777#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
778#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
779#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
780#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
781#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
782#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
783#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
784#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
785#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
786 /* used. */
Andrew Vasquez45ebeb52006-08-01 13:48:14 -0700787#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
789#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
790#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
791#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
792#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
793#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
794#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
795#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
796#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
797#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
798#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
799#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
800#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400801#define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
802#define MBA_FW_STARTING 0x8051 /* Firmware starting */
803#define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
804#define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
805#define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
806#define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
807#define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
808 Notification */
809#define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
Armen Baloyanb6511d92013-08-27 01:37:31 -0400810#define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
Armen Baloyan0f8cdff2014-02-26 04:14:57 -0500811#define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
Santosh Vernekar7d613ac2012-08-22 14:21:03 -0400812/* 83XX FCoE specific */
813#define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
814
Arun Easifafbda92012-08-22 14:21:16 -0400815/* Interrupt type codes */
816#define INTR_ROM_MB_SUCCESS 0x1
817#define INTR_ROM_MB_FAILED 0x2
818#define INTR_MB_SUCCESS 0x10
819#define INTR_MB_FAILED 0x11
820#define INTR_ASYNC_EVENT 0x12
821#define INTR_RSP_QUE_UPDATE 0x13
822#define INTR_RSP_QUE_UPDATE_83XX 0x14
823#define INTR_ATIO_QUE_UPDATE 0x1C
824#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
825
Giridhar Malavali9a069e12010-01-12 13:02:47 -0800826/* ISP mailbox loopback echo diagnostic error code */
827#define MBS_LB_RESET 0x17
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828/*
829 * Firmware options 1, 2, 3.
830 */
831#define FO1_AE_ON_LIPF8 BIT_0
832#define FO1_AE_ALL_LIP_RESET BIT_1
833#define FO1_CTIO_RETRY BIT_3
834#define FO1_DISABLE_LIP_F7_SW BIT_4
835#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
Andrew Vasquez3d716442005-07-06 10:30:26 -0700836#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
838#define FO1_SET_EMPHASIS_SWING BIT_8
839#define FO1_AE_AUTO_BYPASS BIT_9
840#define FO1_ENABLE_PURE_IOCB BIT_10
841#define FO1_AE_PLOGI_RJT BIT_11
842#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
843#define FO1_AE_QUEUE_FULL BIT_13
844
845#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
846#define FO2_REV_LOOPBACK BIT_1
847
848#define FO3_ENABLE_EMERG_IOCB BIT_0
849#define FO3_AE_RND_ERROR BIT_1
850
Andrew Vasquez3d716442005-07-06 10:30:26 -0700851/* 24XX additional firmware options */
852#define ADD_FO_COUNT 3
853#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
854#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
855
856#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
857
858#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
859
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860/*
861 * ISP mailbox commands
862 */
863#define MBC_LOAD_RAM 1 /* Load RAM. */
864#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
866#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
867#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
868#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
869#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
870#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
871#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
872#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
873#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
874#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
875#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
Andrew Vasquezf6ef3b12005-08-26 19:10:20 -0700876#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
878#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
879#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
880#define MBC_RESET 0x18 /* Reset. */
881#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
882#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
883#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
884#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
885#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
886#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
887#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
888#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
889#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
890#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
891#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
892#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
893#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
894#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
Giridhar Malavali6246b8a2012-02-09 11:15:34 -0800895#define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
897#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
Andrew Vasquezaf11f642012-02-09 11:15:43 -0800898#define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
900#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
Joe Carnuccio90687a12013-02-08 01:57:59 -0500901#define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
902#define MBC_DATA_RATE 0x5d /* Data Rate */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
904#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
905 /* Initialization Procedure */
906#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
907#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
908#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
909#define MBC_TARGET_RESET 0x66 /* Target Reset. */
910#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
911#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
912#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
913#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
914#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
915#define MBC_LIP_RESET 0x6c /* LIP reset. */
916#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
917 /* commandd. */
918#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
919#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
920#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
921#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
922#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
923#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
924#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
925#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
926#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
927#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
928#define MBC_LUN_RESET 0x7E /* Send LUN reset */
929
Andrew Vasquez3d716442005-07-06 10:30:26 -0700930/*
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -0400931 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
932 * should be defined with MBC_MR_*
933 */
934#define MBC_MR_DRV_SHUTDOWN 0x6A
935
936/*
Andrew Vasquez3d716442005-07-06 10:30:26 -0700937 * ISP24xx mailbox commands
938 */
Joe Carnucciodb64e932013-10-30 03:38:18 -0400939#define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
940#define MBC_READ_SERDES 0x4 /* Read serdes word. */
Chad Dupuisf73cb692014-02-26 04:15:06 -0500941#define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700942#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
943#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
Andrew Vasquezd8b45212006-10-02 12:00:43 -0700944#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700945#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700946#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700947#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
Joe Carnuccioad0ecd62009-03-24 09:08:12 -0700948#define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
Andrew Vasquez88729e52006-06-23 16:10:50 -0700949#define MBC_READ_SFP 0x31 /* Read SFP Data. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700950#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
951#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
952#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
953#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
954#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
955#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
956#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
Joe Carnuccio61e1b262013-02-08 01:57:48 -0500957#define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700958#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
Chad Dupuis8fcd6b82012-08-22 14:21:06 -0400959#define MBC_PORT_RESET 0x120 /* Port Reset */
Sarang Radke23f2ebd2010-05-28 15:08:21 -0700960#define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
961#define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700962
Madhuranath Iyengarb1d46982010-09-03 15:20:54 -0700963/*
964 * ISP81xx mailbox commands
965 */
966#define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
967
Joe Carnuccioe8887c52014-04-11 16:54:17 -0400968/*
969 * ISP8044 mailbox commands
970 */
971#define MBC_SET_GET_ETH_SERDES_REG 0x150
972#define HCS_WRITE_SERDES 0x3
973#define HCS_READ_SERDES 0x4
974
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975/* Firmware return data sizes */
976#define FCAL_MAP_SIZE 128
977
978/* Mailbox bit definitions for out_mb and in_mb */
979#define MBX_31 BIT_31
980#define MBX_30 BIT_30
981#define MBX_29 BIT_29
982#define MBX_28 BIT_28
983#define MBX_27 BIT_27
984#define MBX_26 BIT_26
985#define MBX_25 BIT_25
986#define MBX_24 BIT_24
987#define MBX_23 BIT_23
988#define MBX_22 BIT_22
989#define MBX_21 BIT_21
990#define MBX_20 BIT_20
991#define MBX_19 BIT_19
992#define MBX_18 BIT_18
993#define MBX_17 BIT_17
994#define MBX_16 BIT_16
995#define MBX_15 BIT_15
996#define MBX_14 BIT_14
997#define MBX_13 BIT_13
998#define MBX_12 BIT_12
999#define MBX_11 BIT_11
1000#define MBX_10 BIT_10
1001#define MBX_9 BIT_9
1002#define MBX_8 BIT_8
1003#define MBX_7 BIT_7
1004#define MBX_6 BIT_6
1005#define MBX_5 BIT_5
1006#define MBX_4 BIT_4
1007#define MBX_3 BIT_3
1008#define MBX_2 BIT_2
1009#define MBX_1 BIT_1
1010#define MBX_0 BIT_0
1011
Joe Carnuccioc46e65c2013-08-27 01:37:35 -04001012#define RNID_TYPE_SET_VERSION 0x9
Joe Carnucciofe52f6e2013-02-08 01:58:03 -05001013#define RNID_TYPE_ASIC_TEMP 0xC
Joe Carnuccio3a117112013-02-08 01:58:00 -05001014
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015/*
1016 * Firmware state codes from get firmware state mailbox command
1017 */
1018#define FSTATE_CONFIG_WAIT 0
1019#define FSTATE_WAIT_AL_PA 1
1020#define FSTATE_WAIT_LOGIN 2
1021#define FSTATE_READY 3
1022#define FSTATE_LOSS_OF_SYNC 4
1023#define FSTATE_ERROR 5
1024#define FSTATE_REINIT 6
1025#define FSTATE_NON_PART 7
1026
1027#define FSTATE_CONFIG_CORRECT 0
1028#define FSTATE_P2P_RCV_LIP 1
1029#define FSTATE_P2P_CHOOSE_LOOP 2
1030#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1031#define FSTATE_FATAL_ERROR 4
1032#define FSTATE_LOOP_BACK_CONN 5
1033
1034/*
1035 * Port Database structure definition
1036 * Little endian except where noted.
1037 */
1038#define PORT_DATABASE_SIZE 128 /* bytes */
1039typedef struct {
1040 uint8_t options;
1041 uint8_t control;
1042 uint8_t master_state;
1043 uint8_t slave_state;
1044 uint8_t reserved[2];
1045 uint8_t hard_address;
1046 uint8_t reserved_1;
1047 uint8_t port_id[4];
1048 uint8_t node_name[WWN_SIZE];
1049 uint8_t port_name[WWN_SIZE];
1050 uint16_t execution_throttle;
1051 uint16_t execution_count;
1052 uint8_t reset_count;
1053 uint8_t reserved_2;
1054 uint16_t resource_allocation;
1055 uint16_t current_allocation;
1056 uint16_t queue_head;
1057 uint16_t queue_tail;
1058 uint16_t transmit_execution_list_next;
1059 uint16_t transmit_execution_list_previous;
1060 uint16_t common_features;
1061 uint16_t total_concurrent_sequences;
1062 uint16_t RO_by_information_category;
1063 uint8_t recipient;
1064 uint8_t initiator;
1065 uint16_t receive_data_size;
1066 uint16_t concurrent_sequences;
1067 uint16_t open_sequences_per_exchange;
1068 uint16_t lun_abort_flags;
1069 uint16_t lun_stop_flags;
1070 uint16_t stop_queue_head;
1071 uint16_t stop_queue_tail;
1072 uint16_t port_retry_timer;
1073 uint16_t next_sequence_id;
1074 uint16_t frame_count;
1075 uint16_t PRLI_payload_length;
1076 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1077 /* Bits 15-0 of word 0 */
1078 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1079 /* Bits 15-0 of word 3 */
1080 uint16_t loop_id;
1081 uint16_t extended_lun_info_list_pointer;
1082 uint16_t extended_lun_stop_list_pointer;
1083} port_database_t;
1084
1085/*
1086 * Port database slave/master states
1087 */
1088#define PD_STATE_DISCOVERY 0
1089#define PD_STATE_WAIT_DISCOVERY_ACK 1
1090#define PD_STATE_PORT_LOGIN 2
1091#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1092#define PD_STATE_PROCESS_LOGIN 4
1093#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1094#define PD_STATE_PORT_LOGGED_IN 6
1095#define PD_STATE_PORT_UNAVAILABLE 7
1096#define PD_STATE_PROCESS_LOGOUT 8
1097#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1098#define PD_STATE_PORT_LOGOUT 10
1099#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1100
1101
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -07001102#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1103#define QLA_ZIO_DISABLED 0
1104#define QLA_ZIO_DEFAULT_TIMER 2
1105
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106/*
1107 * ISP Initialization Control Block.
1108 * Little endian except where noted.
1109 */
1110#define ICB_VERSION 1
1111typedef struct {
1112 uint8_t version;
1113 uint8_t reserved_1;
1114
1115 /*
1116 * LSB BIT 0 = Enable Hard Loop Id
1117 * LSB BIT 1 = Enable Fairness
1118 * LSB BIT 2 = Enable Full-Duplex
1119 * LSB BIT 3 = Enable Fast Posting
1120 * LSB BIT 4 = Enable Target Mode
1121 * LSB BIT 5 = Disable Initiator Mode
1122 * LSB BIT 6 = Enable ADISC
1123 * LSB BIT 7 = Enable Target Inquiry Data
1124 *
1125 * MSB BIT 0 = Enable PDBC Notify
1126 * MSB BIT 1 = Non Participating LIP
1127 * MSB BIT 2 = Descending Loop ID Search
1128 * MSB BIT 3 = Acquire Loop ID in LIPA
1129 * MSB BIT 4 = Stop PortQ on Full Status
1130 * MSB BIT 5 = Full Login after LIP
1131 * MSB BIT 6 = Node Name Option
1132 * MSB BIT 7 = Ext IFWCB enable bit
1133 */
1134 uint8_t firmware_options[2];
1135
1136 uint16_t frame_payload_size;
1137 uint16_t max_iocb_allocation;
1138 uint16_t execution_throttle;
1139 uint8_t retry_count;
1140 uint8_t retry_delay; /* unused */
1141 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1142 uint16_t hard_address;
1143 uint8_t inquiry_data;
1144 uint8_t login_timeout;
1145 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1146
1147 uint16_t request_q_outpointer;
1148 uint16_t response_q_inpointer;
1149 uint16_t request_q_length;
1150 uint16_t response_q_length;
1151 uint32_t request_q_address[2];
1152 uint32_t response_q_address[2];
1153
1154 uint16_t lun_enables;
1155 uint8_t command_resource_count;
1156 uint8_t immediate_notify_resource_count;
1157 uint16_t timeout;
1158 uint8_t reserved_2[2];
1159
1160 /*
1161 * LSB BIT 0 = Timer Operation mode bit 0
1162 * LSB BIT 1 = Timer Operation mode bit 1
1163 * LSB BIT 2 = Timer Operation mode bit 2
1164 * LSB BIT 3 = Timer Operation mode bit 3
1165 * LSB BIT 4 = Init Config Mode bit 0
1166 * LSB BIT 5 = Init Config Mode bit 1
1167 * LSB BIT 6 = Init Config Mode bit 2
1168 * LSB BIT 7 = Enable Non part on LIHA failure
1169 *
1170 * MSB BIT 0 = Enable class 2
1171 * MSB BIT 1 = Enable ACK0
1172 * MSB BIT 2 =
1173 * MSB BIT 3 =
1174 * MSB BIT 4 = FC Tape Enable
1175 * MSB BIT 5 = Enable FC Confirm
1176 * MSB BIT 6 = Enable command queuing in target mode
1177 * MSB BIT 7 = No Logo On Link Down
1178 */
1179 uint8_t add_firmware_options[2];
1180
1181 uint8_t response_accumulation_timer;
1182 uint8_t interrupt_delay_timer;
1183
1184 /*
1185 * LSB BIT 0 = Enable Read xfr_rdy
1186 * LSB BIT 1 = Soft ID only
1187 * LSB BIT 2 =
1188 * LSB BIT 3 =
1189 * LSB BIT 4 = FCP RSP Payload [0]
1190 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1191 * LSB BIT 6 = Enable Out-of-Order frame handling
1192 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1193 *
1194 * MSB BIT 0 = Sbus enable - 2300
1195 * MSB BIT 1 =
1196 * MSB BIT 2 =
1197 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -07001198 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199 * MSB BIT 5 = enable 50 ohm termination
1200 * MSB BIT 6 = Data Rate (2300 only)
1201 * MSB BIT 7 = Data Rate (2300 only)
1202 */
1203 uint8_t special_options[2];
1204
1205 uint8_t reserved_3[26];
1206} init_cb_t;
1207
1208/*
1209 * Get Link Status mailbox command return buffer.
1210 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001211#define GLSO_SEND_RPS BIT_0
1212#define GLSO_USE_DID BIT_3
1213
Andrew Vasquez43ef0582008-01-17 09:02:08 -08001214struct link_statistics {
1215 uint32_t link_fail_cnt;
1216 uint32_t loss_sync_cnt;
1217 uint32_t loss_sig_cnt;
1218 uint32_t prim_seq_err_cnt;
1219 uint32_t inval_xmit_word_cnt;
1220 uint32_t inval_crc_cnt;
Harish Zunjarrao032d8dd2008-07-10 16:55:50 -07001221 uint32_t lip_cnt;
1222 uint32_t unused1[0x1a];
Andrew Vasquez43ef0582008-01-17 09:02:08 -08001223 uint32_t tx_frames;
1224 uint32_t rx_frames;
Joe Carnucciofabbb8d2013-08-27 01:37:40 -04001225 uint32_t discarded_frames;
1226 uint32_t dropped_frames;
1227 uint32_t unused2[1];
Andrew Vasquez43ef0582008-01-17 09:02:08 -08001228 uint32_t nos_rcvd;
1229};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230
1231/*
1232 * NVRAM Command values.
1233 */
1234#define NV_START_BIT BIT_2
1235#define NV_WRITE_OP (BIT_26+BIT_24)
1236#define NV_READ_OP (BIT_26+BIT_25)
1237#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1238#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1239#define NV_DELAY_COUNT 10
1240
1241/*
1242 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1243 */
1244typedef struct {
1245 /*
1246 * NVRAM header
1247 */
1248 uint8_t id[4];
1249 uint8_t nvram_version;
1250 uint8_t reserved_0;
1251
1252 /*
1253 * NVRAM RISC parameter block
1254 */
1255 uint8_t parameter_block_version;
1256 uint8_t reserved_1;
1257
1258 /*
1259 * LSB BIT 0 = Enable Hard Loop Id
1260 * LSB BIT 1 = Enable Fairness
1261 * LSB BIT 2 = Enable Full-Duplex
1262 * LSB BIT 3 = Enable Fast Posting
1263 * LSB BIT 4 = Enable Target Mode
1264 * LSB BIT 5 = Disable Initiator Mode
1265 * LSB BIT 6 = Enable ADISC
1266 * LSB BIT 7 = Enable Target Inquiry Data
1267 *
1268 * MSB BIT 0 = Enable PDBC Notify
1269 * MSB BIT 1 = Non Participating LIP
1270 * MSB BIT 2 = Descending Loop ID Search
1271 * MSB BIT 3 = Acquire Loop ID in LIPA
1272 * MSB BIT 4 = Stop PortQ on Full Status
1273 * MSB BIT 5 = Full Login after LIP
1274 * MSB BIT 6 = Node Name Option
1275 * MSB BIT 7 = Ext IFWCB enable bit
1276 */
1277 uint8_t firmware_options[2];
1278
1279 uint16_t frame_payload_size;
1280 uint16_t max_iocb_allocation;
1281 uint16_t execution_throttle;
1282 uint8_t retry_count;
1283 uint8_t retry_delay; /* unused */
1284 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1285 uint16_t hard_address;
1286 uint8_t inquiry_data;
1287 uint8_t login_timeout;
1288 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1289
1290 /*
1291 * LSB BIT 0 = Timer Operation mode bit 0
1292 * LSB BIT 1 = Timer Operation mode bit 1
1293 * LSB BIT 2 = Timer Operation mode bit 2
1294 * LSB BIT 3 = Timer Operation mode bit 3
1295 * LSB BIT 4 = Init Config Mode bit 0
1296 * LSB BIT 5 = Init Config Mode bit 1
1297 * LSB BIT 6 = Init Config Mode bit 2
1298 * LSB BIT 7 = Enable Non part on LIHA failure
1299 *
1300 * MSB BIT 0 = Enable class 2
1301 * MSB BIT 1 = Enable ACK0
1302 * MSB BIT 2 =
1303 * MSB BIT 3 =
1304 * MSB BIT 4 = FC Tape Enable
1305 * MSB BIT 5 = Enable FC Confirm
1306 * MSB BIT 6 = Enable command queuing in target mode
1307 * MSB BIT 7 = No Logo On Link Down
1308 */
1309 uint8_t add_firmware_options[2];
1310
1311 uint8_t response_accumulation_timer;
1312 uint8_t interrupt_delay_timer;
1313
1314 /*
1315 * LSB BIT 0 = Enable Read xfr_rdy
1316 * LSB BIT 1 = Soft ID only
1317 * LSB BIT 2 =
1318 * LSB BIT 3 =
1319 * LSB BIT 4 = FCP RSP Payload [0]
1320 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1321 * LSB BIT 6 = Enable Out-of-Order frame handling
1322 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1323 *
1324 * MSB BIT 0 = Sbus enable - 2300
1325 * MSB BIT 1 =
1326 * MSB BIT 2 =
1327 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -07001328 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329 * MSB BIT 5 = enable 50 ohm termination
1330 * MSB BIT 6 = Data Rate (2300 only)
1331 * MSB BIT 7 = Data Rate (2300 only)
1332 */
1333 uint8_t special_options[2];
1334
1335 /* Reserved for expanded RISC parameter block */
1336 uint8_t reserved_2[22];
1337
1338 /*
1339 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1340 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1341 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1342 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1343 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1344 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1345 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1346 * LSB BIT 7 = Rx Sensitivity 1G bit 3
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001347 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1349 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1350 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1351 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1352 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1353 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1354 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1355 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1356 *
1357 * LSB BIT 0 = Output Swing 1G bit 0
1358 * LSB BIT 1 = Output Swing 1G bit 1
1359 * LSB BIT 2 = Output Swing 1G bit 2
1360 * LSB BIT 3 = Output Emphasis 1G bit 0
1361 * LSB BIT 4 = Output Emphasis 1G bit 1
1362 * LSB BIT 5 = Output Swing 2G bit 0
1363 * LSB BIT 6 = Output Swing 2G bit 1
1364 * LSB BIT 7 = Output Swing 2G bit 2
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001365 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366 * MSB BIT 0 = Output Emphasis 2G bit 0
1367 * MSB BIT 1 = Output Emphasis 2G bit 1
1368 * MSB BIT 2 = Output Enable
1369 * MSB BIT 3 =
1370 * MSB BIT 4 =
1371 * MSB BIT 5 =
1372 * MSB BIT 6 =
1373 * MSB BIT 7 =
1374 */
1375 uint8_t seriallink_options[4];
1376
1377 /*
1378 * NVRAM host parameter block
1379 *
1380 * LSB BIT 0 = Enable spinup delay
1381 * LSB BIT 1 = Disable BIOS
1382 * LSB BIT 2 = Enable Memory Map BIOS
1383 * LSB BIT 3 = Enable Selectable Boot
1384 * LSB BIT 4 = Disable RISC code load
1385 * LSB BIT 5 = Set cache line size 1
1386 * LSB BIT 6 = PCI Parity Disable
1387 * LSB BIT 7 = Enable extended logging
1388 *
1389 * MSB BIT 0 = Enable 64bit addressing
1390 * MSB BIT 1 = Enable lip reset
1391 * MSB BIT 2 = Enable lip full login
1392 * MSB BIT 3 = Enable target reset
1393 * MSB BIT 4 = Enable database storage
1394 * MSB BIT 5 = Enable cache flush read
1395 * MSB BIT 6 = Enable database load
1396 * MSB BIT 7 = Enable alternate WWN
1397 */
1398 uint8_t host_p[2];
1399
1400 uint8_t boot_node_name[WWN_SIZE];
1401 uint8_t boot_lun_number;
1402 uint8_t reset_delay;
1403 uint8_t port_down_retry_count;
1404 uint8_t boot_id_number;
1405 uint16_t max_luns_per_target;
1406 uint8_t fcode_boot_port_name[WWN_SIZE];
1407 uint8_t alternate_port_name[WWN_SIZE];
1408 uint8_t alternate_node_name[WWN_SIZE];
1409
1410 /*
1411 * BIT 0 = Selective Login
1412 * BIT 1 = Alt-Boot Enable
1413 * BIT 2 =
1414 * BIT 3 = Boot Order List
1415 * BIT 4 =
1416 * BIT 5 = Selective LUN
1417 * BIT 6 =
1418 * BIT 7 = unused
1419 */
1420 uint8_t efi_parameters;
1421
1422 uint8_t link_down_timeout;
1423
Andrew Vasquezcca53352005-08-26 19:08:30 -07001424 uint8_t adapter_id[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425
1426 uint8_t alt1_boot_node_name[WWN_SIZE];
1427 uint16_t alt1_boot_lun_number;
1428 uint8_t alt2_boot_node_name[WWN_SIZE];
1429 uint16_t alt2_boot_lun_number;
1430 uint8_t alt3_boot_node_name[WWN_SIZE];
1431 uint16_t alt3_boot_lun_number;
1432 uint8_t alt4_boot_node_name[WWN_SIZE];
1433 uint16_t alt4_boot_lun_number;
1434 uint8_t alt5_boot_node_name[WWN_SIZE];
1435 uint16_t alt5_boot_lun_number;
1436 uint8_t alt6_boot_node_name[WWN_SIZE];
1437 uint16_t alt6_boot_lun_number;
1438 uint8_t alt7_boot_node_name[WWN_SIZE];
1439 uint16_t alt7_boot_lun_number;
1440
1441 uint8_t reserved_3[2];
1442
1443 /* Offset 200-215 : Model Number */
1444 uint8_t model_number[16];
1445
1446 /* OEM related items */
1447 uint8_t oem_specific[16];
1448
1449 /*
1450 * NVRAM Adapter Features offset 232-239
1451 *
1452 * LSB BIT 0 = External GBIC
1453 * LSB BIT 1 = Risc RAM parity
1454 * LSB BIT 2 = Buffer Plus Module
1455 * LSB BIT 3 = Multi Chip Adapter
1456 * LSB BIT 4 = Internal connector
1457 * LSB BIT 5 =
1458 * LSB BIT 6 =
1459 * LSB BIT 7 =
1460 *
1461 * MSB BIT 0 =
1462 * MSB BIT 1 =
1463 * MSB BIT 2 =
1464 * MSB BIT 3 =
1465 * MSB BIT 4 =
1466 * MSB BIT 5 =
1467 * MSB BIT 6 =
1468 * MSB BIT 7 =
1469 */
1470 uint8_t adapter_features[2];
1471
1472 uint8_t reserved_4[16];
1473
1474 /* Subsystem vendor ID for ISP2200 */
1475 uint16_t subsystem_vendor_id_2200;
1476
1477 /* Subsystem device ID for ISP2200 */
1478 uint16_t subsystem_device_id_2200;
1479
1480 uint8_t reserved_5;
1481 uint8_t checksum;
1482} nvram_t;
1483
1484/*
1485 * ISP queue - response queue entry definition.
1486 */
1487typedef struct {
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04001488 uint8_t entry_type; /* Entry type. */
1489 uint8_t entry_count; /* Entry count. */
1490 uint8_t sys_define; /* System defined. */
1491 uint8_t entry_status; /* Entry Status. */
1492 uint32_t handle; /* System defined handle */
1493 uint8_t data[52];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 uint32_t signature;
1495#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1496} response_t;
1497
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04001498/*
1499 * ISP queue - ATIO queue entry definition.
1500 */
1501struct atio {
1502 uint8_t entry_type; /* Entry type. */
1503 uint8_t entry_count; /* Entry count. */
1504 uint8_t data[58];
1505 uint32_t signature;
1506#define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1507};
1508
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509typedef union {
1510 uint16_t extended;
1511 struct {
1512 uint8_t reserved;
1513 uint8_t standard;
1514 } id;
1515} target_id_t;
1516
1517#define SET_TARGET_ID(ha, to, from) \
1518do { \
1519 if (HAS_EXTENDED_IDS(ha)) \
1520 to.extended = cpu_to_le16(from); \
1521 else \
1522 to.id.standard = (uint8_t)from; \
1523} while (0)
1524
1525/*
1526 * ISP queue - command entry structure definition.
1527 */
1528#define COMMAND_TYPE 0x11 /* Command entry */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529typedef struct {
1530 uint8_t entry_type; /* Entry type. */
1531 uint8_t entry_count; /* Entry count. */
1532 uint8_t sys_define; /* System defined. */
1533 uint8_t entry_status; /* Entry Status. */
1534 uint32_t handle; /* System handle. */
1535 target_id_t target; /* SCSI ID */
1536 uint16_t lun; /* SCSI LUN */
1537 uint16_t control_flags; /* Control flags. */
1538#define CF_WRITE BIT_6
1539#define CF_READ BIT_5
1540#define CF_SIMPLE_TAG BIT_3
1541#define CF_ORDERED_TAG BIT_2
1542#define CF_HEAD_TAG BIT_1
1543 uint16_t reserved_1;
1544 uint16_t timeout; /* Command timeout. */
1545 uint16_t dseg_count; /* Data segment count. */
1546 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1547 uint32_t byte_count; /* Total byte count. */
1548 uint32_t dseg_0_address; /* Data segment 0 address. */
1549 uint32_t dseg_0_length; /* Data segment 0 length. */
1550 uint32_t dseg_1_address; /* Data segment 1 address. */
1551 uint32_t dseg_1_length; /* Data segment 1 length. */
1552 uint32_t dseg_2_address; /* Data segment 2 address. */
1553 uint32_t dseg_2_length; /* Data segment 2 length. */
1554} cmd_entry_t;
1555
1556/*
1557 * ISP queue - 64-Bit addressing, command entry structure definition.
1558 */
1559#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1560typedef struct {
1561 uint8_t entry_type; /* Entry type. */
1562 uint8_t entry_count; /* Entry count. */
1563 uint8_t sys_define; /* System defined. */
1564 uint8_t entry_status; /* Entry Status. */
1565 uint32_t handle; /* System handle. */
1566 target_id_t target; /* SCSI ID */
1567 uint16_t lun; /* SCSI LUN */
1568 uint16_t control_flags; /* Control flags. */
1569 uint16_t reserved_1;
1570 uint16_t timeout; /* Command timeout. */
1571 uint16_t dseg_count; /* Data segment count. */
1572 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1573 uint32_t byte_count; /* Total byte count. */
1574 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1575 uint32_t dseg_0_length; /* Data segment 0 length. */
1576 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1577 uint32_t dseg_1_length; /* Data segment 1 length. */
1578} cmd_a64_entry_t, request_t;
1579
1580/*
1581 * ISP queue - continuation entry structure definition.
1582 */
1583#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1584typedef struct {
1585 uint8_t entry_type; /* Entry type. */
1586 uint8_t entry_count; /* Entry count. */
1587 uint8_t sys_define; /* System defined. */
1588 uint8_t entry_status; /* Entry Status. */
1589 uint32_t reserved;
1590 uint32_t dseg_0_address; /* Data segment 0 address. */
1591 uint32_t dseg_0_length; /* Data segment 0 length. */
1592 uint32_t dseg_1_address; /* Data segment 1 address. */
1593 uint32_t dseg_1_length; /* Data segment 1 length. */
1594 uint32_t dseg_2_address; /* Data segment 2 address. */
1595 uint32_t dseg_2_length; /* Data segment 2 length. */
1596 uint32_t dseg_3_address; /* Data segment 3 address. */
1597 uint32_t dseg_3_length; /* Data segment 3 length. */
1598 uint32_t dseg_4_address; /* Data segment 4 address. */
1599 uint32_t dseg_4_length; /* Data segment 4 length. */
1600 uint32_t dseg_5_address; /* Data segment 5 address. */
1601 uint32_t dseg_5_length; /* Data segment 5 length. */
1602 uint32_t dseg_6_address; /* Data segment 6 address. */
1603 uint32_t dseg_6_length; /* Data segment 6 length. */
1604} cont_entry_t;
1605
1606/*
1607 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1608 */
1609#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1610typedef struct {
1611 uint8_t entry_type; /* Entry type. */
1612 uint8_t entry_count; /* Entry count. */
1613 uint8_t sys_define; /* System defined. */
1614 uint8_t entry_status; /* Entry Status. */
1615 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1616 uint32_t dseg_0_length; /* Data segment 0 length. */
1617 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1618 uint32_t dseg_1_length; /* Data segment 1 length. */
1619 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1620 uint32_t dseg_2_length; /* Data segment 2 length. */
1621 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1622 uint32_t dseg_3_length; /* Data segment 3 length. */
1623 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1624 uint32_t dseg_4_length; /* Data segment 4 length. */
1625} cont_a64_entry_t;
1626
Arun Easibad75002010-05-04 15:01:30 -07001627#define PO_MODE_DIF_INSERT 0
Arun Easi9e522cd2012-08-22 14:21:31 -04001628#define PO_MODE_DIF_REMOVE 1
1629#define PO_MODE_DIF_PASS 2
1630#define PO_MODE_DIF_REPLACE 3
1631#define PO_MODE_DIF_TCP_CKSUM 6
Arun Easibad75002010-05-04 15:01:30 -07001632#define PO_ENABLE_INCR_GUARD_SEED BIT_3
Arun Easibad75002010-05-04 15:01:30 -07001633#define PO_DISABLE_GUARD_CHECK BIT_4
Quinn Tranf83adb62014-04-11 16:54:43 -04001634#define PO_DISABLE_INCR_REF_TAG BIT_5
1635#define PO_DIS_HEADER_MODE BIT_7
1636#define PO_ENABLE_DIF_BUNDLING BIT_8
1637#define PO_DIS_FRAME_MODE BIT_9
1638#define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1639#define PO_DIS_VALD_APP_REF_ESC BIT_11
1640
1641#define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1642#define PO_DIS_REF_TAG_REPL BIT_13
1643#define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1644#define PO_DIS_REF_TAG_VALD BIT_15
1645
Arun Easibad75002010-05-04 15:01:30 -07001646/*
1647 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1648 */
1649struct crc_context {
1650 uint32_t handle; /* System handle. */
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04001651 __le32 ref_tag;
1652 __le16 app_tag;
Arun Easibad75002010-05-04 15:01:30 -07001653 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1654 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04001655 __le16 guard_seed; /* Initial Guard Seed */
1656 __le16 prot_opts; /* Requested Data Protection Mode */
1657 __le16 blk_size; /* Data size in bytes */
Arun Easibad75002010-05-04 15:01:30 -07001658 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1659 * only) */
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04001660 __le32 byte_count; /* Total byte count/ total data
Arun Easibad75002010-05-04 15:01:30 -07001661 * transfer count */
1662 union {
1663 struct {
1664 uint32_t reserved_1;
1665 uint16_t reserved_2;
1666 uint16_t reserved_3;
1667 uint32_t reserved_4;
1668 uint32_t data_address[2];
1669 uint32_t data_length;
1670 uint32_t reserved_5[2];
1671 uint32_t reserved_6;
1672 } nobundling;
1673 struct {
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04001674 __le32 dif_byte_count; /* Total DIF byte
Arun Easibad75002010-05-04 15:01:30 -07001675 * count */
1676 uint16_t reserved_1;
Quinn Tranc7ee3bd2014-06-02 07:02:16 -04001677 __le16 dseg_count; /* Data segment count */
Arun Easibad75002010-05-04 15:01:30 -07001678 uint32_t reserved_2;
1679 uint32_t data_address[2];
1680 uint32_t data_length;
1681 uint32_t dif_address[2];
1682 uint32_t dif_length; /* Data segment 0
1683 * length */
1684 } bundling;
1685 } u;
1686
1687 struct fcp_cmnd fcp_cmnd;
1688 dma_addr_t crc_ctx_dma;
1689 /* List of DMA context transfers */
1690 struct list_head dsd_list;
1691
1692 /* This structure should not exceed 512 bytes */
1693};
1694
1695#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1696#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1697
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698/*
1699 * ISP queue - status entry structure definition.
1700 */
1701#define STATUS_TYPE 0x03 /* Status entry. */
1702typedef struct {
1703 uint8_t entry_type; /* Entry type. */
1704 uint8_t entry_count; /* Entry count. */
1705 uint8_t sys_define; /* System defined. */
1706 uint8_t entry_status; /* Entry Status. */
1707 uint32_t handle; /* System handle. */
1708 uint16_t scsi_status; /* SCSI status. */
1709 uint16_t comp_status; /* Completion status. */
1710 uint16_t state_flags; /* State flags. */
1711 uint16_t status_flags; /* Status flags. */
1712 uint16_t rsp_info_len; /* Response Info Length. */
1713 uint16_t req_sense_length; /* Request sense data length. */
1714 uint32_t residual_length; /* Residual transfer length. */
1715 uint8_t rsp_info[8]; /* FCP response information. */
1716 uint8_t req_sense_data[32]; /* Request sense data. */
1717} sts_entry_t;
1718
1719/*
1720 * Status entry entry status
1721 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001722#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1724#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1725#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1726#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1727#define RF_BUSY BIT_1 /* Busy */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001728#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1729 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1730#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1731 RF_INV_E_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732
1733/*
1734 * Status entry SCSI status bit definitions.
1735 */
1736#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1737#define SS_RESIDUAL_UNDER BIT_11
1738#define SS_RESIDUAL_OVER BIT_10
1739#define SS_SENSE_LEN_VALID BIT_9
1740#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1741
1742#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1743#define SS_BUSY_CONDITION BIT_3
1744#define SS_CONDITION_MET BIT_2
1745#define SS_CHECK_CONDITION BIT_1
1746
1747/*
1748 * Status entry completion status
1749 */
1750#define CS_COMPLETE 0x0 /* No errors */
1751#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1752#define CS_DMA 0x2 /* A DMA direction error. */
1753#define CS_TRANSPORT 0x3 /* Transport error. */
1754#define CS_RESET 0x4 /* SCSI bus reset occurred */
1755#define CS_ABORTED 0x5 /* System aborted command. */
1756#define CS_TIMEOUT 0x6 /* Timeout error. */
1757#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
Arun Easibad75002010-05-04 15:01:30 -07001758#define CS_DIF_ERROR 0xC /* DIF error detected */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759
1760#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1761#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1762#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1763 /* (selection timeout) */
1764#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1765#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1766#define CS_PORT_BUSY 0x2B /* Port Busy */
1767#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
Chad Dupuisf934c9d2014-04-11 16:54:31 -04001768#define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1769 failure */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1771#define CS_UNKNOWN 0x81 /* Driver defined */
1772#define CS_RETRY 0x82 /* Driver defined */
1773#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1774
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04001775#define CS_BIDIR_RD_OVERRUN 0x700
1776#define CS_BIDIR_RD_WR_OVERRUN 0x707
1777#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1778#define CS_BIDIR_RD_UNDERRUN 0x1500
1779#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1780#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1781#define CS_BIDIR_DMA 0x200
Linus Torvalds1da177e2005-04-16 15:20:36 -07001782/*
1783 * Status entry status flags
1784 */
1785#define SF_ABTS_TERMINATED BIT_10
1786#define SF_LOGOUT_SENT BIT_13
1787
1788/*
1789 * ISP queue - status continuation entry structure definition.
1790 */
1791#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1792typedef struct {
1793 uint8_t entry_type; /* Entry type. */
1794 uint8_t entry_count; /* Entry count. */
1795 uint8_t sys_define; /* System defined. */
1796 uint8_t entry_status; /* Entry Status. */
1797 uint8_t data[60]; /* data */
1798} sts_cont_entry_t;
1799
1800/*
1801 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1802 * structure definition.
1803 */
1804#define STATUS_TYPE_21 0x21 /* Status entry. */
1805typedef struct {
1806 uint8_t entry_type; /* Entry type. */
1807 uint8_t entry_count; /* Entry count. */
1808 uint8_t handle_count; /* Handle count. */
1809 uint8_t entry_status; /* Entry Status. */
1810 uint32_t handle[15]; /* System handles. */
1811} sts21_entry_t;
1812
1813/*
1814 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1815 * structure definition.
1816 */
1817#define STATUS_TYPE_22 0x22 /* Status entry. */
1818typedef struct {
1819 uint8_t entry_type; /* Entry type. */
1820 uint8_t entry_count; /* Entry count. */
1821 uint8_t handle_count; /* Handle count. */
1822 uint8_t entry_status; /* Entry Status. */
1823 uint16_t handle[30]; /* System handles. */
1824} sts22_entry_t;
1825
1826/*
1827 * ISP queue - marker entry structure definition.
1828 */
1829#define MARKER_TYPE 0x04 /* Marker entry. */
1830typedef struct {
1831 uint8_t entry_type; /* Entry type. */
1832 uint8_t entry_count; /* Entry count. */
1833 uint8_t handle_count; /* Handle count. */
1834 uint8_t entry_status; /* Entry Status. */
1835 uint32_t sys_define_2; /* System defined. */
1836 target_id_t target; /* SCSI ID */
1837 uint8_t modifier; /* Modifier (7-0). */
1838#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1839#define MK_SYNC_ID 1 /* Synchronize ID */
1840#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1841#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1842 /* clear port changed, */
1843 /* use sequence number. */
1844 uint8_t reserved_1;
1845 uint16_t sequence_number; /* Sequence number of event */
1846 uint16_t lun; /* SCSI LUN */
1847 uint8_t reserved_2[48];
1848} mrk_entry_t;
1849
1850/*
1851 * ISP queue - Management Server entry structure definition.
1852 */
1853#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1854typedef struct {
1855 uint8_t entry_type; /* Entry type. */
1856 uint8_t entry_count; /* Entry count. */
1857 uint8_t handle_count; /* Handle count. */
1858 uint8_t entry_status; /* Entry Status. */
1859 uint32_t handle1; /* System handle. */
1860 target_id_t loop_id;
1861 uint16_t status;
1862 uint16_t control_flags; /* Control flags. */
1863 uint16_t reserved2;
1864 uint16_t timeout;
1865 uint16_t cmd_dsd_count;
1866 uint16_t total_dsd_count;
1867 uint8_t type;
1868 uint8_t r_ctl;
1869 uint16_t rx_id;
1870 uint16_t reserved3;
1871 uint32_t handle2;
1872 uint32_t rsp_bytecount;
1873 uint32_t req_bytecount;
1874 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1875 uint32_t dseg_req_length; /* Data segment 0 length. */
1876 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1877 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1878} ms_iocb_entry_t;
1879
1880
1881/*
1882 * ISP queue - Mailbox Command entry structure definition.
1883 */
1884#define MBX_IOCB_TYPE 0x39
1885struct mbx_entry {
1886 uint8_t entry_type;
1887 uint8_t entry_count;
1888 uint8_t sys_define1;
1889 /* Use sys_define1 for source type */
1890#define SOURCE_SCSI 0x00
1891#define SOURCE_IP 0x01
1892#define SOURCE_VI 0x02
1893#define SOURCE_SCTP 0x03
1894#define SOURCE_MP 0x04
1895#define SOURCE_MPIOCTL 0x05
1896#define SOURCE_ASYNC_IOCB 0x07
1897
1898 uint8_t entry_status;
1899
1900 uint32_t handle;
1901 target_id_t loop_id;
1902
1903 uint16_t status;
1904 uint16_t state_flags;
1905 uint16_t status_flags;
1906
1907 uint32_t sys_define2[2];
1908
1909 uint16_t mb0;
1910 uint16_t mb1;
1911 uint16_t mb2;
1912 uint16_t mb3;
1913 uint16_t mb6;
1914 uint16_t mb7;
1915 uint16_t mb9;
1916 uint16_t mb10;
1917 uint32_t reserved_2[2];
1918 uint8_t node_name[WWN_SIZE];
1919 uint8_t port_name[WWN_SIZE];
1920};
1921
1922/*
1923 * ISP request and response queue entry sizes
1924 */
1925#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1926#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1927
1928
1929/*
1930 * 24 bit port ID type definition.
1931 */
1932typedef union {
1933 uint32_t b24 : 24;
1934
1935 struct {
Malahal Nainenib889d532007-03-12 10:41:26 -07001936#ifdef __BIG_ENDIAN
1937 uint8_t domain;
1938 uint8_t area;
1939 uint8_t al_pa;
Dave Jones0fd30f72009-07-13 16:27:46 -04001940#elif defined(__LITTLE_ENDIAN)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941 uint8_t al_pa;
1942 uint8_t area;
1943 uint8_t domain;
Malahal Nainenib889d532007-03-12 10:41:26 -07001944#else
1945#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1946#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947 uint8_t rsvd_1;
1948 } b;
1949} port_id_t;
1950#define INVALID_PORT_ID 0xFFFFFF
1951
1952/*
1953 * Switch info gathering structure.
1954 */
1955typedef struct {
1956 port_id_t d_id;
1957 uint8_t node_name[WWN_SIZE];
1958 uint8_t port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001959 uint8_t fabric_port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001960 uint16_t fp_speed;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05001961 uint8_t fc4_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962} sw_info_t;
1963
Chad Dupuise8c72ba2010-07-23 15:28:25 +05001964/* FCP-4 types */
1965#define FC4_TYPE_FCP_SCSI 0x08
1966#define FC4_TYPE_OTHER 0x0
1967#define FC4_TYPE_UNKNOWN 0xff
1968
Linus Torvalds1da177e2005-04-16 15:20:36 -07001969/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001970 * Fibre channel port type.
1971 */
1972 typedef enum {
1973 FCT_UNKNOWN,
1974 FCT_RSCN,
1975 FCT_SWITCH,
1976 FCT_BROADCAST,
1977 FCT_INITIATOR,
1978 FCT_TARGET
1979} fc_port_type_t;
1980
1981/*
1982 * Fibre channel port structure.
1983 */
1984typedef struct fc_port {
1985 struct list_head list;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08001986 struct scsi_qla_host *vha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987
1988 uint8_t node_name[WWN_SIZE];
1989 uint8_t port_name[WWN_SIZE];
1990 port_id_t d_id;
1991 uint16_t loop_id;
1992 uint16_t old_loop_id;
1993
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04001994 uint16_t tgt_id;
1995 uint16_t old_tgt_id;
1996
Sarang Radke09ff7012010-03-19 17:03:59 -07001997 uint8_t fcp_prio;
1998
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001999 uint8_t fabric_port_name[WWN_SIZE];
2000 uint16_t fp_speed;
2001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002 fc_port_type_t port_type;
2003
2004 atomic_t state;
2005 uint32_t flags;
2006
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007 int login_retry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002008
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08002009 struct fc_rport *rport, *drport;
Andrew Vasquezad3e0ed2005-08-26 19:08:10 -07002010 u32 supported_classes;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07002011
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002012 uint8_t fc4_type;
Arun Easib3b02e62012-02-09 11:15:39 -08002013 uint8_t scan_state;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002014
2015 unsigned long last_queue_full;
2016 unsigned long last_ramp_up;
2017
2018 uint16_t port_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002019} fc_port_t;
2020
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002021#include "qla_mr.h"
2022
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023/*
2024 * Fibre channel port/lun states.
2025 */
2026#define FCS_UNCONFIGURED 1
2027#define FCS_DEVICE_DEAD 2
2028#define FCS_DEVICE_LOST 3
2029#define FCS_ONLINE 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07002030
Chad Dupuisec426e12011-03-30 11:46:32 -07002031static const char * const port_state_str[] = {
2032 "Unknown",
2033 "UNCONFIGURED",
2034 "DEAD",
2035 "LOST",
2036 "ONLINE"
2037};
2038
Linus Torvalds1da177e2005-04-16 15:20:36 -07002039/*
2040 * FC port flags.
2041 */
2042#define FCF_FABRIC_DEVICE BIT_0
2043#define FCF_LOGIN_NEEDED BIT_1
Andrew Vasquezf08b7252010-01-12 12:59:48 -08002044#define FCF_FCP2_DEVICE BIT_2
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07002045#define FCF_ASYNC_SENT BIT_3
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002046#define FCF_CONF_COMP_SUPPORTED BIT_4
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047
2048/* No loop ID flag. */
2049#define FC_NO_LOOP_ID 0x1000
2050
2051/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002052 * FC-CT interface
2053 *
2054 * NOTE: All structures are big-endian in form.
2055 */
2056
2057#define CT_REJECT_RESPONSE 0x8001
2058#define CT_ACCEPT_RESPONSE 0x8002
Andrew Vasquez4346b142006-12-13 19:20:28 -08002059#define CT_REASON_INVALID_COMMAND_CODE 0x01
Andrew Vasquezcca53352005-08-26 19:08:30 -07002060#define CT_REASON_CANNOT_PERFORM 0x09
Andrew Vasquez3fe7cfb2008-04-03 13:13:23 -07002061#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
Andrew Vasquezcca53352005-08-26 19:08:30 -07002062#define CT_EXPL_ALREADY_REGISTERED 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -07002063
2064#define NS_N_PORT_TYPE 0x01
2065#define NS_NL_PORT_TYPE 0x02
2066#define NS_NX_PORT_TYPE 0x7F
2067
2068#define GA_NXT_CMD 0x100
2069#define GA_NXT_REQ_SIZE (16 + 4)
2070#define GA_NXT_RSP_SIZE (16 + 620)
2071
2072#define GID_PT_CMD 0x1A1
2073#define GID_PT_REQ_SIZE (16 + 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074
2075#define GPN_ID_CMD 0x112
2076#define GPN_ID_REQ_SIZE (16 + 4)
2077#define GPN_ID_RSP_SIZE (16 + 8)
2078
2079#define GNN_ID_CMD 0x113
2080#define GNN_ID_REQ_SIZE (16 + 4)
2081#define GNN_ID_RSP_SIZE (16 + 8)
2082
2083#define GFT_ID_CMD 0x117
2084#define GFT_ID_REQ_SIZE (16 + 4)
2085#define GFT_ID_RSP_SIZE (16 + 32)
2086
2087#define RFT_ID_CMD 0x217
2088#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2089#define RFT_ID_RSP_SIZE 16
2090
2091#define RFF_ID_CMD 0x21F
2092#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2093#define RFF_ID_RSP_SIZE 16
2094
2095#define RNN_ID_CMD 0x213
2096#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2097#define RNN_ID_RSP_SIZE 16
2098
2099#define RSNN_NN_CMD 0x239
2100#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2101#define RSNN_NN_RSP_SIZE 16
2102
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002103#define GFPN_ID_CMD 0x11C
2104#define GFPN_ID_REQ_SIZE (16 + 4)
2105#define GFPN_ID_RSP_SIZE (16 + 8)
2106
2107#define GPSC_CMD 0x127
2108#define GPSC_REQ_SIZE (16 + 8)
2109#define GPSC_RSP_SIZE (16 + 2 + 2)
2110
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002111#define GFF_ID_CMD 0x011F
2112#define GFF_ID_REQ_SIZE (16 + 4)
2113#define GFF_ID_RSP_SIZE (16 + 128)
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002114
Andrew Vasquezcca53352005-08-26 19:08:30 -07002115/*
2116 * HBA attribute types.
2117 */
2118#define FDMI_HBA_ATTR_COUNT 9
2119#define FDMI_HBA_NODE_NAME 1
2120#define FDMI_HBA_MANUFACTURER 2
2121#define FDMI_HBA_SERIAL_NUMBER 3
2122#define FDMI_HBA_MODEL 4
2123#define FDMI_HBA_MODEL_DESCRIPTION 5
2124#define FDMI_HBA_HARDWARE_VERSION 6
2125#define FDMI_HBA_DRIVER_VERSION 7
2126#define FDMI_HBA_OPTION_ROM_VERSION 8
2127#define FDMI_HBA_FIRMWARE_VERSION 9
2128#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2129#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2130
2131struct ct_fdmi_hba_attr {
2132 uint16_t type;
2133 uint16_t len;
2134 union {
2135 uint8_t node_name[WWN_SIZE];
2136 uint8_t manufacturer[32];
2137 uint8_t serial_num[8];
2138 uint8_t model[16];
2139 uint8_t model_desc[80];
2140 uint8_t hw_version[16];
2141 uint8_t driver_version[32];
2142 uint8_t orom_version[16];
2143 uint8_t fw_version[16];
2144 uint8_t os_version[128];
2145 uint8_t max_ct_len[4];
2146 } a;
2147};
2148
2149struct ct_fdmi_hba_attributes {
2150 uint32_t count;
2151 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2152};
2153
2154/*
2155 * Port attribute types.
2156 */
Andrew Vasquez8a85e1712007-09-20 14:07:41 -07002157#define FDMI_PORT_ATTR_COUNT 6
Andrew Vasquezcca53352005-08-26 19:08:30 -07002158#define FDMI_PORT_FC4_TYPES 1
2159#define FDMI_PORT_SUPPORT_SPEED 2
2160#define FDMI_PORT_CURRENT_SPEED 3
2161#define FDMI_PORT_MAX_FRAME_SIZE 4
2162#define FDMI_PORT_OS_DEVICE_NAME 5
2163#define FDMI_PORT_HOST_NAME 6
2164
Andrew Vasquez58815692007-07-19 15:05:58 -07002165#define FDMI_PORT_SPEED_1GB 0x1
2166#define FDMI_PORT_SPEED_2GB 0x2
2167#define FDMI_PORT_SPEED_10GB 0x4
2168#define FDMI_PORT_SPEED_4GB 0x8
2169#define FDMI_PORT_SPEED_8GB 0x10
2170#define FDMI_PORT_SPEED_16GB 0x20
Chad Dupuisf73cb692014-02-26 04:15:06 -05002171#define FDMI_PORT_SPEED_32GB 0x40
Andrew Vasquez58815692007-07-19 15:05:58 -07002172#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2173
Andrew Vasquezcca53352005-08-26 19:08:30 -07002174struct ct_fdmi_port_attr {
2175 uint16_t type;
2176 uint16_t len;
2177 union {
2178 uint8_t fc4_types[32];
2179 uint32_t sup_speed;
2180 uint32_t cur_speed;
2181 uint32_t max_frame_size;
2182 uint8_t os_dev_name[32];
2183 uint8_t host_name[32];
2184 } a;
2185};
2186
2187/*
2188 * Port Attribute Block.
2189 */
2190struct ct_fdmi_port_attributes {
2191 uint32_t count;
2192 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2193};
2194
2195/* FDMI definitions. */
2196#define GRHL_CMD 0x100
2197#define GHAT_CMD 0x101
2198#define GRPL_CMD 0x102
2199#define GPAT_CMD 0x110
2200
2201#define RHBA_CMD 0x200
2202#define RHBA_RSP_SIZE 16
2203
2204#define RHAT_CMD 0x201
2205#define RPRT_CMD 0x210
2206
2207#define RPA_CMD 0x211
2208#define RPA_RSP_SIZE 16
2209
2210#define DHBA_CMD 0x300
2211#define DHBA_REQ_SIZE (16 + 8)
2212#define DHBA_RSP_SIZE 16
2213
2214#define DHAT_CMD 0x301
2215#define DPRT_CMD 0x310
2216#define DPA_CMD 0x311
2217
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218/* CT command header -- request/response common fields */
2219struct ct_cmd_hdr {
2220 uint8_t revision;
2221 uint8_t in_id[3];
2222 uint8_t gs_type;
2223 uint8_t gs_subtype;
2224 uint8_t options;
2225 uint8_t reserved;
2226};
2227
2228/* CT command request */
2229struct ct_sns_req {
2230 struct ct_cmd_hdr header;
2231 uint16_t command;
2232 uint16_t max_rsp_size;
2233 uint8_t fragment_id;
2234 uint8_t reserved[3];
2235
2236 union {
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002237 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002238 struct {
2239 uint8_t reserved;
2240 uint8_t port_id[3];
2241 } port_id;
2242
2243 struct {
2244 uint8_t port_type;
2245 uint8_t domain;
2246 uint8_t area;
2247 uint8_t reserved;
2248 } gid_pt;
2249
2250 struct {
2251 uint8_t reserved;
2252 uint8_t port_id[3];
2253 uint8_t fc4_types[32];
2254 } rft_id;
2255
2256 struct {
2257 uint8_t reserved;
2258 uint8_t port_id[3];
2259 uint16_t reserved2;
2260 uint8_t fc4_feature;
2261 uint8_t fc4_type;
2262 } rff_id;
2263
2264 struct {
2265 uint8_t reserved;
2266 uint8_t port_id[3];
2267 uint8_t node_name[8];
2268 } rnn_id;
2269
2270 struct {
2271 uint8_t node_name[8];
2272 uint8_t name_len;
2273 uint8_t sym_node_name[255];
2274 } rsnn_nn;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002275
2276 struct {
2277 uint8_t hba_indentifier[8];
2278 } ghat;
2279
2280 struct {
2281 uint8_t hba_identifier[8];
2282 uint32_t entry_count;
2283 uint8_t port_name[8];
2284 struct ct_fdmi_hba_attributes attrs;
2285 } rhba;
2286
2287 struct {
2288 uint8_t hba_identifier[8];
2289 struct ct_fdmi_hba_attributes attrs;
2290 } rhat;
2291
2292 struct {
2293 uint8_t port_name[8];
2294 struct ct_fdmi_port_attributes attrs;
2295 } rpa;
2296
2297 struct {
2298 uint8_t port_name[8];
2299 } dhba;
2300
2301 struct {
2302 uint8_t port_name[8];
2303 } dhat;
2304
2305 struct {
2306 uint8_t port_name[8];
2307 } dprt;
2308
2309 struct {
2310 uint8_t port_name[8];
2311 } dpa;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002312
2313 struct {
2314 uint8_t port_name[8];
2315 } gpsc;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002316
2317 struct {
2318 uint8_t reserved;
2319 uint8_t port_name[3];
2320 } gff_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002321 } req;
2322};
2323
2324/* CT command response header */
2325struct ct_rsp_hdr {
2326 struct ct_cmd_hdr header;
2327 uint16_t response;
2328 uint16_t residual;
2329 uint8_t fragment_id;
2330 uint8_t reason_code;
2331 uint8_t explanation_code;
2332 uint8_t vendor_unique;
2333};
2334
2335struct ct_sns_gid_pt_data {
2336 uint8_t control_byte;
2337 uint8_t port_id[3];
2338};
2339
2340struct ct_sns_rsp {
2341 struct ct_rsp_hdr header;
2342
2343 union {
2344 struct {
2345 uint8_t port_type;
2346 uint8_t port_id[3];
2347 uint8_t port_name[8];
2348 uint8_t sym_port_name_len;
2349 uint8_t sym_port_name[255];
2350 uint8_t node_name[8];
2351 uint8_t sym_node_name_len;
2352 uint8_t sym_node_name[255];
2353 uint8_t init_proc_assoc[8];
2354 uint8_t node_ip_addr[16];
2355 uint8_t class_of_service[4];
2356 uint8_t fc4_types[32];
2357 uint8_t ip_address[16];
2358 uint8_t fabric_port_name[8];
2359 uint8_t reserved;
2360 uint8_t hard_address[3];
2361 } ga_nxt;
2362
2363 struct {
Chad Dupuis642ef982012-02-09 11:15:57 -08002364 /* Assume the largest number of targets for the union */
2365 struct ct_sns_gid_pt_data
2366 entries[MAX_FIBRE_DEVICES_MAX];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002367 } gid_pt;
2368
2369 struct {
2370 uint8_t port_name[8];
2371 } gpn_id;
2372
2373 struct {
2374 uint8_t node_name[8];
2375 } gnn_id;
2376
2377 struct {
2378 uint8_t fc4_types[32];
2379 } gft_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002380
2381 struct {
2382 uint32_t entry_count;
2383 uint8_t port_name[8];
2384 struct ct_fdmi_hba_attributes attrs;
2385 } ghat;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002386
2387 struct {
2388 uint8_t port_name[8];
2389 } gfpn_id;
2390
2391 struct {
2392 uint16_t speeds;
2393 uint16_t speed;
2394 } gpsc;
Chad Dupuise8c72ba2010-07-23 15:28:25 +05002395
2396#define GFF_FCP_SCSI_OFFSET 7
2397 struct {
2398 uint8_t fc4_features[128];
2399 } gff_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400 } rsp;
2401};
2402
2403struct ct_sns_pkt {
2404 union {
2405 struct ct_sns_req req;
2406 struct ct_sns_rsp rsp;
2407 } p;
2408};
2409
2410/*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002411 * SNS command structures -- for 2200 compatibility.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412 */
2413#define RFT_ID_SNS_SCMD_LEN 22
2414#define RFT_ID_SNS_CMD_SIZE 60
2415#define RFT_ID_SNS_DATA_SIZE 16
2416
2417#define RNN_ID_SNS_SCMD_LEN 10
2418#define RNN_ID_SNS_CMD_SIZE 36
2419#define RNN_ID_SNS_DATA_SIZE 16
2420
2421#define GA_NXT_SNS_SCMD_LEN 6
2422#define GA_NXT_SNS_CMD_SIZE 28
2423#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2424
2425#define GID_PT_SNS_SCMD_LEN 6
2426#define GID_PT_SNS_CMD_SIZE 28
Chad Dupuis642ef982012-02-09 11:15:57 -08002427/*
2428 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2429 * adapters.
2430 */
2431#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002432
2433#define GPN_ID_SNS_SCMD_LEN 6
2434#define GPN_ID_SNS_CMD_SIZE 28
2435#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2436
2437#define GNN_ID_SNS_SCMD_LEN 6
2438#define GNN_ID_SNS_CMD_SIZE 28
2439#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2440
2441struct sns_cmd_pkt {
2442 union {
2443 struct {
2444 uint16_t buffer_length;
2445 uint16_t reserved_1;
2446 uint32_t buffer_address[2];
2447 uint16_t subcommand_length;
2448 uint16_t reserved_2;
2449 uint16_t subcommand;
2450 uint16_t size;
2451 uint32_t reserved_3;
2452 uint8_t param[36];
2453 } cmd;
2454
2455 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2456 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2457 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2458 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2459 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2460 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2461 } p;
2462};
2463
Andrew Vasquez54333832005-11-09 15:49:04 -08002464struct fw_blob {
2465 char *name;
2466 uint32_t segs[4];
2467 const struct firmware *fw;
2468};
2469
Linus Torvalds1da177e2005-04-16 15:20:36 -07002470/* Return data from MBC_GET_ID_LIST call. */
2471struct gid_list_info {
2472 uint8_t al_pa;
2473 uint8_t area;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002474 uint8_t domain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002475 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2476 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002477 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002479
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002480/* NPIV */
2481typedef struct vport_info {
2482 uint8_t port_name[WWN_SIZE];
2483 uint8_t node_name[WWN_SIZE];
2484 int vp_id;
2485 uint16_t loop_id;
2486 unsigned long host_no;
2487 uint8_t port_id[3];
2488 int loop_state;
2489} vport_info_t;
2490
2491typedef struct vport_params {
2492 uint8_t port_name[WWN_SIZE];
2493 uint8_t node_name[WWN_SIZE];
2494 uint32_t options;
2495#define VP_OPTS_RETRY_ENABLE BIT_0
2496#define VP_OPTS_VP_DISABLE BIT_1
2497} vport_params_t;
2498
2499/* NPIV - return codes of VP create and modify */
2500#define VP_RET_CODE_OK 0
2501#define VP_RET_CODE_FATAL 1
2502#define VP_RET_CODE_WRONG_ID 2
2503#define VP_RET_CODE_WWPN 3
2504#define VP_RET_CODE_RESOURCES 4
2505#define VP_RET_CODE_NO_MEM 5
2506#define VP_RET_CODE_NOT_FOUND 6
2507
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002508struct qla_hw_data;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07002509struct rsp_que;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002510/*
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002511 * ISP operations
2512 */
2513struct isp_operations {
2514
2515 int (*pci_config) (struct scsi_qla_host *);
2516 void (*reset_chip) (struct scsi_qla_host *);
2517 int (*chip_diag) (struct scsi_qla_host *);
2518 void (*config_rings) (struct scsi_qla_host *);
2519 void (*reset_adapter) (struct scsi_qla_host *);
2520 int (*nvram_config) (struct scsi_qla_host *);
2521 void (*update_fw_options) (struct scsi_qla_host *);
2522 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2523
2524 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2525 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2526
David Howells7d12e782006-10-05 14:55:46 +01002527 irq_handler_t intr_handler;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002528 void (*enable_intrs) (struct qla_hw_data *);
2529 void (*disable_intrs) (struct qla_hw_data *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002530
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07002531 int (*abort_command) (srb_t *);
Hannes Reinecke9cb78c12014-06-25 15:27:36 +02002532 int (*target_reset) (struct fc_port *, uint64_t, int);
2533 int (*lun_reset) (struct fc_port *, uint64_t, int);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002534 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2535 uint8_t, uint8_t, uint16_t *, uint8_t);
Andrew Vasquez1c7c6352005-07-06 10:30:57 -07002536 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2537 uint8_t, uint8_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002538
2539 uint16_t (*calc_req_entries) (uint16_t);
2540 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
Andrew Vasquez8c958a92005-07-06 10:30:47 -07002541 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
Andrew Vasquezcca53352005-08-26 19:08:30 -07002542 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2543 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002544
2545 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2546 uint32_t, uint32_t);
2547 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2548 uint32_t);
2549
2550 void (*fw_dump) (struct scsi_qla_host *, int);
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002551
2552 int (*beacon_on) (struct scsi_qla_host *);
2553 int (*beacon_off) (struct scsi_qla_host *);
2554 void (*beacon_blink) (struct scsi_qla_host *);
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002555
2556 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2557 uint32_t, uint32_t);
2558 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2559 uint32_t);
Andrew Vasquez30c47662007-01-29 10:22:21 -08002560
2561 int (*get_flash_version) (struct scsi_qla_host *, void *);
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002562 int (*start_scsi) (srb_t *);
Giridhar Malavalia9083012010-04-12 17:59:55 -07002563 int (*abort_isp) (struct scsi_qla_host *);
Giridhar Malavali706f4572011-11-18 09:03:16 -08002564 int (*iospace_config)(struct qla_hw_data*);
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002565 int (*initialize_adapter)(struct scsi_qla_host *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002566};
2567
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002568/* MSI-X Support *************************************************************/
2569
2570#define QLA_MSIX_CHIP_REV_24XX 3
2571#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2572#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2573
2574#define QLA_MSIX_DEFAULT 0x00
2575#define QLA_MSIX_RSP_Q 0x01
2576
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002577#define QLA_MIDX_DEFAULT 0
2578#define QLA_MIDX_RSP_Q 1
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002579#define QLA_PCI_MSIX_CONTROL 0xa2
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002580#define QLA_83XX_PCI_MSIX_CONTROL 0x92
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002581
2582struct scsi_qla_host;
2583
2584struct qla_msix_entry {
2585 int have_irq;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002586 uint32_t vector;
2587 uint16_t entry;
2588 struct rsp_que *rsp;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002589};
2590
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002591#define WATCH_INTERVAL 1 /* number of seconds */
2592
Andrew Vasquez0971de72008-04-03 13:13:18 -07002593/* Work events. */
2594enum qla_work_type {
2595 QLA_EVT_AEN,
Andrew Vasquez8a659572009-02-08 20:50:12 -08002596 QLA_EVT_IDC_ACK,
Andrew Vasquezac280b62009-08-20 11:06:05 -07002597 QLA_EVT_ASYNC_LOGIN,
2598 QLA_EVT_ASYNC_LOGIN_DONE,
2599 QLA_EVT_ASYNC_LOGOUT,
2600 QLA_EVT_ASYNC_LOGOUT_DONE,
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07002601 QLA_EVT_ASYNC_ADISC,
2602 QLA_EVT_ASYNC_ADISC_DONE,
Andrew Vasquez3420d362009-10-13 15:16:45 -07002603 QLA_EVT_UEVENT,
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002604 QLA_EVT_AENFX,
Andrew Vasquez0971de72008-04-03 13:13:18 -07002605};
2606
2607
2608struct qla_work_evt {
2609 struct list_head list;
2610 enum qla_work_type type;
2611 u32 flags;
2612#define QLA_EVT_FLAG_FREE 0x1
2613
2614 union {
2615 struct {
2616 enum fc_host_event_code code;
2617 u32 data;
2618 } aen;
Andrew Vasquez8a659572009-02-08 20:50:12 -08002619 struct {
2620#define QLA_IDC_ACK_REGS 7
2621 uint16_t mb[QLA_IDC_ACK_REGS];
2622 } idc_ack;
Andrew Vasquezac280b62009-08-20 11:06:05 -07002623 struct {
2624 struct fc_port *fcport;
2625#define QLA_LOGIO_LOGIN_RETRIED BIT_0
2626 u16 data[2];
2627 } logio;
Andrew Vasquez3420d362009-10-13 15:16:45 -07002628 struct {
2629 u32 code;
2630#define QLA_UEVENT_CODE_FW_DUMP 0
2631 } uevent;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002632 struct {
2633 uint32_t evtcode;
2634 uint32_t mbx[8];
2635 uint32_t count;
2636 } aenfx;
2637 struct {
2638 srb_t *sp;
2639 } iosb;
2640 } u;
Andrew Vasquez0971de72008-04-03 13:13:18 -07002641};
2642
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002643struct qla_chip_state_84xx {
2644 struct list_head list;
2645 struct kref kref;
2646
2647 void *bus;
2648 spinlock_t access_lock;
2649 struct mutex fw_update_mutex;
2650 uint32_t fw_update;
2651 uint32_t op_fw_version;
2652 uint32_t op_fw_size;
2653 uint32_t op_fw_seq_size;
2654 uint32_t diag_fw_version;
2655 uint32_t gold_fw_version;
2656};
2657
Harish Zunjarraoe5f5f6f2008-07-10 16:55:49 -07002658struct qla_statistics {
2659 uint32_t total_isp_aborts;
Harish Zunjarrao49fd4622008-09-11 21:22:47 -07002660 uint64_t input_bytes;
2661 uint64_t output_bytes;
Joe Carnucciofabbb8d2013-08-27 01:37:40 -04002662 uint64_t input_requests;
2663 uint64_t output_requests;
2664 uint32_t control_requests;
2665
2666 uint64_t jiffies_at_last_reset;
Harish Zunjarraoe5f5f6f2008-07-10 16:55:49 -07002667};
2668
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04002669struct bidi_statistics {
2670 unsigned long long io_count;
2671 unsigned long long transfer_bytes;
2672};
2673
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002674/* Multi queue support */
2675#define MBC_INITIALIZE_MULTIQ 0x1f
2676#define QLA_QUE_PAGE 0X1000
2677#define QLA_MQ_SIZE 32
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002678#define QLA_MAX_QUEUES 256
2679#define ISP_QUE_REG(ha, id) \
Chad Dupuisf73cb692014-02-26 04:15:06 -05002680 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
Andrew Vasquezda9b1d52013-08-27 01:37:30 -04002681 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
2682 ((void __iomem *)ha->iobase))
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002683#define QLA_REQ_QUE_ID(tag) \
2684 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2685#define QLA_DEFAULT_QUE_QOS 5
2686#define QLA_PRECONFIG_VPORTS 32
2687#define QLA_MAX_VPORTS_QLA24XX 128
2688#define QLA_MAX_VPORTS_QLA25XX 256
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002689/* Response queue data structure */
2690struct rsp_que {
2691 dma_addr_t dma;
2692 response_t *ring;
2693 response_t *ring_ptr;
Andrew Vasquez08029992009-03-24 09:07:55 -07002694 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2695 uint32_t __iomem *rsp_q_out;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002696 uint16_t ring_index;
2697 uint16_t out_ptr;
Joe Carnuccio7c6300e2014-04-11 16:54:37 -04002698 uint16_t *in_ptr; /* queue shadow in index */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002699 uint16_t length;
2700 uint16_t options;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002701 uint16_t rid;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002702 uint16_t id;
2703 uint16_t vp_idx;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002704 struct qla_hw_data *hw;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002705 struct qla_msix_entry *msix;
2706 struct req_que *req;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07002707 srb_t *status_srb; /* status continuation entry */
Anirban Chakraborty68ca9492009-04-06 22:33:41 -07002708 struct work_struct q_work;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002709
2710 dma_addr_t dma_fx00;
2711 response_t *ring_fx00;
2712 uint16_t length_fx00;
2713 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002714};
2715
2716/* Request queue data structure */
2717struct req_que {
2718 dma_addr_t dma;
2719 request_t *ring;
2720 request_t *ring_ptr;
Andrew Vasquez08029992009-03-24 09:07:55 -07002721 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2722 uint32_t __iomem *req_q_out;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002723 uint16_t ring_index;
2724 uint16_t in_ptr;
Joe Carnuccio7c6300e2014-04-11 16:54:37 -04002725 uint16_t *out_ptr; /* queue shadow out index */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002726 uint16_t cnt;
2727 uint16_t length;
2728 uint16_t options;
2729 uint16_t rid;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002730 uint16_t id;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002731 uint16_t qos;
2732 uint16_t vp_idx;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002733 struct rsp_que *rsp;
Chad Dupuis8d93f552013-01-30 03:34:37 -05002734 srb_t **outstanding_cmds;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002735 uint32_t current_outstanding_cmd;
Chad Dupuis8d93f552013-01-30 03:34:37 -05002736 uint16_t num_outstanding_cmds;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002737 int max_q_depth;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002738
2739 dma_addr_t dma_fx00;
2740 request_t *ring_fx00;
2741 uint16_t length_fx00;
2742 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002743};
2744
Giridhar Malavali9a069e12010-01-12 13:02:47 -08002745/* Place holder for FW buffer parameters */
2746struct qlfc_fw {
2747 void *fw_buf;
2748 dma_addr_t fw_dma;
2749 uint32_t len;
2750};
2751
Saurav Kashyap0e8cd712014-01-14 20:40:38 -08002752struct scsi_qlt_host {
2753 void *target_lport_ptr;
2754 struct mutex tgt_mutex;
2755 struct mutex tgt_host_action_mutex;
2756 struct qla_tgt *qla_tgt;
2757};
2758
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002759struct qlt_hw_data {
2760 /* Protected by hw lock */
2761 uint32_t enable_class_2:1;
2762 uint32_t enable_explicit_conf:1;
2763 uint32_t ini_mode_force_reverse:1;
2764 uint32_t node_name_set:1;
2765
2766 dma_addr_t atio_dma; /* Physical address. */
2767 struct atio *atio_ring; /* Base virtual address */
2768 struct atio *atio_ring_ptr; /* Current address. */
2769 uint16_t atio_ring_index; /* Current index. */
2770 uint16_t atio_q_length;
Arun Easiaa230bc2013-01-30 03:34:39 -05002771 uint32_t __iomem *atio_q_in;
2772 uint32_t __iomem *atio_q_out;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002773
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002774 struct qla_tgt_func_tmpl *tgt_ops;
Chad Dupuis8d93f552013-01-30 03:34:37 -05002775 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002776 uint16_t current_handle;
2777
2778 struct qla_tgt_vp_map *tgt_vp_map;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002779
2780 int saved_set;
2781 uint16_t saved_exchange_count;
2782 uint32_t saved_firmware_options_1;
2783 uint32_t saved_firmware_options_2;
2784 uint32_t saved_firmware_options_3;
2785 uint8_t saved_firmware_options[2];
2786 uint8_t saved_add_firmware_options[2];
2787
2788 uint8_t tgt_node_name[WWN_SIZE];
2789};
2790
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002791/*
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002792 * Qlogic host adapter specific data structure.
2793*/
2794struct qla_hw_data {
2795 struct pci_dev *pdev;
2796 /* SRB cache. */
2797#define SRB_MIN_REQ 128
2798 mempool_t *srb_mempool;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002799
2800 volatile struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002801 uint32_t mbox_int :1;
2802 uint32_t mbox_busy :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002803 uint32_t disable_risc_code_load :1;
2804 uint32_t enable_64bit_addressing :1;
2805 uint32_t enable_lip_reset :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002806 uint32_t enable_target_reset :1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002807 uint32_t enable_lip_full_login :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002808 uint32_t enable_led_scheme :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08002809
Andrew Vasquez3d716442005-07-06 10:30:26 -07002810 uint32_t msi_enabled :1;
2811 uint32_t msix_enabled :1;
Andrew Vasquezd4c760c2006-06-23 16:10:39 -07002812 uint32_t disable_serdes :1;
Andrew Vasquez4346b142006-12-13 19:20:28 -08002813 uint32_t gpsc_supported :1;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002814 uint32_t npiv_supported :1;
Andrew Vasquez85880802009-12-15 21:29:46 -08002815 uint32_t pci_channel_io_perm_failure :1;
Andrew Vasquezdf613b92008-01-17 09:02:17 -08002816 uint32_t fce_enabled :1;
Joe Carnuccio1d2874d2009-03-24 09:08:06 -07002817 uint32_t fac_supported :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08002818
Lalit Chandivade2533cf62009-03-24 09:08:07 -07002819 uint32_t chip_reset_done :1;
Andrew Vasquezcbc8eb62009-06-03 09:55:17 -07002820 uint32_t running_gold_fw :1;
Andrew Vasquez85880802009-12-15 21:29:46 -08002821 uint32_t eeh_busy :1;
Anirban Chakraborty7163ea82009-08-05 09:18:40 -07002822 uint32_t cpu_affinity_enabled :1;
Anirban Chakraborty31557542009-12-02 10:36:55 -08002823 uint32_t disable_msix_handshake :1;
Sarang Radke09ff7012010-03-19 17:03:59 -07002824 uint32_t fcp_prio_enabled :1;
Giridhar Malavali71905752011-02-23 15:27:10 -08002825 uint32_t isp82xx_fw_hung:1;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04002826 uint32_t nic_core_hung:1;
Giridhar Malavali71905752011-02-23 15:27:10 -08002827
2828 uint32_t quiesce_owner:1;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04002829 uint32_t nic_core_reset_hdlr_active:1;
2830 uint32_t nic_core_reset_owner:1;
Giridhar Malavalib6d0d9d2012-05-15 14:34:25 -04002831 uint32_t isp82xx_no_md_cap:1;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04002832 uint32_t host_shutting_down:1;
Chad Dupuisbf5b8ad2012-08-22 14:21:24 -04002833 uint32_t idc_compl_status:1;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002834
2835 uint32_t mr_reset_hdlr_active:1;
2836 uint32_t mr_intr_valid:1;
2837 /* 34 bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002838 } flags;
2839
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002840 /* This spinlock is used to protect "io transactions", you must
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002841 * acquire it before doing any IO to the card, eg with RD_REG*() and
2842 * WRT_REG*() for the duration of your entire commandtransaction.
2843 *
2844 * This spinlock is of lower priority than the io request lock.
2845 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002846
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002847 spinlock_t hardware_lock ____cacheline_aligned;
Andrew Vasquez285d0322007-10-19 15:59:17 -07002848 int bars;
Benjamin Herrenschmidt09483912007-12-20 15:28:09 +11002849 int mem_only;
Chad Dupuisf73cb692014-02-26 04:15:06 -05002850 device_reg_t *iobase; /* Base I/O address */
Andrew Vasquez37765412008-01-17 09:02:09 -08002851 resource_size_t pio_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002852
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002853#define MIN_IOBASE_LEN 0x100
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002854 dma_addr_t bar0_hdl;
2855
2856 void __iomem *cregbase;
2857 dma_addr_t bar2_hdl;
2858#define BAR0_LEN_FX00 (1024 * 1024)
2859#define BAR2_LEN_FX00 (128 * 1024)
2860
2861 uint32_t rqstq_intr_code;
2862 uint32_t mbx_intr_code;
2863 uint32_t req_que_len;
2864 uint32_t rsp_que_len;
2865 uint32_t req_que_off;
2866 uint32_t rsp_que_off;
2867
2868 /* Multi queue data structs */
Chad Dupuisf73cb692014-02-26 04:15:06 -05002869 device_reg_t *mqiobase;
2870 device_reg_t *msixbase;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002871 uint16_t msix_count;
2872 uint8_t mqenable;
2873 struct req_que **req_q_map;
2874 struct rsp_que **rsp_q_map;
2875 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2876 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07002877 uint8_t max_req_queues;
2878 uint8_t max_rsp_queues;
Anirban Chakraborty73208df2008-12-09 16:45:39 -08002879 struct qla_npiv_entry *npiv_info;
2880 uint16_t nvram_npiv_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002881
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002882 uint16_t switch_cap;
2883#define FLOGI_SEQ_DEL BIT_8
2884#define FLOGI_MID_SUPPORT BIT_10
2885#define FLOGI_VSAN_SUPPORT BIT_12
2886#define FLOGI_SP_SUPPORT BIT_13
Anirban Chakrabortye5b68a62009-04-06 22:33:50 -07002887
2888 uint8_t port_no; /* Physical port of adapter */
2889
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002890 /* Timeout timers. */
2891 uint8_t loop_down_abort_time; /* port down timer */
2892 atomic_t loop_down_timer; /* loop down timer */
2893 uint8_t link_down_timeout; /* link down timeout */
2894 uint16_t max_loop_id;
Chad Dupuis642ef982012-02-09 11:15:57 -08002895 uint16_t max_fibre_devices; /* Maximum number of targets */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002896
Linus Torvalds1da177e2005-04-16 15:20:36 -07002897 uint16_t fb_rev;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002898 uint16_t min_external_loopid; /* First external loop Id */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002899
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002900#define PORT_SPEED_UNKNOWN 0xFFFF
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002901#define PORT_SPEED_1GB 0x00
2902#define PORT_SPEED_2GB 0x01
2903#define PORT_SPEED_4GB 0x03
2904#define PORT_SPEED_8GB 0x04
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002905#define PORT_SPEED_16GB 0x05
Chad Dupuisf73cb692014-02-26 04:15:06 -05002906#define PORT_SPEED_32GB 0x06
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08002907#define PORT_SPEED_10GB 0x13
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002908 uint16_t link_data_rate; /* F/W operating speed */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002909
2910 uint8_t current_topology;
2911 uint8_t prev_topology;
2912#define ISP_CFG_NL 1
2913#define ISP_CFG_N 2
2914#define ISP_CFG_FL 4
2915#define ISP_CFG_F 8
2916
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002917 uint8_t operating_mode; /* F/W operating mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002918#define LOOP 0
2919#define P2P 1
2920#define LOOP_P2P 2
2921#define P2P_LOOP 3
Linus Torvalds1da177e2005-04-16 15:20:36 -07002922 uint8_t interrupts_on;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002923 uint32_t isp_abort_cnt;
2924
2925#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2926#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08002927#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002928#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
2929#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
Chad Dupuisf73cb692014-02-26 04:15:06 -05002930#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04002931#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
2932
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002933 uint32_t device_type;
2934#define DT_ISP2100 BIT_0
2935#define DT_ISP2200 BIT_1
2936#define DT_ISP2300 BIT_2
2937#define DT_ISP2312 BIT_3
2938#define DT_ISP2322 BIT_4
2939#define DT_ISP6312 BIT_5
2940#define DT_ISP6322 BIT_6
2941#define DT_ISP2422 BIT_7
2942#define DT_ISP2432 BIT_8
2943#define DT_ISP5422 BIT_9
2944#define DT_ISP5432 BIT_10
2945#define DT_ISP2532 BIT_11
2946#define DT_ISP8432 BIT_12
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08002947#define DT_ISP8001 BIT_13
Giridhar Malavalia9083012010-04-12 17:59:55 -07002948#define DT_ISP8021 BIT_14
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002949#define DT_ISP2031 BIT_15
2950#define DT_ISP8031 BIT_16
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002951#define DT_ISPFX00 BIT_17
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002952#define DT_ISP8044 BIT_18
Chad Dupuisf73cb692014-02-26 04:15:06 -05002953#define DT_ISP2071 BIT_19
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04002954#define DT_ISP2271 BIT_20
2955#define DT_ISP_LAST (DT_ISP2271 << 1)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002956
Arun Easie02587d2011-08-16 11:29:23 -07002957#define DT_T10_PI BIT_25
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002958#define DT_IIDMA BIT_26
2959#define DT_FWI2 BIT_27
2960#define DT_ZIO_SUPPORTED BIT_28
2961#define DT_OEM_001 BIT_29
2962#define DT_ISP2200A BIT_30
2963#define DT_EXTENDED_IDS BIT_31
2964#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2965#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2966#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2967#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2968#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2969#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2970#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2971#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2972#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2973#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2974#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2975#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2976#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2977#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08002978#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002979#define IS_QLA81XX(ha) (IS_QLA8001(ha))
Giridhar Malavalia9083012010-04-12 17:59:55 -07002980#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002981#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002982#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
2983#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04002984#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
Chad Dupuisf73cb692014-02-26 04:15:06 -05002985#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04002986#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002987
2988#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2989 IS_QLA6312(ha) || IS_QLA6322(ha))
2990#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2991#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2992#define IS_QLA25XX(ha) (IS_QLA2532(ha))
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002993#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002994#define IS_QLA84XX(ha) (IS_QLA8432(ha))
Joe Carnuccio2c5bbbb2014-04-11 16:54:13 -04002995#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08002996#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2997 IS_QLA84XX(ha))
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08002998#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002999 IS_QLA8031(ha) || IS_QLA8044(ha))
3000#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003001#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
Giridhar Malavalia9083012010-04-12 17:59:55 -07003002 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003003 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
Chad Dupuisf73cb692014-02-26 04:15:06 -05003004 IS_QLA8044(ha) || IS_QLA27XX(ha))
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08003005#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha))
Giridhar Malavalib77ed252014-02-26 04:15:12 -05003006#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
Chad Dupuisf73cb692014-02-26 04:15:06 -05003007#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3008 IS_QLA27XX(ha))
3009#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3010 IS_QLA27XX(ha))
Andrew Vasquezac280b62009-08-20 11:06:05 -07003011#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003012
Arun Easie02587d2011-08-16 11:29:23 -07003013#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003014#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3015#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3016#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3017#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3018#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08003019#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
Chad Dupuisf73cb692014-02-26 04:15:06 -05003020#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3021 IS_QLA27XX(ha))
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04003022#define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
Saurav Kashyap81178772012-08-22 14:21:04 -04003023/* Bit 21 of fw_attributes decides the MCTP capabilities */
3024#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3025 ((ha)->fw_attributes_ext[0] & BIT_0))
Arun Easi9e522cd2012-08-22 14:21:31 -04003026#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha))
3027#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha))
3028#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3029#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha))
3030#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3031 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
Arun Easiaa230bc2013-01-30 03:34:39 -05003032#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha))
Arun Easi33c36c02013-01-30 03:34:41 -05003033#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
Joe Carnuccio7c6300e2014-04-11 16:54:37 -04003034#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003035
3036 /* HBA serial number */
3037 uint8_t serial0;
3038 uint8_t serial1;
3039 uint8_t serial2;
3040
3041 /* NVRAM configuration data */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003042#define MAX_NVRAM_SIZE 4096
3043#define VPD_OFFSET MAX_NVRAM_SIZE / 2
Andrew Vasquez3d716442005-07-06 10:30:26 -07003044 uint16_t nvram_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003045 uint16_t nvram_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07003046 void *nvram;
andrew.vasquez@qlogic.com6f641792006-03-09 14:27:34 -08003047 uint16_t vpd_size;
3048 uint16_t vpd_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07003049 void *vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003050
3051 uint16_t loop_reset_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003052 uint8_t retry_count;
3053 uint8_t login_timeout;
3054 uint16_t r_a_tov;
3055 int port_down_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003056 uint8_t mbx_count;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003057 uint8_t aen_mbx_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003058
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003059 uint32_t login_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003060 /* SNS command interfaces. */
3061 ms_iocb_entry_t *ms_iocb;
3062 dma_addr_t ms_iocb_dma;
3063 struct ct_sns_pkt *ct_sns;
3064 dma_addr_t ct_sns_dma;
3065 /* SNS command interfaces for 2200. */
3066 struct sns_cmd_pkt *sns_cmd;
3067 dma_addr_t sns_cmd_dma;
3068
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003069#define SFP_DEV_SIZE 256
3070#define SFP_BLOCK_SIZE 64
3071 void *sfp_data;
3072 dma_addr_t sfp_data_dma;
Andrew Vasquez88729e52006-06-23 16:10:50 -07003073
Giridhar Malavalib5d03292009-10-13 15:16:48 -07003074#define XGMAC_DATA_SIZE 4096
Andrew Vasquezce0423f2009-06-03 09:55:13 -07003075 void *xgmac_data;
3076 dma_addr_t xgmac_data_dma;
3077
Giridhar Malavalib5d03292009-10-13 15:16:48 -07003078#define DCBX_TLV_DATA_SIZE 4096
Andrew Vasquez11bbc1d2009-06-03 09:55:14 -07003079 void *dcbx_tlv;
3080 dma_addr_t dcbx_tlv_dma;
3081
Christoph Hellwig39a11242006-02-14 18:46:22 +01003082 struct task_struct *dpc_thread;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003083 uint8_t dpc_active; /* DPC routine is active */
3084
Linus Torvalds1da177e2005-04-16 15:20:36 -07003085 dma_addr_t gid_list_dma;
3086 struct gid_list_info *gid_list;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07003087 int gid_list_info_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003088
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07003089 /* Small DMA pool allocations -- maximum 256 bytes in length. */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003090#define DMA_POOL_SIZE 256
Linus Torvalds1da177e2005-04-16 15:20:36 -07003091 struct dma_pool *s_dma_pool;
3092
3093 dma_addr_t init_cb_dma;
Andrew Vasquez3d716442005-07-06 10:30:26 -07003094 init_cb_t *init_cb;
3095 int init_cb_size;
Andrew Vasquezb64b0e82009-03-24 09:08:01 -07003096 dma_addr_t ex_init_cb_dma;
3097 struct ex_init_cb_81xx *ex_init_cb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003098
Andrew Vasquez5ff1d582010-05-04 15:01:26 -07003099 void *async_pd;
3100 dma_addr_t async_pd_dma;
3101
Andrew Vasquez7a677352012-02-09 11:15:56 -08003102 void *swl;
3103
Linus Torvalds1da177e2005-04-16 15:20:36 -07003104 /* These are used by mailbox operations. */
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003105 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3106 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3107 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003108
3109 mbx_cmd_t *mcp;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003110 struct mbx_cmd_32 *mcp32;
3111
Linus Torvalds1da177e2005-04-16 15:20:36 -07003112 unsigned long mbx_cmd_flags;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003113#define MBX_INTERRUPT 1
3114#define MBX_INTR_WAIT 2
Linus Torvalds1da177e2005-04-16 15:20:36 -07003115#define MBX_UPDATE_FLASH_ACTIVE 3
3116
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003117 struct mutex vport_lock; /* Virtual port synchronization */
Arun Easifeafb7b2010-09-03 14:57:00 -07003118 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003119 struct completion mbx_cmd_comp; /* Serialize mbx access */
Marcus Barrow0b05a1f2008-01-17 09:02:13 -08003120 struct completion mbx_intr_comp; /* Used for completion notification */
Sarang Radke23f2ebd2010-05-28 15:08:21 -07003121 struct completion dcbx_comp; /* For set port config notification */
Chad Dupuisf356bef2013-02-08 01:58:04 -05003122 struct completion lb_portup_comp; /* Used to wait for link up during
3123 * loopback */
3124#define DCBX_COMP_TIMEOUT 20
3125#define LB_PORTUP_COMP_TIMEOUT 10
3126
Sarang Radke23f2ebd2010-05-28 15:08:21 -07003127 int notify_dcbx_comp;
Chad Dupuisf356bef2013-02-08 01:58:04 -05003128 int notify_lb_portup_comp;
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04003129 struct mutex selflogin_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003130
Linus Torvalds1da177e2005-04-16 15:20:36 -07003131 /* Basic firmware related information. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003132 uint16_t fw_major_version;
3133 uint16_t fw_minor_version;
3134 uint16_t fw_subminor_version;
3135 uint16_t fw_attributes;
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08003136 uint16_t fw_attributes_h;
3137 uint16_t fw_attributes_ext[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003138 uint32_t fw_memory_size;
3139 uint32_t fw_transfer_size;
Andrew Vasquez441d1072006-05-17 15:09:34 -07003140 uint32_t fw_srisc_address;
3141#define RISC_START_ADDRESS_2100 0x1000
3142#define RISC_START_ADDRESS_2300 0x800
3143#define RISC_START_ADDRESS_2400 0x100000
Andrew Vasquez24a08132009-03-24 09:08:16 -07003144 uint16_t fw_xcb_count;
Chad Dupuis8d93f552013-01-30 03:34:37 -05003145 uint16_t fw_iocb_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003146
Chad Dupuisf73cb692014-02-26 04:15:06 -05003147 uint32_t fw_shared_ram_start;
3148 uint32_t fw_shared_ram_end;
3149
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003150 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003151 uint8_t fw_seriallink_options[4];
Andrew Vasquez3d716442005-07-06 10:30:26 -07003152 uint16_t fw_seriallink_options24[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003153
Andrew Vasquez55a96152009-03-24 09:08:03 -07003154 uint8_t mpi_version[3];
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08003155 uint32_t mpi_capabilities;
Andrew Vasquez55a96152009-03-24 09:08:03 -07003156 uint8_t phy_version[3];
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08003157
Chad Dupuisf73cb692014-02-26 04:15:06 -05003158 /* Firmware dump template */
3159 void *fw_dump_template;
3160 uint32_t fw_dump_template_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003161 /* Firmware dump information. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07003162 struct qla2xxx_fw_dump *fw_dump;
3163 uint32_t fw_dump_len;
Andrew Vasquezd4e3e042006-05-17 15:09:50 -07003164 int fw_dumped;
Hiral Patel61f098d2014-04-11 16:54:21 -04003165 unsigned long fw_dump_cap_flags;
3166#define RISC_PAUSE_CMPL 0
3167#define DMA_SHUTDOWN_CMPL 1
3168#define ISP_RESET_CMPL 2
3169#define RISC_RDY_AFT_RESET 3
3170#define RISC_SRAM_DUMP_CMPL 4
3171#define RISC_EXT_MEM_DUMP_CMPL 5
Linus Torvalds1da177e2005-04-16 15:20:36 -07003172 int fw_dump_reading;
Saurav Kashyapedaa5c72014-04-11 16:54:14 -04003173 int prev_minidump_failed;
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07003174 dma_addr_t eft_dma;
3175 void *eft;
Saurav Kashyap81178772012-08-22 14:21:04 -04003176/* Current size of mctp dump is 0x086064 bytes */
3177#define MCTP_DUMP_SIZE 0x086064
3178 dma_addr_t mctp_dump_dma;
3179 void *mctp_dump;
3180 int mctp_dumped;
3181 int mctp_dump_reading;
Andrew Vasquezbb99de62009-01-05 11:18:08 -08003182 uint32_t chain_offset;
Andrew Vasquezdf613b92008-01-17 09:02:17 -08003183 struct dentry *dfs_dir;
3184 struct dentry *dfs_fce;
3185 dma_addr_t fce_dma;
3186 void *fce;
3187 uint32_t fce_bufs;
3188 uint16_t fce_mb[8];
3189 uint64_t fce_wr, fce_rd;
3190 struct mutex fce_mutex;
3191
Andrew Vasquez3d716442005-07-06 10:30:26 -07003192 uint32_t pci_attr;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003193 uint16_t chip_revision;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003194
3195 uint16_t product_id[4];
3196
3197 uint8_t model_number[16+1];
3198#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
Joe Carnuccio1ee27142008-07-10 16:55:53 -07003199 char model_desc[80];
Andrew Vasquezcca53352005-08-26 19:08:30 -07003200 uint8_t adapter_id[16+1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003201
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003202 /* Option ROM information. */
3203 char *optrom_buffer;
3204 uint32_t optrom_size;
3205 int optrom_state;
3206#define QLA_SWAITING 0
3207#define QLA_SREADING 1
3208#define QLA_SWRITING 2
Joe Carnucciob7cc1762007-09-20 14:07:35 -07003209 uint32_t optrom_region_start;
3210 uint32_t optrom_region_size;
Chad Dupuis7a8ab9c2014-02-26 04:14:56 -05003211 struct mutex optrom_mutex;
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003212
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003213/* PCI expansion ROM image information. */
Andrew Vasquez30c47662007-01-29 10:22:21 -08003214#define ROM_CODE_TYPE_BIOS 0
3215#define ROM_CODE_TYPE_FCODE 1
3216#define ROM_CODE_TYPE_EFI 3
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003217 uint8_t bios_revision[2];
3218 uint8_t efi_revision[2];
3219 uint8_t fcode_revision[16];
Andrew Vasquez30c47662007-01-29 10:22:21 -08003220 uint32_t fw_revision[4];
3221
Madhuranath Iyengar0f2d9622010-07-23 15:28:26 +05003222 uint32_t gold_fw_version[4];
3223
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08003224 /* Offsets for flash/nvram access (set to ~0 if not used). */
3225 uint32_t flash_conf_off;
3226 uint32_t flash_data_off;
3227 uint32_t nvram_conf_off;
3228 uint32_t nvram_data_off;
3229
Andrew Vasquez7d232c72008-04-03 13:13:22 -07003230 uint32_t fdt_wrt_disable;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003231 uint32_t fdt_wrt_enable;
Andrew Vasquez7d232c72008-04-03 13:13:22 -07003232 uint32_t fdt_erase_cmd;
3233 uint32_t fdt_block_size;
3234 uint32_t fdt_unprotect_sec_cmd;
3235 uint32_t fdt_protect_sec_cmd;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003236 uint32_t fdt_wrt_sts_reg_cmd;
Andrew Vasquez7d232c72008-04-03 13:13:22 -07003237
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003238 uint32_t flt_region_flt;
3239 uint32_t flt_region_fdt;
3240 uint32_t flt_region_boot;
3241 uint32_t flt_region_fw;
3242 uint32_t flt_region_vpd_nvram;
Andrew Vasquez3d79038f2009-03-24 09:08:14 -07003243 uint32_t flt_region_vpd;
3244 uint32_t flt_region_nvram;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003245 uint32_t flt_region_npiv_conf;
Andrew Vasquezcbc8eb62009-06-03 09:55:17 -07003246 uint32_t flt_region_gold_fw;
Sarang Radke09ff7012010-03-19 17:03:59 -07003247 uint32_t flt_region_fcp_prio;
Giridhar Malavalia9083012010-04-12 17:59:55 -07003248 uint32_t flt_region_bootload;
Andrew Vasquezc00d8992008-09-11 21:22:49 -07003249
Linus Torvalds1da177e2005-04-16 15:20:36 -07003250 /* Needed for BEACON */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003251 uint16_t beacon_blink_led;
3252 uint8_t beacon_color_state;
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08003253#define QLA_LED_GRN_ON 0x01
3254#define QLA_LED_YLW_ON 0x02
3255#define QLA_LED_ABR_ON 0x04
3256#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3257 /* ISP2322: red, green, amber. */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003258 uint16_t zio_mode;
3259 uint16_t zio_timer;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08003260
Anirban Chakraborty73208df2008-12-09 16:45:39 -08003261 struct qla_msix_entry *msix_entries;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003262
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003263 struct list_head vp_list; /* list of VP */
3264 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3265 sizeof(unsigned long)];
3266 uint16_t num_vhosts; /* number of vports created */
3267 uint16_t num_vsans; /* number of vsan created */
3268 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3269 int cur_vport_count;
3270
3271 struct qla_chip_state_84xx *cs84xx;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003272 struct qla_statistics qla_stats;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003273 struct isp_operations *isp_ops;
Anirban Chakraborty68ca9492009-04-06 22:33:41 -07003274 struct workqueue_struct *wq;
Giridhar Malavali9a069e12010-01-12 13:02:47 -08003275 struct qlfc_fw fw_buf;
Sarang Radke09ff7012010-03-19 17:03:59 -07003276
3277 /* FCP_CMND priority support */
3278 struct qla_fcp_prio_cfg *fcp_prio_cfg;
Giridhar Malavalia9083012010-04-12 17:59:55 -07003279
3280 struct dma_pool *dl_dma_pool;
3281#define DSD_LIST_DMA_POOL_SIZE 512
3282
3283 struct dma_pool *fcp_cmnd_dma_pool;
3284 mempool_t *ctx_mempool;
3285#define FCP_CMND_DMA_POOL_SIZE 512
3286
3287 unsigned long nx_pcibase; /* Base I/O address */
3288 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
3289 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
Giridhar Malavalia9083012010-04-12 17:59:55 -07003290
3291 uint32_t crb_win;
3292 uint32_t curr_window;
3293 uint32_t ddr_mn_window;
3294 unsigned long mn_win_crb;
3295 unsigned long ms_win_crb;
3296 int qdr_sn_window;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003297 uint32_t fcoe_dev_init_timeout;
3298 uint32_t fcoe_reset_timeout;
Giridhar Malavalia9083012010-04-12 17:59:55 -07003299 rwlock_t hw_lock;
3300 uint16_t portnum; /* port number */
3301 int link_width;
3302 struct fw_blob *hablob;
3303 struct qla82xx_legacy_intr_set nx_legacy_intr;
3304
3305 uint16_t gbl_dsd_inuse;
3306 uint16_t gbl_dsd_avail;
3307 struct list_head gbl_dsd_list;
3308#define NUM_DSD_CHAIN 4096
Harish Zunjarrao9c2b2972010-05-28 15:08:23 -07003309
3310 uint8_t fw_type;
3311 __le32 file_prd_off; /* File firmware product offset */
Giridhar Malavali08de2842011-08-16 11:31:44 -07003312
3313 uint32_t md_template_size;
3314 void *md_tmplt_hdr;
3315 dma_addr_t md_tmplt_hdr_dma;
3316 void *md_dump;
3317 uint32_t md_dump_size;
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003318
Chad Dupuis5f16b332012-08-22 14:21:00 -04003319 void *loop_id_map;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003320
3321 /* QLA83XX IDC specific fields */
3322 uint32_t idc_audit_ts;
Santosh Vernekar454073c2013-08-27 01:37:48 -04003323 uint32_t idc_extend_tmo;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003324
3325 /* DPC low-priority workqueue */
3326 struct workqueue_struct *dpc_lp_wq;
3327 struct work_struct idc_aen;
3328 /* DPC high-priority workqueue */
3329 struct workqueue_struct *dpc_hp_wq;
3330 struct work_struct nic_core_reset;
3331 struct work_struct idc_state_handler;
3332 struct work_struct nic_core_unrecoverable;
Chad Dupuisf3ddac12013-10-30 03:38:16 -04003333 struct work_struct board_disable;
Santosh Vernekar7d613ac2012-08-22 14:21:03 -04003334
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003335 struct mr_data_fx00 mr;
3336
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003337 struct qlt_hw_data tgt;
Chad Dupuisa1b23c52014-02-26 04:15:12 -05003338 int allow_cna_fw_dump;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003339};
3340
3341/*
3342 * Qlogic scsi host structure
3343 */
3344typedef struct scsi_qla_host {
3345 struct list_head list;
3346 struct list_head vp_fcports; /* list of fcports */
3347 struct list_head work_list;
Andrew Vasquezf999f4c2009-06-03 09:55:28 -07003348 spinlock_t work_lock;
3349
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003350 /* Commonly used flags and state information. */
3351 struct Scsi_Host *host;
3352 unsigned long host_no;
3353 uint8_t host_str[16];
3354
3355 volatile struct {
3356 uint32_t init_done :1;
3357 uint32_t online :1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003358 uint32_t reset_active :1;
3359
3360 uint32_t management_server_logged_in :1;
3361 uint32_t process_response_queue :1;
Arun Easibad75002010-05-04 15:01:30 -07003362 uint32_t difdix_supported:1;
Arun Easifeafb7b2010-09-03 14:57:00 -07003363 uint32_t delete_progress:1;
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003364
3365 uint32_t fw_tgt_reported:1;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003366 } flags;
3367
3368 atomic_t loop_state;
3369#define LOOP_TIMEOUT 1
3370#define LOOP_DOWN 2
3371#define LOOP_UP 3
3372#define LOOP_UPDATE 4
3373#define LOOP_READY 5
3374#define LOOP_DEAD 6
3375
3376 unsigned long dpc_flags;
3377#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3378#define RESET_ACTIVE 1
3379#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3380#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3381#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3382#define LOOP_RESYNC_ACTIVE 5
3383#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3384#define RSCN_UPDATE 7 /* Perform an RSCN update. */
Shyam Sundarddb9b122009-03-24 09:08:10 -07003385#define RELOGIN_NEEDED 8
3386#define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3387#define ISP_ABORT_RETRY 10 /* ISP aborted. */
3388#define BEACON_BLINK_NEEDED 11
3389#define REGISTER_FDMI_NEEDED 12
3390#define FCPORT_UPDATE_NEEDED 13
3391#define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
3392#define UNLOADING 15
3393#define NPIV_CONFIG_NEEDED 16
Giridhar Malavalia9083012010-04-12 17:59:55 -07003394#define ISP_UNRECOVERABLE 17
3395#define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
Madhuranath Iyengarb1d46982010-09-03 15:20:54 -07003396#define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
Saurav Kashyap579d12b2010-12-21 16:00:14 -08003397#define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003398#define SCR_PENDING 21 /* SCR in target mode */
Chad Dupuis50280c02013-10-30 03:38:14 -04003399#define PORT_UPDATE_NEEDED 22
3400#define FX00_RESET_RECOVERY 23
3401#define FX00_TARGET_SCAN 24
3402#define FX00_CRITEMP_RECOVERY 25
Armen Baloyane8f5e952013-10-30 03:38:17 -04003403#define FX00_HOST_INFO_RESEND 26
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003404
3405 uint32_t device_flags;
Shyam Sundarddb9b122009-03-24 09:08:10 -07003406#define SWITCH_FOUND BIT_0
3407#define DFLG_NO_CABLE BIT_1
Giridhar Malavalia9083012010-04-12 17:59:55 -07003408#define DFLG_DEV_FAILED BIT_5
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003409
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003410 /* ISP configuration data. */
3411 uint16_t loop_id; /* Host adapter loop id */
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04003412 uint16_t self_login_loop_id; /* host adapter loop id
3413 * get it on self login
3414 */
3415 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
3416 * no need of allocating it for
3417 * each command
3418 */
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003419
3420 port_id_t d_id; /* Host adapter port id */
3421 uint8_t marker_needed;
3422 uint16_t mgmt_svr_loop_id;
3423
3424
3425
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003426 /* Timeout timers. */
3427 uint8_t loop_down_abort_time; /* port down timer */
3428 atomic_t loop_down_timer; /* loop down timer */
3429 uint8_t link_down_timeout; /* link down timeout */
3430
3431 uint32_t timer_active;
3432 struct timer_list timer;
3433
3434 uint8_t node_name[WWN_SIZE];
3435 uint8_t port_name[WWN_SIZE];
3436 uint8_t fabric_node_name[WWN_SIZE];
Andrew Vasquezbad70012009-04-06 22:33:38 -07003437
3438 uint16_t fcoe_vlan_id;
3439 uint16_t fcoe_fcf_idx;
3440 uint8_t fcoe_vn_port_mac[6];
3441
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003442 uint32_t vp_abort_cnt;
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003443
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003444 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003445 uint16_t vp_idx; /* vport ID */
3446
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003447 unsigned long vp_flags;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07003448#define VP_IDX_ACQUIRED 0 /* bit no 0 */
3449#define VP_CREATE_NEEDED 1
3450#define VP_BIND_NEEDED 2
3451#define VP_DELETE_NEEDED 3
3452#define VP_SCR_NEEDED 4 /* State Change Request registration */
3453 atomic_t vp_state;
3454#define VP_OFFLINE 0
3455#define VP_ACTIVE 1
3456#define VP_FAILED 2
3457// #define VP_DISABLE 3
3458 uint16_t vp_err_state;
3459 uint16_t vp_prev_err_state;
3460#define VP_ERR_UNKWN 0
3461#define VP_ERR_PORTDWN 1
3462#define VP_ERR_FAB_UNSUPPORTED 2
3463#define VP_ERR_FAB_NORESOURCES 3
3464#define VP_ERR_FAB_LOGOUT 4
3465#define VP_ERR_ADAP_NORESOURCES 5
Anirban Chakraborty7b867cf2008-11-06 10:40:19 -08003466 struct qla_hw_data *hw;
Saurav Kashyap0e8cd712014-01-14 20:40:38 -08003467 struct scsi_qlt_host vha_tgt;
Anirban Chakraborty2afa19a2009-04-06 22:33:40 -07003468 struct req_que *req;
Giridhar Malavalia9083012010-04-12 17:59:55 -07003469 int fw_heartbeat_counter;
3470 int seconds_since_last_heartbeat;
Saurav Kashyap2be21fa2012-05-15 14:34:16 -04003471 struct fc_host_statistics fc_host_stat;
3472 struct qla_statistics qla_stats;
Saurav Kashyapa9b6f7222012-08-22 14:21:01 -04003473 struct bidi_statistics bidi_stats;
Arun Easifeafb7b2010-09-03 14:57:00 -07003474
3475 atomic_t vref_count;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003476 struct qla8044_reset_template reset_tmplt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003477} scsi_qla_host_t;
3478
Nicholas Bellinger2d70c102012-05-15 14:34:28 -04003479#define SET_VP_IDX 1
3480#define SET_AL_PA 2
3481#define RESET_VP_IDX 3
3482#define RESET_AL_PA 4
3483struct qla_tgt_vp_map {
3484 uint8_t idx;
3485 scsi_qla_host_t *vha;
3486};
3487
Linus Torvalds1da177e2005-04-16 15:20:36 -07003488/*
3489 * Macros to help code, maintain, etc.
3490 */
3491#define LOOP_TRANSITION(ha) \
3492 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
Andrew Vasquez23443b12005-12-06 10:57:06 -08003493 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -07003494 atomic_read(&ha->loop_state) == LOOP_DOWN)
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07003495
Giridhar Malavali8ae6d9c2013-03-28 08:21:23 -04003496#define STATE_TRANSITION(ha) \
3497 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3498 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
3499
Arun Easifeafb7b2010-09-03 14:57:00 -07003500#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3501 atomic_inc(&__vha->vref_count); \
3502 mb(); \
3503 if (__vha->flags.delete_progress) { \
3504 atomic_dec(&__vha->vref_count); \
3505 __bail = 1; \
3506 } else { \
3507 __bail = 0; \
3508 } \
3509} while (0)
3510
3511#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3512 atomic_dec(&__vha->vref_count); \
3513} while (0)
3514
Linus Torvalds1da177e2005-04-16 15:20:36 -07003515/*
3516 * qla2x00 local function return status codes
3517 */
3518#define MBS_MASK 0x3fff
3519
3520#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3521#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3522#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3523#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3524#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3525#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3526#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3527#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3528#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3529#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3530
3531#define QLA_FUNCTION_TIMEOUT 0x100
3532#define QLA_FUNCTION_PARAMETER_ERROR 0x101
3533#define QLA_FUNCTION_FAILED 0x102
3534#define QLA_MEMORY_ALLOC_FAILED 0x103
3535#define QLA_LOCK_TIMEOUT 0x104
3536#define QLA_ABORTED 0x105
3537#define QLA_SUSPENDED 0x106
3538#define QLA_BUSY 0x107
Andrew Vasquezcca53352005-08-26 19:08:30 -07003539#define QLA_ALREADY_REGISTERED 0x109
Linus Torvalds1da177e2005-04-16 15:20:36 -07003540
Linus Torvalds1da177e2005-04-16 15:20:36 -07003541#define NVRAM_DELAY() udelay(10)
3542
Linus Torvalds1da177e2005-04-16 15:20:36 -07003543/*
3544 * Flash support definitions
3545 */
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08003546#define OPTROM_SIZE_2300 0x20000
3547#define OPTROM_SIZE_2322 0x100000
3548#define OPTROM_SIZE_24XX 0x100000
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07003549#define OPTROM_SIZE_25XX 0x200000
Andrew Vasquez3a03eb72009-01-05 11:18:11 -08003550#define OPTROM_SIZE_81XX 0x400000
Giridhar Malavalia9083012010-04-12 17:59:55 -07003551#define OPTROM_SIZE_82XX 0x800000
Giridhar Malavali6246b8a2012-02-09 11:15:34 -08003552#define OPTROM_SIZE_83XX 0x1000000
Giridhar Malavalia9083012010-04-12 17:59:55 -07003553
3554#define OPTROM_BURST_SIZE 0x1000
3555#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003556
Arun Easibad75002010-05-04 15:01:30 -07003557#define QLA_DSDS_PER_IOCB 37
3558
Giridhar Malavali4d78c972010-07-23 15:28:35 +05003559#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3560
Giridhar Malavali58548cb2010-09-03 15:20:56 -07003561#define QLA_SG_ALL 1024
3562
Giridhar Malavali4d78c972010-07-23 15:28:35 +05003563enum nexus_wait_type {
3564 WAIT_HOST = 0,
3565 WAIT_TARGET,
3566 WAIT_LUN,
3567};
3568
Linus Torvalds1da177e2005-04-16 15:20:36 -07003569#include "qla_gbl.h"
3570#include "qla_dbg.h"
3571#include "qla_inline.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07003572#endif